Display device and driving method thereof, source driving chip and timing controller

Abstract

This application provides a display device and its driving method, source driver chip, and timing controller. A row of pixels in the display device is electrically connected to two gate lines. Pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1 form a first pixel group. Pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i form a second pixel group. Along the row direction, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i-1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i have the opposite polarity to the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. This results in the arrangement direction of pixel groups with the same polarity having a tilt angle greater than 135 degrees relative to the row direction, improving the problem of slanted head-shaking patterns.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method, a source driver chip, and a timing controller. Background Technology

[0002] Data Line Sharing (DLS) architecture liquid crystal display panels reduce the number of data lines by increasing the number of gate lines, thereby reducing the number of source driver chips used and achieving cost reduction. In a DLS architecture liquid crystal display panel, each row of pixels is electrically connected to two gate lines. One gate line is connected to the pixels in the odd-numbered columns of that row, and the other gate line is connected to the pixels in the even-numbered columns of that row. One data line is electrically connected to two columns of pixels.

[0003] In DLS (Digital Substances) LCD panels, the polarity inversion method of pixels directly affects image quality. Existing DLS LCD panels typically employ a column-flip polarity inversion method, where pixels in adjacent columns along the row direction have opposite polarities. When the display panel size is small, this polarity inversion method makes the vertical wavy lines (or "hairline") issue less noticeable. However, as the display panel size increases, the pixel area also increases, and the vertical wavy lines caused by the column-flip method become increasingly apparent.

[0004] To mitigate the vertical crosstalk issue, existing technologies have improved the polarity reversal method, resulting in some improvement. However, the improved polarity reversal method still exhibits diagonal crosstalk along the 45-degree and 135-degree directions, which can still affect display quality for visually sensitive users. Furthermore, the current polarity reversal method involves frequent horizontal polarity changes, leading to greater coupling with the common electrode and more pronounced horizontal crosstalk, further impacting the display panel's image quality.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device and its driving method, source driver chip and timing controller, which aim to improve the problem of slanted head-shaking patterns in display devices with DLS architecture.

[0007] This application provides a display device, which includes a display panel. The display panel includes multiple data lines, multiple gate lines, and multiple pixels. The multiple pixels are arranged in a multi-row, multi-column pixel array. The multiple data lines include an adjacent j-th data line and a (j+1)-th data line. A row of pixels on the display panel is electrically connected to two gate lines. One of the two gate lines is electrically connected to a pixel in an odd-numbered column of the row, and the other gate line is electrically connected to a pixel in an even-numbered column of the row. Data line j is electrically connected to the pixels in column 2j-1 and column 2j. The pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1 form the first pixel group. The four pixels in the first pixel group have the same polarity, and the polarities of the two first pixel groups adjacent to each other along the column direction and electrically connected to the j-th data line are opposite. Data line j+1 is electrically connected to the pixels in column 2j+1 and column 2j+2. The pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i+1 form the first pixel group. The pixels in row 2i and row 2i constitute the i-th second pixel group. The four pixels in this second pixel group have the same polarity, and the polarities of the two adjacent second pixel groups along the column direction that are electrically connected to the (j+1)-th data line are opposite. Along the row direction, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i-1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. The polarity of the pixels in column +1 and the pixels in column 2j+2 located in row 2i is opposite. The polarity of the pixels in column 2j-1 and the pixels in column 2j located in row 2i+1 is the same as that of the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+1. The polarity of the pixels in column 2j-1 and the pixels in column 2j located in row 2i+2 is opposite to that of the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2. Where i is a positive integer and j is a positive integer.

[0008] This application also provides a driving method for a display device, the display device including a display panel, the display panel including multiple gate lines, multiple data lines and multiple pixels, the multiple pixels being arranged in a multi-row, multi-column pixel array, a row of pixels of the display panel being electrically connected to two gate lines, the driving method including: the j-th data line outputting a data signal to the (2j-1)-th column of pixels and the 2j-th column of pixels electrically connected to the j-th data line; the (j+1)-th data line outputting a data signal to the (2j+1)-th column of pixels and the 2j+2-th column of pixels electrically connected to the (j+1)-th data line. Output data signals; wherein, the pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1 constitute the i-th first pixel group, the four pixels in the first pixel group receive data signals with the same polarity, and the adjacent two first pixel groups electrically connected to the j-th data line along the column direction receive data signals with opposite polarities; the pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i constitute the i-th second pixel group, the four pixels in the second pixel group receive data signals with the same polarity. According to the polarity of the signals, the data signals received by two adjacent second pixel groups electrically connected to the (j+1)th data line along the column direction have opposite polarities; along the row direction, the data signals received by the pixels in the (2j-1)th column and the pixels in the (2i-1)th row of the (2j)th column have the same polarity as the data signals received by the pixels in the (2j+1)th column and the pixels in the (2i)th row of the (2j+2)th column have the same polarity, and the data signals received by the pixels in the (2j-1)th column and the pixels in the (2i)th row of the (2j+1)th column and the pixels in the (2i)th row of the (2j+2)th column have the same polarity as the data signals received by the pixels in the (2j-1)th column and the pixels in the (2i)th row of the (2j+1)th column and the pixels in the (2i)th row have the same polarity as the data signals received by the pixels in the (2j+1)th column and the pixels in the (2i)th row of the (2j+2)th column have the same polarity as the data signals received by the pixels in the (2j+1)th column and the pixels in the (2i)th row have the same polarity. The data signals received by the pixels in row 2i have opposite polarities. The data signals received by the pixels in column 2j-1 and the pixels in column 2j located in row 2i+1 have the same polarity as those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+1. The data signals received by the pixels in column 2j-1 and the pixels in column 2j located in row 2i+2 have opposite polarities to those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2. Where i is a positive integer and j is a positive integer.

[0009] This application also provides a source driver chip, which includes multiple data output channels, including a first channel, a second channel, a third channel, and a fourth channel; the source driver chip also includes a switching module, which is electrically connected to the second channel and the third channel; the first channel corresponds to the j-th data line, the second channel corresponds to the (j+1)-th data line, the third channel corresponds to the (j+2)-th data line, and the fourth channel corresponds to the (j+3)-th data line; the switching module is configured to switch the output connections of the second channel and the third channel, and the output port of the second channel after the switch is electrically connected to the (j+2)-th data line, and the output port of the third channel is electrically connected to the (j+1)-th data line; where j is a positive integer.

[0010] This application also provides a timing controller configured to receive image data and output processed image data to a source driver chip. The source driver chip includes multiple data output channels, including a first channel, a second channel, a third channel, and a fourth channel. The first channel corresponds to the j-th data line, the second channel corresponds to the (j+1)-th data line, the third channel corresponds to the (j+2)-th data line, and the fourth channel corresponds to the (j+3)-th data line. The timing controller is configured to rearrange the image data by swapping the image data corresponding to the (2j+1)-th and (2j+2)-th columns of pixels with the image data corresponding to the (2j+3)-th and (2j+4)-th columns of pixels. After the swap, the image data corresponding to the (2j+1)-th and (2j+2)-th columns of pixels are output to the third channel of the source driver chip, and the image data corresponding to the (2j+3)-th and (2j+4)-th columns of pixels are output to the second channel of the source driver chip. Here, j is a positive integer.

[0011] The display device provided in the embodiments of this application re-plans the pixel polarity arrangement, such that the pixels in the 2j-1 column and the 2j column, which are electrically connected to the j-th data line, located in the 2i and 2i+1 rows respectively, form a first pixel group; and the pixels in the 2j+1 column and the 2j+2 column, which are electrically connected to the j-th data line, located in the 2i-1 and 2i rows respectively, form a second pixel group. The first pixel group and the second pixel group are offset by one row in the column direction. Along the row direction, the pixels in the 2j-1 column and the 2j column, located in the 2i-1 row, have the same polarity as the pixels in the 2j+1 column and the 2j+2 column, located in the 2i-1 row; and the pixels in the 2j-1 column and the 2j column, located in the 2i row, have the opposite polarity to the pixels in the 2j+1 column and the 2j+2 column, located in the 2i row. This polarity arrangement results in a tilt angle greater than 135 degrees relative to the row direction for pixel groups of the same polarity on the display panel. Compared to the 45-degree and 135-degree slanted head-shaking patterns in the prior art, the embodiments of this application adjust the direction of the head-shaking patterns to a direction with a larger tilt angle. Since the larger the tilt angle, the less sensitive the human eye is to the head-shaking patterns, the display quality of the display device in the embodiments of this application is improved. Simultaneously, along the row direction, there are cases where four consecutive pixels in four adjacent columns have the same polarity. Compared to the prior art where the polarity of adjacent two columns of pixels changes alternately along the row direction, the embodiments of this application reduce the number of polarity changes, correspondingly reducing the coupling with the common electrode and improving the horizontal crosstalk problem.

[0012] The display device provided in the embodiments of this application further includes a source driver chip and a timing controller. The source driver chip includes a switching module, which is electrically connected to the second channel and the third channel. The switching module swaps the output connections of the second channel and the third channel, so that the output port of the second channel is electrically connected to the (j+2)th data line, and the output port of the third channel is electrically connected to the (j+1)th data line. The polarities of the data signals output by the first channel, the second channel, the third channel, and the fourth channel are positive, negative, positive, and negative, respectively. After being swapped by the switching module, the polarities of the data signals received by the j-th data line and the (j+1)th data line are both positive, and the polarities of the data signals received by the (j+2)th data line and the (j+3)th data line are both negative, thereby achieving a polarity arrangement in which four consecutive columns of pixels along the row direction have the same polarity. The timing controller rearranges the original image data, swapping the image data of the corresponding pixels in column 2j+1 and column 2j+2 with the image data of the corresponding pixels in column 2j+3 and column 2j+4. After the swapping module, the image data is transmitted to the corresponding pixel column, ensuring the correctness of the image display.

[0013] The driving method provided in the embodiments of this application improves the diagonal head-shaking pattern and horizontal crosstalk problem by controlling the pixel switches that are turned on at various times and the polarity of the data signals output by each channel, so that the pixels of the display panel present the above-mentioned polarity arrangement. The source driver chip provided in the embodiments of this application achieves the switching of adjacent channel output connections through a switching module, and, in conjunction with the image data rearrangement processing of the timing controller, realizes the above-mentioned polarity arrangement output. The timing controller provided in the embodiments of this application, through image data rearrangement processing, in conjunction with the switching module of the source driver chip, ensures that image data is transmitted to the corresponding pixel column. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0015] Figure 2 A schematic diagram of the polarity arrangement of a liquid crystal display panel using a horizontal four-point flipping method combined with a dual short-arm pixel architecture, provided for embodiments of this application.

[0016] Figure 3 A schematic diagram of a source driver chip provided for an embodiment of this application.

[0017] Figure 4 A schematic diagram showing a comparison of the data packet transmission order of a timing controller before and after switching, provided for embodiments of this application. Detailed Implementation

[0018] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0020] The technical solutions of different embodiments of this application can be combined with each other.

[0021] Embodiments of this application provide a display device, such as... Figure 1As shown, the display device includes a display panel DP, a timing controller TCON, and a source driver chip SDIC. The display panel DP is a liquid crystal display panel, including multiple data lines DL, multiple gate lines GL, and multiple pixels PX. The multiple pixels PX are arranged in a multi-row, multi-column pixel array. The display panel DP also includes a gate driver circuit GOA, which is electrically connected to the multiple gate lines GL. The gate driver circuit GOA outputs gate scan signals to the multiple gate lines GL to control the on / off switching of each row of pixels PX. The source driver chip SDIC is electrically connected to the multiple data lines DL and outputs data signals to the multiple data lines DL. The timing controller TCON receives image data from the system on chip (SOC), decodes the image data, performs mapping processing on the decoded image data, and transmits the mapped image data to the source driver chip SDIC.

[0022] The display panel (DP) employs a Data Line Sharing (DLS) architecture. This architecture reduces the number of data lines (DL) by increasing the number of gate lines (GL), thereby reducing the number of source driver chips (SDICs) and lowering costs. In the DLS architecture, each row of pixels in the DP is electrically connected to two gate lines (GL). One gate line (GL) is electrically connected to the pixels in the odd-numbered columns of that row, and the other gate line (GL) is electrically connected to the pixels in the even-numbered columns. One data line (DL) is electrically connected to two columns of pixels, either via two short connecting lines or one long connecting line and one short connecting line. When the data line (DL) is connected to two columns of pixels via two short connecting lines, it is located between the two columns of pixels. When the data line (DL) is connected to two columns of pixels via one long connecting line and one short connecting line, it is located on one side of the entire structure formed by the two columns of pixels.

[0023] like Figure 2 As shown, multiple data lines DL include the j-th data line and the (j+1)-th data line, where j is a positive integer. The j-th data line is electrically connected to the pixels in column 2j-1 and column 2j. The j-th data line is located between the pixels in column 2j-1 and column 2j. The pixels in column 2j-1 and column 2j located in rows 2i and 2i+1 form the i-th first pixel group, where i is a positive integer. The four pixels in the first pixel group have the same polarity, i.e., all are positive or all are negative. The polarities of two adjacent first pixel groups along the column direction that are electrically connected to the j-th data line are opposite, i.e., the positive and negative polarities of the multiple first pixel groups arranged along the column direction alternate.

[0024] The (j+1)th data line is electrically connected to the pixels in columns 2j+1 and 2j+2. The (j+1)th data line lies between the pixels in columns 2j+1 and 2j+2. The pixels in rows 2i-1 and 2i of columns 2j+1 and 2j+2 form the ith second pixel group. The four pixels in each second pixel group have the same polarity, either all positive or all negative. The polarities of two adjacent second pixel groups along the column direction that are electrically connected to the (j+1)th data line are opposite; that is, the positive and negative polarities of the multiple second pixel groups arranged along the column direction alternate.

[0025] The first and second pixel groups are offset by one row in the column direction. The first pixel group consists of pixels located in rows 2i and 2i+1, and the second pixel group consists of pixels located in rows 2i-1 and 2i. This offset relationship causes pixels of the same polarity to be arranged in a tilted direction on the display panel DP.

[0026] Along the row direction, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i-1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i have the opposite polarity to the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i+2 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2.

[0027] In embodiments of this application, the multiple data lines DL further include an adjacent (j+2)th data line and a (j+3)th data line. The (j+2)th data line is electrically connected to the (2j+3)th and (2j+4)th column pixels. The (j+2)th data line is located between the (2j+3)th and (2j+4)th column pixels. The pixels in the (2j+3)th and (2j+4)th columns located in the 2i and (2i+1)th rows constitute the ith third pixel group. The four pixels in the third pixel group have the same polarity. The polarities of two adjacent third pixel groups along the column direction that are electrically connected to the (j+2)th data line are opposite.

[0028] The (j+3)th data line is electrically connected to the pixels in columns 2j+5 and 2j+6. The (j+3)th data line lies between the pixels in columns 2j+5 and 2j+6. The pixels in rows 2i-1 and 2i of columns 2j+5 and 2j+6 form the ith fourth pixel group. The four pixels in the fourth pixel group have the same polarity. The polarities of two adjacent fourth pixel groups electrically connected to the (j+3)th data line along the column direction are opposite.

[0029] Along the row direction, the pixels in columns 2j+1 and 2j+2 located in row 2i-1 have the opposite polarity to the pixels in columns 2j+3 and 2j+4 located in row 2i-1. The pixels in columns 2j+1 and 2j+2 located in row 2i have the same polarity as the pixels in columns 2j+3 and 2j+4 located in row 2i. The pixels in columns 2j+1 and 2j+2 located in row 2i+1 have the opposite polarity to the pixels in columns 2j+3 and 2j+4 located in row 2i+1. The pixels in columns 2j+1 and 2j+2 located in row 2i+2 have the same polarity as the pixels in columns 2j+3 and 2j+4 located in row 2i+2.

[0030] Along the row direction, the pixels in columns 2j+3 and 2j+4 located in row 2i-1 have the same polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i-1. The pixels in columns 2j+3 and 2j+4 located in row 2i have the opposite polarity to the pixels in columns 2j+5 and 2j+6 located in row 2i. The pixels in columns 2j+3 and 2j+4 located in row 2i+1 have the same polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i+1. The pixels in columns 2j+3 and 2j+4 located in row 2i+2 have the opposite polarity to the pixels in columns 2j+5 and 2j+6 located in row 2i+2.

[0031] In the embodiments of this application, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1, the pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i, the pixels in column 2j+3 and the pixels in column 2j+4 located in rows 2i and 2i+1, and the pixels in column 2j+5 and the pixels in column 2j+6 located in rows 2i+1 and 2i+2 are all either positive or negative. The tilt angle α of the arrangement direction of pixels with either positive or negative polarity relative to the row direction is greater than 135 degrees, for example, the tilt angle α is 155 degrees.

[0032] The pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1, the pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i+1 and 2i+2, the pixels in column 2j+3 and the pixels in column 2j+4 located in rows 2i+2 and 2i+3, and the pixels in column 2j+5 and the pixels in column 2j+6 located in rows 2i+3 and 2i+4 all have a polarity that is either positive or negative. The orientation of the pixels with a polarity that is either positive or negative has a tilt angle α relative to the row direction that is greater than 135 degrees, for example, this tilt angle α is 155 degrees.

[0033] In the embodiments of this application, the tilt angle α of the arrangement direction of pixel groups of the same polarity on the display panel DP relative to the row direction is not within the range of 0 degrees to 90 degrees. (See Table 1 and...) Figure 2 As shown, compared to the 45-degree and 135-degree slanted head-shaking wrinkles in the prior art, the embodiments of this application adjust the direction of the head-shaking wrinkles to 155 degrees. Since the larger the tilt angle α, the less sensitive the human eye is to head-shaking wrinkles, the display quality of the display device in the embodiments of this application is improved. Simultaneously, in the row direction, there are cases where four consecutive pixels in four adjacent columns have the same polarity. Compared to the prior art where the polarity of adjacent two columns of pixels alternates along the row direction, the embodiments of this application reduce the number of polarity changes, correspondingly reducing the coupling between the pixel electrode and the common electrode, thus improving the horizontal crosstalk problem. The embodiments of this application use a polarity flipping method where every four pixels are grouped together in the horizontal direction.

[0034]

[0035] Table 1

[0036] Table 2 Taking a 3840×2160 resolution ultra-high-definition display panel (DP) as an example, as shown in Tables 1 and 2, the DP display panel includes eight columns of pixels and eight rows of pixels. The first to eighth columns of pixels correspond to columns 2j-1 to 2j+6, respectively. The first to eighth rows of pixels correspond to rows 2i-3 to 2i+4, respectively. The first data line 1 is electrically connected to the first and second columns of pixels; the second data line 2 is electrically connected to the third and fourth columns of pixels; the third data line 3 is electrically connected to the fifth and sixth columns of pixels; and the fourth data line 4 is electrically connected to the seventh and eighth columns of pixels.

[0037] In the first row of pixels, the first and second columns have positive polarity, the third and fourth columns have positive polarity, the fifth and sixth columns have negative polarity, and the seventh and eighth columns have negative polarity. In the second row of pixels, the first and second columns have negative polarity, the third and fourth columns have positive polarity, the fifth and sixth columns have positive polarity, and the seventh and eighth columns have negative polarity. In the third row of pixels, the first and second columns have negative polarity, the third and fourth columns have negative polarity, the fifth and sixth columns have positive polarity, and the seventh and eighth columns have positive polarity. In the fourth row of pixels, the first and second columns of pixels have positive polarity, the third and fourth columns have negative polarity, the fifth and sixth columns have negative polarity, and the seventh and eighth columns have positive polarity. The polarity arrangement of the pixels in the fifth to eighth rows is the same as that of the pixels in the first to fourth rows.

[0038] The display device provided in the embodiments of this application further includes a source driver chip SDIC and a timing controller TCON. The timing controller TCON receives image data from the system chip, decodes the image data, performs mapping processing on the decoded image data, and transmits the mapped image data to the source driver chip SDIC. For example... Figure 3 As shown, the source driver chip SDIC includes at least one switching module and multiple data output channels. The multiple data output channels include a first channel CH1, a second channel CH2, a third channel CH3, and a fourth channel CH4. The first channel CH1 corresponds to the j-th data line, the second channel CH2 corresponds to the (j+1)-th data line, the third channel CH3 corresponds to the (j+2)-th data line, and the fourth channel CH4 corresponds to the (j+3)-th data line. Each channel corresponds to one output pin of the source driver chip SDIC, and each output pin is electrically connected to one data line DL.

[0039] The switching module electrically connects the second channel CH2 and the third channel CH3. The switching module then swaps the output connections of the second channel CH2 and the third channel CH3. After the swap, the output port of the second channel CH2 is electrically connected to the (j+2)th data line, and the output port of the third channel CH3 is electrically connected to the (j+1)th data line.

[0040] The data signals output from the first channel CH1, the second channel CH2, the third channel CH3, and the fourth channel CH4 have polarities of positive, negative, positive, and negative, respectively. After being switched by the switching module, the data signal received by the j-th data line has a positive polarity, the data signal received by the (j+1)-th data line has a positive polarity, the data signal received by the (j+2)-th data line has a negative polarity, and the data signal received by the (j+3)-th data line has a negative polarity. This achieves a polarity arrangement where four consecutive columns of pixels along the row direction have the same polarity.

[0041] Because the switching module swaps the output connections of the second channel CH2 and the third channel CH3, the corresponding image data of the second channel CH2 and the third channel CH3 are also swapped simultaneously, resulting in image display disorder on the display panel DP. To solve this problem, the timing controller TCON rearranges the image data.

[0042] The timing controller TCON receives the raw image data. The raw image data consists of columns 1 through 8, arranged in column order. The first column corresponds to pixels in column 2j-1, the second column to pixel 2j, the third column to pixel 2j+1, the fourth column to pixel 2j+2, the fifth column to pixel 2j+3, the sixth column to pixel 2j+4, the seventh column to pixel 2j+5, and the eighth column to pixel 2j+6. The timing controller TCON transmits the image data in 8-bit RGB format, with each data packet containing either 4 or 8 pixels.

[0043] like Figure 4 As shown, the timing controller TCON rearranges the original image data, swapping the third and fourth columns of image data with the fifth and sixth columns. The swapped image data is then output to the source driver chip SDIC in the following order: first column, second column, fifth column, sixth column, third column, fourth column, seventh column, and eighth column. In other words, the data is converted into the sequence CH1, CH3, CH2, and CH4 for transmission.

[0044] After the switching module, the first and second column image data are transmitted to the (2j-1)th and (2j)th column pixels via the j-th data line; the third and fourth column image data are transmitted to the (2j+1)th and (2j+2)th column pixels via the (j+2)th data line; the fifth and sixth column image data are transmitted to the (2j+3)th and (2j+4)th column pixels via the (j+2)th data line; and the seventh and eighth column image data are transmitted to the (2j+5)th and (2j+6)th column pixels via the (j+3)th data line. After the channel switching by the source driver chip SDIC, the image is restored to the normal CH1, CH2, CH3, CH4 order, thus ensuring the correctness of the image display.

[0045] In embodiments of this application, the multiple data output channels further include a fifth channel CH5, a sixth channel CH6, a seventh channel CH7, and an eighth channel CH8. The fifth channel CH5 corresponds to the (j+4)th data line, the sixth channel CH6 corresponds to the (j+5)th data line, the seventh channel CH7 corresponds to the (j+6)th data line, and the eighth channel CH8 corresponds to the (j+7)th data line. The switching module also electrically connects the sixth channel CH6 and the seventh channel CH7. The switching module swaps the output connections of the sixth channel CH6 and the seventh channel CH7. After the swap, the output port of the sixth channel CH6 is electrically connected to the (j+6)th data line, and the output port of the seventh channel CH7 is electrically connected to the (j+5)th data line.

[0046] Embodiments of this application also provide a driving method for a display device. The display device includes a display panel DP, which includes multiple gate lines GL, multiple data lines DL, and multiple pixels PX. The multiple pixels PX are arranged in a multi-row, multi-column pixel array. One row of pixels on the display panel DP is electrically connected to two gate lines GL.

[0047] The driving method includes: the j-th data line outputting data signals to the (2j-1)th column pixels and the 2jth column pixels electrically connected to the j-th data line; and the (j+1)th data line outputting data signals to the (2j+1)th column pixels and the 2j+2th column pixels electrically connected to the (j+1)th data line.

[0048] The pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1 constitute the i-th first pixel group. The four pixels in the first pixel group receive data signals with the same polarity. Adjacent first pixel groups electrically connected to the j-th data line along the column direction receive data signals with opposite polarities. The pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i constitute the i-th second pixel group. The four pixels in the second pixel group receive data signals with the same polarity. Adjacent second pixel groups electrically connected to the j+1-th data line along the column direction receive data signals with opposite polarities.

[0049] Along the row direction, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 have the same data signal polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. The pixels in column 2j-1 and the pixels in column 2j located in row 2i have the opposite data signal polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. The pixels in column 2j-1 and the pixels in column 2j located in row 2i+2 have the same data signal polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2.

[0050] The driving method further includes: the (j+2)th data line outputting data signals to the (2j+3)th and (2j+4)th column pixels electrically connected to the (j+2)th data line; and the (j+3)th data line outputting data signals to the (2j+5)th and (2j+6)th column pixels electrically connected to the (j+3)th data line.

[0051] The pixels in columns 2j+3 and 2j+4 located in rows 2i and 2i+1 respectively constitute the i-th third pixel group. The four pixels in this third pixel group receive data signals with the same polarity. Adjacent third pixel groups electrically connected to the (j+2)-th data line along the column direction receive data signals with opposite polarities. The pixels in columns 2j+5 and 2j+6 located in rows 2i-1 and 2i respectively constitute the i-th fourth pixel group. The four pixels in this fourth pixel group receive data signals with the same polarity. Adjacent fourth pixel groups electrically connected to the (j+3)-th data line along the column direction receive data signals with opposite polarities.

[0052] Along the row direction, the pixels in columns 2j+1 and 2j+2 located in row 2i-1 receive data signals with opposite polarities to those in columns 2j+3 and 2j+4 located in row 2i-1. The pixels in columns 2j+1 and 2j+2 located in row 2i receive data signals with the same polarity as those in columns 2j+3 and 2j+4 located in row 2i. The pixels in columns 2j+1 and 2j+2 located in row 2i+1 receive data signals with opposite polarities to those in columns 2j+3 and 2j+4 located in row 2i+1. The pixels in columns 2j+1 and 2j+2 located in row 2i+2 receive data signals with the same polarity as those in columns 2j+3 and 2j+4 located in row 2i+2.

[0053] Along the row direction, the pixels in columns 2j+3 and 2j+4 located in row 2i-1 have the same data signal polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i-1. The pixels in columns 2j+3 and 2j+4 located in row 2i have the opposite data signal polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i. The pixels in columns 2j+3 and 2j+4 located in row 2i+1 have the same data signal polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i+1. The pixels in columns 2j+3 and 2j+4 located in row 2i+2 have the opposite data signal polarity as the pixels in columns 2j+5 and 2j+6 located in row 2i+2.

[0054] The display device also includes a source driver chip SDIC and a timing controller TCON. The source driver chip SDIC includes multiple data output channels and at least one switching module. The multiple data output channels include a first channel CH1, a second channel CH2, a third channel CH3, and a fourth channel CH4. The first channel CH1 corresponds to the j-th data line, the second channel CH2 corresponds to the (j+1)-th data line, the third channel CH3 corresponds to the (j+2)-th data line, and the fourth channel CH4 corresponds to the (j+3)-th data line.

[0055] The driving method also includes: the timing controller TCON receives raw image data from the system chip, decodes the raw image data, rearranges the decoded raw image data, and swaps the image data corresponding to the 2j+1 and 2j+2 columns of pixels with the image data corresponding to the 2j+3 and 2j+4 columns of pixels; the timing controller TCON outputs the rearranged image data to the source driver chip SDIC; the switching module switches the output connection of the second channel CH2 and the third channel CH3, so that the output port of the second channel CH2 is electrically connected to the j+2 data line, and the output port of the third channel CH3 is electrically connected to the j+1 data line.

[0056] After being rearranged by the timing controller TCON and swapped by the swapping module, the image data corresponding to the 2j-1 and 2j columns of pixels are transmitted to the 2j-1 and 2j columns of pixels via the j-th data line; the image data corresponding to the 2j+1 and 2j+2 columns of pixels are transmitted to the 2j+1 and 2j+2 columns of pixels via the j+1 data line; the image data corresponding to the 2j+3 and 2j+4 columns of pixels are transmitted to the 2j+3 and 2j+4 columns of pixels via the j+2 data line; and the image data corresponding to the 2j+5 and 2j+6 columns of pixels are transmitted to the 2j+5 and 2j+6 columns of pixels via the j+3 data line.

[0057] The polarities of the data signals output from the first channel CH1, the second channel CH2, the third channel CH3, and the fourth channel CH4 are positive, negative, positive, and negative, respectively. After being switched by the switching module, the data signal received by the j-th data line is positive, the data signal received by the (j+1)-th data line is positive, the data signal received by the (j+2)-th data line is negative, and the data signal received by the (j+3)-th data line is negative.

[0058] The multiple data output channels also include channel 5 (CH5), channel 6 (CH6), channel 7 (CH7), and channel 8 (CH8). Channel 5 (CH5) corresponds to the (j+4)th data line, channel 6 (CH6) corresponds to the (j+5)th data line, channel 7 (CH7) corresponds to the (j+6)th data line, and channel 8 (CH8) corresponds to the (j+7)th data line.

[0059] The driving method also includes: the timing controller TCON rearranges the original image data, swapping the image data corresponding to the 2j+9th and 2j+10th column pixels with the image data corresponding to the 2j+11th and 2j+12th column pixels; the switching module switches the output connection of the sixth channel CH6 and the seventh channel CH7, and the output port of the sixth channel CH6 after the switch is electrically connected to the j+6th data line, and the output port of the seventh channel CH7 is electrically connected to the j+5th data line.

[0060] As shown in Table 2, the driving method further includes: at a first moment, turning on the switch of the pixel located in row 2i-1 and column 2j-1, column 2j+1, column 2j+3 and column 2j+5, writing a positive data signal to the pixel in column 2j-1 through the first channel CH1, writing a positive data signal to the pixel in column 2j+1 through the third channel CH3 via the switching module, writing a negative data signal to the pixel in column 2j+3 through the second channel CH2 via the switching module, and writing a negative data signal to the pixel in column 2j+5 through the fourth channel CH4.

[0061] At the second moment, the switch located in row 2i-1 and in columns 2j, 2j+2, 2j+4, and 2j+6 is turned on. A positive data signal is written to the column 2j pixel through the first channel CH1, a positive data signal is written to the column 2j+2 pixel through the third channel CH3 via the switching module, a negative data signal is written to the column 2j+4 pixel through the second channel CH2 via the switching module, and a negative data signal is written to the column 2j+6 pixel through the fourth channel CH4.

[0062] At the third moment, the switches located in row 2i and in columns 2j-1, 2j+1, 2j+3, and 2j+5 are turned on. A negative data signal is written to the pixel in column 2j-1 through the first channel CH1, a positive data signal is written to the pixel in column 2j+1 through the third channel CH3 via the switching module, a positive data signal is written to the pixel in column 2j+3 through the second channel CH2 via the switching module, and a negative data signal is written to the pixel in column 2j+5 through the fourth channel CH4.

[0063] At the fourth moment, the switch located in row 2i and in columns 2j, 2j+2, 2j+4, and 2j+6 is turned on. A negative data signal is written to the 2j column pixel through the first channel CH1, a positive data signal is written to the 2j+2 column pixel through the third channel CH3 via the switching module, a positive data signal is written to the 2j+4 column pixel through the second channel CH2 via the switching module, and a negative data signal is written to the 2j+6 column pixel through the fourth channel CH4.

[0064] At the fifth moment, the switch located in row 2i+1 and in columns 2j-1, 2j+1, 2j+3, and 2j+5 is turned on. A negative data signal is written to the pixel in column 2j-1 through the first channel CH1, a negative data signal is written to the pixel in column 2j+1 through the third channel CH3 via the switching module, a positive data signal is written to the pixel in column 2j+3 through the second channel CH2 via the switching module, and a positive data signal is written to the pixel in column 2j+5 through the fourth channel CH4.

[0065] At the sixth moment, the switch located in row 2i+1 and in columns 2j, 2j+2, 2j+4, and 2j+6 is turned on. A negative data signal is written to the column 2j pixel through the first channel CH1, a negative data signal is written to the column 2j+2 pixel through the third channel CH3 via the switching module, a positive data signal is written to the column 2j+4 pixel through the second channel CH2 via the switching module, and a positive data signal is written to the column 2j+6 pixel through the fourth channel CH4.

[0066] At the seventh moment, the switch located in row 2i+2 and in columns 2j-1, 2j+1, 2j+3, and 2j+5 is turned on. A positive data signal is written to the column 2j-1 pixel through the first channel CH1, a negative data signal is written to the column 2j+1 pixel through the third channel CH3 via the switching module, a negative data signal is written to the column 2j+3 pixel through the second channel CH2 via the switching module, and a positive data signal is written to the column 2j+5 pixel through the fourth channel CH4.

[0067] At the eighth moment, the switch located in row 2i+2 and in columns 2j, 2j+2, 2j+4, and 2j+6 is turned on. A positive data signal is written to the column 2j pixel through the first channel CH1, a negative data signal is written to the column 2j+2 pixel through the third channel CH3 via the switching module, a negative data signal is written to the column 2j+4 pixel through the second channel CH2 via the switching module, and a positive data signal is written to the column 2j+6 pixel through the fourth channel CH4.

[0068] Embodiments of this application also provide a source driver chip SDIC. For example... Figure 3 As shown, the source driver chip SDIC includes multiple data output channels. These channels are CH1, CH2, CH3, and CH4. The SDIC also includes a switching module. This module electrically connects CH2 and CH3. CH1 corresponds to the j-th data line, CH2 to the (j+1)-th data line, CH3 to the (j+2)-th data line, and CH4 to the (j+3)-th data line, where j is a positive integer. The four channels of the SDIC are grouped together: CH1, CH2, CH3, and CH4.

[0069] The switching module swaps the output connections of the second channel CH2 and the third channel CH3. After the swap, the output port of the second channel CH2 is electrically connected to the (j+2)th data line, and the output port of the third channel CH3 is electrically connected to the (j+1)th data line.

[0070] The polarities of the data signals output from the first channel CH1, the second channel CH2, the third channel CH3, and the fourth channel CH4 are positive, negative, positive, and negative, respectively. After being switched by the switching module, the data signal received by the j-th data line is positive, the data signal received by the (j+1)-th data line is positive, the data signal received by the (j+2)-th data line is negative, and the data signal received by the (j+3)-th data line is negative.

[0071] Multiple data output channels also include channel 5 (CH5), channel 6 (CH6), channel 7 (CH7), and channel 8 (CH8). Channel 5 (CH5) corresponds to the (j+4)th data line, channel 6 (CH6) corresponds to the (j+5)th data line, channel 7 (CH7) corresponds to the (j+6)th data line, and channel 8 (CH8) corresponds to the (j+7)th data line. The switching module also electrically connects channel 6 (CH6) and channel 7 (CH7). The switching module swaps the output connections of channel 6 (CH6) and channel 7 (CH7). After the swap, the output port of channel 6 (CH6) is electrically connected to the (j+6)th data line, and the output port of channel 7 (CH7) is electrically connected to the (j+5)th data line.

[0072] Embodiments of this application also provide a timing controller TCON. For example... Figure 4 As shown, the timing controller TCON receives image data from the system chip, decodes the image data, performs mapping processing on the decoded image data, and outputs the processed image data to the source driver chip SDIC. The source driver chip SDIC includes multiple data output channels, namely channel CH1, channel CH2, channel CH3, and channel CH4. Channel CH1 corresponds to the j-th data line, channel CH2 corresponds to the (j+1)-th data line, channel CH3 corresponds to the (j+2)-th data line, and channel CH4 corresponds to the (j+3)-th data line. The timing controller TCON rearranges the image data by swapping the image data corresponding to the (2j+1)th and (2j+2)th columns of pixels with the image data corresponding to the (2j+3)th and (2j+4)th columns of pixels. The swapped image data corresponding to the (2j+1)th and (2j+2)th columns of pixels are then output to the third channel CH3 of the source driver chip SDIC, and the swapped image data corresponding to the (2j+3)th and (2j+4)th columns of pixels are output to the second channel CH2 of the source driver chip SDIC, where j is a positive integer.

[0073] The timing controller TCON also swaps the image data corresponding to the 2j+9th and 2j+10th columns with the image data corresponding to the 2j+11th and 2j+12th columns. After the swap, the image data corresponding to the 2j+9th and 2j+10th columns are output to the seventh channel CH7 of the source driver chip SDIC, and the image data corresponding to the 2j+11th and 2j+12th columns are output to the sixth channel CH6 of the source driver chip SDIC.

[0074] The display device, driving method, source driver chip SDIC, and timing controller TCON provided in the embodiments of this application are applicable to DLS architecture liquid crystal display panel products in the fields of televisions, computer monitors, and commercial displays. The embodiments of this application adjust the direction of the head-shaking pattern from 45 degrees and 135 degrees to 155 degrees. Since the steeper the slope, the less easily the human eye notices the head-shaking pattern, thus improving the image quality of the display panel DP at the subjective viewing angle α. Simultaneously, four consecutive pixels in the horizontal polarity flip reduce the number of polarity changes by half compared to existing technologies, reducing coupling relative to the common electrode and improving the horizontal crosstalk problem.

[0075] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes multiple data lines, multiple gate lines, and multiple pixels. The multiple pixels are arranged in a multi-row, multi-column pixel array, and the multiple data lines include an adjacent j-th data line and a j+1-th data line. A row of pixels in the display panel is electrically connected to two gate lines. One of the two gate lines is electrically connected to the pixels in the odd-numbered columns of the row of pixels, and the other gate line is electrically connected to the pixels in the even-numbered columns of the row of pixels. The j-th data line is electrically connected to the pixels in the (2j-1)-th column and the pixels in the 2j-th column. The pixels in the (2j-1)-th column and the pixels in the 2j-th column located in the 2i-th row and the 2i+1-th row constitute the i-th first pixel group. The four pixels in the first pixel group have the same polarity, and the polarities of the two first pixel groups that are adjacent to each other along the column direction and electrically connected to the j-th data line are opposite. The (j+1)th data line is electrically connected to the (2j+1)th column pixel and the (2j+2)th column pixel. The pixels in the (2j+1)th column pixel and the (2j+2)th column pixel located in the (2i-1)th row and the (2i)th row constitute the i-th second pixel group. The four pixels in the second pixel group have the same polarity, and the polarities of the two second pixel groups that are adjacent to each other along the column direction and electrically connected to the (j+1)th data line are opposite. Along the row direction, the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i-1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i have the opposite polarity to the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i-1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i+1 have the same polarity as the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+1. The pixels in column 2j-1 and the pixels in column 2j located in row 2i+2 have the opposite polarity to the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2. Where i is a positive integer and j is a positive integer.

2. The display device according to claim 1, characterized in that, The multiple data lines include the (j+2)th data line and the (j+3)th data line, which are adjacent to each other; The (j+2)th data line is electrically connected to the (2j+3)th and (2j+4)th column pixels. The pixels in the (2j+3)th and (2j+4)th columns located in the (2i)th and (2i+1)th rows form the (i)th third pixel group. The four pixels in the third pixel group have the same polarity, and the polarities of the two third pixel groups that are adjacent to each other along the column direction and electrically connected to the (j+2)th data line are opposite. The (j+3)th data line is electrically connected to the (2j+5)th and (2j+6)th column pixels. The pixels in the (2j+5)th and (2j+6)th columns located in the (2i-1)th and (2i)th rows form the ith fourth pixel group. The four pixels in the fourth pixel group have the same polarity, and the polarities of the two fourth pixel groups that are adjacent to each other along the column direction and electrically connected to the (j+3)th data line are opposite. Along the row direction, the pixels in the 2j+1 and 2j+2 columns located in the 2i-1 row have opposite polarities to the pixels in the 2j+3 and 2j+4 columns located in the 2i-1 row; the pixels in the 2j+1 and 2j+2 columns located in the 2i row have the same polarity as the pixels in the 2j+3 and 2j+4 columns located in the 2i row; the pixels in the 2j+1 and 2j+2 columns located in the 2i+1 row have opposite polarities to the pixels in the 2j+3 and 2j+4 columns located in the 2i+1 row; and the pixels in the 2j+1 and 2j+2 columns located in the 2i+2 row have the same polarity as the pixels in the 2j+3 and 2j+4 columns located in the 2i+2 row. Along the row direction, the pixels in the 2j+3 and 2j+4 columns located in row 2i-1 have the same polarity as the pixels in the 2j+5 and 2j+6 columns located in row 2i-1. The pixels in the 2j+3 and 2j+4 columns located in row 2i have the opposite polarity to the pixels in the 2j+5 and 2j+6 columns located in row 2i. The pixels in the 2j+3 and 2j+4 columns located in row 2i+1 have the same polarity as the pixels in the 2j+5 and 2j+6 columns located in row 2i+1. The pixels in the 2j+3 and 2j+4 columns located in row 2i+2 have the opposite polarity to the pixels in the 2j+5 and 2j+6 columns located in row 2i+2.

3. The display device according to claim 2, characterized in that, The display device further includes a source driver chip and a timing controller. The timing controller is configured to receive image data, process the image data, and output it to the source driver chip. The source driver chip includes at least one switching module and multiple data output channels, including a first channel, a second channel, a third channel, and a fourth channel. The first channel corresponds to the j-th data line, the second channel corresponds to the (j+1)-th data line, the third channel corresponds to the (j+2)-th data line, and the fourth channel corresponds to the (j+3)-th data line; The switching module is electrically connected to the second channel and the third channel. The switching module is configured to switch the output connections of the second channel and the third channel. After the switch, the output port of the second channel is electrically connected to the (j+2)th data line, and the output port of the third channel is electrically connected to the (j+1)th data line.

4. The display device according to claim 3, characterized in that, The polarities of the data signals output by the first channel, the second channel, the third channel, and the fourth channel are positive, negative, positive, and negative, respectively. After being switched by the switching module, the polarity of the data signal received by the j-th data line is positive, the polarity of the data signal received by the (j+1)-th data line is positive, the polarity of the data signal received by the (j+2)-th data line is negative, and the polarity of the data signal received by the (j+3)-th data line is negative.

5. The display device according to claim 4, characterized in that, The timing controller is configured as follows: Receive raw image data, which includes a first column of image data to an eighth column of image data arranged in column order. The first column of image data corresponds to the 2j-1th column of pixels, the second column of image data corresponds to the 2jth column of pixels, the third column of image data corresponds to the 2j+1th column of pixels, the fourth column of image data corresponds to the 2j+2nd column of pixels, the fifth column of image data corresponds to the 2j+3rd column of pixels, the sixth column of image data corresponds to the 2j+4th column of pixels, the seventh column of image data corresponds to the 2j+5th column of pixels, and the eighth column of image data corresponds to the 2j+6th column of pixels. The original image data is rearranged by swapping the third and fourth columns of image data with the fifth and sixth columns of image data, so that the swapped image data is output to the source driver chip in the order of the first column of image data, the second column of image data, the fifth column of image data, the sixth column of image data, the third column of image data, the fourth column of image data, the seventh column of image data, and the eighth column of image data. After being exchanged by the exchange module, the first column of image data and the second column of image data are transmitted to the (2j-1)th and 2jth columns of pixels via the jth data line; the third column of image data and the fourth column of image data are transmitted to the (2j+1)th and 2j+2th columns of pixels via the (j+1)th data line; the fifth column of image data and the sixth column of image data are transmitted to the (2j+3)th and 2j+4th columns of pixels via the (j+2)th data line; and the seventh column of image data and the eighth column of image data are transmitted to the (2j+5)th and 2j+6th columns of pixels via the (j+3)th data line.

6. The display device according to claim 3, characterized in that, The plurality of data output channels also include a fifth channel, a sixth channel, a seventh channel, and an eighth channel, wherein the fifth channel corresponds to the (j+4)th data line, the sixth channel corresponds to the (j+5)th data line, the seventh channel corresponds to the (j+6)th data line, and the eighth channel corresponds to the (j+7)th data line; The switching module is also electrically connected to the sixth channel and the seventh channel. The switching module is configured to switch the output connections of the sixth channel and the seventh channel. After the switch, the output port of the sixth channel is electrically connected to the (j+6)th data line, and the output port of the seventh channel is electrically connected to the (j+5)th data line.

7. The display device according to claim 2, characterized in that, The pixels in column 2j-1 and the pixels in column 2j located in row 2i-1, the pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i, the pixels in column 2j+3 and the pixels in column 2j+4 located in rows 2i and 2i+1, and the pixels in column 2j+5 and the pixels in column 2j+6 located in rows 2i+1 and 2i+2 are all either positive or negative. The arrangement direction of the pixels with either positive or negative polarity has an angle of inclination greater than 135 degrees relative to the row direction. The polarity of the pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1, the pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i+1 and 2i+2, the pixels in column 2j+3 and the pixels in column 2j+4 located in rows 2i+2 and 2i+3, and the pixels in column 2j+5 and the pixels in column 2j+6 located in rows 2i+3 and 2i+4 are both positive and negative. The arrangement direction of the pixels with the polarity of either positive or negative has an angle of inclination greater than 135 degrees relative to the row direction.

8. A driving method for a display device, characterized in that, The display device includes a display panel, which includes multiple gate lines, multiple data lines, and multiple pixels. The multiple pixels are arranged in a multi-row, multi-column pixel array. Each row of pixels on the display panel is electrically connected to two gate lines. The driving method includes: The j-th data line outputs data signals to the (2j-1)-th and (2j)-th columns of pixels electrically connected to the j-th data line; The (j+1)th data line outputs data signals to the (2j+1)th and (2j+2)th columns of pixels electrically connected to the (j+1)th data line; The pixels in column 2j-1 and the pixels in column 2j located in rows 2i and 2i+1 constitute the i-th first pixel group. The four pixels in the first pixel group receive data signals with the same polarity. The adjacent two first pixel groups electrically connected to the j-th data line along the column direction receive data signals with opposite polarities. The pixels in column 2j+1 and the pixels in column 2j+2 located in rows 2i-1 and 2i constitute the i-th second pixel group. The four pixels in the second pixel group receive data signals with the same polarity. The adjacent two second pixel groups electrically connected to the j+1 data line along the column direction receive data signals with opposite polarities. Along the row direction, the data signals received by the pixels in column 2j-1 and the pixels in column 2j located in row 2i-1 are the same polarity as those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. The data signals received by the pixels in column 2j-1 and the pixels in column 2j located in row 2i are opposite in polarity to those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i. The data signals received by the pixels in column 2j-1 and the pixels in column 2j located in row 2i+1 are the same polarity as those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2 are opposite in polarity to those received by the pixels in column 2j+1 and the pixels in column 2j+2 located in row 2i+2. Where i is a positive integer and j is a positive integer.

9. A source driver chip, characterized in that, The source driver chip includes multiple data output channels, including a first channel, a second channel, a third channel, and a fourth channel; The source driver chip also includes a switching module, which is electrically connected to the second channel and the third channel; The first channel corresponds to the j-th data line, the second channel corresponds to the (j+1)-th data line, the third channel corresponds to the (j+2)-th data line, and the fourth channel corresponds to the (j+3)-th data line. The switching module is configured to switch the output connections of the second channel and the third channel. After the switch, the output port of the second channel is electrically connected to the (j+2)th data line, and the output port of the third channel is electrically connected to the (j+1)th data line. Where j is a positive integer.

10. A timing controller, characterized in that, The timing controller is configured to receive image data and output the processed image data to the source driver chip. The source driver chip includes multiple data output channels, including a first channel, a second channel, a third channel, and a fourth channel. The first channel corresponds to the j-th data line, the second channel corresponds to the (j+1)-th data line, the third channel corresponds to the (j+2)-th data line, and the fourth channel corresponds to the (j+3)-th data line. The timing controller is configured to rearrange the image data by swapping the image data corresponding to the 2j+1 and 2j+2 columns of pixels with the image data corresponding to the 2j+3 and 2j+4 columns of pixels. The swapped image data corresponding to the 2j+1 and 2j+2 columns of pixels is then output to the third channel of the source driver chip, and the swapped image data corresponding to the 2j+3 and 2j+4 columns of pixels is then output to the second channel of the source driver chip. Where j is a positive integer.

Images