Fault early warning method, system and ring network box of integrated primary and secondary ring network box

Abstract

This invention relates to the field of smart distribution network and power equipment condition monitoring technology, and particularly to a fault early warning method, system, and ring network box for integrated primary and secondary ring network boxes. The method constructs a dynamic physical consistency constraint graph based on electrical topology and switch states, verifies multi-source time-series data, extracts conflicting data when constraints are violated, and updates it attenuation to obtain a basic confidence level. Simultaneously, it combines the real-time computing power of edge computing units to assess the expected inference time. Using the basic confidence level and expected inference time as joint gating conditions, when the confidence level exceeds the limit or the inference faces timeout risk, a second early warning path is triggered to output a conclusion within the deadline and generate early warning traceability data. This invention couples data consistency with edge computing power risk, avoiding decision delays and distortions, and ensuring the baseline reliability and traceability of early warnings under complex operating conditions.

Description

Technical Field

[0001] This invention relates to the field of smart distribution network and power equipment condition monitoring technology, and in particular to a fault early warning method, system and ring network box for a primary and secondary integrated ring network box. Background Technology

[0002] With the development of distribution network automation, integrated primary and secondary ring main units (RMUs) serve as important nodes in the distribution network. These units typically integrate primary-side electrical measurement components and secondary-side protection devices, with edge-side computing units processing the collected operational data to achieve operational status monitoring and fault early warning. Existing fault early warning technologies are mostly based on primary-side electrical measurement data and secondary-side protection status data, employing data-driven models or preset criteria to output early warning conclusions.

[0003] The inventors discovered that the aforementioned conventional early warning mechanisms have significant limitations and hidden dangers in actual, complex outdoor operating conditions. Firstly, multi-source time-series data naturally differ in sampling frequency, time alignment, measurement point binding relationships, and switch state transitions. Furthermore, under the influence of electromagnetic interference, sensor aging, and communication jitter, physical and logical inconsistencies or distortions can easily occur between data from different measurement points. Existing technologies typically lack cross-validation and conflict localization mechanisms based on electrical topology and conservation relationships. When conflicting or distorted data directly enters the upper-level early warning model, it can easily lead to unstable early warning conclusions and false alarms or missed alarms.

[0004] Secondly, high-precision early warning models often have high computational overhead. When fault disturbances cause a surge in transient data or an increase in concurrent tasks at the edge, the task queuing and inference time of the edge computing unit will increase significantly. At the same time, the heat dissipation conditions inside the sealed enclosure of the ring network box are limited, and the junction temperature of the core chip is prone to rising, triggering underlying thermal protection behaviors such as frequency reduction, further compressing the available computing power. Under these circumstances, existing technologies mostly adopt static scheduling strategies, which fail to couple and constrain the real-time computing power boundary at the edge with the time window required for fault early warning, resulting in the risk of timeout in early warning inference and making it difficult to output effective early warning conclusions within the required deadline.

[0005] Third, the early warning results of ring network boxes usually need to support post-event review and maintenance. Existing technologies do not retain enough key data and triggering basis in the early warning decision-making process. When abnormal situations such as path switching or inference timeout occur, it is difficult to effectively trace the source of conflicting data, gating parameters and triggering reasons, which is not conducive to subsequent closed-loop correction and model adaptive updates.

[0006] Therefore, there is an urgent need for a fault early warning method and system for integrated primary and secondary ring network enclosures, so that reliable early warning conclusions can be output within the early warning deadline in complex scenarios where multi-source data consistency is disturbed and edge computing power is limited, and the early warning process can be traced and subsequently closed-loop corrected. Summary of the Invention

[0007] (i) The technical problem to be solved by the present invention is that when the integrated primary and secondary ring network box is used to provide fault warning for complex distribution network conditions, the existing technology is difficult to effectively identify the physical and logical conflicts that occur in multi-source time series data, and it is difficult to accurately assess the timeliness risk of the warning task when the computing power of the edge device is limited. It lacks a dynamic degradation and retention mechanism that couples the consistency status of multi-source data with the real-time computing resources of the edge side, which makes it easy for conflicting measurement sequences to be directly input into the warning link with uncontrollable time consumption, thereby causing decision delays, distorted conclusions and untraceable abnormal operating conditions during the warning deadline.

[0008] (II) Technical Solution To address the aforementioned technical problems, a fault early warning method for a primary and secondary integrated ring network enclosure is provided, applied to an early warning system deployed in an edge computing unit. The method includes: S1. Obtain multi-source time-series data of the primary and secondary integrated ring network box, wherein the multi-source time-series data includes at least primary side electrical measurement data and secondary side protection status data; S2. Based on the electrical topology connection relationship and switch state transition relationship of the ring network box, construct a dynamic physical consistency constraint diagram; S3. Input the multi-source time series data into the dynamic physical consistency constraint graph for consistency verification. When a constraint violation is detected, extract the target conflict data set that causes the conflict, and perform a decay update on the preset initial confidence based on the target conflict data set to generate a basic confidence. S4. Based on the preset maximum allowable delay, or the mapping relationship between the warning level and the warning deadline, determine the fault warning deadline, and in conjunction with the real-time computing resource status of the edge computing unit, evaluate the expected inference time of the first warning path. S5. Use the basic confidence level and the expected inference time as joint gating conditions: when the basic confidence level is not lower than the preset confidence level lower bound and the expected inference time does not exceed the fault warning deadline, execute the first warning path to output the warning conclusion; otherwise, trigger the second warning path to output the warning conclusion within the fault warning deadline. S6. Generate and cache the early warning traceability data corresponding to the early warning conclusion. The early warning traceability data includes at least the target conflict data set, the parameters of the joint gating condition, and the determination basis for triggering the second early warning path.

[0009] A dynamic physical consistency constraint graph is constructed based on the electrical topology connection relationship and switch state transition relationship of the ring network box. Consistency verification is performed on multi-source time-series data. When constraint violation is detected, the target conflict data set is extracted to perform decay update on the preset initial confidence level. This transforms the physical and logical conflicts of the underlying multi-source data into a quantitative indicator characterizing data reliability. By combining the real-time computing resource status assessment of the edge computing unit to predict the inference time, and using the basic confidence level and the predicted inference time as joint gating conditions, the data consistency status is deeply coupled with the real-time computing power risk on the edge side. When the data confidence level exceeds the limit or the inference faces the risk of timeout, a second early warning path is decisively triggered, and a conclusion is output within the fault early warning deadline. At the same time, early warning traceability data containing the conflict set and judgment basis is generated. This avoids the direct input of conflicting measurement sequences into the time-consuming and uncontrollable early warning link, eliminates the risk of decision delay and conclusion distortion within the early warning deadline, ensures the bottom-line reliability of early warning decisions under complex operating conditions, and achieves accurate traceability of the abnormal operating condition triggering and degradation process.

[0010] Furthermore, the construction of the dynamic physical consistency constraint graph and the input of the multi-source time-series data into the dynamic physical consistency constraint graph for consistency verification include: extracting the measurement point binding fingerprints of the multi-source time-series data in the measurement link; establishing physical conservation nodes based on the electrical topology connection relationship, and mapping the multi-source time-series data matching the measurement point binding fingerprints to the corresponding physical conservation nodes; extracting the input and output time-series data of each physical conservation node within a preset time window, calculating the conservation deviation between the input and output time-series data, and determining whether the conservation deviation meets the preset electrical tolerance conditions.

[0011] By extracting fingerprints from measurement points and mapping time-series data to corresponding physical conservation nodes, a spatial correspondence can be established between discrete time-series data in multi-source acquisition links and the actual electrical topology of the ring network box, eliminating time-series misalignment caused by differences in transmission links between different measurement points. Simultaneously, by calculating the conservation deviation between the input and output time-series data of the physical conservation nodes within a preset time window and comparing this deviation with preset electrical tolerance conditions, the validity verification of the underlying data is transformed into a logical judgment conforming to the physical conservation law. Therefore, before the time-series data is input into the downstream early warning path, single-point distorted data caused by local sensor failures, electromagnetic interference, or communication anomalies can be identified, preventing distorted waveforms carrying physical logical conflicts from directly participating in subsequent early warning calculations and ensuring the data consistency of the input source for the early warning model.

[0012] Further, the step of extracting the target conflict data set that triggers the conflict when a constraint violation is detected, and performing a decay update on a preset initial confidence level based on the target conflict data set to generate a basic confidence level, includes: calculating the deviation contribution of each data item to the conservation deviation for the multi-source time-series data mapped to the physical conservation node where the constraint violation occurred; determining the data items whose deviation contribution meets preset screening conditions as the target conflict data set; obtaining the node importance weight corresponding to the target conflict data set in the electrical topology connection relationship; calculating a decay penalty value based on the deviation contribution of each data item and the corresponding node importance weight, and performing a decay update on the preset initial confidence level using the decay penalty value to obtain the basic confidence level.

[0013] By calculating the contribution of each data item to the conservation bias and extracting the target conflict data set according to preset screening conditions, specific data items causing physical conservation failures can be extracted from the mixed multi-source sequences where constraints are violated. This refines the granularity of conflict location to the level of a single measurement point, avoiding the indiscriminate discarding of all measurement data within the entire time window due to local measurement point anomalies. Simultaneously, by obtaining the node importance weight of the target conflict data set in the electrical topology and combining this weight with the bias contribution to calculate the attenuation penalty value, the local distortion amplitude of abnormal data is coupled and quantified with its global impact on the distribution network topology. Thus, the binary state labeling of traditional data verification, which is either black or white, is transformed into a continuous dynamic attenuation mechanism for data reliability. This allows the generated basic confidence level to objectively reflect the overall usability of the current multi-source time series data, providing a precise quantitative basis for the gating decision of the subsequent model inference path.

[0014] Preferably, after performing attenuation updates on the preset initial confidence level based on the target conflict data set to generate a basic confidence level, the method further includes: when determining that the target conflict data set contains current time-series data from the primary-side electrical measurement data, extracting the integral difference and / or waveform asymmetry features of adjacent positive and negative half-waves within the corresponding data frame; when determining that the DC bias micro-saturation distortion condition is met based on the integral difference and / or the waveform asymmetry features, performing waveform reconstruction on the distorted half-wave using historical feature parameters of the undistorted half-wave; and performing compensation updates on the basic confidence level based on the waveform repair measures before and after reconstruction, and using the updated basic confidence level as the input to the joint gating condition.

[0015] By extracting the integral difference and / or waveform asymmetry features of adjacent positive and negative half-waves within the current time-series data frame, the DC bias magnetic micro-saturation phenomenon occurring in primary-side transformers under complex electromagnetic environments or heavy load switching conditions can be accurately identified, tracing the apparent numerical conflicts back to the underlying physical sensing distortion mechanism. Furthermore, when the distortion condition is met, the waveform of the distorted half-wave is reconstructed using the historical features of the undistorted half-wave. In essence, this utilizes the physical symmetry of AC electrical systems to specifically repair the contaminated local waveform, restoring the true waveform representation of the electrical measurement data. Subsequently, the basic confidence level is compensated and updated based on the waveform repair metric, allowing the confidence level decay caused by specific physical distortions to be dynamically corrected. This avoids non-fault-state electromagnetic interference such as transformer micro-saturation being misjudged as permanent data failure, recovering measurement features with repair value, improving the availability of multi-source time-series data, and providing high-quality confidence input with underlying physical correction for downstream joint gating decisions.

[0016] Preferably, the step of assessing the estimated inference time of the first warning path by combining the real-time computing resource status of the edge computing unit includes: real-time acquisition of the core chip junction temperature and concurrent task queue length of the edge computing unit; calculating the thermal safety time window from the current core chip junction temperature to triggering the underlying hardware frequency reduction based on a preset temperature-frequency response relationship; and correcting the estimated inference time of the first warning path under the current resource status by combining the thermal safety time window and the concurrent task queue length.

[0017] By collecting the junction temperature of the core chip of the edge computing unit and the queue length of the concurrent task queue in real time, the physical and thermodynamic state of the edge device at the bottom layer and the task load of the upper layer software can be jointly characterized. On this basis, the thermal safety time window for triggering the frequency reduction of the underlying hardware is calculated based on the preset temperature-frequency response relationship. In essence, the thermal protection mechanism of the semiconductor chip is transformed into a time-domain boundary condition that constrains the calculation time of the complex early warning model. Furthermore, when evaluating the time taken for the first high-precision warning path, the thermal safety time window is combined with the concurrent task queuing length to proactively correct the expected inference time. This overcomes the limitation of traditional computing power assessment relying solely on the static nominal frequency of the processor, and incorporates the risk of nonlinear attenuation of computing power caused by the closed high-temperature environment of the ring network box and sudden failures into the calculation cycle consideration. It avoids severe tailing of the inference process caused by sudden hardware frequency reduction under high load conditions, so that the corrected expected inference time can truly reflect the actual computing delivery capability of edge devices under extreme conditions, providing a timely assessment basis for subsequent joint gating degradation decisions that conforms to the harsh reality of outdoor engineering.

[0018] Preferably, the triggering of the second early warning path, which outputs an early warning conclusion within the fault early warning deadline, includes: Extract the transient amplitude abrupt change and phase direction characteristics of the primary side electrical measurement data within the current time window; When the transient amplitude change exceeds a preset safety setting value and the duration reaches a preset time threshold, and the phase direction feature meets a preset fault direction condition, the warning conclusion is output.

[0019] By extracting the transient amplitude mutation and phase direction characteristics of primary electrical measurement data when the second early warning path is triggered, the early warning mechanism can be reduced from a time-consuming high-dimensional data-driven model to a deterministic logic judgment based on basic electrical parameters. At the same time, the transient amplitude mutation is judged by the dual constraints of preset safety setting value and preset time threshold, and the fault direction is screened by combining phase direction characteristics. In essence, a directional protection criterion that can shield transient non-fault disturbances (such as lightning inrush current or switch operation overvoltage) is constructed. Thus, in extreme cases where edge computing units face exhaustion of computing resources or large-scale logical conflicts of multi-source data, the complex reasoning process that is time-consuming and uncontrollable is bypassed, and the conclusion is quickly output based on the transient physical boundary conditions within the underlying time window. This avoids the early warning system missing the strict fault warning deadline due to waiting for high-precision calculation or data correction, and ensures that key nodes of the distribution network have the timeliness of bottom-line defense and the objective certainty of action direction in times of crisis.

[0020] Furthermore, after generating and caching the early warning tracing data corresponding to the early warning conclusion, the method further includes: monitoring the computing resource status and network communication load of the edge computing unit; when the computing resource status and network communication load meet the preset idle conditions, retrieving the early warning tracing data, performing offline feature tracing and supplementary calculation on the multi-source time-series data associated with the target conflict data set; updating the constraint parameters of the dynamic physical consistency constraint graph based on the supplementary calculation results, and / or correcting the preset confidence lower bound or the model parameters of the first early warning path.

[0021] By monitoring the computing resource status and network communication load of edge computing units, and retrieving early warning tracing data for offline supplementary calculation when preset idle conditions are met, the online early warning task with high real-time requirements and the offline tracing task with high computing power consumption can be decoupled in the time dimension. In essence, it utilizes the idle computing power troughs in the operating cycle of edge devices to perform in-depth secondary analysis of historical abnormal samples that trigger path degradation or logical conflicts. Then, after obtaining the supplementary calculation results, the constraint parameters of the dynamic physical consistency constraint graph, the preset confidence lower bound, or the model parameters of the first early warning path are updated and corrected, and the offline analysis conclusions are transformed into the iterative basis of system parameters, constructing a closed-loop adaptive feedback mechanism based on real operating conditions. As a result, the system avoids repeated unnecessary defensive degradation due to the solidification of judgment thresholds when facing slow changes in distribution network topology or seasonal operating condition drift. This allows the early warning system to extract boundary features under extreme operating conditions for autonomous evolution during long-term operation, and achieves long-term dynamic optimization of the edge-side diagnostic model and physical constraint boundaries without preempting core real-time protection computing power.

[0022] This invention also provides a fault early warning system for a primary and secondary integrated ring network enclosure, comprising: The electrical measurement component is configured on the primary side of the integrated primary and secondary ring network box and is used to collect primary side electrical measurement data. A secondary protection device is configured on the secondary side of the integrated primary and secondary ring network box and is used to output secondary protection status data. The edge computing unit is connected to the electrical measurement component and the secondary protection device via communication links to obtain multi-source time-series data containing the primary electrical measurement data and the secondary protection status data. The edge computing unit is configured with a fault warning logic architecture, which includes: The consistency graph construction module is used to construct a dynamic physical consistency constraint graph based on the electrical topology connection relationship and switch state transition relationship of the ring network box; The dynamic conflict verification module is used to input the multi-source time series data into the dynamic physical consistency constraint graph for consistency verification. When a constraint violation is detected, the target conflict data set that caused the conflict is extracted, and the preset initial confidence is decayed and updated based on the target conflict data set to generate a basic confidence. The resource consumption time assessment module is used to determine the fault warning deadline based on the preset maximum allowable delay or the mapping relationship between the warning level and the warning deadline, and to assess the expected inference time of the first warning path in conjunction with the real-time computing resource status of the edge computing unit. The joint gating and early warning module is used to use the basic confidence level and the expected inference time as joint gating conditions: when the basic confidence level is not lower than the preset confidence level lower bound and the expected inference time does not exceed the fault early warning deadline, the first early warning path is executed to output the early warning conclusion; otherwise, the second early warning path is triggered to output the early warning conclusion within the fault early warning deadline. The traceability data generation module is used to generate and cache the early warning traceability data corresponding to the early warning conclusion. The early warning traceability data includes at least the target conflict data set, the parameters of the joint gating conditions, and the determination criteria for triggering the second early warning path.

[0023] The present invention also provides a primary and secondary integrated ring network box, which includes: a box body; A primary-side electrical measurement component, disposed within the enclosure, is used to collect primary-side electrical measurement data; A secondary protection device, configured inside the enclosure, is used to output secondary protection status data; An edge computing unit is configured inside the enclosure and is connected to the primary side electrical measurement component and the secondary side protection device via communication links to obtain multi-source time-series data containing the primary side electrical measurement data and the secondary side protection status data. The edge computing unit includes at least one processor and a memory communicatively connected to the at least one processor; The memory stores computer instructions, which, when executed by the at least one processor, implement the fault early warning method for the primary and secondary integrated ring network box described above.

[0024] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the fault early warning method for the primary and secondary integrated ring network enclosure described in any of the above claims.

[0025] By integrating the early warning logic architecture with primary and secondary side measurement and protection hardware into the edge computing unit of the complete ring network box, the physical consistency verification of multi-source data and the gating degradation mechanism can be executed at the local end of the distribution network; the dependence of the fault early warning process on the main station communication bandwidth and cloud computing power is reduced, enabling the system and ring network box to have independent early warning decision-making capabilities under communication-constrained conditions.

[0026] (III) Beneficial effects of the present invention: By constructing a dynamic physical consistency constraint graph based on the electrical topology connection relationship and switch state transition relationship of the ring network box, consistency verification is performed on multi-source time-series data, and when constraint violation is detected, the target conflict data set is extracted to perform decay update on the preset initial confidence level, thereby transforming the physical and logical conflicts of the underlying multi-source data into quantitative indicators characterizing data reliability; By combining the real-time computing resource status assessment of the edge computing unit to predict the inference time, and using the basic confidence level and the predicted inference time as joint gating conditions, the data consistency status is deeply coupled with the real-time computing power risk on the edge side, thereby decisively triggering the second early warning path when the data confidence level exceeds the limit or the inference faces the risk of timeout, and outputting the conclusion within the fault early warning deadline, while generating early warning traceability data containing the conflict set and judgment basis; This avoids the direct input of conflicting measurement sequences into the time-consuming and uncontrollable early warning link, eliminates the risk of decision delay and conclusion distortion within the early warning deadline, ensures the bottom-line reliability of early warning decisions under complex working conditions, and realizes accurate traceability of the abnormal working condition triggering and degradation process. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 A schematic diagram of the system hardware architecture of a primary and secondary integrated ring network box provided in one embodiment of the present invention; Figure 2 This is a schematic diagram of a fault early warning method for a primary and secondary integrated ring network box provided in one embodiment of the present invention. Detailed Implementation

[0029] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Specific Implementation

[0030] This embodiment provides a fault early warning method, a fault early warning system, and a primary and secondary integrated ring network enclosure, and provides a corresponding computer-readable storage medium. This solution is applicable to ring network enclosure scenarios in smart distribution networks where local status monitoring and fault early warning are required. It is particularly suitable for operating conditions where multi-source measurements and status data exhibit asynchronous timing, complex measurement point binding relationships, and limited edge-side computing power and thermal boundaries during fault disturbances or high-load operation.

[0031] See Figure 1 The primary and secondary integrated ring network box of this embodiment includes a box body, and a primary side electrical measurement component, a secondary side protection device and an edge computing unit arranged in the box body.

[0032] The primary-side electrical measurement component is used to collect primary-side electrical measurement data. This component can be any or a combination of current / voltage transformers, electronic transformers, or other electrical measurement sensors. To support different accuracy and power consumption requirements, its analog-to-digital conversion circuit can employ a low-power ADC based on a SAR architecture or a high-precision ADC based on a Delta-Sigma architecture. Its sampling frequency is not limited to a single fixed value; for example, it can be flexibly configured to 4kHz, 10kHz, or 12.8kHz, etc., according to the transient and steady-state analysis requirements of the distribution network, to form a multi-dimensional digital time-series sampling sequence.

[0033] The secondary protection device is used to output secondary protection status data. The secondary protection device can be a measurement and control terminal, a protection measurement and control integrated device, or an intelligent electronic device (IED), used to output status data related to switch contact status, protection pressure plate, alarm events, etc.

[0034] The edge computing unit, serving as the carrier of fault early warning logic, is configured within the enclosure and includes at least one processor and a memory communicatively connected to the at least one processor. To support complex multi-source data processing, the processor is not limited to a specific architecture; it can be a heterogeneous SoC chip integrating an ARM core and an NPU neural network engine, a logic operation array combining an FPGA and a DSP, or an x86 architecture motherboard supporting industrial-grade edge computing.

[0035] The edge computing unit also integrates a board-level temperature acquisition component for real-time acquisition of the core chip junction temperature. The engineering implementation of this temperature acquisition component includes, but is not limited to: an independent digital temperature chip that communicates via an I2C / SPI interface, a thermistor array directly embedded inside the core chip package, or a PT100 / PT1000 platinum resistance thermometer attached to the surface of the heat dissipation substrate of the main heat source in conjunction with an analog conditioning circuit.

[0036] Furthermore, the edge computing unit can obtain the concurrent task queue length through various low-level system-level calls. For example, in environments running a real-time operating system (RTOS), it can obtain the length by directly reading the Ready Queue status register; in environments running time-sharing operating systems such as Linux, it can be obtained through the statistics interface of the CFS scheduler or the system file tree (such as the / proc or / sys directory); and in lightweight bare-metal or microkernel environments, it can be obtained by monitoring the task stack depth of the thread pool. These multi-dimensional parameter acquisition mechanisms collectively form a computing power evaluation data path on the edge side, encompassing both physical thermodynamic states and upper-layer software load.

[0037] Regarding communication links, the edge computing unit connects to both primary and secondary components via these links. These communication links include, but are not limited to, industrial Ethernet, redundant CAN buses, RS-485 serial buses, or fiber optic / cable links supporting the IEC 61850 standard. To support subsequent consistency checks and conflict localization, the multi-source time-series data carries identification information characterizing the physical data source during transmission encapsulation. This identification information, serving as the carrier for "measurement point binding fingerprints," also has various implementation forms, such as any one or a combination of information from the following: network layer device MAC or IP address, physical layer channel port number, application layer SV / GOOSE control block identifier (APPID), or data link layer VLAN tag.

[0038] In terms of storage organization, the memory may include volatile storage areas (such as SRAM or DDR series memory) and non-volatile storage areas (such as eMMC, NAND Flash, or EEPROM), and is divided into four partitions in logical or physical addresses according to the data processing lifecycle: One is the map configuration area, which is used to persistently store the configuration parameters related to the local electrical topology connection relationship of the ring network box and the Kirchhoff conservation nodes; Secondly, there is a multi-source data buffer, preferably using a ring buffer or ping-pong buffer mechanism, to synchronize timestamp alignment and roll-over buffering of multi-source time-series data containing measurement point-bound fingerprints; The third is the feature calculation and gating evaluation work area, which serves as intermediate computing memory for temporarily storing high-frequency read / write variables required for conservation bias calculation, target conflict data extraction, waveform reconstruction compensation, confidence dynamic decay, inference time consumption deduction, and joint gating determination. Fourthly, there is a traceable data storage area, which serves as an independent data retention sector. It is used to persistently store abnormal data slices (conflict sets), current junction temperature / queue length parameters, and the criteria for triggering the second early warning path when degradation is triggered, so as to support offline auditing and model correction during system idle periods.

[0039] Supported by the aforementioned hardware entities, communication bus, and storage partitions, when the computer instructions stored in the memory are executed by the processor, multiple functional modules (consistency graph construction module, dynamic conflict verification module, resource consumption time assessment module, joint gating early warning module, and traceability data generation module) are logically instantiated within the edge computing unit into a fault early warning logic architecture. The coordinated operation of each module physically relies strictly on the processor's data scheduling of each storage area, bus interaction, and the operating system's task scheduling mechanism. The specific execution method of the fault early warning method will be explained in detail below, in conjunction with steps S1 to S6.

[0040] like Figure 2 As shown, the fault early warning method for the primary and secondary integrated ring network box in this embodiment specifically includes the following steps: Step S1: Synchronous Acquisition and Computation Slice Organization of Multi-Source Timing Data. After the underlying operating system and bus communication of the edge computing unit are ready, the processor executes step S1 to acquire the multi-source timing data of the integrated primary and secondary ring network enclosure. The multi-source timing data includes at least primary-side electrical measurement data and secondary-side protection status data. Relying on the aforementioned multi-source data buffer, the processor continuously reads data packets sent from the underlying bus. To establish a unified computation time base, the processor extracts the time identifier information carried by each data frame at the software logic layer. The time identifier information can be a header timestamp, underlying sampling sequence number, local arrival time stamp, or a combination thereof. Relying on the underlying hardware clock or a high-precision time synchronization protocol (such as the IEEE 1588 PTP protocol or hardware pulse-per-second), the processor performs timing alignment operations on high-frequency primary-side electrical sampling points and low-frequency secondary-side status events. Through pointer offsets and index associations in memory, the processor integrates multi-source data with different sampling rates into a computation slice sequence under the same time segment, thereby providing an aligned input source for subsequent consistency analysis.

[0041] Step S2: Memory Construction and Topology Mapping of the Dynamic Physical Consistency Constraint Graph. After acquiring and aligning the data slices, the processor executes step S2 to construct a dynamic physical consistency constraint graph based on the electrical topology connections and switch state transition relationships of the ring network box. The specific algorithm implementation process is as follows: The processor first reads the static connection parameters in the graph configuration area and initializes a directed graph or adjacency matrix data structure in the feature calculation work area. In this data structure, the vertex set of the matrix is ​​defined as a physical conservation node, and the edge set is defined as an electrical transmission link. Subsequently, the processor parses the secondary protection state data in the corresponding time slice and extracts the switch displacement flags to obtain the switch state transition relationships. When the logic determines that a switch node has undergone a state change from closed to open, the processor synchronously sets the weight of the directed graph edge corresponding to that branch to zero in the dynamic physical consistency constraint graph, or removes the connection relationship from the adjacency matrix. Through this software update mechanism, the algorithm model can map the connectivity changes of the distribution network physical circuits in real time, ensuring that the topology model used for subsequent verification matches the actual operating conditions.

[0042] Step S3: Physical Consistency Verification, Anomaly Tracing, and Confidence Decay and Compensation. After the constraint graph is constructed, the processor enters the core data discrimination algorithm layer. The processor executes step S3, inputting the multi-source time-series data into the dynamic physical consistency constraint graph for consistency verification. When a constraint violation is detected, the processor extracts the target conflict data set that caused the conflict and performs a decay update on the preset initial confidence based on the target conflict data set to generate a basic confidence. Specifically, the process of constructing the dynamic physical consistency constraint graph and inputting the multi-source time-series data into the dynamic physical consistency constraint graph for consistency verification includes: the processor first extracts the measurement point binding fingerprints of the multi-source time-series data in the measurement link; then, it establishes physical conservation nodes based on the electrical topology connection relationship and maps the multi-source time-series data that matches the measurement point binding fingerprints to the corresponding physical conservation nodes. After memory mapping is completed, the processor extracts the input and output timing data of each physical conservation node within a preset time window, calculates the conservation deviation between the input and output timing data, and determines whether the conservation deviation meets the preset electrical tolerance conditions. In the algorithm configuration, the length of the preset time window can be adjusted according to the power frequency cycle, transient duration characteristics, and alignment accuracy, for example, covering one or more power frequency steady-state cycles. The calculation of the conservation deviation is preferably based on Kirchhoff's Current Law (KCL), and the core algebraic formula can be expressed as ΔI=|∑Iin-∑Iout|; in other equivalent implementations, this conservation deviation can also be determined based on power balance, energy conservation, or phasor consistency. The preset electrical tolerance conditions can be pre-tuned or dynamically calibrated based on line parameters, measurement errors, and operational fluctuations to form a tolerance threshold band for judging exceeding limits.

[0043] When the conservation deviation exceeds the preset electrical tolerance condition, the system determines that a constraint violation has occurred. To achieve fine-grained isolation of abnormal data and avoid marking the entire window of data as invalid, the system extracts the target conflict data set that caused the conflict when a constraint violation is detected, and performs a decay update on the preset initial confidence level based on the target conflict data set to generate a base confidence level. This includes: for the multi-source time-series data mapped to the physical conservation node where the constraint violation occurred, the processor calculates the deviation contribution of each data item to the conservation deviation in the feature calculation work area; this contribution can be obtained by calculating the proportion of the distorted variable of a single channel measurement value to the total conservation deviation. Subsequently, data items whose deviation contribution meets the preset screening conditions (e.g., ranking first in numerical order or exceeding a specific threshold) are determined as the target conflict data set. Further, the processor obtains the node importance weight corresponding to the target conflict data set in the electrical topology connection relationship; this weight is represented by coefficient parameters in the mapping table in the algorithm. Then, based on the deviation contribution of each data item and the corresponding node importance weight, a decay penalty value is calculated, and the decay penalty value is used to perform a decay update on the preset initial confidence level to obtain the basic confidence level. The processor deducts the aforementioned decay penalty value from the preset initial confidence level (e.g., the system's preset reliability benchmark value) proportionally and outputs the continuously quantized basic confidence level.

[0044] Furthermore, to address the electromagnetic disturbances that are easily triggered during transient processes in the distribution network, the algorithm layer introduces waveform error reconstruction logic. After performing attenuation updates on the preset initial confidence level based on the target conflict data set to generate a basic confidence level, the algorithm further includes: when it is determined that the target conflict data set contains current time-series data from the primary-side electrical measurement data, the processor calls a numerical integration algorithm to extract the integral difference and / or waveform asymmetry features of adjacent positive and negative half-waves within the corresponding data frame. Then, when it is determined that the DC bias magnetic micro-saturation distortion condition is met based on the integral difference and / or the waveform asymmetry features, the processor performs waveform reconstruction on the distorted half-wave using historical feature parameters of the undistorted half-wave. This reconstruction algorithm can be implemented using numerical methods such as time axis mirroring, interpolation fitting, or historical template replacement to repair contaminated distortion sections. After reconstruction, the processor performs compensation updates on the basic confidence level based on the waveform repair measurements before and after reconstruction, and uses the updated basic confidence level as input to the joint gating condition. The repair metric can be determined using indicators such as error improvement, residual convergence, or goodness of fit. For example, the mean squared error (MSE) improvement rate of the sequences before and after reconstruction can be calculated, and the processor can adjust the previously deducted base confidence value accordingly based on this metric. This underlying reconstruction and confidence compensation mechanism effectively prevents false isolation caused by transient operating conditions and maximizes the availability of data input for the early warning model.

[0045] Step S4: Mathematical evaluation of the expected inference time based on real-time computing power boundaries. Within the synchronization period for generating basic confidence, the system not only needs to quantify data quality but also must evaluate the execution capability of the underlying hardware. The processor executes step S4, determining the fault warning deadline based on the preset maximum allowable delay or the mapping relationship between the warning level and the warning deadline, and evaluating the expected inference time of the first warning path in conjunction with the real-time computing resource status of the edge computing unit. The fault warning deadline (denoted as T_deadline) can be a fixed hard real-time constraint (e.g., requiring output within 100ms) or a mapping hierarchy of different warning levels (e.g., a level 1 short-circuit fault mapped to 20ms, and a level 2 overload mapped to 500ms).

[0046] Regarding the quantification and time-consuming assessment of computing power status, in step S4, the assessment of the estimated inference time of the first warning path, combined with the real-time computing resource status of the edge computing unit, includes: the processor first collects the junction temperature (denoted as θ) of the core chip of the edge computing unit and the queue length of the concurrent task queue (denoted as L_q) in real time through the underlying sensors and system interface. The junction temperature θ can be obtained by reading the digital temperature sensor register on the I2C bus, and the queue length L_q can be obtained by the ready queue pointer of the operating system kernel. Subsequently, based on the preset temperature-frequency response relationship, the processor calculates the thermal safety time window (denoted as T_safe) from the current core chip junction temperature until the underlying hardware frequency reduction is triggered. This calculation logic maps to the chip's dynamic voltage-frequency adjustment (DVFS) protection mechanism, the core of which is to determine how long the chip can run at the highest nominal frequency under the current heat rate before being forced to reduce the frequency. After calculating this window, the processor further combines the thermal safety time window and the queue length of the concurrent task queue to correct the estimated inference time of the first warning path under the current resource status. In the specific underlying formula, the corrected predicted inference time (denoted as T_est) can be calculated using the formula T_est = (T_base / K_f(θ)) + (L_q × T_avg). Here, T_base is the baseline time of the first warning path model under nominal computing power; T_avg is the average scheduling cost of a single queued task; and K_f(θ) is the frequency degradation coefficient related to the core chip junction temperature. When T_est predicts that the time will exceed the thermal safety window T_safe, K_f(θ) is less than 1 (indicating that computing power attenuation leads to longer time consumption); otherwise, K_f(θ) equals 1. Through this mathematical formula, the system achieves accurate extrapolation of the nonlinear attenuation of computing power under extreme high temperatures or sudden high loads.

[0047] Step S5: Joint Gating and Adaptive Degradation Decision Based on Physical Features. After obtaining accurate time-consuming predictions and data confidence levels, the system enters the routing decision node of the early warning strategy. The processor executes step S5, using the base confidence level and the expected inference time as joint gating conditions: when the base confidence level is not lower than a preset lower bound and the expected inference time does not exceed the fault early warning deadline, the first early warning path is executed to output the early warning conclusion; otherwise, the second early warning path is triggered, and the early warning conclusion is output within the fault early warning deadline. Logically, this joint gating condition can be expressed as a Boolean algebraic expression: (C_base ≥ C_limit) AND (T_est ≤ T_deadline). Only when this expression is true will the system start the time-consuming and data-quality-critical first early warning path (such as deep neural network inference); once any condition is broken, the system decisively cuts off the first path and triggers degradation protection.

[0048] For the rapid backup execution logic after degradation, in step S5, triggering the second early warning path and outputting an early warning conclusion within the fault early warning deadline includes: extracting the transient amplitude change and phase direction features of the primary side electrical measurement data within the current time window. In algorithm implementation, the processor bypasses complex high-dimensional models and directly performs fast calculations on the underlying waveform slices. The transient amplitude change (denoted as ΔM) can be calculated using the difference formula ΔM = |X(n) - X(nN)|, where X(n) is the current sampling point and X(nN) is the corresponding point of the previous power frequency cycle; the phase direction feature can be obtained by calculating the transient zero-sequence power direction, with the core formula being P_0 = ∑(U_0(k) × I_0(k)). Furthermore, when the transient amplitude change exceeds a preset safety setting value and its duration reaches a preset time threshold, and the phase direction feature meets the preset fault direction condition, the early warning conclusion is output. For example, the differential mutation amount ΔM is required to be greater than the safety setting value for 5 consecutive milliseconds (to filter high-frequency inrush current spikes), and the sign of the zero-sequence power integral P_0 must satisfy the positive fault characteristics, i.e., fast blockout output. The second early warning path ensures that the system still has absolute timeliness for bottom-line defense when computing resources are exhausted by using algebraic operations and physical criteria that regress deterministically.

[0049] Step S6: Persistent Retention of Warning Data and Idle Period Closed-Loop Autonomous Evolution. After outputting the warning conclusion for any path and triggering the corresponding protection action, the system must provide data support for subsequent operation and maintenance audits and model optimization. The processor executes step S6 to generate and cache the warning traceability data corresponding to the warning conclusion. The warning traceability data includes at least the target conflict data set, the parameters of the joint gating condition (such as the specific junction temperature θ, queue length L_q, and calculated inference time T_est at the moment of triggering degradation), and the judgment criteria for triggering the second warning path (such as the value of transient amplitude change ΔM). The processor packages the above core parameters into a structured log and persistently writes it to the traceability sector of non-volatile memory.

[0050] More importantly, the early warning system possesses the ability to self-correct and dynamically evolve using historical anomaly slices. In step S6, after generating and caching the early warning traceability data corresponding to the early warning conclusion, the system further includes: the underlying operating system task scheduler continuously monitors the computing resource status and network communication load of the edge computing unit; when the computing resource status and network communication load meet preset idle conditions (e.g., CPU idle rate greater than 80% and network bandwidth utilization rate less than 10%), the processor retrieves the early warning traceability data and performs offline feature tracing and supplementary calculations on the multi-source time-series data associated with the target conflict data set. With sufficient idle computing power, the processor can perform deep secondary analysis on anomaly samples that were previously downgraded due to insufficient computing power or time. Finally, the processor updates the constraint parameters of the dynamic physical consistency constraint graph based on the supplementary calculation results, and / or corrects the preset confidence lower bound or the model parameters of the first early warning path. In the specific parameter correction mechanism, the system preferably uses the exponential moving average (EMA) algorithm to update the system threshold. For example, the formula for correcting the pre-set lower bound of confidence can be expressed as: C_limit(new) = α × C_limit(old) + (1-α) × C_offline, where C_offline is the true confidence requirement calculated by supplementing historical anomaly data using a high-precision model during idle time, and α is a smoothing weighting factor (e.g., 0.8). This idle-time feedback formula decouples online high real-time tasks from offline high-time-consuming tasks on the time axis, enabling the early warning system to extract boundary features under extreme conditions for autonomous evolution during long-term operation, thus realizing a mathematical closed loop for parameter optimization.

[0051] Based on the method flow described in steps S1 to S6 above, this embodiment also provides a logically corresponding fault early warning system. Each functional module in this system (such as the consistency graph construction module, dynamic conflict verification module, resource consumption time evaluation module, etc.) is physically instantiated as the execution process of specific software code running by the processor inside the edge computing unit. Simultaneously, this embodiment further provides a computer-readable storage medium. The computer-readable storage medium can be non-volatile, such as read-only memory (ROM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or phase-change memory (PCM); or it can be volatile, such as random access memory (RAM). Computer program instructions are persistently or temporarily stored on this storage medium. When these computer program instructions are read and executed by the processor of the edge computing unit or equivalent computing power terminal within the ring network enclosure, all the method logic involved in steps S1 to S6 above, such as data acquisition, physical verification, computing power gating degradation, and offline closed-loop correction, can be fully implemented.

[0052] It should be noted that, in the foregoing description of this embodiment, to ensure sufficient disclosure of the technical solution and engineering reproducibility, a large number of specific algorithm formulas and hardware calling mechanisms have been introduced. Examples include the calculation of the conserved deviation algebraic sum based on Kirchhoff's Current Law (KCL), micro-saturation discrimination based on the area integral of the positive and negative half-waves of the current, queuing length acquisition based on the ReadyQueue, and parameter correction formulas based on the Exponential Moving Average (EMA). The aforementioned specific mathematical models and interface calling methods are merely preferred instantiation schemes of this invention under specific hardware platforms and typical distribution network conditions, and do not constitute a substantial limitation on the scope of protection of this case. In actual engineering evolution and cross-platform porting, those skilled in the art can make equivalent substitutions for the aforementioned specific algorithms without departing from the core joint gating and physical verification logic of this invention. For example, the conservation deviation check can be replaced with energy balance calculation based on instantaneous reactive power theory (pq theory); the integral area difference algorithm can be equivalently replaced with singular value detection based on wavelet transform; or the EMA correction logic can be replaced with parameter state estimation based on Kalman filter. Such conventional algorithm modifications or mathematical equivalent derivations based on the underlying physical conservation mechanism and computing power perception mechanism all fall strictly within the protection scope defined in this application.

[0053] Furthermore, the terms "first," "second," etc., appearing in this document (e.g., first warning path, second warning path) are used only to logically distinguish different processing mechanisms or data branches, and should not be construed as indicating or implying the relative importance between the paths, nor do they imply a specific number of technical features or the absolute chronological order of execution. The features guided by terms such as "preferredly" and "in a specific implementation condition," appearing in this document, are intended to provide best practice references and are not necessary conditions for implementing this invention.

[0054] Finally, it should be noted that the above-described embodiments are only used to illustrate the technical solutions and physical implementation logic of the present invention in detail, and are not intended to limit its scope of protection. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions (such as changes in sensor selection, shifts in underlying communication protocols, or changes in the operating system) do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of protection of the technical solutions of the embodiments of the present invention.

Claims

1. A fault early warning method for a primary and secondary integrated ring network box, characterized in that, The method, applied to an early warning system deployed on an edge computing unit, includes: S1. Obtain multi-source time-series data of the primary and secondary integrated ring network box, wherein the multi-source time-series data includes at least primary side electrical measurement data and secondary side protection status data; S2. Based on the electrical topology connection relationship and switch state transition relationship of the ring network box, construct a dynamic physical consistency constraint diagram; S3. Input the multi-source time series data into the dynamic physical consistency constraint graph for consistency verification. When a constraint violation is detected, extract the target conflict data set that causes the conflict, and perform a decay update on the preset initial confidence based on the target conflict data set to generate a basic confidence. S4. Based on the preset maximum allowable delay, or the mapping relationship between the warning level and the warning deadline, determine the fault warning deadline, and in conjunction with the real-time computing resource status of the edge computing unit, evaluate the expected inference time of the first warning path. S5. Use the basic confidence level and the expected inference time as joint gating conditions: when the basic confidence level is not lower than the preset confidence level lower bound and the expected inference time does not exceed the fault warning deadline, execute the first warning path to output the warning conclusion; otherwise, trigger the second warning path to output the warning conclusion within the fault warning deadline. S6. Generate and cache the early warning traceability data corresponding to the early warning conclusion. The early warning traceability data includes at least the target conflict data set, the parameters of the joint gating condition, and the determination basis for triggering the second early warning path.

2. The fault early warning method for the primary and secondary integrated ring network box according to claim 1, characterized in that, The construction of the dynamic physical consistency constraint graph and the input of the multi-source time-series data into the dynamic physical consistency constraint graph for consistency verification include: Extract the fingerprints of the measurement points in the measurement link from the multi-source time-series data; A physical conservation node is established based on the electrical topology connection relationship, and the multi-source time series data that matches the fingerprint of the measurement point is mapped to the corresponding physical conservation node; Within a preset time window, the input timing data and output timing data of each physical conservation node are extracted, the conservation deviation between the input timing data and the output timing data is calculated, and it is determined whether the conservation deviation meets the preset electrical tolerance condition.

3. The fault early warning method for the primary and secondary integrated ring network box according to claim 2, characterized in that, The step of extracting the target conflict data set that triggers the conflict upon detecting a constraint violation, and performing a decay update on the preset initial confidence level based on the target conflict data set to generate a base confidence level, includes: For the multi-source time-series data mapped to the physical conservation nodes where constraints are violated, calculate the deviation contribution of each data item to the conservation deviation; The data items whose deviation contribution meets the preset screening conditions are identified as the target conflict data set; Obtain the node importance weights corresponding to the target conflict data set in the electrical topology connection relationship; The decay penalty value is calculated based on the deviation contribution of each data item and the corresponding node importance weight, and the decay penalty value is used to perform decay update on the preset initial confidence level to obtain the basic confidence level.

4. The fault early warning method for the integrated primary and secondary ring network box according to claim 1, characterized in that, After performing a decay update on the preset initial confidence level based on the target conflict data set to generate a base confidence level, the process further includes: When determining that the target conflict data set contains current time series data in the primary side electrical measurement data, extract the integral difference between adjacent positive half-waves and negative half-waves and / or waveform asymmetry features within the corresponding data frame; When the DC bias magnetic micro-saturation distortion condition is met based on the integral difference and / or the waveform asymmetry characteristics, waveform reconstruction is performed on the distorted half-wave using the historical characteristic parameters of the undistorted half-wave. Based on the waveform repair measures before and after reconstruction, the baseline confidence is compensated and updated, and the updated baseline confidence is used as the input to the joint gating condition.

5. The fault early warning method for the integrated primary and secondary ring network box according to claim 1, characterized in that, The step of assessing the estimated inference time of the first early warning path by combining the real-time computing resource status of the edge computing unit includes: Real-time acquisition of the junction temperature of the core chip of the edge computing unit and the queue length of the concurrent task queue; Based on the preset temperature-frequency response relationship, the thermal safety time window from the current core chip junction temperature to triggering the underlying hardware frequency reduction is calculated. By combining the thermal safety time window with the concurrent task queue length, the estimated inference time of the first warning path under the current resource status is corrected.

6. The fault early warning method for the primary and secondary integrated ring network box according to claim 1, characterized in that, The second early warning path is triggered, and an early warning conclusion is output within the fault early warning deadline, including: Extract the transient amplitude abrupt change and phase direction characteristics of the primary side electrical measurement data within the current time window; When the transient amplitude change exceeds a preset safety setting value and the duration reaches a preset time threshold, and the phase direction feature meets a preset fault direction condition, the warning conclusion is output.

7. The fault early warning method for the primary and secondary integrated ring network box according to any one of claims 1 to 6, characterized in that, After generating and caching the early warning traceability data corresponding to the early warning conclusion, the method further includes: Monitor the computing resource status and network communication load of the edge computing unit; When the computing resource status and the network communication load meet the preset idle conditions, the early warning tracing data is retrieved, and offline feature tracing and supplementary calculation are performed on the multi-source time series data associated with the target conflict data set; Based on the supplementary calculation results, the constraint parameters of the dynamic physical consistency constraint graph are updated, and / or the model parameters of the preset confidence lower bound or the first early warning path are corrected.

8. A fault early warning system for a primary and secondary integrated ring network enclosure, comprising: The electrical measurement component is configured on the primary side of the integrated primary and secondary ring network box and is used to collect primary side electrical measurement data. A secondary protection device is configured on the secondary side of the integrated primary and secondary ring network box and is used to output secondary protection status data. The edge computing unit is connected to the electrical measurement component and the secondary protection device via communication links to obtain multi-source time-series data containing the primary electrical measurement data and the secondary protection status data. The edge computing unit is characterized by being equipped with a fault early warning logic architecture, which includes: The consistency graph construction module is used to construct a dynamic physical consistency constraint graph based on the electrical topology connection relationship and switch state transition relationship of the ring network box; The dynamic conflict verification module is used to input the multi-source time series data into the dynamic physical consistency constraint graph for consistency verification. When a constraint violation is detected, the target conflict data set that caused the conflict is extracted, and the preset initial confidence is decayed and updated based on the target conflict data set to generate a basic confidence. The resource consumption time assessment module is used to determine the fault warning deadline based on the preset maximum allowable delay or the mapping relationship between the warning level and the warning deadline, and to assess the expected inference time of the first warning path in conjunction with the real-time computing resource status of the edge computing unit. The joint gating and early warning module is used to use the basic confidence level and the expected inference time as joint gating conditions: when the basic confidence level is not lower than the preset confidence level lower bound and the expected inference time does not exceed the fault early warning deadline, the first early warning path is executed to output the early warning conclusion; otherwise, the second early warning path is triggered to output the early warning conclusion within the fault early warning deadline. The traceability data generation module is used to generate and cache the early warning traceability data corresponding to the early warning conclusion. The early warning traceability data includes at least the target conflict data set, the parameters of the joint gating conditions, and the determination criteria for triggering the second early warning path.

9. A primary and secondary integrated ring network cage, comprising: Box; A primary-side electrical measurement component, disposed within the enclosure, is used to collect primary-side electrical measurement data; A secondary protection device, configured inside the enclosure, is used to output secondary protection status data; An edge computing unit is configured inside the enclosure and is connected to the primary side electrical measurement component and the secondary side protection device via communication links to obtain multi-source time-series data containing the primary side electrical measurement data and the secondary side protection status data. The edge computing unit is characterized in that it includes at least one processor and a memory communicatively connected to the at least one processor; The memory stores computer instructions, which, when executed by the at least one processor, implement the fault early warning method for the primary and secondary integrated ring network box as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the fault early warning method for the primary and secondary integrated ring network box as described in any one of claims 1 to 7.

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