Single-wire communication method, device, and storage medium
By analyzing the input signal to configure the target parameters and dynamically adjusting the single-wire communication frequency, the problem of poor compatibility of single-wire communication technology in high-frequency and complex electromagnetic environments is solved, achieving stable and high-frequency communication compatibility and real-time performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI YINGJIXIN SEMICON CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-06-02
AI Technical Summary
Existing single-wire communication technology has poor compatibility in high-frequency communication scenarios and complex electromagnetic environments, cannot meet diverse communication needs, and its fixed frequency makes it difficult to adjust in real time.
By parsing the input signal to obtain configuration information, dynamically configuring target parameters, adjusting the communication frequency to adapt to slave devices with different speeds, and using the PLL clock module to accurately identify the level clock number, an output signal that can be recognized by the target device is generated.
It achieves stable communication in high-frequency communication and complex electromagnetic environments, improves compatibility and real-time performance, and meets diverse communication needs.
Smart Images
Figure CN122137737A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a single-wire communication method, device and storage medium. Background Technology
[0002] In the field of communication technology, single-wire communication has been widely used in many fields such as industrial control, intelligent sensing, consumer electronics, and automotive electronics due to its significant advantages, including fewer interfaces, simple hardware structure, low wiring cost, and small footprint. For example, in microelectronic devices, its streamlined interface design can effectively adapt to the trend of miniaturization and integration of devices, and meet the layout requirements of limited internal space.
[0003] However, most single-wire communication technologies employ asynchronous communication modes, which, due to their inherent technical architecture limitations, suffer from insurmountable defects, hindering their application in high-frequency communication scenarios and complex electromagnetic environments. Traditional single-wire asynchronous communication frequencies are typically fixed; once the communication system is deployed, it's difficult to dynamically adjust them in real-time according to actual communication needs. When adapting to slave devices with different speeds or addressing transmission link losses, hardware circuitry or underlying protocols must be redesigned, resulting in poor compatibility and an inability to meet diverse high-frequency communication requirements. Summary of the Invention
[0004] One objective of this application is to provide a single-wire communication method, device, and storage medium to improve the technical problem of poor compatibility of related technologies and inability to meet diverse high-frequency communication requirements.
[0005] The first aspect of this invention provides a single-wire communication method applied to an electronic device. The single-wire communication device includes a host and multiple slave devices connected in sequence, wherein the electronic device is a slave device among the multiple slave devices. The single-wire communication method includes: In response to an input signal sent by a first target device, the input signal is parsed to obtain first configuration information, wherein the first target device is a master or a slave device; Based on the first configuration information of the input signal, target parameters are configured to obtain target configuration information, wherein the target parameters are the number of clock cycles of the input signal within the target data period; In response to the first target data in the target configuration information that matches the second target device, an output signal is obtained according to the target parameters and the first target data, wherein the second target device is a slave device of the next level of the reference device, the reference device is a slave device that responds to the input signal, and the output signal is a signal that can be recognized by the second target device; Based on the target configuration information, the communication frequency at which the reference device forwards the output signal to the second target device is adjusted to obtain the target frequency; The output signal is sent to the second target device at the target frequency so that the second target device performs a communication operation.
[0006] Optionally, in a first implementation of the first aspect of the present invention, the input signal consists of a first level and a second level with different level types, and the step of configuring target parameters based on the first configuration information of the input signal to obtain target configuration information includes: Based on the first configuration information, the clock count of the first level and the clock count of the second level are configured to obtain the configured clock count of the first level and the configured clock count of the second level. Target configuration information that matches the first configuration information is determined based on the clock count of the first level after configuration and the clock count of the second level after configuration.
[0007] Optionally, in a second implementation of the first aspect of the present invention, the target configuration information includes a register data frame, and the first target data in the target configuration information that matches the second target device includes: Obtain second target data matching the reference device from the register data frame, and store the second target data in a preset register, wherein the second target data is a portion of the data in the register data frame; The unmatched data in the register data frame excluding the second target data is taken as the first target data.
[0008] Optionally, in a third implementation of the first aspect of the present invention, the target configuration information further includes a read / write mode configuration header, a register address configuration header, and a data length configuration header, and the step of obtaining the second target data matching the reference device from the register data frame and storing the second target data into a preset register includes: In response to the read / write mode configuration header, it is determined that the reference device has entered write mode; In response to the register address configuration header, determine the target register address; In response to the data length configuration header, determine the number of words in the second target data; Based on the number of words in the second target data, and in response to the reference device entering write mode, the second target data is stored in the target register address.
[0009] Optionally, in a fourth implementation of the first aspect of the present invention, obtaining the output signal based on the target parameter and the first target data includes: The pulse width of the first level and the pulse width of the second level are determined based on the clock count of the configured first level and the clock count of the configured second level. The output signal is obtained based on the output level sequence of the pulse width of the first level and the pulse width of the second level, and the first target data.
[0010] Optionally, in a fifth implementation of the first aspect of the present invention, before parsing the input signal in response to the input signal sent by the first target device to obtain the first configuration information, the method further includes: acquiring the clock count of the first level and the clock count of the second level in the input signal; Determine the ratio of the clock count of the first level to the clock count of the second level, and identify the input signal based on the ratio.
[0011] Optionally, in a sixth implementation of the first aspect of the present invention, determining the ratio of the clock count of the first level to the clock count of the second level, and identifying the input signal based on the ratio, includes: In response to the ratio relationship being such that the number of clock cycles at the first level is greater than the number of clock cycles at the second level, the input signal is identified as a first communication signal; In response to the ratio relationship being that the number of clock cycles at the first level is less than the number of clock cycles at the second level, the input signal is identified as a second communication signal.
[0012] Optionally, in a seventh implementation of the first aspect of the present invention, configuring the target parameters based on the first configuration information of the input signal to obtain the target configuration information includes: Each time an input signal is received, the target parameters are configured once based on the first configuration information of the input signal to obtain the target configuration information.
[0013] A second aspect of the present invention provides an electronic device including a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, wherein, when the processor executes the one or more computer programs, the electronic device enables the single-wire communication method described above.
[0014] A third aspect of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the single-wire communication method described above.
[0015] The embodiments of this application can achieve the following technical effects: By parsing the input signal, the first configuration information is obtained; based on the first configuration information of the input signal, target parameters are configured to obtain target configuration information; by configuring the clock number of the input signal within the target data period, the communication frequency of the reference device forwarding the output signal to the second target device is adjusted to obtain the target frequency; by using the first target data and target parameters in the target configuration information that match the second target device, the output signal is obtained. The output signal is a signal that can be recognized by the second target device. The output signal is sent to the second target device at the target frequency, which improves the problem of fixed frequency in conventional single-line communication. It can simultaneously adjust the communication frequency by configuring the target parameters to meet the needs of diverse high-frequency communication and stable communication, thus improving compatibility. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a single-line communication device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 3 A flowchart illustrating a single-line communication method provided in an embodiment of this application; Figure 4 A schematic diagram of a register write operation provided in an embodiment of this application; Figure 5 The level sequence diagram provided for the embodiments of this application; Figure 6 This is a schematic diagram of the structure of a single-wire communication device provided in an embodiment of this application; Figure 7 This is another structural schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0019] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.
[0020] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.
[0021] Please see Figure 1 , Figure 1 This is a schematic diagram of a single-line communication device provided in an embodiment of this application. The single-line communication device 100 includes a host 11 and multiple slave devices connected in sequence.
[0022] The host 11 is used to transmit communication signals, which are used to transmit control commands and other data. The control commands are used to control the slave device to complete the communication operation. The slave device is used to receive communication signals and send target signals to the next slave device. The target signal is a signal that can be recognized by the next slave device.
[0023] The host 11 is connected to the slave devices and the slave devices are connected to each other via only one data cable.
[0024] The specific device configurations of the master unit 11 and the slave unit are as follows: Common specific device types for host computer 11 include microcontrollers / microcontrollers (MCUs), industrial control hosts, etc. Specifically, microcontrollers / microcontrollers (MCUs) include STM32 series, 51 microcontrollers, PIC microcontrollers, etc. Industrial control hosts include programmable logic controllers (PLCs), industrial PCs (IPCs), host computers, etc.
[0025] Taking an industrial control host as an example, with a programmable logic controller (PLC) as the host 11, common specific devices for slave devices can be relay modules, frequency converter slave control units, pneumatic valve controllers, etc.
[0026] Please see Figure 2 , Figure 2This is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of this application. Another electronic device 200 is also provided in this application. The electronic device 200 is one of a plurality of slave devices. The electronic device 200 includes an input port 21, a decoding module 22, a frequency control module 23, an output port 24, a PLL clock module 25, and a register 26. The input port 21, frequency control module 23, output port 24, PLL clock module 25, and register 26 are respectively connected to the decoding module 22.
[0027] Input port 21 is used to receive input signals sent by the first target device and can perform filtering and shaping on the input signals. The first target device is either the master device 11 or the slave device, and the input signal is a communication signal including control commands and other data. In industrial environments, there are interference sources such as frequency converters, relay switches, and motor start / stop devices, which can easily generate electromagnetic interference (EMI), power ripple, and high-frequency noise, leading to input signal distortion. Filtering and shaping effectively resist complex interference in industrial environments, significantly reducing problems such as header parsing errors and data loss caused by input signal distortion, and ensuring the accuracy of read and write operations on register 26.
[0028] The decoding module 22 is used to parse the input signal to obtain the first configuration information. The decoding module 22 sends the first configuration information to the register 26, the frequency control module 23, and the output port 24 respectively. The first configuration information is configuration information containing first target data and second target data. The first target data is data that can be identified by the next-level slave device, and the second target data is data containing control instructions.
[0029] The frequency control module 23 is used to configure target parameters, which are the number of clocks for the input signal within the target data period. The target data period refers to the return-to-zero code period corresponding to a single binary symbol. The return-to-zero code period refers to the period of the sum of the durations of the complete high and low levels corresponding to a single return-to-zero code. A return-to-zero code represents a signal unit of one binary digit. For example, the level sequence representing 0 is 0 code, and the level sequence representing 1 is 1 code. The level sequence refers to the sequence of high / low voltage states that alternate with time according to the return-to-zero code encoding rules. The number of clocks refers to the number of PLL clock pulses that last for the high / low levels of the input signal within the target data period, using the PLL clock as the counting reference. The PLL clock refers to the synchronous clock signal generated by the phase-locked loop circuit built into the slave device.
[0030] Output port 24 is connected to the input terminal of the next-level slave device. The target configuration information is sent through the frequency control module 23. Output port 24 is used to convert the second target data into a target signal with the target frequency and send the target signal to the next-level slave device.
[0031] PLL clock module 25 is used to count the number of clock cycles for high and low levels in the input signal.
[0032] Register 26 is used to store the second target data.
[0033] The electronic device 200 provided in this application embodiment can achieve highly reliable, low-latency, and interference-resistant communication and control effects. The input signal received from the input port 21 is accurately distinguished by the high and low level clock ratios of the input signal through the decoding module 22 combined with the 72MHz reference clock count of the PLL clock module 25, avoiding bit errors caused by inaccurate clocking. At the same time, the target parameters are configured through the frequency control module 23 to ensure that the decoding timing is strictly synchronized with the target communication frequency. The decoding module 22 directly writes the parsed control instructions into the register 26. The register 26 is linked with the peripheral drive circuit to achieve seamless connection between instruction parsing, writing, and execution. Based on the high-precision counting of the PLL clock module 25 and the judgment of the high and low level clock ratios of the input signal, electromagnetic interference can be effectively resisted. Even if the level signal fluctuates slightly, the input signal can be accurately identified by the clock ratio.
[0034] In this embodiment, a programmable logic controller (PLC) is used as an example. The PLC acts as the master (11), and the pneumatic valve controller acts as the slave (2MHz), enabling the transmission of communication signals. If a low-frequency communication of 2MHz is used between the PLC and the pneumatic valve controller, a single return-to-zero code period is 36 72MHz PLL clock cycles, corresponding to a period duration of approximately 500ns. The total transmission delay of the pneumatic valve controller's feedback signal and the transmission delay of the PLC issuing the start command exceed 1ms, which cannot meet the linkage timing requirements. The linkage timing requirements refer to the time coordination requirements that the pneumatic valve controller must follow when performing the entire process of receiving, parsing, and storing input signals. This ensures that the actions of each module in the pneumatic valve controller are triggered according to a preset timing sequence, avoiding problems such as signal parsing errors and input signal writing failures caused by timing misalignment, thus guaranteeing the reliability and real-time performance of the single-line communication device 100 throughout the entire process.
[0035] If the programmable logic controller (PLC) and the pneumatic valve controller use 8MHz high-frequency communication, the single return-to-zero code cycle is shortened to nine 72MHz PLL clocks, corresponding to a cycle length of approximately 125ns. The total delay of bidirectional signal transmission can be controlled within 300ns. The transmission delay of the pneumatic valve controller feedback signal and the transmission delay of the PLC issuing the start command total no more than 1ms, meeting the linkage timing requirements and enabling high-frequency communication between the master 11 and the slave 11.
[0036] Because it is asynchronous communication, the communicating parties usually need to agree on a fixed frequency for communication. Therefore, adjusting the communication frequency between the master 11 and the slave, and between slaves, is the core of adapting to the diverse high-frequency communication needs of industrial scenarios.
[0037] Therefore, this application embodiment also provides a single-wire communication method for adjusting the communication frequency between the master 11 and the slave device, and between slave devices. Please refer to... Figure 3 , Figure 3 This is a flowchart illustrating a single-wire communication method provided in an embodiment of this application. The single-wire communication method includes: S31: In response to the input signal sent by the first target device, parse the input signal to obtain the first configuration information, wherein the first target device is the host 11 or the slave device.
[0038] In step S31, the first target device transmits the input signal to the parsing module through the input port 21. The parsing module parses the input signal to obtain the first configuration information. The first configuration information is configuration information containing the first target data and the second target data. The first target data is data that can be recognized by the next-level slave device, and the second target data is data containing control instructions. The control instructions are used to control the slave device to complete the communication operation.
[0039] S32: Configure target parameters based on the first configuration information of the input signal to obtain target configuration information, wherein the target parameter is the number of clock cycles of the input signal within the target data period.
[0040] In step S32, the target parameters can be dynamically switched according to the input signal to adapt to multi-frequency communication requirements such as 2MHz / 4MHz / 6MHz / 8MHz. The number of high and low level clock cycles is counted using the target parameters as a benchmark to avoid bit errors caused by communication frequency mismatch. Based on the proportion judgment rule of the target configuration information, level fluctuations caused by industrial electromagnetic interference can be effectively resisted, ensuring communication stability. The proportion judgment rule is based on the target parameters, distinguishing between 0 / 1 codes by statistically analyzing the proportion of high and low level clock cycles.
[0041] S33: In response to the first target data matching the second target device in the target configuration information, an output signal is obtained based on the target parameters and the first target data, wherein the second target device is the next-level slave of the reference device, the reference device is the slave responding to the input signal, and the output signal is a signal that can be recognized by the second target device.
[0042] In step S33, after the reference device decodes the input signal, it filters out the first target data that matches the address of the second target device. Then, based on the target parameters and according to the proportion judgment rule, the first target data is encoded into a level sequence, and an output signal that can be recognized by the second target device is generated according to the level sequence. The first target data may include the address of the second target device, function instructions, or feedback data. By filtering data through address matching, erroneous instruction issuance is avoided, ensuring the directional transmission of data between the host 11 and the slave 11.
[0043] S34: Adjust the communication frequency of the reference device forwarding the output signal to the second target device based on the target configuration information to obtain the target frequency; In step S34, the target parameters are specifically the number of clock cycles for the first level and the second level within the target data period. The first level is either high or low, and the second level is either low or high. A 72MHz PLL clock is used to identify the communication frequency of the first configuration information. A certain number of input levels are collected within one target data period. The target frequency is configured according to the communication frequency of the first configuration information. The number of level clock cycles is counted based on the PLL clock module 25 to avoid frequency misjudgment caused by industrial interference and ensure timing synchronization of multi-level communication.
[0044] S35: Send an output signal to the second target device at the target frequency so that the second target device can perform a communication operation.
[0045] In step S35, the reference device sends the encoded output signal from output port 24 to the second target device at the adjusted target frequency. The second target device parses the output signal and performs communication operations such as command transmission and reception and data feedback based on the clock frequency ratio rule corresponding to the same target frequency. The target signal is transmitted directionally at the target frequency, and the second target device can respond quickly and complete the communication operation, meeting the real-time requirements of industry.
[0046] This application embodiment obtains first configuration information by parsing the input signal, configures target parameters based on the first configuration information of the input signal to obtain target configuration information, adjusts the communication frequency of the reference device forwarding the output signal to the second target device by configuring the clock number of the input signal within the target data period to obtain the target frequency, and obtains the output signal by using the first target data and target parameters in the target configuration information that match the second target device, and sends the output signal to the second target device at the target frequency. This improves the problem of fixed frequency in conventional single-line communication, and can simultaneously adjust the communication frequency by configuring the target parameters to meet the needs of diverse high-frequency communication and stable communication, thus improving compatibility.
[0047] The input signal consists of a first level and a second level with different level types. In step S32, the following steps can also be performed: S321: Based on the first configuration information, configure the clock count of the first level and the clock count of the second level to obtain the configured clock count of the first level and the configured clock count of the second level.
[0048] In step S321, the clock count of the first level and the clock count of the second level are configured according to the communication frequency in the first configuration information. For example, a 72MHz PLL clock module 25 is used to generate 2MHz, 4MHz, 6MHz and 8MHz return-to-zero codes. The communication frequency configuration uses 2 bits. The binary codes 0b00, 0b01, 0b10, and 0b11 are mapped to frequencies of 2MHz, 4MHz, 6MHz, and 8MHz respectively, controlling the slave device to forward the return-to-zero (RZ) code. The binary codes 0b00, 0b01, 0b10, and 0b11 are the binary values of the 2-bit communication frequency configuration. Binary code 0b00 corresponds to a frequency of 2MHz, binary code 0b01 corresponds to a frequency of 4MHz, binary code 0b10 corresponds to a frequency of 6MHz, and binary code 0b11 corresponds to a frequency of 8MHz. To enable output module 52 to generate RZ codes at four frequencies, frequency control module 23 configures the RZ code periods to be 36, 18, 12, and 9 clock cycles respectively, and configures the high-level times of the 0 / 1 codes to be 9 / 27, 4 / 14, 3 / 9, and 3 / 6 clock cycles respectively. For example, if a 72MHz PLL clock module 25 generates a 2MHz RZ code, then one data cycle is 36 clock cycles. If the input signal sent by the first target device is 0, a high level is sent for the first 9 clock cycles and a low level is sent for the next 27 clock cycles. If the input signal sent by the first target device is 1, a high level is sent for the first 27 clock cycles and a low level is sent for the next 9 clock cycles.
[0049] S322: Determine target configuration information that matches the first configuration information based on the clock count of the configured first level and the clock count of the configured second level.
[0050] In step S322, the number of level clocks is used directly as the basis for judgment to avoid frequency configuration deviation and ensure that the target configuration information corresponds accurately with the first configuration information.
[0051] In this embodiment of the application, the target configuration information includes a register data frame, and the following steps may also be performed in step S33: S331: Obtain the second target data that matches the reference device from the register data frame, and store the second target data into the preset register 26, wherein the second target data is a part of the data in the register data frame.
[0052] In step S331, the reference device filters out the second target data that matches its own address from the register data frame; and stores the second target data in the device's preset register 26 for hardware execution or feedback by the reference device. In this embodiment, extracting the second target data that matches its own address avoids executing instructions from other devices, eliminates erroneous operations, and storing the second target data in register 26 enables fast reading and writing of the second target data, meeting the rapid response requirements in industrial scenarios.
[0053] S333: Use the unmatched data in the register data frame after removing the second target data as the first target data.
[0054] In step S333, the register data frame contains target data from multiple slave devices. After the reference device filters out the second target data that matches itself, it defines the remaining unmatched data in the register data frame as the first target data.
[0055] In this embodiment of the application, the target configuration information further includes a read / write mode configuration header, a register address configuration header, and a data length configuration header. Step S331 further includes the following steps: S3311: In response to the read / write mode configuration header, determine that the reference device has entered write mode.
[0056] In step S3311, the read / write mode configuration header carries configuration instructions for register read / write operations. Write mode refers to the operation mode in which the first target device writes data / instructions to the reference device register via the communication link. Please refer to [link to relevant documentation]. Figure 4 , Figure 4This is a schematic diagram of a register write operation provided in an embodiment of this application. The target configuration information includes a communication frequency configuration header, a read / write mode configuration header, a register address configuration header, a data length configuration header, a null operator, first target data, and second target data. Each time an input signal is sent to the next slave device, the next slave device stores the target data matching its own into its own register. The master device 11 inputs the input signal to slave device 12 through input port SDI. Slave device 12 stores the second target data and sends the remaining data to slave device 13 through input port SDI2. Slave device 13 stores the first target data and sends the remaining data to slave device 14 through input port SDI3. Slave device 14 stores the third target data and sends the remaining data to slave device 15 through input port SDI4. Slave device 15 stores the fourth target data. The content of the target configuration information can be increased or decreased according to the number of slave devices, and is not limited to the communication method of four slave devices. The write configuration bit is 0b1, and the read / write configuration is 1 bit. Single-bit binary encoding is used to control the operation type of the reference device register. Encoding 0b0 indicates that the instruction reference device performs a read register operation, that is, reads the stored device status, parameters and other data from register 26; encoding 0b1 indicates that the instruction reference device performs a write register operation, that is, writes the second target data sent down to register 26.
[0057] S3312: In response to the register address configuration header, determine the target register address.
[0058] In step S3312, the register address configuration header carries the unique identifier code of the target register inside the reference device. The target register address refers to the unique identifier code of register 26 inside the reference device to be read / written. The register address configuration is 7 bits, and 7 bits of binary number can represent 2. 7 Different addresses, register addresses are used to distinguish different function registers within the reference device 26. The header is configured based on the register addresses to determine the target register address of the reference device.
[0059] S3313: In response to the data length configuration header, determine the number of words in the second target data.
[0060] In step S3313, the data length configuration header is used to specify the number of words in the second target data to be transmitted. The data length configuration is 7 bits, and the maximum data length that the data length configuration header can represent is 127 units, which meets the needs of short command and small batch parameter transmission in industrial control without occupying too much bandwidth.
[0061] S3314: Based on the number of words of the second target data and in response to the reference device entering write mode, store the second target data to the target register address.
[0062] In step S3314, the reference device first identifies the number of words in the second target data. At the same time, after detecting that it has entered the write mode triggered by the read / write configuration bit 0b1, it accurately stores the complete second target data into the corresponding register inside the reference device according to the 7-bit target register address.
[0063] The following steps may also be performed in step S33: S332: Determine the pulse width of the first level and the pulse width of the second level based on the clock count of the configured first level and the clock count of the configured second level.
[0064] In step S332, pulse width refers to the duration for which a level signal remains in the same state. Using a 72MHz PLL clock as a reference, the clock counts of the configured first level and the second level are converted into the actual duration of the level's duration.
[0065] The conversion formula is: Pulse width = Number of clock cycles × ; By converting the clock counts of the first level and the second level into pulse widths, estimation errors in the level duration are avoided, ensuring the timing accuracy of the output level sequence.
[0066] S334: The output signal is obtained based on the output level sequence of the pulse width of the first level and the pulse width of the second level, and the first target data.
[0067] In step S334, a level sequence conforming to the return-to-zero code rule is generated according to the calculated pulse width of the first level and the pulse width of the second level; then the level sequence is encoded and mapped with the first target data to finally obtain an output signal that can be recognized by the second target device.
[0068] In some embodiments, before parsing the input signal and obtaining the first configuration information in response to the input signal sent by the first target device, the single-wire communication method further includes: acquiring the clock count of the first level and the clock count of the second level in the input signal; determining the ratio of the clock count of the first level and the clock count of the second level; and identifying the input signal based on the ratio.
[0069] Please see Figure 5 , Figure 5 The level sequence diagram provided in this application embodiment allows the reference device to obtain the boundaries of different data periods through the level sequence, thereby locking the complete duration of a single return-to-zero code in the input signal, i.e., the time span of one return-to-zero code, with a 72MHz PLL clock as the timing reference; the clock count of the first level and the clock count of the second level within the statistical data period are counted, and the input signal is identified based on the ratio of the clock count of the first level and the clock count of the second level, which is the relationship between the proportion of the first level and the second level within the data period.
[0070] In some embodiments, determining the ratio of the clock count of the first level to the clock count of the second level, and identifying the input signal based on the ratio includes: identifying the input signal as a first communication signal in response to the ratio of the clock count of the first level being greater than the clock count of the second level; and identifying the input signal as a second communication signal in response to the ratio of the clock count of the first level being less than the clock count of the second level.
[0071] Taking a high level as the first level and a low level as the second level as an example, if the clock count of the first level is greater than the clock count of the second level, the input signal is identified as the first communication signal, which is a 1 code; if the clock count of the first level is less than the clock count of the second level, the input signal is identified as the second communication signal, which is a 0 code. The type of input signal is determined by the ratio of the high and low level clock counts, rather than the absolute level value, resulting in stronger resistance to industrial electromagnetic interference.
[0072] In some embodiments, configuring target parameters based on first configuration information of the input signal to obtain target configuration information includes: configuring target parameters once based on the first configuration information of the input signal each time an input signal is received, thereby obtaining target configuration information.
[0073] Using a single target data cycle as the time unit, at the start of the target data cycle, the reference device selects a frequency matching the first configuration information from a preset range of 2MHz, 4MHz, 6MHz, and 8MHz control slave forwarding return-to-zero codes. The first target device sends the first configuration information once for each input signal transmission. The reference device changes the frequency of the data cycle according to the first configuration information. If the frequency configurations of the first target device and the reference device are the same, the frequency of the data cycle is also the same, meaning there is no need to adjust the communication frequency.
[0074] In summary, the embodiments of this application have at least the following technical effects: 1) The embodiments of this application can improve the problem of fixed frequency in conventional single-line communication, and can simultaneously adjust the communication frequency by configuring target parameters to meet the needs of diverse high-frequency communication and stable communication, thereby improving compatibility.
[0075] 2) This application embodiment specifies four communication frequencies. The communication frequency can be adjusted in real time each time an input signal is sent, which can conveniently meet the requirements of high-speed communication and communication stability in harsh environments.
[0076] 3) Based on the high-precision counting of the PLL clock module 25 and the determination of the high and low level clock ratio of 0 / 1 code, the embodiments of this application can effectively resist electromagnetic interference. Even if the level signal fluctuates slightly, the zero code can be accurately identified by the clock ratio.
[0077] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.
[0078] As another aspect of the embodiments of this application, this application provides a single-wire communication device. The single-wire communication device can be a software module, which includes several instructions stored in a memory. A processor can access the memory, call the instructions, and execute them to complete the single-wire communication method described in the various embodiments above.
[0079] In some embodiments, the single-wire communication device can also be constructed from hardware components. For example, the single-wire communication device can be constructed from one or more chips, which can work in coordination to complete the single-wire communication method described in the various embodiments above. As another example, the single-wire communication device can also be constructed from various logic devices, such as general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, ARM (Acorn RISC Machine) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components.
[0080] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a single-line communication device provided in an embodiment of this application. The single-line communication device 500 includes: an input module 51, an output module 52, a decoding module 22, and a frequency control module 23.
[0081] The input module 51 is used to receive input signals sent by the first target device.
[0082] The output module 52 is used to send an output signal to the second target device at the target frequency.
[0083] The decoding module 22 is used to parse the input signal and obtain the first configuration information.
[0084] The frequency control module 23 is used to configure target parameters based on the first configuration information of the input signal to obtain target configuration information, wherein the target parameter is the number of clock cycles of the input signal within the target data period, responding to the first target data in the target configuration information that matches the second target device, and obtaining an output signal based on the target parameter and the first target data, wherein the second target device is the next-level slave of the reference device, the reference device is a slave responding to the input signal, the output signal is a signal that can be recognized by the second target device, and the communication frequency of the reference device forwarding the output signal to the second target device is adjusted based on the target configuration information to obtain the target frequency.
[0085] In some embodiments, the frequency control module 23 is specifically configured to configure the clock count of the first level and the clock count of the second level based on the first configuration information, obtain the configured clock count of the first level and the configured clock count of the second level, and determine the target configuration information that matches the first configuration information based on the configured clock count of the first level and the configured clock count of the second level.
[0086] In some embodiments, the decoding module 22 is specifically used to obtain second target data that matches the reference device from the register data frame, and store the second target data in a preset register 26, wherein the second target data is a portion of the data in the register data frame, and the unmatched data in the register data frame excluding the second target data is used as the first target data.
[0087] In some embodiments, the frequency control module 23 is specifically configured to determine that the reference device enters the write mode in response to the read / write mode configuration header, determine the target register address in response to the register address configuration header, determine the number of words of the second target data in response to the data length configuration header, and store the second target data to the target register address based on the number of words of the second target data and in response to the reference device entering the write mode.
[0088] In some embodiments, the output module 52 is specifically used to determine the pulse width of the first level and the pulse width of the second level based on the clock count of the configured first level and the clock count of the configured second level, and to obtain an output signal based on the output level sequence of the pulse width of the first level and the pulse width of the second level and the first target data.
[0089] In some embodiments, the decoding module 22 is specifically used to acquire the target data period of the input signal, collect the clock count of the first level and the clock count of the second level in the input signal within the target data period, determine the ratio of the clock count of the first level and the clock count of the second level, and identify the input signal based on the ratio.
[0090] In some embodiments, the decoding module 22 is specifically configured to identify the input signal as a first communication signal when the clock count of the first level with a proportional relationship is greater than the clock count of the second level, and to identify the input signal as a second communication signal when the clock count of the first level with a proportional relationship is less than the clock count of the second level.
[0091] In some embodiments, the decoding module 22 is specifically used to select a frequency that is different from the communication frequency in the previous data period from at least two preset communication frequencies as the target frequency when the target data period arrives, wherein the previous data period is the data period arranged before the target data period.
[0092] Please see Figure 7 , Figure 7 This is another structural schematic diagram of an electronic device provided in an embodiment of this application. As another aspect of an embodiment of this application, an electronic device 200 is provided. The electronic device 200 includes one or more processors 27 and a memory 28. The memory 28 is connected to one or more processors 27, for example, via a bus.
[0093] Processor 27 is configured to support the electronic device 200 in performing the corresponding functions in the methods described in the above method embodiments. Processor 27 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
[0094] Memory 28 is used to store program code, etc. Memory 28 may include volatile memory (VM), such as random access memory (RAM); memory 28 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 28 may also include combinations of the above types of memory.
[0095] The memory 28 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the single-wire communication method in the embodiments of this application. The processor 27 executes various functional applications and data processing of the single-wire communication method and the single-wire communication device 500 by running the non-volatile software programs, instructions, and modules stored in the memory 28, that is, it realizes the functions of the single-wire communication method and the various modules or units of the single-wire communication device 500 provided in the above method embodiments.
[0096] The memory 28 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the single-wire communication device 500, etc. In some embodiments, the memory 28 may optionally include remotely located memories 28 relative to the processor 27, which can be connected to the single-wire communication device 500 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0097] The one or more modules are stored in the memory 28. When executed by the one or more processors 27, they perform the single-line communication method in any of the above method embodiments. For example, they perform the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.
[0098] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by an electronic device 200, cause the electronic device 200 to perform the method described in the foregoing embodiments.
[0099] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0100] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.
Claims
1. A single-wire communication method, characterized in that, Applied to electronic devices, a single-wire communication device includes a master unit and multiple slave units connected in sequence, wherein the electronic device is a slave unit among the multiple slave units, and the single-wire communication method includes: In response to an input signal sent by a first target device, the input signal is parsed to obtain first configuration information, wherein the first target device is a master or a slave device; Based on the first configuration information of the input signal, target parameters are configured to obtain target configuration information, wherein the target parameters are the number of clock cycles of the input signal within the target data period; In response to the first target data in the target configuration information that matches the second target device, an output signal is obtained according to the target parameters and the first target data, wherein the second target device is a slave device of the next level of the reference device, the reference device is a slave device that responds to the input signal, and the output signal is a signal that can be recognized by the second target device; Based on the target configuration information, the communication frequency at which the reference device forwards the output signal to the second target device is adjusted to obtain the target frequency; The output signal is sent to the second target device at the target frequency so that the second target device performs a communication operation.
2. The single-line communication method according to claim 1, characterized in that, The input signal consists of a first level and a second level with different level types. The target configuration information obtained by configuring the target parameters based on the first configuration information of the input signal includes: Based on the first configuration information, the clock count of the first level and the clock count of the second level are configured to obtain the configured clock count of the first level and the configured clock count of the second level. Target configuration information that matches the first configuration information is determined based on the clock count of the first level after configuration and the clock count of the second level after configuration.
3. The single-line communication method according to claim 2, characterized in that, The target configuration information includes a register data frame, and the first target data in the target configuration information that matches the second target device includes: Obtain second target data matching the reference device from the register data frame, and store the second target data in a preset register, wherein the second target data is a portion of the data in the register data frame; The unmatched data in the register data frame excluding the second target data is taken as the first target data.
4. The single-line communication method according to claim 3, characterized in that, The target configuration information also includes a read / write mode configuration header, a register address configuration header, and a data length configuration header. Obtaining the second target data matching the reference device from the register data frame and storing the second target data into a preset register includes: In response to the read / write mode configuration header, it is determined that the reference device has entered write mode; In response to the register address configuration header, determine the target register address; In response to the data length configuration header, determine the number of words in the second target data; Based on the number of words in the second target data, and in response to the reference device entering write mode, the second target data is stored in the target register address.
5. The single-line communication method according to claim 2, characterized in that, The step of obtaining the output signal based on the target parameters and the first target data includes: The pulse width of the first level and the pulse width of the second level are determined based on the clock count of the configured first level and the clock count of the configured second level. The output signal is obtained based on the output level sequence of the pulse width of the first level and the pulse width of the second level, and the first target data.
6. The single-wire communication method according to any one of claims 1 to 5, characterized in that, Before parsing the input signal in response to the input signal sent by the first target device to obtain the first configuration information, the method further includes: acquiring the clock count of the first level and the clock count of the second level in the input signal; Determine the ratio of the clock count of the first level to the clock count of the second level, and identify the input signal based on the ratio.
7. The single-wire communication method according to claim 6, characterized in that, Determining the ratio of the clock counts of the first level to the clock counts of the second level, and identifying the input signal based on the ratio, includes: In response to the ratio relationship being such that the number of clock cycles at the first level is greater than the number of clock cycles at the second level, the input signal is identified as a first communication signal; In response to the ratio relationship being that the number of clock cycles at the first level is less than the number of clock cycles at the second level, the input signal is identified as a second communication signal.
8. The single-line communication method according to claim 1, characterized in that, The first configuration information based on the input signal is used to configure the target parameters, and the target configuration information is obtained by: Each time an input signal is received, the target parameters are configured once based on the first configuration information of the input signal to obtain the target configuration information.
9. An electronic device, characterized in that, The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, the processor causing the electronic device to implement the single-wire communication method as described in any one of claims 1-8 when executing the one or more computer programs.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the single-wire communication method as described in any one of claims 1-8.