An intelligent teaching and training service system

Abstract

This invention relates to the field of automated training technology and discloses an intelligent teaching and training service system, including a host computer terminal, an industrial control terminal, a hardware-in-the-loop fieldbus gateway, and physical actuators. The host computer terminal generates a mapping dictionary and sends it to the hardware-in-the-loop fieldbus gateway. The gateway extracts uplink messages, calculates the system energy integral value, corrects the basic safety constraint matrix, and generates a dynamic constraint matrix. The gateway intercepts downlink messages, predicts the physical state vector, and overwrites the message when it exceeds the safety range, sending it to the physical actuator. It also sends an anomaly tracing feedback message in conjunction with the mapping dictionary. This invention can intercept abnormal control commands at the underlying hardware level to prevent physical equipment from being damaged by collisions, dynamically shrink the safety boundary based on the real-time energy state of the equipment, and accurately trace underlying control anomalies to training code statements, effectively improving the efficiency of debugging training code and ensuring the safety of the training system.

Description

Technical Field

[0001] This invention relates to the field of automated training technology, specifically to an intelligent teaching and training service system. Background Technology

[0002] In current industrial automation teaching and training processes, control code is typically written on a host computer and driven by an industrial control terminal and fieldbus to operate the underlying physical actuators. This training mode helps operators intuitively verify the control logic.

[0003] In actual teaching and training environments, trainees often lack engineering experience, leading to logical errors or out-of-bounds instructions in their control code. Existing protection mechanisms mostly rely on software limit switches within the controller or mechanical limit switches at the device's end, resulting in a certain physical lag in their actual response. When downlink control messages with abnormal parameters are sent, the system often cannot proactively intercept them within the microsecond-level high-speed bus communication cycle, causing collisions or damage to physical actuators.

[0004] Meanwhile, the safety protection boundaries of conventional training systems are usually set as fixed static parameters. In actual operation, physical equipment will accumulate internal heat and mechanical fatigue after experiencing continuous high-frequency acceleration and deceleration or heavy-load operation. If the system cannot sense the real-time energy status of the equipment and dynamically adjust the safe operating threshold, and continues to use the broad initial static boundary, it can easily induce overload of electrical components or damage to mechanical structures.

[0005] Furthermore, when the training system triggers a hardware alarm or shutdown due to an erroneous command, the exception information captured by the fieldbus is only the low-level process data object index and hexadecimal byte stream. There is no direct semantic connection between this low-level communication data and the high-level training code written in the host computer. Without a reverse mapping mechanism, trainees find it difficult to directly locate the specific line of code causing the fault from the low-level bus messages, resulting in time-consuming and laborious code debugging and troubleshooting processes, thus reducing the efficiency of teaching and training. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides an intelligent teaching and training service system that solves the problems in existing teaching and training systems, such as logical errors in training code that can easily lead to damage to physical actuators, static safety protection boundaries that cannot adapt to the real-time operating energy status of equipment, and the difficulty in accurately tracing abnormalities in the underlying bus control to specific training code statements.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] An intelligent teaching and training service system includes a host computer terminal, an industrial control terminal, a hardware-in-the-loop fieldbus gateway, and a physical actuator;

[0009] The host computer terminal is used to configure and issue control codes and perform anomaly diagnosis; the industrial control terminal is used to execute the control codes and generate downlink control messages; the hardware-in-the-loop fieldbus gateway is used to intercept messages and perform security interception; and the physical actuator is used to receive control commands and perform actions.

[0010] The host computer terminal is connected to the industrial control terminal, and the hardware-in-the-loop fieldbus gateway is connected in series on the fieldbus physical link between the industrial control terminal and the physical actuator. The hardware-in-the-loop fieldbus gateway establishes a direct communication channel with the host computer terminal.

[0011] The host computer terminal is used to generate a mapping dictionary and send it to the hardware-in-the-loop fieldbus gateway;

[0012] The hardware-in-the-loop fieldbus gateway is used to initialize the basic safety constraint matrix, extract the data payload of the uplink feedback message sent by the physical actuator, and generate a dynamic constraint matrix based on the data payload of the uplink feedback message and the basic safety constraint matrix.

[0013] The downlink control message sent by the industrial control terminal is intercepted, and the physical state vector is deduced and predicted based on the downlink control message. When the predicted physical state vector exceeds the safety range of the dynamic constraint matrix, the downlink control message is overwritten and sent to the physical actuator, and an anomaly tracing feedback message is sent to the host computer terminal according to the mapping dictionary.

[0014] Furthermore, the host computer terminal is specifically used for:

[0015] The training code is parsed to generate a control instruction dependency graph topology.

[0016] The mapping dictionary is generated by binding the leaf nodes in the control command dependency graph topology with the physical addresses specified by the fieldbus communication protocol.

[0017] The mapping dictionary is sent to the memory of the hardware-in-the-loop fieldbus gateway via the direct communication channel to complete the hardening and loading process.

[0018] Furthermore, the hardware-in-the-loop fieldbus gateway is specifically used for:

[0019] When overwriting a downlink control message, extract the physical anomaly context data and the process data object index number and byte offset from the downlink control message before overwriting.

[0020] The corresponding leaf node is located by mapping the dictionary and the control instruction dependency graph is traversed in reverse to extract the set of potential error nodes;

[0021] The set of potential error nodes and the physical anomaly context data are encapsulated into an anomaly tracing feedback message and sent to the host computer terminal.

[0022] Specifically, when the downlink control message is overwritten, the target control variable values, the predicted physical state vector, and the corresponding dynamic constraint extreme values ​​in the downlink control message are extracted as physical anomaly context data.

[0023] Extract the process data object index number and byte offset from the downlink control message before overwriting;

[0024] Locate the corresponding leaf node in the mapping dictionary, perform a reverse graph traversal along the topology of the control instruction dependency graph, and extract the training code line numbers bound to the relevant nodes to form a set of potential error nodes;

[0025] The set of potential error nodes and the physical anomaly context data are encapsulated into an anomaly tracing feedback message and sent to the host computer terminal.

[0026] Furthermore, the topology of the control command dependency graph is a directed acyclic graph;

[0027] The root node and intermediate nodes of the directed acyclic graph represent conditional branch judgment statements and intermediate state variables.

[0028] The directed edges of the directed acyclic graph represent the temporal order of the control logic execution and the data flow direction of variable assignment;

[0029] The leaf nodes of the directed acyclic graph represent the underlying driving variables output to the physical actuator.

[0030] Furthermore, the hardware-in-the-loop fieldbus gateway includes a field-programmable gate array processor, a microprocessor, and a dual-port random access memory;

[0031] The network protocol layer message parsing terminal of the field-programmable gate array processor is connected to the dual-port random access memory.

[0032] The matrix operation terminal of the microprocessor is connected to the dual-port random access memory;

[0033] The field-programmable gate array processor and the microprocessor respectively interact with message data and operation instructions through the dual-port random access memory.

[0034] Furthermore, the field-programmable gate array processor is used to intercept downlink control messages and extract the values ​​of target control variables;

[0035] The microprocessor is used to call the mapping dictionary to map the target control variable values ​​into memory, and substitute the current actual physical state vector of the physical actuator and the target control variable values ​​into the discrete-time state-space model for forward recursive calculation to generate the predicted physical state vector for the next communication cycle.

[0036] Furthermore, the microprocessor is specifically used for:

[0037] Read the data payload of the uplink feedback message;

[0038] Extract the current DC bus voltage, real-time current value, and real-time angular velocity of the physical actuator;

[0039] The instantaneous total power of the system in the current cycle is calculated based on the DC bus voltage, real-time current value, and real-time angular velocity. The system energy integral value is obtained by discretizing and accumulating the instantaneous total power of the system using a preset time sliding window.

[0040] Furthermore, the microprocessor is also used for:

[0041] The dynamic shrinkage factor is calculated based on the system energy integral value and the nonlinear decay model.

[0042] The position, velocity, and acceleration thresholds of the basic safety constraint matrix are corrected based on the dynamic contraction factor to generate a dynamic constraint matrix containing dynamic thresholds.

[0043] Specifically, the minimum physical travel coordinate threshold and the maximum physical travel coordinate threshold are extracted from the basic safety constraint matrix, the center coordinates of the activity space are calculated, and half of the difference between the maximum physical travel coordinate threshold and the minimum physical travel coordinate threshold is calculated as the maximum allowable displacement deviation.

[0044] The dynamic contraction factor is multiplied by the maximum allowable displacement deviation and then superimposed onto the coordinates of the center of the active space to generate a dynamic position extremum that contracts toward the center.

[0045] The dynamic contraction factor is multiplied by the maximum positive allowable operating speed threshold to generate the dynamic maximum allowable operating speed threshold;

[0046] The dynamic contraction factor is multiplied by the maximum permissible operating acceleration threshold to generate the dynamic maximum permissible operating acceleration threshold;

[0047] By combining the dynamic position extreme value with the dynamic maximum allowable operating speed threshold and the dynamic maximum allowable operating acceleration threshold, a dynamic constraint matrix is ​​generated that includes the minimum dynamic physical travel coordinate threshold, the maximum dynamic physical travel coordinate threshold, the dynamic maximum allowable operating speed threshold, and the dynamic maximum allowable operating acceleration threshold.

[0048] Furthermore, the field-programmable gate array processor is specifically used for:

[0049] Before the downlink control message is removed from the hardware delay buffer, the media access control layer data payload in the buffer is overwritten at the hardware level.

[0050] The data bytes corresponding to the target control variable values ​​that are outside the safe range are forcibly overwritten with safe hold frame data containing a fast stop instruction and a target speed setting of zero;

[0051] After updating the cyclic redundancy check code of the security hold frame data, it is sent to the physical actuator.

[0052] Furthermore, the host computer terminal is also used for:

[0053] Receive and parse the anomaly tracing feedback message to obtain physical anomaly context data and a set of potential error nodes;

[0054] Based on the online running status of the training code recorded inside the host computer terminal, the unique code transfer path that causes out-of-bounds calculation is selected from the set of potential error nodes;

[0055] Mark fault codes and output diagnostic prompts in the visual editing interface of the training code.

[0056] The intelligent teaching and training service system provided by this invention has the following beneficial effects:

[0057] This invention intercepts downlink control messages via a hardware-in-the-loop fieldbus gateway and uses a discrete-time state-space model for forward recursive calculations to predict the physical state vector for the next cycle. When the predicted physical state vector exceeds the safe range of the dynamic constraint matrix, the system directly forces an overwrite of the media access control layer data load at the hardware level before the message is removed from the hardware delay buffer, setting the target speed to zero and injecting a fast shutdown command. This mechanism achieves low-level interception before erroneous control commands reach the physical actuators, preventing physical device collisions or damage caused by code logic errors during practical training.

[0058] This invention calculates the instantaneous total power by real-time reading of the DC bus voltage, current, and angular velocity of the physical actuator, and obtains the system energy integral value by combining it with a time sliding window. Then, a nonlinear decay model is used to generate a dynamic contraction factor to correct the basic safety constraint matrix. This method changes the traditional static threshold setting method, enabling the system's position extrema and velocity / acceleration thresholds to dynamically contract according to the real-time energy accumulation state of the equipment. It automatically tightens the safety boundary when the equipment is under continuous high load operation, reducing the risk of mechanical fatigue and electrical thermal overload.

[0059] This invention generates a directed acyclic graph topology by parsing training code and binds leaf nodes to physical addresses to create a mapping dictionary. When a gateway triggers a downlink packet overwrite operation, the system uses the process data object index number and byte offset of the original packet to perform a reverse graph traversal along the topology to locate potential error nodes. It then combines this with the online running status to select a unique code transfer path. This tracing method establishes a path from underlying communication packet anomalies to higher-level application code statements, allowing direct marking of the specific line of code that triggered the out-of-bounds action on the host computer interface, thus improving the efficiency of debugging and error finding in training code. Attached Figure Description

[0060] Figure 1 This is an architecture diagram of an intelligent teaching and training service system according to an embodiment of the present invention;

[0061] Figure 2 This is a flowchart of the intelligent teaching and training service method according to an embodiment of the present invention;

[0062] Figure 3 This is a flowchart illustrating the derivation of a dynamic constraint matrix for a hardware-in-the-loop fieldbus gateway according to an embodiment of the present invention.

[0063] Figure 4 This is a flowchart illustrating downlink look-ahead prediction and truncation in a hardware-in-the-loop fieldbus gateway according to an embodiment of the present invention.

[0064] Figure 5 This is a flowchart illustrating how a hardware-in-the-loop fieldbus gateway performs anomaly tracing and feedback according to an embodiment of the present invention.

[0065] Figure 6 This is a comparison diagram of motion trajectory and boundary interception under abnormal continuous acceleration conditions according to an embodiment of the present invention. Detailed Implementation

[0066] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] See Figure 1 This invention provides an intelligent teaching and training service system, including a host computer terminal, an industrial control terminal, a hardware-in-the-loop fieldbus gateway, and a physical actuator.

[0068] The host computer terminal connects to the industrial control terminal via a standard Ethernet network. A fieldbus communication link is established between the industrial control terminal and the physical actuators. A hardware-in-the-loop fieldbus gateway is connected in series on the physical fieldbus link between the industrial control terminal and the physical actuators. The hardware-in-the-loop fieldbus gateway is configured with an independent out-of-band communication network interface and establishes a direct communication channel with the host computer terminal through the out-of-band communication network.

[0069] The hardware-in-the-loop fieldbus gateway integrates a heterogeneous processor architecture, including a field-programmable gate array (FPGA) processor for parsing network protocol layer messages and a microprocessor for performing matrix operations. The gateway also features a dual-port random access memory (RAM) for high-speed interaction between message data and computational instructions.

[0070] like Figure 2 As shown in the figure, this embodiment of the invention provides an intelligent teaching and training service method, including the following steps:

[0071] S10: The host computer terminal receives the training code, parses it to generate a dependency graph, and sends out a mapping dictionary. The hardware-in-the-loop fieldbus gateway initializes and loads the basic safety constraint matrix.

[0072] Specifically, the host computer terminal receives the training code input, the compiler front end parses the training code to generate a control instruction dependency graph topology, binds the leaf nodes in the control instruction dependency graph topology to the physical addresses specified by the fieldbus communication protocol to generate a mapping dictionary, and sends the mapping dictionary to the memory of the hardware-in-the-loop fieldbus gateway through the out-of-band communication network to complete the hardening loading. At the same time, the hardware-in-the-loop fieldbus gateway initializes and loads the basic safety constraint matrix in memory.

[0073] S20: The industrial control terminal executes the training code logic and sends downlink control messages, while the physical actuator generates actions and sends uplink feedback messages to the uplink.

[0074] Specifically, the industrial control terminal periodically executes the internally compiled training code logic and continuously sends downlink control messages to the fieldbus. The physical actuator generates actions according to the received instructions and sends uplink feedback messages to the uplink during the bus communication cycle.

[0075] S30, the hardware-in-the-loop fieldbus gateway extracts the underlying electrical and motion parameters and calculates the instantaneous power and system energy integral value.

[0076] Specifically, the hardware-in-the-loop fieldbus gateway reads the data load of the uplink feedback message, extracts the current underlying electrical parameters and motion state parameters of the physical actuator, calculates the instantaneous power of the current cycle based on the underlying electrical parameters, and integrates the instantaneous power with a preset time sliding window to obtain the system's energy integral value.

[0077] S40, the hardware-in-the-loop fieldbus gateway inputs the system energy integral value into the basic safety constraint matrix for parameter correction, and outputs a dynamic constraint matrix with boundary contraction characteristics.

[0078] S50, the hardware-in-the-loop fieldbus gateway intercepts downlink control messages, extracts the target control variable values, performs kinematic deduction, and generates a predicted physical state vector.

[0079] Specifically, the hardware-in-the-loop fieldbus gateway intercepts downlink control messages sent by the industrial control terminal within the same communication cycle, parses and extracts the target control variable values ​​from the message load, calls the pre-stored mapping dictionary to map the target control variable values ​​into the system memory, and performs kinematic deduction by combining the current physical actuator state parameters with the extracted target control variable values ​​to generate the predicted physical state vector for the next communication cycle.

[0080] S60, when the predicted physical state vector is within a safe range, maintains the data structure of the downlink control message unchanged and transparently forwards it to the physical actuator.

[0081] Specifically, the hardware-in-the-loop fieldbus gateway compares the predicted physical state vector with the dynamic constraint matrix in terms of spatial range. When the predicted physical state vector is within the safe range defined by the dynamic constraint matrix, the data structure of the downlink control message remains unchanged and is transparently forwarded to the physical actuator.

[0082] S70: When the predicted physical state vector exceeds the safe range, the hardware-in-the-loop fieldbus gateway directly overwrites the message, replacing it with a safety hold frame and sends it.

[0083] Specifically, when the predicted physical state vector exceeds the safety range defined by the dynamic constraint matrix, the hardware-in-the-loop fieldbus gateway directly overwrites the data load of the downlink control message within the remaining time margin of the current communication cycle, replacing it with a safety hold frame that allows the physical actuator to hover and sending it to the physical actuator.

[0084] S80 records the address of the abnormal target control variable, traces the set of potential error nodes, packages a diagnostic message and sends it to the host computer terminal, and marks the code location.

[0085] Specifically, the hardware-in-the-loop fieldbus gateway records the bus address of the target control variable that caused the out-of-bounds exception. By querying the mapping dictionary, it traces back to the set of potential error nodes associated in the code structure. The set of potential error nodes is packaged into a diagnostic message and sent to the host computer terminal through the out-of-band communication network. The host computer terminal parses the diagnostic message and marks the corresponding training code location in the programming interface.

[0086] like Figure 1 As shown in the figure, an intelligent teaching and training service system provided by this invention includes, at the hardware level, a host computer terminal, an industrial control terminal, a hardware-in-the-loop fieldbus gateway, and a physical actuator. The host computer terminal is used to configure and issue control codes and perform anomaly diagnosis; the industrial control terminal is used to execute the control codes and generate downlink control messages; the hardware-in-the-loop fieldbus gateway is used to intercept messages and perform security interception; and the physical actuator is used to receive control commands and perform actions.

[0087] To clarify the implementation approach of the system architecture of this invention, the specific hardware configuration of each component module is described in detail below. The host computer terminal is specifically a personal computer, workstation, or industrial server running an integrated programming development environment (IDE). The industrial control terminal is specifically a programmable logic controller (PLC), a programmable automation controller (PLA), or an industrial personal computer based on a fieldbus. The physical actuators specifically include servo drivers, servo motors, pneumatic solenoid valves, cylinder assemblies, and associated position sensors.

[0088] The host computer terminal establishes a communication connection with the industrial control terminal via a standard Ethernet physical cable. This communication connection uses either a transmission control protocol or a user datagram protocol for non-real-time downloading of the training logic program and monitoring of the terminal's operating status. A fieldbus physical cable is configured between the industrial control terminal and the physical actuators. This fieldbus specifically uses an industrial real-time Ethernet bus that supports microsecond-level communication cycles, such as EtherCAT or PROFINET.

[0089] A hardware-in-the-loop (HIL) fieldbus gateway is connected in series on the physical link to the fieldbus between the industrial control terminal and the physical actuator. The HIL fieldbus gateway is configured with at least two real-time fieldbus communication interfaces, defined as an input port and an output port. The input port connects to the industrial control terminal, and the output port connects to the communication interface of the physical actuator, thereby disconnecting the original direct connection at the physical layer and enabling physical interception and forwarding of fieldbus data link layer data frames. Its basic working principle is that the HIL fieldbus gateway exists as a transparent bridge node in the fieldbus communication topology. Without changing the original master-slave network connection structure and node physical addresses, it introduces downlink data frames from the industrial control terminal and uplink data frames from the physical actuator into its internal processing circuitry for data link layer monitoring and processing before sending them out from the corresponding ports, thus maintaining the physical continuity of the communication link.

[0090] The hardware-in-the-loop fieldbus gateway device also has an independent out-of-band communication network interface. The hardware-in-the-loop fieldbus gateway establishes a direct physical cable connection with the host computer terminal through this out-of-band communication network interface, forming an out-of-band communication channel independent of the underlying fieldbus real-time control cycle. This out-of-band communication channel is used to transmit static mapping dictionaries and anomaly diagnostic messages, avoiding bandwidth consumption on the underlying control bus.

[0091] The internal hardware circuit design of the hardware-in-the-loop fieldbus gateway features a heterogeneous processor architecture on its internal circuit board. This architecture includes a field-programmable gate array (FPGA) processor and a microprocessor. The FPGA processor integrates media access control layer protocol parsing logic at the hardware level, with its pins directly connected to the physical layer transceiver chip. This allows for real-time decoding and load stripping of incoming and outgoing data frames within a preset bus communication cycle. The microprocessor integrates a floating-point arithmetic unit or a digital signal processing core to perform floating-point energy integration and multidimensional state matrix multiplication (where floating-point energy integration refers to the summation of sampled electrical signal values ​​with decimal precision over time; multidimensional state matrix multiplication refers to linear algebraic multiplication of the determinant containing multidimensional state variables such as position, velocity, and acceleration).

[0092] The internal circuitry of the hardware-in-the-loop fieldbus gateway also includes a dual-port random access memory (DRAM). The memory controller pins of both the field-programmable gate array (FPGA) processor and the microprocessor are connected to the address and data buses of the DRAM via hardware traces. The DRAM provides two independent read / write control ports for concurrent access by both processors, enabling the bus message payload data extracted by the FPGA processor to be mapped to a memory address within one clock cycle for the microprocessor to read, thus achieving cross-processor data sharing.

[0093] In terms of specific data processing division of labor, the field-programmable gate array (FPGA) processor is responsible for the low-level high-speed data flow scheduling and protocol layer data stripping, organizing it into standard data blocks and writing it into the dual-port random access memory (DRAM). The microprocessor, as the main control and arithmetic unit, reads data blocks from the DRAM on demand for upper-level algorithm processing, and then writes the processing results back to the memory for the FPGA processor to reassemble and send to the bus. For the hardware timing control and bus arbitration logic of the DRAM, those skilled in the art can use conventional integrated circuit inter-chip communication design specifications for configuration. Its hardware circuit design and timing calibration are well-known technologies in the field and will not be elaborated upon here.

[0094] To establish data communication channels between physical entities within the system, the initial communication configuration method for the system hardware architecture includes the following steps:

[0095] S101: The host computer terminal sends a connection establishment request to the industrial control terminal through the standard Ethernet interface, and after the handshake is successful, it sends out the compiled low-level executable file.

[0096] S102, the hardware-in-the-loop fieldbus gateway initializes its internal out-of-band communication network interface protocol stack, initiates a socket connection request to the specified network port of the host terminal, and establishes a data dictionary embedding and diagnostic data feedback channel.

[0097] S103, the industrial control terminal sends a network initialization broadcast frame to the input port of the hardware-in-the-loop fieldbus gateway through its fieldbus communication master station interface;

[0098] S104, the field-programmable gate array processor of the hardware-in-the-loop fieldbus gateway performs physical layer pass-through of broadcast frames to the output port. The internal processing time of this pass-through process is controlled within the nanosecond to microsecond range to meet the parameter requirements of industrial real-time Ethernet for communication jitter.

[0099] S105, the communication slave interface of the physical actuator receives broadcast frames and replies with response frames to the industrial control terminal, completing the alignment and calibration of the underlying device enumeration and real-time periodic synchronization clock.

[0100] Before officially entering the underlying real-time control cycle, the intelligent teaching and training service system provided in this embodiment of the invention needs to complete configuration work through the host computer terminal. This configuration work is to solve the data isolation problem between the high-level control logic code and the underlying physical bus communication protocol, and to establish a precise mapping channel between the source code logic execution node and the underlying message physical address.

[0101] The host computer terminal serves as the configuration master station, internally running an integrated development environment and compiler components for the training code. The host computer terminal is not only responsible for the routine compilation and distribution of the training code, but also for the task of parsing the code logic in a simplified manner and generating a readable configuration file for the underlying gateway.

[0102] In practice, the configuration process of the host computer terminal includes the following steps:

[0103] S201, the host computer terminal receives the training code input by the user in the integrated development environment. The training code uses a standard logic programming language in the field of industrial control. The compiler front-end inside the host computer terminal performs lexical and syntactic analysis on the received training code, transforming the text-formatted code sequence into an abstract syntax tree. For the specific implementation process of lexical analysis and syntax tree construction in compiler principles, those skilled in the art can design it using existing compiler generation tools combined with industrial control language standards. The underlying abstract syntax tree generation algorithm is a well-known technology in this field and will not be elaborated here.

[0104] S202, the host computer terminal traverses the generated abstract syntax tree, extracts variable data dependencies and control transfer logic paths during code execution, and constructs a control instruction dependency graph topology in memory. This control instruction dependency graph topology is represented as a directed acyclic graph (DAG) in terms of data structure. Since industrial control logic is characterized by top-down sequential execution, conditional branches, or finite state transitions, it can be fully expressed by an acyclic graph structure. The control instruction dependency graph topology consists of a sequence of nodes and a set of directed edge sequences. The root and intermediate nodes within the topology represent conditional branch judgment statements and intermediate state variables in the training code; the directed edges connecting the nodes represent the temporal order of control logic execution and the data flow of variable assignment; the leaf nodes at the edges represent the underlying driving variables that are ultimately output to the physical actuators. Here, the underlying driving variables refer to the specific values ​​that directly affect the physical device registers and determine the device terminal's actions, such as the target position register value or target speed register value for controlling motor rotation.

[0105] S203, the host computer terminal parses the pre-installed device description file of the fieldbus system. The device description file records all readable and writable register parameter information of the physical actuators in the bus network. The host computer terminal extracts the addresses of the underlying physical variables related to the training control from the device description file. In practice, these underlying physical variable addresses are represented by the dictionary index number of the process data object defined by the real-time Ethernet protocol and its specific byte offset in the bus cyclic data frame payload.

[0106] S204: The host computer terminal extracts all leaf nodes in the control instruction dependency graph topology, binds each leaf node representing the upper-layer output action with the extracted underlying physical variable address, and generates a mapping dictionary. This mapping dictionary is structurally represented as a key-value hash table, where the key is the variable identifier in the host computer training code, and the value is a combination of the index number and byte offset of the underlying device data dictionary.

[0107] In this embodiment, the mapping dictionary is a set of key-value pairs used to establish the correspondence between the upper computer training code logic and the underlying fieldbus communication address. The key is the leaf node of the control instruction dependency graph topology in the upper computer training code (i.e., the underlying drive variable output to the physical actuator), and the value is the physical address specified by the fieldbus communication protocol. Each leaf node corresponds to a unique fieldbus physical address, and each fieldbus physical address is bound to only one leaf node, with no duplicate mapping relationships. After the mapping dictionary is generated, it is sent by the upper computer terminal to the memory of the hardware-in-the-loop fieldbus gateway for permanent loading and is not arbitrarily modified during operation. It can be called by the microprocessor of the hardware-in-the-loop fieldbus gateway to realize the bidirectional mapping between the underlying fieldbus message address and the upper computer training code node, which is used for anomaly tracing and message parsing. The mapping dictionary takes a hash table as an example, and is described as follows: the key is "motor target speed" (corresponding to the leaf node of the control instruction dependency graph), and the value is "process data object index number 0x60FF + byte offset 0-1" (corresponding to the fieldbus physical address); the key is "cylinder extension and retraction instruction" (corresponding to the leaf node), and the value is "process data object index number 0x6000 + byte offset 2-3", so as to achieve a precise correspondence between each underlying drive variable and the fieldbus physical address.

[0108] S205, the host computer terminal reads the pre-set basic safety constraint matrix. The basic safety constraint matrix is ​​a set of multi-dimensional parameters, including the limit stroke coordinates of each motion axis of the physical actuator in a static environment, the maximum permissible operating speed, and the bounding box coordinate parameters of the mechanical interference space between the actuators. Specifically, the basic safety constraint matrix... The mathematical expression for this is defined as a set of column vectors containing the extreme values ​​of multiple state variables, or a boundary constant matrix. Taking a single-axis motion system as an example, its basic safety constraint matrix can be simplified as follows:

[0109] ;

[0110] in, and These represent the minimum and maximum physical travel coordinate thresholds allowed for the physical actuator, respectively. This represents the maximum permissible forward operating speed threshold for the physical actuator; This represents the maximum permissible operating acceleration threshold of the physical actuator. The specific values ​​of each threshold parameter within the aforementioned basic safety constraint matrix are determined by the manufacturer's mechanical parameter nameplate for the physical actuator, or by the implementer manually dragging the actuator to the physical interference boundary in a static environment, measuring the values ​​on-site, and then inputting them into the host computer terminal for persistent storage.

[0111] S206, the host computer terminal integrates and packages the completed control instruction dependency graph topology, mapping dictionary, and basic safety constraint matrix into a system initialization configuration file. The host computer terminal uses an out-of-band communication network channel to transmit the system initialization configuration file to the hardware-in-the-loop fieldbus gateway.

[0112] In step S207, the microprocessor of the hardware-in-the-loop fieldbus gateway receives the system initialization configuration file and writes the topology data and mapping dictionary data contained within it into a designated memory area of ​​the dual-port random access memory in a fixed address block format. This step enables the hardware-in-the-loop fieldbus gateway to determine the attributes of the upper-layer logical control node corresponding to the underlying message data through table lookup addressing, even without source code parsing capabilities, thus completing the parameter loading and memory configuration synchronization before system operation.

[0113] After configuration, the intelligent teaching and training service system provided in this embodiment of the invention enters the real-time operation phase. The industrial control terminal and the physical actuators engage in periodic low-level interactions via a fieldbus. This interaction mechanism constitutes the basic data link for the system's real-time control and status feedback, and is also a physical prerequisite for the subsequent gateway to execute interception and protection actions.

[0114] The industrial control system operates based on a periodic scanning mechanism. The industrial control terminal and the physical actuator exchange data frames according to a microsecond-level communication cycle under the synchronization mechanism of a real-time clock.

[0115] In practice, the underlying interaction process between the industrial control terminal and the physical actuator includes the following steps:

[0116] The S301 industrial control terminal is equipped with a real-time operating system. Following a preset fieldbus communication cycle, the industrial control terminal cyclically scans and executes the internally compiled training code logic. Within each communication cycle, the industrial control terminal generates a target action instruction based on the code logic calculation results. In practice, this target action instruction includes target control variable values, which specifically represent control words, target position coordinates, target speed, or target torque.

[0117] The industrial control terminal encapsulates the generated target action command into a downlink control message according to the frame format of the fieldbus communication protocol, and sends it to the fieldbus physical link through the communication master station interface. The data payload of the downlink control message is organized according to the cyclic synchronous communication mode. The target control variable value is mapped to the received process data object, and arranged in the payload segment of the data link layer frame with a fixed byte length and offset according to the pre-configured device data dictionary.

[0118] S302, the communication slave interface of the physical actuator receives downlink control messages from the fieldbus in real time. The microcontroller inside the physical actuator unpacks the media access control layer data load of the downlink control message and extracts the target action command. According to the target action command, the physical actuator drives the internal power amplifier circuit or solenoid valve to control the servo motor or cylinder assembly to produce the corresponding mechanical motion. For the three-closed-loop control principle of current loop, speed loop and position loop based on space vector pulse width modulation inside the servo driver, those skilled in the art can implement it using standard AC servo control algorithms. The closed-loop control algorithm is well known in the art and will not be described in detail here.

[0119] In the synchronous operation of the driven mechanical components, the S303 physical actuator continuously collects the underlying electrical and mechanical parameters of the device during operation using its built-in sensing hardware. Specifically, the physical actuator acquires the current actual mechanical position and real-time angular velocity of the servo motor rotor through a configured photoelectric encoder. It also acquires the effective value of the actual phase current output from the inverter bridge arm through a built-in Hall current sensor array and obtains the real-time voltage value of the internal DC bus through a voltage divider sampling circuit. These acquired parameters collectively constitute the underlying physical data characterizing the current operating state of the physical actuator.

[0120] In S304, the physical actuator writes the acquired low-level physical data and status words representing equipment fault and readiness states into its internal transmit buffer register. Corresponding to the downlink control message, the physical actuator organizes the low-level physical data in the transmit buffer register into a transmit process data object and fills it into the data payload area of ​​the uplink feedback message according to the same fixed byte offset mapping rule. Before the end of the current fieldbus communication cycle, the physical actuator sends this uplink feedback message to the uplink via the communication slave interface. This uplink feedback message returns along the bus topology and is received by the industrial control terminal, thus completing a complete control loop from status sampling and logic operation to actuator command issuance. This control loop continues uninterrupted during system operation.

[0121] During operation, the intelligent teaching and training service system provided in this embodiment of the invention requires the hardware-in-the-loop fieldbus gateway to acquire the real-time operating status of the physical actuators. The gateway obtains underlying physical parameters by bypassing and parsing data frames in the underlying communication link, and extracts energy parameters characterizing the operating status of the physical devices without adding physical sensors. These energy parameters are used to quantitatively evaluate the current motion state of the system, providing a numerical benchmark for subsequent dynamic adjustment of safety boundaries.

[0122] In some embodiments, the process of parsing uplink energy parameters by the hardware-in-the-loop fieldbus gateway includes the following steps:

[0123] In the S401, the field-programmable gate array (FPGA) processor inside the hardware-in-the-loop fieldbus gateway bypasses and listens to the uplink feedback messages flowing through the uplink during each bus communication cycle using the media access control layer circuitry. The FPGA processor calls a pre-loaded mapping dictionary in the dual-port random access memory (DRAM) and, based on the recorded device process data object index number and byte offset, directly extracts the corresponding binary data segment from the data payload of the uplink feedback message. The FPGA processor performs format conversion on the extracted binary data segment, extracts the current DC bus voltage, real-time current value, and real-time angular velocity of the physical actuator, and writes these underlying electrical and motion parameters into the shared memory area of ​​the DRAM.

[0124] In the S402, the microprocessor inside the hardware-in-the-loop fieldbus gateway reads low-level physical parameters from the shared memory area within the same bus communication cycle. When performing a quantitative assessment of the system's energy state, the critical state of the equipment is not only related to the current operating speed but also closely related to the electrical and kinetic energy stored within the system. Based on the extracted DC bus voltage and real-time current values, the microprocessor calculates the instantaneous electrical power of the physical actuator at the current moment. Simultaneously, the microprocessor reads the historical angular velocity from the previous communication cycle, calculates the difference between it and the current real-time angular velocity, and divides it by the communication cycle duration to obtain the current real-time angular acceleration. The microprocessor multiplies the real-time angular acceleration by the mechanical rotational inertia parameters configured during system initialization to derive the current mechanical resistance torque of the physical actuator. This torque is then multiplied by the real-time angular velocity to calculate the system's instantaneous mechanical power.

[0125] For mathematical models in electrical machinery that calculate electrical input power based on voltage and current and derive mechanical output power based on rotational speed and inertia, those skilled in the art can use the standard power equations in general motor control theory to write programs. The underlying physical conversion principles are well-known technologies in this field and will not be elaborated here. The microprocessor performs a weighted summation of the instantaneous electrical power and the instantaneous mechanical power according to the energy conversion efficiency factor specified by the equipment to obtain the total instantaneous power of the physical actuator in the current communication cycle.

[0126] The S403 microprocessor records the instantaneous total power of the system over multiple consecutive bus communication cycles and performs discretized cumulative integration calculation on the instantaneous total power using a preset time sliding window to obtain the system energy integral value characterizing the current high-energy state of the device. This integration calculation mechanism can smooth the communication sampling noise of a single bus communication cycle and accurately reflect the kinetic energy accumulation trend of the physical actuator over a recent time period. In digital communication systems, continuous integration needs to be converted into discrete summation operations based on bus communication cycles. The mathematical expression for its discretized integral is defined as:

[0127] ;

[0128] In the formula, Indicates the current number System energy integral value per bus communication cycle; This is the discrete time sequence number of the current bus communication cycle; The historical bus communication cycle sequence number variable within the time sliding window; Indicates the first in history Total instantaneous power of the system in one bus communication cycle; This indicates the fixed communication cycle duration of the fieldbus, and its unit is seconds; This indicates the total number of bus communication cycles contained within the time sliding window.

[0129] Regarding the total number of bus communication cycles in the above calculation formula Its specific value is determined by the longest braking response time of the physical actuator and the communication cycle length of the fieldbus, specifically calculated by dividing the longest braking response time by the communication cycle length. In engineering implementation configuration, this value is set as a fixed integer constant containing tens to hundreds of communication cycles. During the configuration phase, this parameter is written into the configuration file by the host computer terminal and sent to the hardware-in-the-loop fieldbus gateway for loading the fixed parameter.

[0130] The intelligent teaching and training service system provided in this invention, after acquiring the energy integral value representing the high-energy state of the system, performs dynamic constraint matrix derivation by the hardware-in-the-loop fieldbus gateway. In actual industrial control scenarios, static safety boundaries cannot effectively cope with the mechanical inertia generated when equipment operates at high speeds. When the physical actuator is in a high kinetic energy or high electrical load state, if only fixed physical boundaries are used for protection and interception, the equipment will still experience mechanical collisions or interference due to inertial sliding after the command is cut off. Therefore, this system introduces a dynamic boundary contraction mechanism based on energy state, so that the safe operating space of the equipment shrinks inward as the total energy of the system increases, reserving sufficient braking buffer distance for the physical actuator in advance.

[0131] like Figure 3 As shown, in specific implementation, the process of the hardware-in-the-loop fieldbus gateway deriving the dynamic constraint matrix includes the following steps:

[0132] S501, the microprocessor of the hardware-in-the-loop fieldbus gateway reads the current... The system energy integral value for the current bus communication cycle. The microprocessor will then... The system energy integral value of each bus communication cycle is input into a preset nonlinear decay model to calculate a dynamic shrinkage factor used to quantify the boundary reduction ratio. This dynamic shrinkage factor exhibits a nonlinear decay characteristic as the system energy increases. In specific engineering implementations, the nonlinear decay model is calculated using the mathematical expression of a negative exponential decay function, defined as:

[0133] In the formula, Indicates the current number Dynamic contraction factor per bus communication cycle; Indicates the current number System energy integral value per bus communication cycle; It is a natural constant; This represents the preset dynamic contraction sensitivity coefficient, and its value is a constant greater than 0.

[0134] Regarding the dynamic shrinkage sensitivity coefficient in the formula Its specific value is determined by the rated mechanical braking torque of the physical actuator and the maximum allowable braking slip distance. In specific configurations, the weaker the mechanical braking capability or the smaller the frictional damping of the equipment, the larger the calibrated value of this coefficient should be to ensure a more sensitive boundary contraction response under high-energy conditions. When the physical actuator is stationary or operating at low load and slow speed, the system energy integral value approaches 0, and the calculated dynamic contraction factor approaches 1, maintaining the maximum physical activity space defined by the basic safety constraint matrix. When the physical actuator is operating at high speed and high acceleration, the current... The system energy integral value of the current bus communication cycle has increased significantly. The dynamic shrinkage factor of each bus communication cycle exhibits a numerical decay of less than 1.

[0135] S502, the microprocessor reads the basic security constraint matrix stored in the dual-port random access memory during the system initialization phase. The microprocessor then calculates the current... The dynamic shrinkage factor of each bus communication cycle is used as a scalar multiplier to synchronously correct the boundary extremum parameters contained within the basic safety constraint matrix. To avoid the drift of the zero point of the device's physical motion coordinate system caused by direct absolute coordinate multiplication, the microprocessor adopts a relative shrinkage algorithm based on the coordinates of the center of the physical actuator's activity space.

[0136] In terms of the specific matrix element update principle, the microprocessor extracts the minimum and maximum physical travel coordinate thresholds from the basic safety constraint matrix, calculates their average as the center coordinates of the activity space, and calculates half of the difference between the two as the maximum permissible displacement deviation. The microprocessor multiplies the dynamic contraction factor by this displacement deviation and then superimposes it onto the center coordinates, thereby generating the dynamic position extremum that contracts towards the center (the specific calculation process corresponds to the following). and (Update formula). Simultaneously, the microprocessor will update the current formula. The dynamic contraction factor for each bus communication cycle is directly multiplied by the maximum allowable positive operating speed threshold and the maximum allowable operating acceleration threshold. The specific dynamic constraint parameter update formula is defined as follows:

[0137] ;

[0138] ;

[0139] ;

[0140] ;

[0141] In the formula, Indicates the current number Minimum dynamic physical travel coordinate threshold for each bus communication cycle; Indicates the current number Maximum dynamic physical travel coordinate threshold per bus communication cycle; This indicates the updated dynamic maximum allowed running speed threshold; This indicates the updated dynamic maximum allowable running acceleration threshold; This indicates the minimum physical travel coordinate threshold allowed for the physical actuator; This indicates the maximum physical travel coordinate threshold allowed for the physical actuator; This represents the maximum permissible forward operating speed threshold for the physical actuator; This indicates the maximum permissible operating acceleration threshold for the physical actuator; Indicates the current number The dynamic shrinkage factor for each bus communication cycle.

[0142] S503, the microprocessor, through the aforementioned scaling calculation, outputs a dynamic constraint matrix with boundary shrinkage characteristics. This dynamic constraint matrix... The mathematical expression is constructed as follows:

[0143] ;

[0144] In the formula, This represents a dynamic constraint matrix with boundary shrinkage characteristics.

[0145] The microprocessor writes the updated dynamic constraint matrix back to a designated memory block in the dual-port random access memory, overwriting the historical matrix data from the previous cycle within the current bus communication cycle. This mechanism ensures that subsequent modules, when making interception decisions, can always invoke dynamically shrinking safety boundaries that match the actual level of danger of the physical actuator. For the low-level operations of the microprocessor performing floating-point multiplication and memory data block overwriting updates in memory, those skilled in the art can use standard digital signal processing library functions for compilation and implementation. The underlying addressing and memory rewriting mechanisms are well-known technologies in the field and will not be elaborated upon here.

[0146] In the intelligent teaching and training service system provided in this embodiment of the invention, the hardware-in-the-loop fieldbus gateway is used to execute low-level security defense actions during operation. In conventional industrial control training scenarios, the control logic issued by the host computer terminal may contain software errors such as logical infinite loops or out-of-bounds addressing. To prevent these erroneous instructions from causing real mechanical collisions in the physical actuators, the system adopts a downlink look-ahead prediction and truncation mechanism to complete hardware physical isolation before the instruction actually reaches the physical actuator.

[0147] From a control mechanism perspective, look-ahead prediction refers to the system's ability to calculate the expected physical response at the next moment using a discrete-time state-space model, based on the known current physical state and the target instruction to be issued within the current communication cycle. At the hardware communication level, since fieldbus data frames are transmitted bit-by-bit serially, to complete the entire closed loop from data acquisition, prediction calculation to data overwriting within the same microsecond-level communication cycle, the field-programmable gate array processor inside the hardware-in-the-loop fieldbus gateway utilizes a first-in-first-out queue to construct a hardware delay buffer. This hardware delay buffer physically stores the effective payload of the flowing data frames for several microseconds, thus providing a physical time window for the microprocessor's matrix forward recursion algorithm.

[0148] like Figure 4 As shown, in specific implementation, the process of the hardware-in-the-loop fieldbus gateway performing downlink look-ahead prediction and truncation includes the following steps:

[0149] The S601, a field-programmable gate array (FPGA) processor in a hardware-in-the-loop fieldbus gateway, receives downlink control messages from industrial control terminals in real time and imports the data payload of the downlink control messages into a hardware delay buffer. The FPGA processor uses its internal hardware decoding circuitry to synchronously parse the medium access control layer data of the message, directly extracting the target control variable value for the current cycle. This target control variable value is specifically represented as a target position setpoint or a target speed setpoint. The microprocessor reads the extracted target control variable value and calls a mapping dictionary pre-loaded in dual-port random access memory (DRAM), mapping and associating it with the corresponding control node in memory through a lookup table comparison.

[0150] The S602 microprocessor, combining the current actual operating state of the physical actuator, deduces the predicted physical state vector for the next communication cycle using a discrete-time state-space model. The microprocessor reads the current position coordinates and real-time operating speed from the shared memory area. It then substitutes the current state data and the extracted target control variable values ​​into the discrete-time state-space model for forward recursive calculation. The formula for calculating the predicted physical state vector using the discrete-time state-space model is defined as follows:

[0151] ;

[0152] In the formula, This represents the predicted physical state vector for the next communication cycle, whose internal elements include the predicted position coordinates and the predicted velocity value. Indicates the physical actuator in the current... The actual physical state vector of each bus communication cycle; This represents the target control variable numerical vector extracted from the downlink control message; The discrete state transition matrix of the system representing the physical actuator is determined by the mechanical inertia and damping characteristics of the device itself; This represents the discrete input control matrix of the system. In practical implementation, the matrix... and This can be derived from the discretized system dynamics equations (such as the motor torque balance equations), reflecting the degree to which the current speed and position are affected by the previous state and the current control input. Regarding the matrices in the above formulas... and The specific numerical parameters inside are obtained during the system initialization and configuration phase by performing standard step response tests on physical entities, or by directly mapping and converting based on the mechanical parameters of the equipment at the factory. These parameters are then stored as static parameters in the gateway memory by the host computer terminal for the microprocessor to access.

[0153] S603, the microprocessor will calculate the predicted physical state vector for the next communication cycle. Update the generated dynamic constraint matrix with the one from the previous processing step Multi-dimensional boundary comparison is performed. Specifically, the microprocessor extracts the predicted position coordinates and predicted velocity values ​​from the predicted physical state vector, and then determines whether the predicted position coordinates are between the minimum and maximum physical travel coordinate thresholds defined by the dynamic constraint matrix, and whether the absolute value of the predicted velocity value is less than the dynamic maximum allowable operating speed threshold.

[0154] S604: When any element within the predicted physical state vector exceeds the safety threshold defined by the dynamic constraint matrix, the microprocessor determines that the downlink instruction will cause a physical out-of-bounds error or a high-energy collision. The microprocessor immediately triggers a hardware interrupt signal to the field-programmable gate array processor.

[0155] The S605, in response to an interrupt signal, directly overwrites the Media Access Control (MAC) layer data payload within the buffer at the hardware level before the downlink control message leaves the hardware delay buffer. The S605 replaces the data bytes corresponding to out-of-bounds target control variable values, forcibly overwriting them with secure hold-up frame data.

[0156] In practice, the safety hold frame data is configured with the control word modified to a fast stop command, and the target speed setpoint is forcibly overwritten to 0. The field-programmable gate array processor then updates the cyclic redundancy check (CRC) code of the safety hold frame data and sends it from the output port to the physical actuator. For the recalculation and appending of the CRC code in industrial Ethernet data frames, those skilled in the art can use standard verification algorithm hardware circuits for configuration; the verification recalculation mechanism is well-known in the field and will not be elaborated here. This underlying tampering and overwriting logic ensures that the physical actuator receives a safety hold command forcibly modified by the gateway, thus achieving physical state interception protection to maintain network communication continuity without severing the fieldbus physical connection or causing communication timeouts at the upper-layer network master station.

[0157] After completing the underlying hardware security interception, the intelligent teaching and training service system provided in this embodiment of the invention needs to address the issues of state asynchrony between the upper and lower control computers and the difficulty in locating errors. The hardware-in-the-loop fieldbus gateway, through an anomaly tracing and feedback module, reverse-maps the underlying physical security events into logical error sources in the upper computer training code.

[0158] In typical industrial control systems, anomalies in low-level bus devices often manifest only as communication errors or device shutdowns, making it difficult for upper-level programmers to directly identify which line of control code caused the physical out-of-bounds error. The anomaly tracing mechanism in this invention utilizes the topology and mapping relationships established during the configuration phase to perform initial reverse tracing from physical state to code logic within the gateway, and then hands it over to the upper-level computer for final location.

[0159] like Figure 5 As shown, in some embodiments, the process of a hardware-in-the-loop fieldbus gateway performing anomaly tracing and feedback includes the following steps:

[0160] In S701, when the microprocessor of the hardware-in-the-loop fieldbus gateway determines that the predicted physical state vector exceeds the safety threshold defined by the dynamic constraint matrix and triggers a truncation operation, the microprocessor synchronously generates an exception event record in memory. The microprocessor extracts the truncated target control variable values, the predicted physical state parameters that triggered the out-of-bounds violation, and the corresponding dynamic constraint extreme values ​​within the current communication cycle, and writes them as physical exception context data into a buffer queue.

[0161] In S702, the microprocessor reads the underlying data frame information that triggered the exception and extracts the process data object index number and corresponding byte offset of the target control variable contained in the data frame. The microprocessor calls the mapping dictionary stored in the dual-port random access memory during the system initialization phase. The microprocessor performs a reverse lookup operation, comparing the address of the underlying physical variable with the mapping dictionary to locate the corresponding leaf node, thereby obtaining the corresponding upper-level output control variable identifier in the training code.

[0162] In S703, the microprocessor reads the control instruction dependency graph topology, which is also stored in memory. Starting from the leaf node obtained through localization, the microprocessor performs a reverse graph traversal operation along the directed edges of the control instruction dependency graph topology. The microprocessor sequentially visits the intermediate nodes and the root node that have a data flow dependency relationship with the leaf node, obtaining the conditional branches and assignment statements in the code logic that affect the output variable. The microprocessor extracts the line numbers of the training code bound within these nodes, forming a set of potential error nodes. This reverse graph traversal operation is used to find potential defect sources associated with the code structure. For the reverse depth-first search and node attribute extraction algorithm for directed acyclic graphs, those skilled in the art can use standard data structure graph theory algorithms for program design; the graph traversal and node addressing mechanisms are well-known technologies in the field and will not be elaborated further here.

[0163] In the S704 microprocessor, the extracted set of potential error nodes, including the training code line numbers and physical anomaly context data, is reassembled and encapsulated into an anomaly tracing feedback message according to a preset communication protocol format. To avoid occupying or affecting the microsecond-level real-time control cycle of the fieldbus, the microprocessor asynchronously sends the anomaly tracing feedback message to the host computer terminal through an out-of-band communication network channel independent of the fieldbus.

[0164] After receiving the anomaly tracing feedback message, the host computer terminal of the S705 parses the data through its internal integrated development environment. The host computer terminal imports the parsed physical out-of-bounds state and potential error node set into the debugging module. Combining this with its internally recorded online running status of the training code (e.g., program pointer position or intermediate variable cache), the host computer terminal filters out the unique code transfer path that actually caused the out-of-bounds calculation from the potential error node set (i.e., in a code structure with multiple conditional branch statements, the specific logical execution flow that actually executes and ultimately issues the out-of-bounds error instruction). The host computer terminal highlights the specific line of code that caused the fault in the visual editing interface of the training code and outputs diagnostic prompts indicating which dynamic constraint extreme values ​​were exceeded. This step allows trainees to observe the specific manifestations of logical defects at the physical control level without touching the underlying physical hardware, thereby completing the correction and iteration of the control logic.

[0165] The following describes a specific application example:

[0166] In this embodiment, the physical actuator is a ball screw linear module with a stroke calibration of 500mm, driven by an AC servo motor. The industrial control terminal adopts a programmable logic controller based on the EtherCAT fieldbus, with a fixed communication cycle time for the fieldbus. Set to 0.001s (i.e. 1ms).

[0167] Trainees wrote point-to-point motion control logic on a host computer terminal. It was discovered that this logic had a software defect: the deceleration trigger condition was not configured, causing the control commands to continuously output the maximum acceleration setpoint.

[0168] The host computer terminal compiles and generates a control instruction dependency graph, binds the target location variable to the 0x607A index (representing the target location) of the underlying device data dictionary (i.e., the register address table that comes with the physical device at the factory), generates a mapping dictionary (i.e., a relationship table generated by this system to bind the host computer code variables to the addresses of the underlying device data dictionary one by one), and sends the mapping dictionary to the hardware-in-the-loop fieldbus gateway.

[0169] At the same time, the gateway loads the basic security constraint matrix and sets the minimum physical travel coordinate threshold according to the device nameplate. =0mm, maximum physical travel coordinate threshold =500mm. The total number of bus communication cycles included within the system initialization setting time sliding window. =100 (i.e., includes 100 communication cycles), and a preset dynamic shrinkage sensitivity coefficient is set according to the module's mechanical damping characteristics. =1.5.

[0170] After the system is running, the industrial control terminal periodically issues additional target position commands, and the linear module continuously accelerates towards the 500mm physical limit position.

[0171] As the sliding table's operating speed increases, the real-time current and angular velocity extracted by the gateway also increase. The microprocessor uses the discretized integral formula... Calculate the current number System energy integral value per bus communication cycle As a result, it increases.

[0172] Subsequently, the microprocessor will... System energy integral value per bus communication cycle Substitute into the nonlinear decay model In the middle, calculate the current number of... Dynamic contraction factor per bus communication cycle (Its value gradually decreases to less than 1). The microprocessor uses the update formula. The dynamic constraint matrix is ​​updated in real time. The current [number]th [unit] within the gateway... Maximum dynamic physical travel coordinate threshold per bus communication cycle Starting from an initial 500mm, the diameter shrinks downwards in real time.

[0173] When the runtime reaches approximately 0.85 seconds, the microprocessor reads the downlink control message from the hardware delay buffer and extracts the target control variable value vector from the downlink control message. The microprocessor invokes the discrete-time state-space model. Combined with physical actuators in the current first The actual physical state vector of each bus communication cycle (Position coordinates approximately 415mm) Forward recursion is performed. Calculations show that if the current message is allowed to pass, the predicted position coordinates within the predicted physical state vector for the next communication cycle will exceed the current position coordinates, which have now shrunk to around 415mm. Maximum dynamic physical travel coordinate threshold per bus communication cycle .

[0174] Once the truncation condition is met, the microprocessor triggers a hardware interrupt. Before the downlink control message is removed from the buffer, the field-programmable gate array processor overwrites the control word in its data payload with a fast stop instruction, overwrites the target speed with 0, recalculates the cyclic redundancy check code, and then sends it to the servo driver.

[0175] The servo drive executes a stop command. Because the aforementioned dynamic boundary contraction formula pre-reserves braking buffer space, the slide decelerates using approximately 33mm of distance, eventually stopping smoothly at approximately 448mm, without exceeding the 500mm physical limit. The gateway records the underlying variable address at the time of the truncation, traces it back using a mapping dictionary, and sends the abnormal node to the host computer terminal. The programming interface then locates and displays the defective code lacking deceleration logic.

[0176] To verify the effectiveness of the dynamic constraint formula and hardware look-ahead cutoff mechanism of this invention, a control experimental platform was built for testing and verification. Traditional control systems employ purely software-based limit switches, relying on controller software logic to determine whether the current position exceeds a fixed 500mm threshold and issue a stop command. The system of this invention uses a hardware-in-the-loop fieldbus gateway connected in series, with the aforementioned limit switch executed by the gateway's internal microprocessor. Energy integral and A dynamic boundary update algorithm is implemented, and the underlying data frame overwrite truncation function is enabled. Two sets of linear modules are run towards the 500mm physical interference limit under the same defect acceleration code, and their position-time response curves are recorded.

[0177] Reference Figure 6 In the figure, the horizontal axis represents the running time, the vertical axis represents the physical travel coordinate, the horizontal solid line represents the fixed 500mm static physical limit threshold, and the shaded area above the solid line represents the mechanical rigid collision area.

[0178] Figure 6 The dashed line with a hollow circle represents the operating trajectory of a traditional control system. At high speeds, limited by the controller's scan cycle and bus transmission delay, there is a lag when the software system senses a position exceeding the limit and issues a command. For example... Figure 6 As shown, the trajectory penetrates the 500mm static physical limit directly upwards at approximately 0.9 seconds (the position marked by x in the figure), entering the mechanical rigid collision zone (i.e., Figure 6 The shaded area in the image is forcibly stopped in the over-limit area by the rigid resistance of the mechanical stop, causing equipment damage.

[0179] Figure 6 The dashed line represents the dynamic security boundary of the gateway in this invention, derived based on a nonlinear decay formula. Due to the accumulation of kinetic energy as operating time increases, this dynamic security boundary exhibits inward contraction characteristics according to an exponential decay model. Figure 6 The solid line with an asterisk represents the operational trajectory collected in real-world data according to this invention. When this trajectory intersects with the shrinking dynamic safety boundary (dotted line) at approximately 0.85 seconds, the gateway determines that the predicted physical state exceeds the threshold and performs message overwriting at the physical layer. After the intersection, the trajectory slope rapidly decreases, entering a deceleration and coasting phase, and finally comes to a smooth stop at approximately 448mm. ​ The vertical double-headed arrows indicate the safe braking buffer space between the final stopping position and the 500mm static physical limit.

[0180] The above comparison shows that the technical solution of the present invention overcomes the response delay between the communication layer and the software application layer, and adaptively generates a dynamic safety boundary by using the system energy integral value and nonlinear decay model, which reserves physical braking margin for high-speed moving equipment. It can intercept out-of-bounds movement in hardware without cutting off the physical bus, thus ensuring the safety of the training equipment.

[0181] The above description is merely some specific implementations of this application and is not intended to limit the scope of protection of this application. Any variations or substitutions easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An intelligent teaching and training service system, characterized in that, This includes host computer terminals, industrial control terminals, hardware-in-the-loop fieldbus gateways, and physical actuators; The host computer terminal is used to generate a mapping dictionary and send it to the hardware-in-the-loop fieldbus gateway; The hardware-in-the-loop fieldbus gateway is used to initialize the basic safety constraint matrix, extract the data payload of the uplink feedback message sent by the physical actuator, and generate a dynamic constraint matrix based on the data payload of the uplink feedback message and the basic safety constraint matrix. The downlink control message sent by the industrial control terminal is intercepted, and the physical state vector is deduced and predicted based on the downlink control message. When the predicted physical state vector exceeds the safety range of the dynamic constraint matrix, the downlink control message is overwritten and sent to the physical actuator, and an anomaly tracing feedback message is sent to the host computer terminal according to the mapping dictionary.

2. The intelligent teaching and training service system according to claim 1, characterized in that, The host computer terminal is specifically used for: The training code is parsed to generate a control instruction dependency graph topology. The mapping dictionary is generated by binding the leaf nodes in the control command dependency graph topology with the physical addresses specified by the fieldbus communication protocol. The mapping dictionary is sent to the memory of the hardware-in-the-loop fieldbus gateway via the direct communication channel to complete the hardening and loading process.

3. The intelligent teaching and training service system according to claim 2, characterized in that, The hardware-in-the-loop fieldbus gateway is specifically used for: When overwriting a downlink control message, extract the physical anomaly context data and the process data object index number and byte offset from the downlink control message before overwriting. The corresponding leaf node is located by mapping the dictionary and the control instruction dependency graph is traversed in reverse to extract the set of potential error nodes; The set of potential error nodes and the physical anomaly context data are encapsulated into an anomaly tracing feedback message and sent to the host computer terminal.

4. The intelligent teaching and training service system according to claim 2 or 3, characterized in that, The topology of the control command dependency graph is a directed acyclic graph; The root node and intermediate nodes of the directed acyclic graph represent conditional branch judgment statements and intermediate state variables. The directed edges of the directed acyclic graph represent the temporal order of the control logic execution and the data flow direction of variable assignment; The leaf nodes of the directed acyclic graph represent the underlying driving variables output to the physical actuator.

5. The intelligent teaching and training service system according to claim 1, characterized in that, The hardware-in-the-loop fieldbus gateway includes a field-programmable gate array processor, a microprocessor, and a dual-port random access memory. The network protocol layer message parsing terminal of the field-programmable gate array processor is connected to the dual-port random access memory. The matrix operation terminal of the microprocessor is connected to the dual-port random access memory; The field-programmable gate array processor and the microprocessor respectively interact with message data and operation instructions through the dual-port random access memory.

6. The intelligent teaching and training service system according to claim 5, characterized in that, The field-programmable gate array processor is used to intercept downlink control messages and extract the values ​​of target control variables; The microprocessor is used to call the mapping dictionary to map the target control variable values ​​into memory, and substitute the current actual physical state vector of the physical actuator and the target control variable values ​​into the discrete-time state-space model for forward recursive calculation to generate the predicted physical state vector for the next communication cycle.

7. The intelligent teaching and training service system according to claim 6, characterized in that, The microprocessor is specifically used for: Read the data payload of the uplink feedback message; Extract the current DC bus voltage, real-time current value, and real-time angular velocity of the physical actuator; The instantaneous total power of the system in the current cycle is calculated based on the DC bus voltage, real-time current value, and real-time angular velocity. The system energy integral value is obtained by discretizing and accumulating the instantaneous total power of the system using a preset time sliding window.

8. The intelligent teaching and training service system according to claim 7, characterized in that, The microprocessor is also used for: The dynamic shrinkage factor is calculated based on the system energy integral value and the nonlinear decay model; the position, velocity and acceleration thresholds of the basic safety constraint matrix are corrected based on the dynamic shrinkage factor to generate a dynamic constraint matrix containing dynamic thresholds.

9. The intelligent teaching and training service system according to claim 6, characterized in that, The field-programmable gate array processor is specifically used for: Before the downlink control message is removed from the hardware delay buffer, the media access control layer data payload in the buffer is overwritten at the hardware level. The data bytes corresponding to the target control variable values ​​that are outside the safe range are forcibly overwritten with safe hold frame data containing a fast stop instruction and a target speed setting of zero; After updating the cyclic redundancy check code of the security hold frame data, it is sent to the physical actuator.

10. The intelligent teaching and training service system according to claim 3, characterized in that, The host computer terminal is also used for: Receive and parse the anomaly tracing feedback message to obtain physical anomaly context data and a set of potential error nodes; Based on the online running status of the training code recorded inside the host computer terminal, the unique code transfer path that causes out-of-bounds calculation is selected from the set of potential error nodes; Mark fault codes and output diagnostic prompts in the visual editing interface of the training code.

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