Vehicle-mounted projection system and method based on high-speed UART and related device

Abstract

This application provides a vehicle-mounted projection system, method, and related apparatus based on high-speed UART. The vehicle-mounted projection system includes a System-on-a-Chip (SOC) and a projection lamp. The SOC includes a hardware acceleration module, a CPU, and a Vo module. The hardware acceleration module is used to decode and transform the video to be displayed, outputting grayscale pixels. The CPU receives the grayscale pixel data output by the hardware acceleration module, completing projection frame construction, UART frame encapsulation, and RGB pixel mapping. The Vo module is used to read and convert RGB pixels into corresponding level signals for output. The projection lamp is used to receive, parse, and finally project the level signals. This application fully releases the hardware potential of the SOC through the collaborative division of labor between the hardware acceleration module and the CPU, and overcomes the traditional UART transmission bottleneck by leveraging the high-speed output capability of the Vo module. This achieves efficient and stable vehicle-mounted projection while reducing system computing power and hardware costs.

Description

Technical Field

[0001] This application relates to the field of vehicle headlight projection technology, and in particular to a vehicle-mounted projection system, method and related device based on high-speed UART. Background Technology

[0002] With the development of automotive intelligence, in-vehicle high-definition (HD) headlight projection systems need to support dynamic video projection to adapt to complex road conditions and personalized scenario requirements.

[0003] Current in-vehicle projection technology generally suffers from several common technical bottlenecks: First, the dynamic projection data processing chain is cumbersome, resulting in excessive CPU load and causing issues such as stuttering and latency in the projected image, making it difficult to meet the high requirements for display effects. Second, the hardware resources of the core processing chip in the vehicle are not fully explored and rationally utilized, with some high-performance hardware modules remaining idle or operating inefficiently, resulting in wasted hardware resources and limiting the improvement of the overall system operating efficiency. Third, there is a rate bottleneck in the projection data transmission link. Existing interface adaptation solutions either struggle to overcome transmission rate limitations or require additional hardware components, leading to increased system costs and size, and potentially introducing new transmission delays, failing to meet the core requirements of high efficiency, stability, lightweight design, and low cost in the in-vehicle scenario. Summary of the Invention

[0004] This application provides a vehicle-mounted projection system, method, and related apparatus based on high-speed UART. By coordinating the hardware acceleration module and the CPU, the potential of the SOC hardware is fully released. The high-speed output capability of the VO module breaks through the traditional UART transmission bottleneck, thereby reducing system computing power and hardware costs while achieving efficient and stable display of vehicle-mounted projection.

[0005] In a first aspect, this application provides a vehicle-mounted projection system based on high-speed UART. The system includes: a system-on-a-chip (SOC) and a projection lamp. The SOC includes a hardware acceleration module, a central processing unit (CPU), and a video output (VO) module. The hardware acceleration module is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp. The CPU is used to construct a projection frame based on the grayscale pixels, encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data, map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values. The VO module is used to read the RGB pixels and convert the RGB pixels into corresponding level signals for output. The projection lamp is used to receive the level signals, parse the UART bit data in the level signals according to the UART frame format, reconstruct the projection frame, and then project and display it.

[0006] Secondly, this application provides a vehicle-mounted projection method based on high-speed UART. The method is applied to a system-on-a-chip (SoC) of a vehicle-mounted projection system, wherein the vehicle-mounted projection system is the system described in any of the first aspects. The method includes: decoding and transforming the video to be displayed to output grayscale pixels adapted to the projection lamp; constructing a projection frame based on the grayscale pixels; encapsulating a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data; mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, and filling the remaining bits of the RGB pixel with invalid values; reading the RGB pixel through the VO module of the SoC, converting the RGB pixel into a corresponding level signal, and sending the level signal to the projection lamp. The projection lamp is used to receive the level signal and parse the UART bit data in the level signal according to the UART frame format, reconstruct the projection frame, and then project and display it.

[0007] Thirdly, this application provides a vehicle-mounted projection device based on high-speed UART. The device is applied to a system-on-a-chip (SOC) of a vehicle-mounted projection system, wherein the vehicle-mounted projection system is the system described in any of the first aspects. The device includes: a processing unit, configured to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp; construct a projection frame based on the grayscale pixels; encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data; map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values; and an output unit, configured to read the RGB pixels through the VO module of the SOC module, convert the RGB pixels into corresponding level signals, and send the level signals to the projection lamp. The projection lamp is configured to receive the level signals and parse the UART bit data in the level signals according to the UART frame format, restore the projection frame, and then project and display it.

[0008] Fourthly, this application provides a system-on-a-chip (SOC) for executing the steps and instructions described in the second aspect. The SOC includes a hardware acceleration module, a memory, a central processing unit (CPU), a video output (VO) module, and a high-speed bus. The hardware acceleration module includes a video decoding unit and an image processing unit. The video decoding unit, the image processing unit, the CPU, the memory, and the VO module are all interconnected via the high-speed bus. The video decoding unit is used to perform hardware-accelerated decoding of the video to be displayed and output YUV format video frame data. The image processing unit is used to perform image transformation operations on the video frame data and output pixel data adapted to the projector lamp. The CPU is used to coordinate and control the collaborative work of each hardware unit and execute logical scheduling for projection frame construction, UART frame encapsulation, and RGB pixel mapping. The memory is used to cache the pixel data. The VO module is used to read the pixel data from the memory and output the corresponding level signal.

[0009] As can be seen, in this embodiment, the vehicle-mounted projection system includes a system-on-a-chip (SOC) and a projection lamp. The SOC includes a hardware acceleration module, a central processing unit (CPU), and a video output (VO) module. The hardware acceleration module is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp. The CPU is used to construct projection frames based on the grayscale pixels, encapsulating a single grayscale pixel in the projection frame into a UART frame containing multiple UART bits of data; mapping each UART bit in the UART frame to a preset bit of an RGB pixel, and filling the remaining bits of the RGB pixel with invalid values. The VO module is used to read RGB pixels and convert them into corresponding level signals for output. The projection lamp is used to receive the level signals, parse the UART bit data in the level signals according to the UART frame format, reconstruct the projection frame, and then project it for display. This application fully releases the hardware potential of the SOC through the collaborative division of labor between the hardware acceleration module and the CPU, and breaks through the traditional UART transmission bottleneck by leveraging the high-speed output capability of the VO module. While reducing system computing power and hardware costs, it achieves efficient and stable display of vehicle-mounted projection. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A structural block diagram of a prior art vehicle projection system provided in this application embodiment; Figure 2 A schematic diagram of a vehicle-mounted projection system based on high-speed UART provided for an embodiment of this application; Figure 3 This is a schematic diagram of a projection frame provided in an embodiment of this application; Figure 4 A schematic diagram of a UART frame provided in an embodiment of this application; Figure 5 This is a schematic diagram of another vehicle-mounted projection system provided in an embodiment of this application; Figure 6 A schematic diagram of YUV images and single-component Y, U, V images provided in the embodiments of this application; Figure 7 A flowchart illustrating a vehicle-mounted projection method based on high-speed UART provided in this application embodiment; Figure 8 A functional unit structure block diagram of a vehicle-mounted projection device based on high-speed UART provided in an embodiment of this application; Figure 9 This is a schematic diagram of a system-on-a-chip (SOC) provided in an embodiment of this application. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0013] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but in some embodiments includes steps or units not listed, or in some embodiments includes other steps or units inherent to these processes, methods, products, or apparatuses.

[0014] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0015] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone; A and B exist simultaneously; B exists alone. Among them, A and B can be singular or plural.

[0016] In this embodiment, the symbol " / " can indicate that the preceding and following objects are in an "or" relationship. Alternatively, the symbol " / " can also represent a division sign, i.e., performing a division operation. For example, A / B can mean A divided by B.

[0017] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.

[0018] In the embodiments of this application, "equal to" can be used with "greater than" and is applicable to technical solutions used when "greater than" is used; it can also be used with "less than" and is applicable to technical solutions used when "less than" is used. When "equal to" is used with "greater than", it is not used with "less than"; when "equal to" is used with "less than", it is not used with "greater than".

[0019] With the rapid development of automotive intelligent technology, in-vehicle projection systems, as key devices for improving driving safety and the driving experience, are widely used in driving scenarios such as road condition warnings, navigation guidance, and personalized scene displays. The market has placed increasingly higher demands on the real-time dynamic display, image clarity, and lightweight design of in-vehicle projection systems. However, existing in-vehicle projection technology still has many shortcomings that make it difficult to meet these application requirements, detailed below: Please see Figure 1 , Figure 1 This application provides a structural block diagram of a prior art vehicle projection system. Current mainstream vehicle projection systems generally adopt a three-level collaborative architecture of "System-on-a-Chip (SOC) + Microcontroller Unit (MCU) + Projector Lamp." The SOC, as the core processing module, integrates a central processing unit (CPU), hardware acceleration units (including a video processing unit (VPU), an image signal processor (ISP), on-chip memory, and various interface control logic. However, in existing technologies, the hardware acceleration units are often idle or operate inefficiently, with the core data processing tasks primarily handled by the CPU. The MCU is an intermediate control module independent of the SOC, responsible for protocol conversion, timing matching, and peripheral status management, serving as a necessary intermediate bridge connecting the SOC and the projector lamp. The projector lamp, as the display execution module, is equipped with conventional UART, SPI, and other communication interfaces to receive data, reproduce the projected image, and provide feedback on its operating status. The connection relationship between the components is as follows: the CPU inside the SOC establishes a data connection with the MCU through a vehicle bus (such as a CAN bus, SPI bus, or conventional UART bus). The MCU then communicates bidirectionally with the projector lamp through a dedicated communication interface, forming a serial data transmission link from the CPU to the MCU and then to the projector lamp.

[0020] Among them, the conventional UART (Universal Asynchronous Receiver Transmitter) is a general-purpose serial asynchronous communication bus. This bus has two data lines and can realize full-duplex transmission and reception. In embedded systems, it is often used for communication between the host and auxiliary devices. In the automotive lighting scenario, it is used for communication between the SOC and the MCU. The transmission rate is limited by the UART baud rate (commonly up to several Mbps).

[0021] Based on the above three-tier architecture, the projection implementation process of the existing vehicle projection system is as follows: First, the SOC receives the video data to be projected from the vehicle host; then, the CPU inside the SOC decodes the encoded video stream using software algorithms, converts it into raw video frame data, and continues to perform image transformations such as resolution scaling and grayscale conversion of the video frames through software to construct a projection frame adapted to the projector lamp; next, the CPU sends the projection frame data and related control commands to the MCU through the vehicle bus; after receiving the data, the MCU completes protocol conversion and timing matching, adapting the data format to the type supported by the projector lamp; finally, the MCU transmits the adapted data stream to the projector lamp, the projector lamp restores the projection frame and displays it, and at the same time, the operating status data is transmitted back to the CPU through the MCU to realize closed-loop control.

[0022] Practical experience has revealed several insurmountable technical flaws in existing vehicle projection systems: First, data processing efficiency is low and real-time performance is poor. Core video decoding and image transformation tasks rely on CPU software processing, failing to fully utilize the SOC's built-in hardware acceleration unit. This results in excessively high CPU computing power utilization, and the serial transmission link from CPU to MCU to projection lamp suffers from multiple forwarding delays. The combined effect of these factors easily causes stuttering and latency in the projected image, failing to meet the demands of high-definition dynamic projection. Second, the hardware structure is complex, leading to high costs and power consumption. The independent MCU increases hardware procurement costs and vehicle space requirements, and its operation and communication processes consume additional power, failing to meet the demands for lightweight and low-power vehicle devices. Third, data transmission reliability is low. Multiple intermediate forwarding links are susceptible to bus interference, leading to data loss or errors. Furthermore, the complex protocol adaptation logic is prone to timing mismatch issues, affecting projection stability. Fourth, hardware resources are severely wasted. The SOC's built-in hardware acceleration unit is not utilized effectively, resulting in idle high-performance hardware resources and low system resource allocation efficiency.

[0023] Based on the aforementioned technical deficiencies, this application proposes an innovative architecture of "SOC integrated control + direct adaptation of high-speed UART and video output VO module," which has significant advantages over existing technologies: First, it simplifies the hardware structure, reduces cost and power consumption, and eliminates the MCU as an intermediate link. Through the collaborative work of the SOC's internal hardware acceleration unit, CPU, and VO module, it achieves full-process control, reducing hardware costs, space occupation, and system power consumption, thus meeting the lightweight requirements of automotive applications. Second, it optimizes computing power allocation and improves processing efficiency. High-computing-power tasks such as video decoding and image transformation are handled by the hardware acceleration unit, while the CPU only handles low-computing-power logic scheduling, significantly reducing CPU computing power consumption and solving the projection stuttering problem at its source. Third, it shortens the transmission link and ensures display stability. Through the "UART frame encapsulation + RGB pixel mapping" design, the SOC's VO module... It can directly convert data into level signals and output them to the projector, realizing direct transmission from the SOC to the projector, significantly reducing data latency and packet loss risks, and giving high-speed UART stronger anti-interference capabilities in complex vehicle environments; and relying on the high-speed transmission characteristics of the VO module, its efficiency and stability in transmitting UART data are far superior to traditional UART transmission methods. Tests have shown that the transmission baud rate of UART data using the VO module can reach a high-speed baud rate of 40Mbps. Combined with the design of repeating the transmission of each bit, its equivalent actual transmission baud rate can reach 20Mbps, which is hundreds of times higher than the 0.1152Mbps baud rate commonly used in traditional UART; fourth, it improves resource utilization and versatility, fully explores the potential of SOC hardware, and through the RGB pixel preset bit mapping design, it can flexibly adapt to different formats of UART data and projector requirements.

[0024] The technical solution of this application will be described in detail below with reference to specific embodiments.

[0025] Please see Figure 2 , Figure 2 A schematic diagram of a vehicle-mounted projection system based on high-speed UART provided in this application embodiment is shown below. Figure 2 As shown, the vehicle-mounted projection system includes: a system-on-a-chip (SOC) and a projection lamp. The SOC includes a hardware acceleration module, a central processing unit (CPU), and a video output (VO) module. The hardware acceleration module is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp. The CPU is configured to construct a projection frame based on the grayscale pixels, encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data, map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values. The VO module is used to read the RGB pixels and convert the RGB pixels into corresponding level signals for output. The projection lamp is used to receive the level signal, parse the UART bit data in the level signal according to the UART frame format, restore the projection frame, and then project and display it.

[0026] In this embodiment, the vehicle-mounted projection system includes a System-on-Chip (SOC) and a projection lamp adapted to the UART transmission protocol. The SOC serves as the data processing and control core of the entire system, integrating a hardware acceleration module, a CPU, and a VO module. These modules achieve high-speed data interaction and collaborative scheduling through the SOC's internal high-speed bus (such as the AXI bus), creating an integrated mechanism that eliminates the need for an MCU intermediate forwarding unit. Transmission between the SOC and the projection lamp is via high-speed UART. Compared to conventional UART, high-speed UART eliminates the need for a separate UART interface, mapping UART bit data to preset bit positions of RGB pixels. Using RGB pixel signals as the transmission carrier, transmission is completed through the SOC's VO module. The transmission link is simplified to "SOC internal CPU - frame buffer - VO module - projection lamp," eliminating the need for a separate UART hardware interface and intermediate forwarding unit. The VO module's transmission rate matches the SOC's internal bus and directly interfaces with the projection lamp, resulting in significantly higher transmission efficiency and stability than traditional UART. Each component is described in detail below: The hardware acceleration module is a hardware unit specifically designed to handle computationally intensive tasks. Unlike the general-purpose computing of the CPU, it uses dedicated circuits to achieve parallel processing of specific tasks. Specifically, it is responsible for converting the video stream to be displayed transmitted by the vehicle host into grayscale pixel data adapted to the projector lamp.

[0027] In some embodiments, regarding decoding and image transformation of the video to be displayed to output grayscale pixels adapted to the projector, the hardware acceleration module is specifically used to: decode the video to be displayed to obtain an original video frame, the original video frame being in YUV format; extract a single-frame original image of the original video frame according to the video frame rate; scale the original image to an effective display size adapted to the projector; convert the scaled original image into grayscale pixels, the grayscale pixels corresponding to the grayscale display information of the projector; and regarding constructing a projection frame based on the grayscale pixels, the CPU is specifically used to: add a frame header at the beginning position of the grayscale pixels, and sequentially add a check bit and a free bit at the end position of the grayscale pixels to obtain the complete projection frame.

[0028] The video stream to be displayed is encoded using mainstream encoding formats such as H.264. The video source for in-vehicle projection systems typically comes from the vehicle's main unit (such as a navigation system or ADAS system). This video data needs to be transmitted through the vehicle's bus and temporarily stored in the SOC's onboard flash memory. On one hand, the bandwidth of the vehicle's bus is limited. Uncompressed raw video data (such as 1080P resolution, 30 frames per second video, with a raw bitrate of several Gbps) will occupy a large amount of bus resources, causing data transmission stuttering. H.264 encoding can reduce its bitrate to several Mbps, adapting to the transmission capabilities of the vehicle's bus. On the other hand, the SOC's on-chip memory capacity is limited. Compressed H.264 video data can significantly reduce storage usage, avoiding video frame drops due to insufficient memory space.

[0029] Since H.264 encoded video is compressed data and cannot be directly used for projection display, this system uses the Video Decoder Unit (VDec) in the SOC hardware acceleration module to perform decoding processing. The VDec has a built-in dedicated H.264 decoding circuit that can process the inverse operations of intra-frame prediction and inter-frame prediction in parallel, first restoring the compressed H.264 bitstream to the original video frame data.

[0030] The original video frames are in YUV format. YUV is a color encoding format that stores luminance and chrominance information separately, unlike the RGB format which stores the red (R), green (G), and blue (B) primary color components with equal weight. See [link / reference]. Figure 6 , Figure 6This diagram illustrates the YUV image and single-component Y, U, V images provided in this application embodiment. The Y component represents luminance or grayscale information, typically ranging from 0 to 255, where 0 corresponds to pure black and 255 to pure white. This component directly determines the brightness and darkness of the image. The U and V components represent chrominance information, corresponding to blue color difference (U=BY) and red color difference (V=RY), respectively, used to describe the color attributes of the image. Their values ​​typically range from -128 to 127 or 0 to 255 (slight differences depending on the standard). The core advantage of this separation design is that the human eye is far more sensitive to luminance than to chrominance. Therefore, the amount of data can be compressed by "downsampling" the chrominance component without affecting the image quality perceived by the human eye. This format is naturally compatible with mainstream video compression standards such as H.264, and can be directly output after decoding without additional format conversion. For example, in this system, only the Y component needs to be extracted to generate grayscale pixels, without processing the chrominance component. In this vehicle projection system, the hardware acceleration module generates raw YUV video frames after decoding H264 video. This reduces the transmission pressure on the vehicle bus and the SOC on-chip memory usage. It can also quickly generate grayscale pixels by directly extracting the Y component, eliminating the complex calculation of RGB to grayscale conversion. This aligns with the system's core design logic of "hardware acceleration to reduce computing power".

[0031] The original video frames are a continuous sequence of frames. The hardware acceleration module extracts the single-frame YUV image from the original video frames one by one according to the original frame rate of the video (such as 30 frames / second commonly used in car navigation videos). The purpose is to match the display refresh rate of the projector lamp, ensure the smoothness of the projected image, and avoid screen stuttering or frame skipping caused by frame extraction that is too fast or too slow.

[0032] The hardware acceleration module incorporates a built-in Video Processing Unit (VPU) to perform image transformation operations, including resolution scaling and format conversion. The final output grayscale pixel value ranges from 0 to 255 (corresponding to 256 grayscale levels for the projector, where 0 represents the darkest and 255 represents the brightest, directly determining the brightness and detail of the projected image). For the resolution scaling operation, the extracted single-frame YUV raw image resolution is typically the standard resolution of the vehicle-mounted head unit (e.g., 1080P), which does not match the effective display size of the projector (e.g., 800×600 pixels). The hardware acceleration module performs resolution scaling through the built-in VPU. The scaling process uses a bilinear interpolation algorithm, calculating the average brightness and chromaticity of adjacent pixels to generate the target pixel. This ensures that the scaled image is free of stretching and jagged edges, accurately matching the physical display area of ​​the projector, thus solving the problem of "large-resolution images not being clearly displayed on small-sized projectors." Regarding the format conversion operation, since the projector lamp in this system is a grayscale display device and does not require color information, the hardware acceleration module directly extracts the Y component representing brightness from the YUV image, discarding the U and V chromaticity components to generate grayscale pixel data. The value range of this grayscale pixel corresponds to the grayscale display capability of the projector lamp (e.g., 0~255 corresponds to 256 grayscale levels), and the value directly determines the brightness and darkness of the projected image. By directly extracting brightness information through hardware, the complex calculation of "RGB to grayscale" in traditional solutions is replaced, further reducing the CPU's computational load.

[0033] In some embodiments, the effective data for each grayscale pixel is 8 bits.

[0034] The CPU is the logical scheduling core of the entire system. It mainly undertakes lightweight data processing tasks. Its core work is to receive grayscale pixel data output by the hardware acceleration module and complete three key operations: projection frame construction, UART frame encapsulation, and RGB pixel mapping.

[0035] First, the CPU constructs a projection frame based on grayscale pixels. In some embodiments, the frame structure of the projection frame includes a frame header, data bits, a check bit, and idle bits. The frame header occupies 4 grayscale pixels and is used to transmit synchronization signals. The check bit is a CRC check bit, occupying 4 grayscale pixels, and is used to verify the integrity of the grayscale data transmission. The number of grayscale pixels corresponding to the effective display size is 320×80. The total number of pixels in the grayscale projection frame is 25608.

[0036] See Figure 3The projection frame structure is: frame header + data bits + checksum bit + idle bits. The frame header is located at the very beginning of the projection frame, serving as a synchronization marker for the start of the frame; the data bits carry grayscale pixel data; the checksum bit is located after the valid data, used to verify the integrity of the valid data; the idle bits are located at the very end of the projection frame, and their core function is to match the frame period of the projection lamp. The projection lamp display has fixed line blanking and field blanking times, and the idle bits can fill the blank data during the blanking periods, ensuring that the total length of the projection frame is completely synchronized with the display timing of the projection lamp, avoiding the frame skipping problem of "the next frame being displayed before the frame data has been completely transmitted".

[0037] For the data bits, the CPU constructs them according to the display timing of the projector lamp. Specifically, the CPU fills the data bit area with the grayscale pixel data output by the hardware acceleration module in a "top-to-bottom, left-to-right" order, following the projector lamp's preset line-by-line scanning timing. The total length of the data bits perfectly matches the effective display size of the projector lamp. For example, when the effective display size of the projector lamp is 320×80 pixels, the data bits consist of 320×80 consecutive grayscale pixels, with each grayscale pixel corresponding to a physical pixel within the projector lamp's display area. Simultaneously, the CPU strictly aligns the timing of the projector lamp's horizontal and vertical sync signals: one horizontal sync cycle occurs after each line of 320 grayscale pixels is filled; one vertical sync cycle occurs after all 80 lines of pixels are filled. This ensures that the pixel arrangement order in the data bits is precisely synchronized with the projector lamp's scanning rhythm, avoiding issues such as image misalignment, stretching, or missing pixels, and guaranteeing the integrity and consistency of the projected image.

[0038] Secondly, the CPU encapsulates each pixel in the projection frame into a UART frame. Since grayscale pixel data needs to be transmitted via the UART protocol, and the original grayscale pixel data cannot be directly adapted to the UART transmission format, the CPU needs to encapsulate each grayscale pixel.

[0039] In some embodiments, see Figure 4 A UART frame includes a start bit, data bits, a parity bit, and a stop bit. Adjacent UART frames (such as frame n and frame n+1) are separated by a free bit.

[0040] When neither party is sending data, the idle bit remains high (level 1). The start bit is the first bit of the UART frame, used to indicate the start of data transmission. It defaults to low and remains unchanged. Since the idle bit is always high, the UART frame will transition from high to low when data transmission begins, thus determining whether transmission has started. The data bits are used to store the pixel data of the projection frame, and the transmitted data needs to be 5-8 bits; in this embodiment, the data bits are 8 bits. The parity bit is optional and is used to check for errors in data transmission. It is generated by calculating the number of "1"s in the 8 data bits. If the number is odd, the parity bit is 1; if it is even, the parity bit is 0. The receiving end can determine whether an error occurred during data transmission using the same calculation method. For example, if the data bit is 01010001, the data parity bit is 0. The stop bit is 1 / 1.5 or 2 bits, defaults to high, and is used to indicate the end of a data transmission. In this embodiment, the stop bit is 2 bits.

[0041] With this encapsulation, a single grayscale pixel corresponds to 12 bits of UART frame data. A single projection frame includes 25,608 pixel data, corresponding to 25,608 UART frames, and 25,608 × 12 bits of UART bit data.

[0042] In some embodiments, before mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the CPU is further configured to: perform repeated transmission processing on each UART bit data in the UART frame, so that each UART bit data is transmitted continuously at least twice.

[0043] For transmission stability, each UART bit can be transmitted multiple times consecutively. If it is transmitted twice consecutively, then a single projection frame needs to transmit 25608×12×2 bits of UART bit data.

[0044] Finally, RGB pixel mapping is performed. The core purpose of this step is to adapt to the output format of the SOC's VO module. Because the VO module only supports RGB pixel format output and cannot directly output UART frame data, the CPU needs to map each bit of data in the UART frame to a specific bit of the RGB pixel.

[0045] In some embodiments, the RGB pixel is any one of RGB565, RGB888, RGB666, or RGB444.

[0046] In practical implementation, the least significant bit of the R channel of an RGB pixel is typically chosen as the preset bit. This is because the least significant bit of the R channel has strong signal stability and is less affected by external interference during transmission, thus better ensuring data integrity. Simultaneously, to prevent other bits from interfering with valid data, the CPU fills the remaining bits of the RGB pixel with invalid values ​​"0". Taking the RGB565 format as an example, this format contains 16 bits, with 5 bits allocated to the R channel, 6 bits to the G channel, and 5 bits to the B channel. It is a commonly used lightweight RGB pixel format in automotive scenarios, adapting to the bandwidth requirements of the SOC's on-chip memory and the transmission efficiency of the VO module. In this system, the CPU selects a specific bit as the preset bit to carry UART bit data; for example, selecting the 3rd bit in the RGB565 format as the valid bit, and filling the remaining 15 bits with invalid values ​​"0".

[0047] In this vehicle projection system, to address the differentiated adaptation needs of multiple projection lights (such as a left and right projection light), the CPU can be configured via software to flexibly assign dedicated preset bit positions in the RGB pixels that carry UART bit data for different projection lights. Taking the commonly used RGB565 format in vehicle scenarios as an example (16-bit bit arrangement: R4R3R2R1R0G5G4G3G2G1G0B4B3B2B1B0), if the system simultaneously connects to both the left and right projection lights, the CPU will assign specific preset bit positions based on the two projection lights. The hardware receiving characteristics of the projectors are configured with different preset bit positions: For the left projector, the third bit (G3 bit) of the G channel is selected as the preset bit to carry UART bit data, and the remaining 15 bits (R4-R0, G5-G4, G2-G0, B4-B0) are all filled with invalid values ​​"0"; For the right projector, the fourth bit (G4 bit) of the G channel is selected as the preset bit, and the remaining 15 bits (R4-R0, G5, G3-G0, B4-B0) are filled with invalid values ​​"0".

[0048] In some embodiments, the RGB pixels are RGB565 pixels, each RGB565 pixel occupies 2 bytes, and a single projection frame contains 25608×12×2 bits of UART data, corresponding to 25608×12×2 RGB565 pixels. Using RGB565 channel transmission, a total of 25608×12×2×2 bytes of data need to be transmitted.

[0049] In some embodiments, after mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the CPU is further configured to: perform level inversion processing on the RGB pixel and then flush it into a frame buffer of a preset specification.

[0050] After the CPU maps the projection frame to RGB pixels, it needs to flush the RGB pixels into the frame buffer for caching. The frame buffer is a dedicated storage area in the SOC memory, and after flushing is completed, it sends a "data ready" interrupt signal to the VO module.

[0051] For example, a single projection frame corresponds to 25608×12×2×2 bytes of RGB565 pixels, and the corresponding frame buffer capacity is at least 25608×12×2×2 bytes = 1229184 bytes, with a width and height of 1584×388. The total number of pixels in the frame buffer is consistent with the total number of RGB pixel data after inversion.

[0052] Before the CPU flushes the RGB pixels into the frame buffer, it needs to perform level inversion processing on the RGB pixels to resolve the inherent conflict between the stop bit level and the blanking area level of the UART frame. The specific principle is explained below.

[0053] The Video Output (VO) module is a crucial bridge connecting the SOC and the projector. Its core function is to convert the signal format, transforming the CPU-processed digital RGB pixel data into a voltage level signal that can be transmitted via hardware circuitry. In practice, the VO module reads RGB pixel data from the frame buffer according to a preset timing sequence. After reading the RGB pixel data, the VO module uses its integrated digital-to-analog converter (DAC) to convert the digital signal into an analog voltage level signal. The DAC converts discrete digital signals into continuous analog signals. In this system, it specifically converts the "0" and "1" in the digital signal into an analog voltage level signal within the range of 0~3.3V, typically with low voltage corresponding to "0" and high voltage corresponding to "1". After conversion, the VO module outputs the converted voltage level signal through the SOC's GPIO interface. The GPIO interface offers excellent compatibility and stability, ensuring that the voltage level signal remains stable during transmission and meets the projector's reception requirements.

[0054] In some embodiments, in reading the RGB pixels and outputting the corresponding level signals of the RGB pixels, the VO module is specifically used to: read the inverted RGB pixels in the frame buffer and automatically add blanking region data before output, wherein the blanking region data is fixed to a low level of 0; integrate the level signals corresponding to the inverted RGB pixels and the level signals corresponding to the blanking region data into a mixed level signal and output it.

[0055] Upon receiving the "data ready" interrupt signal from the CPU, the VO module initiates the data reading and output process. Specifically, the VO module reads the inverted RGB pixel data line by line from the frame buffer, following a reading rhythm strictly aligned with the projector's scanning timing. During the reading process, the VO module establishes a data transmission link with the frame buffer via the SOC's internal high-speed bus. The read address corresponds one-to-one with the CPU's refresh address (e.g., the first pixel in the first row corresponds to address 0x0000, and the first pixel in the second row corresponds to address 0x0320), ensuring that each inverted RGB pixel is accurately read without omissions or duplicate readings. Before outputting after reading a frame of inverted RGB pixel data, the VO module automatically generates and adds blanking area data based on the projector's display timing parameters. In this embodiment, the blanking area data includes line blanking data and field blanking data: the line blanking data corresponds to the line gaps when the projector scans line by line, with a fixed pixel length of line blanking data added after each line of pixels is scanned; the field blanking data corresponds to the frame gaps when the projector displays frame by frame, with a fixed pixel length of field blanking data added after each frame of pixels is displayed. All blanking area data is fixed at a low level of 0, and its bit format is consistent with that of the RGB pixels to ensure no format conflicts during subsequent signal integration. The VO module integrates a signal integration unit that integrates the level signals (0~3.3V analog levels generated after digital-to-analog conversion) corresponding to the inverted RGB pixels with the low level 0 signals corresponding to the blanking area data in a timing sequence. The integrated hybrid level signal timing structure is as follows: vertical blanking data signal, first row blanking data signal, first row inverted RGB pixel level signal, second row blanking data signal, second row inverted RGB pixel level signal, ..., nth row inverted RGB pixel level signal (n is the pixel width of the projector lamp), and vertical blanking data signal, forming a complete frame of hybrid level signal. Subsequently, the VO module outputs the hybrid level signal through a dedicated output interface (such as an LVDS interface).

[0056] As can be seen from the above, in the UART frame structure, the stop bit level is a fixed high level "1", which is a hard requirement of the UART communication protocol. The core function of the stop bit is to mark the end of a UART frame transmission, allowing the receiving end (projector lamp) to accurately distinguish the boundary between two adjacent UART frames. Only when a high-level stop bit is detected can the receiving end determine that the current UART frame transmission is complete and prepare to receive the next frame of data. Once the stop bit level changes, the boundary recognition of the UART frame will completely fail. In this system, the blanking area data added by the VO module is a fixed low level "0", which is based on the display timing design of the projector lamp. The blanking area corresponds to the horizontal and vertical blanking periods during the projector lamp scanning process. At this time, the display components of the projector lamp are in a "resting" state and do not need to transmit effective pixel data. Therefore, the area is filled with a low level "0" to avoid invalid signals interfering with normal display. It can be seen that the high level "1" of the stop bit and the low level "0" of the blanking area are two fixed and opposing level states. If the two are directly connected or superimposed in the signal transmission link, a natural level conflict will be formed.

[0057] When the valid pixel signal carrying the UART frame and the blanking area signal are integrated into a mixed-level signal by the VO module, if no processing is performed, the high-level "1" of the stop bit will be directly embedded into the low-level "0" sequence of the blanking area. At this time, when the projector receives the signal, it cannot determine whether this high level is a "stop bit of the UART frame" or an "interference signal of the blanking area", which will lead to UART frame parsing misalignment and data loss.

[0058] To resolve this conflict, the CPU performs a global level inversion on the mapped RGB pixels: it flips the level of all bits carrying UART frame data in the RGB pixels, specifically flipping the high level "1" of the UART frame stop bit to a low level "0", and the remaining UART frame data bits also undergo the level inversion; simultaneously, the bits in the RGB pixels filled with invalid values ​​remain at a low level. After this inversion, the level of the UART frame stop bit becomes "0", consistent with the low level "0" logic of the subsequent blanking area, fundamentally avoiding the level conflict between the two. This ensures that when the VO module integrates the valid pixel signal and the blanking area signal, there are no contradictions in timing and level logic, laying the foundation for smooth transmission of mixed-level signals.

[0059] After the first inversion, the VO module integrates the inverted RGB pixel signals with the low-level blanking area signals into a mixed-level signal. However, in this mixed-level signal, all data bit levels of the UART frame are reversed compared to the original logic. If directly transmitted to the projector, it will cause complete errors in UART data parsing. Therefore, an inverter is added between the VO module and the projector. See [link to relevant documentation]. Figure 5 , Figure 5This is a schematic diagram of another vehicle-mounted projection system provided in an embodiment of this application.

[0060] In some embodiments, the system further includes an inverter, which is used to: perform level inversion processing on the mixed level signal so that the inverted RGB pixels are restored to their original levels and the blanking area data is inverted from low level 0 to high level 1 so that the level of the blanking area data matches the high level of the stop bit of the UART frame; and output the inverted mixed level signal.

[0061] The inverter is used to perform global level inversion processing on the mixed-level signal: on the one hand, it flips the level of the UART frame data bits after inversion to restore them to the original logic level, especially restoring the low level "0" of the stop bit to the high level "1", ensuring that the projector can accurately identify the boundary of the UART frame and complete the correct parsing of the data; on the other hand, it flips the blanking area signal that was originally low level "0" to high level "1", forming an identification signal that is significantly different from the valid UART frame signal (alternating high and low levels). The projector can quickly filter out the invalid data in the blanking area by identifying this fixed high-level area and only extract the UART frame data corresponding to the valid pixels.

[0062] In summary, the two phase inversion operations are a targeted solution to the "conflict between the stop bit and blanking area level of the UART frame". The first phase inversion avoids the conflict, and the second phase inversion restores the data and strengthens the identification. The two form a logical closed loop, which not only ensures the integrity of UART data transmission, but also ensures the accuracy of the projection lamp signal interpretation, and ultimately achieves the stable operation of the vehicle projection system.

[0063] The projector lamp, as the display execution unit of the entire system, is used to receive, parse, and finally project the level signal. Its main functions include receiving the inverted mixed-level signal, filtering the blanking area data and extracting the valid level signal, deduplication and verification of UART bit data, parsing the UART frame format, and reassembling and displaying the projection frame. In some embodiments, in receiving the level signal, parsing the UART bit data in the level signal according to the UART frame format, and restoring the projection frame for projection display, the projection lamp is specifically used for: receiving the inverted mixed level signal; filtering the blanking region data in the inverted level signal and extracting the effective level signal carrying the UART bit data; parsing the effective level signal according to the UART frame format to obtain the UART frame; reassembling the UART frame according to the projection frame structure to obtain the projection frame, and converting the projection frame into a driving signal for projection display.

[0064] In practice, the projector receives the inverted, mixed-level signal from the inverter via a compatible high-speed signal receiving interface. This interface has a built-in anti-interference processing unit that filters electromagnetic noise in the vehicle environment, ensuring that the received inverted, mixed-level signal is complete and distortion-free. The inverted, mixed-level signal consists of two parts: first, the effective level signal carrying UART bit data after two inversions; and second, the blanking area data converted to a fixed level after being processed by the inverter. These two parts are integrated sequentially to form a signal structure that meets the timing requirements of the projector display.

[0065] The projector lamp has a built-in signal filtering module that pre-stores the identification characteristics and length parameters of the blanking zone data. Based on the aforementioned technical solution, the blanking zone data, after being processed by the inverter, forms a fixed level identifier. The signal filtering module scans and identifies the received inverted mixed level signal bit by bit according to the preset identifier characteristics: when a continuous signal matching the blanking zone identifier characteristics is detected, and its length matches the preset line blanking or field blanking length, it is determined to be blanking zone data and is directly discarded to avoid interfering with the parsing of valid data; when the blanking zone identifier signal ends and a level signal matching the valid data characteristics appears subsequently, it is determined to be a valid level signal carrying UART bit data, and this part of the signal is then extracted in sequence and temporarily stored in the buffer unit inside the projector lamp, while the timing information of the signal is recorded to match the subsequent display scanning rhythm.

[0066] In some embodiments, before mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the CPU is further configured to: perform repeated transmission processing on each UART bit data in the UART frame, so that each UART bit data is transmitted continuously at least twice; before parsing the valid level signal of the RGB pixel according to the UART frame format, the projection lamp is further configured to: perform deduplication verification on the repeatedly transmitted UART bit data in the extracted valid level signal, and take the bit data with at least two consistent transmission results as valid UART bit data.

[0067] In this process, after the CPU completes the construction of the projection frame and splits it into a UART frame sequence, it enters the pre-processing stage of mapping UART bit data to preset bit positions of RGB pixels. If repeated transmission processing is performed on each UART bit data in the UART frame, the projector lamp, after extracting the valid level signal, enters the pre-processing stage of UART frame format parsing, which involves performing deduplication verification on the repeated transmission UART bit data contained in the extracted valid level signal. Specifically, the deduplication verification module built into the projector lamp first identifies the repeated transmission sequence corresponding to each original UART bit data in the valid level signal according to the repeated transmission rules preset by the CPU, and clarifies the start and end boundaries of each sequence. Subsequently, it performs consistency verification on the consecutive bit data in each repeated transmission sequence, determining whether the bit data transmitted at least twice in the sequence is consistent. If the verification result is consistent, it is determined that the bit data has not been distorted by interference, and the consistent bit data is taken as valid UART bit data; if the verification result is inconsistent, it is determined that there is interference during the transmission of the bit data, and the bit data corresponding to the sequence is discarded (or a fault tolerance mechanism is triggered to call backup data) to ensure the accuracy of the subsequently parsed UART bit data. After completing the deduplication verification and obtaining valid UART bit data, the projector then executes subsequent processes such as UART frame format parsing, projection frame reconstruction, and projection display according to the established logic.

[0068] The projector lamp has a built-in UART protocol parsing module that reads valid level signals from the buffer unit and parses them according to a preset UART frame format. During parsing, the start bit of the UART frame is first identified by detecting level transition edges, thus determining the start boundary of a single UART frame. Then, the level signals of the corresponding number of bits after the start bit are read sequentially as the data bits of the UART frame. After the data bits are read, the level signals of the subsequent corresponding number of bits are extracted as check bits. The integrity of the data bits is verified using a preset check algorithm. If the check passes, the data bits are retained; if the check fails, the current UART frame is discarded to ensure data accuracy. Finally, the end boundary of a single UART frame is determined by detecting a preset stop bit level signal, completing one UART frame parsing cycle. This process is repeated to parse all valid level signals, resulting in a batch of complete UART frames.

[0069] The projector lamp has a built-in frame reassembly module that reads the UART frames output by the UART protocol parsing module and reassembles them according to a preset projection frame structure (frame header + valid grayscale pixel data + check bit + free space). First, it identifies the frame header identifier in the UART frame sequence and fills the grayscale pixel data carried by the UART frame into the valid data area of ​​the projection frame in chronological order, based on the frame header. Then, based on all the grayscale pixel data in the valid data area, it calculates and generates a check bit using a preset algorithm and adds it to the end of the valid data area. Finally, it adds a free space of a preset length to complete the reassembly of the projection frame.

[0070] The projector lamp has a built-in projection driver module that converts the reconstructed projection frame into a drive signal adapted to its own display component. The parameters of this drive signal correspond one-to-one with the grayscale pixel data and are used to control the display component's brightness, grayscale, and other display states. The drive module then outputs the drive signal to the display component, controlling the display component to work according to a preset scanning sequence, accurately projecting the image corresponding to the projection frame onto the target area to complete the projection display.

[0071] In some embodiments, when the UART bit data is not retransmitted, the base transmission baud rate of the VO module for transmitting the UART bit data is not less than 40 Mbps; when the UART bit data is retransmitted, the equivalent actual transmission baud rate of the VO module for transmitting the UART bit data is determined by the base transmission baud rate and the number of retransmissions.

[0072] In this application, the VO module achieves high-speed UART transmission by mapping UART bit data to specific bits of RGB pixels, thus enabling video output. Because the pixel clock of the VO module is much higher than the clock frequency of a traditional UART controller, it can achieve baud rates far exceeding those of traditional UARTs.

[0073] When the system does not perform retransmission of UART bit data, the VO module transmits according to the original UART bit stream, with each UART bit occupying only one pixel cycle. Because the VO module has a high pixel clock frequency, it can achieve a UART transmission baud rate of at least 40 Mbps. However, when the system performs retransmission of UART bit data (e.g., each bit is transmitted twice consecutively), although the physical transmission rate of the VO module remains at least 40 Mbps, the effective actual UART baud rate decreases because each valid UART bit is repeatedly sent. Specifically, after each bit is repeated twice, the effective data rate becomes half of its original value, i.e., at least 20 Mbps.

[0074] As can be seen, in this embodiment, a balance between transmission rate and transmission reliability is achieved by flexibly adjusting the repetition number of UART bits under different transmission modes. Higher transmission rate can be obtained when there is no repetition, which is suitable for scenarios with high real-time requirements; higher anti-interference capability can be obtained when there is repetition, which is suitable for scenarios with high reliability requirements.

[0075] In summary, this in-vehicle projection system, through the close collaboration of the SOC's internal hardware acceleration module, CPU, VO module, and external projection lamp, constructs a closed-loop process from video processing to projection display. Its core advantage lies in leveraging the integrated design of the SOC to successfully eliminate the MCU, which serves as an intermediate relay link in traditional in-vehicle projection systems, significantly shortening the data transmission link. Simultaneously, by having the hardware acceleration module handle high-performance video decoding and image processing tasks, data processing efficiency is effectively improved, and CPU computational power consumption is reduced. Furthermore, through innovative designs of UART frame encapsulation and RGB pixel mapping, combined with the CPU's level inversion of RGB pixels and the inverter's secondary inversion of mixed-level signals, level conflicts between UART frame stop bits and blanking regions are precisely avoided. This achieves accurate adaptation between high-speed UART transmission and the VO module's output format. Moreover, relying on the high-speed transmission characteristics of the VO module, its efficiency and stability in transmitting UART data are far superior to traditional UART transmission methods. Ultimately, this achieves high-definition, low-latency dynamic projection effects in in-vehicle scenarios, fully meeting the needs of various in-vehicle applications such as road condition warnings, navigation guidance, and personalized scene displays.

[0076] It should be noted that this technical solution is not limited to grayscale projection scenarios. Its core architecture and design logic can be fully extended to the field of color projection. By transmitting the RGB three-channel data of color pixels according to customized UART frames, or by adding channel differentiation identifiers to the existing RGB pixel mapping, reliable transmission and projection display of color image data can be achieved without fundamentally adjusting the core SOC integrated control, UART, and VO module adaptation architecture. Furthermore, the components mentioned in the solution are not unique. For example, the hardware acceleration module can be replaced with a dedicated image processing chip with stronger parallel processing capabilities according to actual computing power requirements; the inverter can be replaced with an integrated signal conditioning module with equivalent level conversion functions; and the projection lamp can be adapted to color / grayscale projection devices with different display principles. All such component replacements and equivalent transformations based on the core concept of this solution should be included within the scope of protection of this technology. Furthermore, the aforementioned content of this solution focuses on the core technical logic and key implementation processes, without providing detailed explanations of auxiliary technical details such as data encryption, power management, and heat dissipation design. Moreover, the application scenarios of this technical solution are not limited to vehicle projection. Its core advantages of SOC integrated control and efficient data transmission can be further extended to many fields that require high-reliability, low-latency data transmission and display control, such as smart cockpit displays, vehicle head-up displays (HUDs), and industrial control displays. The aforementioned extended applications, equivalent component replacements, and the auxiliary technical details that are not detailed all fall within the scope of this technical solution and are also covered by the rights and interests of this application.

[0077] Please see Figure 7 , Figure 7 A flowchart illustrating a vehicle-mounted projection method based on high-speed UART provided in this application embodiment is shown below. Figure 7 As shown, the method is applied to a system-on-a-chip (SoC) of an in-vehicle projection system, which is the system described in the above embodiment. The method includes the following steps S701-S705: Step S701: Decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp.

[0078] Step S702: Construct a projection frame based on the grayscale pixels.

[0079] Step S703: Encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple bits of UART data.

[0080] Step S704: Map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values.

[0081] Step S705: The RGB pixels are read through the VO module of the SOC, the RGB pixels are converted into corresponding level signals, and the level signals are sent to the projection lamp. The projection lamp is used to receive the level signals and parse the UART bit data in the level signals according to the UART frame format, restore the projection frame, and then project and display it.

[0082] As can be seen, in this embodiment, the SOC decodes and transforms the video to be displayed, outputting grayscale pixels adapted to the projector lamp; a projection frame is constructed based on the grayscale pixels; a single grayscale pixel in the projection frame is encapsulated into a UART frame containing multiple UART bits; each UART bit in the UART frame is mapped to a preset bit of an RGB pixel, and the remaining bits of the RGB pixel are filled with invalid values; the RGB pixels are read by the SOC's VO module, converted into corresponding level signals, and sent to the projector lamp. The projector lamp receives the level signals and parses the UART bit data in the level signals according to the UART frame format, reconstructs the projection frame, and then projects it for display. It is evident that this application fully unleashes the potential of the SOC hardware, leveraging the high-speed output capability of the VO module to overcome the bottleneck of traditional UART transmission, achieving efficient and stable display of in-vehicle projection while reducing system computing power and hardware costs.

[0083] In some embodiments, after mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the method further includes: performing level inversion processing on the RGB pixel and then flushing it into a frame buffer of a preset specification.

[0084] In some embodiments, reading the RGB pixels and outputting the corresponding level signals of the RGB pixels includes: reading the inverted RGB pixels in the frame buffer and automatically adding blanking region data before output, wherein the blanking region data is fixed at a low level of 0; integrating the level signals corresponding to the inverted RGB pixels and the level signals corresponding to the blanking region data into a mixed level signal and outputting it.

[0085] In some embodiments, the system further includes an inverter, which is used to: perform level inversion processing on the mixed level signal, so that the inverted RGB pixels are restored to their original levels and the blanking area data is inverted from low level 0 to high level 1; and output the inverted mixed level signal.

[0086] In some embodiments, receiving the level signal, parsing the UART bit data in the level signal according to the UART frame format, restoring the projection frame, and then projecting it for display includes: receiving the inverted mixed level signal; filtering the blanking region data in the inverted level signal and extracting the effective level signal carrying the UART bit data; parsing the effective level signal according to the UART frame format to obtain the UART frame; reassembling the UART frame according to the projection frame structure to obtain the projection frame, and converting the projection frame into a drive signal for projection display.

[0087] In some embodiments, before mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the method further includes: performing repeated transmission processing on each UART bit data in the UART frame, so that each UART bit data is transmitted continuously at least twice; before parsing the RGB pixel valid level signal according to the UART frame format, the method further includes: performing deduplication verification on the repeatedly transmitted UART bit data in the extracted valid level signal, and taking the bit data with consistent transmission results at least twice as valid UART bit data.

[0088] In some embodiments, decoding and image transformation of the video to be displayed to output grayscale pixels adapted to the projector lamp includes: decoding the video to be displayed to obtain an original video frame, the original video frame being in YUV format; extracting a single-frame original image of the original video frame according to the video frame rate; scaling the original image to an effective display size adapted to the projector lamp; converting the scaled original image into grayscale pixels, the grayscale pixels corresponding to the grayscale display information of the projector lamp; and constructing a projection frame based on the grayscale pixels includes: adding a frame header at the beginning position of the grayscale pixels and adding a check bit and a free bit sequentially at the end position of the grayscale pixels to obtain the complete projection frame.

[0089] The above primarily describes the solutions of the embodiments of this application from the perspective of the method execution process. It is understood that, in order to achieve the above functions, the server includes the corresponding hardware structure and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in the embodiments provided herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0090] This application embodiment can divide the server into functional units according to the above method example. For example, each function can be divided into different functional units, or two or more functions can be integrated into one processing module. The integrated unit can be implemented in hardware or as a software program module. It should be noted that the unit division in this application embodiment is illustrative and only represents a logical functional division, while other division methods may be used in actual implementation.

[0091] In the case of using integrated units, please refer to Figure 8 , Figure 8 This application provides a functional unit structure block diagram of a vehicle-mounted projection device based on a high-speed UART. The vehicle-mounted projection device is applied to a system-on-a-chip (SoC) of a vehicle-mounted projection system, which is the system described in the above embodiment. The vehicle-mounted projection device includes: The processing unit 801 is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp; construct a projection frame based on the grayscale pixels; encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data; map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values. The output unit 802 is used to read the RGB pixels through the VO module of the SOC module, convert the RGB pixels into corresponding level signals, and send the level signals to the projection lamp. The projection lamp is used to receive the level signals and parse the UART bit data in the level signals according to the UART frame format, restore the projection frame, and then project and display it.

[0092] As can be seen, in this embodiment, the SOC decodes and transforms the video to be displayed, outputting grayscale pixels adapted to the projector lamp; a projection frame is constructed based on the grayscale pixels; a single grayscale pixel in the projection frame is encapsulated into a UART frame containing multiple UART bits; each UART bit in the UART frame is mapped to a preset bit of an RGB pixel, and the remaining bits of the RGB pixel are filled with invalid values; the RGB pixels are read by the SOC's VO module, converted into corresponding level signals, and sent to the projector lamp. The projector lamp receives the level signals and parses the UART bit data in the level signals according to the UART frame format, reconstructs the projection frame, and then projects it for display. It is evident that this application fully unleashes the potential of the SOC hardware, leveraging the high-speed output capability of the VO module to overcome the bottleneck of traditional UART transmission, achieving efficient and stable display of in-vehicle projection while reducing system computing power and hardware costs.

[0093] Please see Figure 9 , Figure 9 This is a schematic diagram of a system-on-a-chip (SOC) provided in an embodiment of this application. The SOC is used to execute the step instructions in the above-described vehicle projection method based on high-speed UART. The SOC includes a hardware acceleration module, a memory, a central processing unit (CPU), a video output (VO) module, and a high-speed bus. The hardware acceleration module includes a video decoding unit and an image processing unit. The video decoding unit, the image processing unit, the CPU, the memory, and the VO module are all interconnected through the high-speed bus. The video decoding unit is used to perform hardware-accelerated decoding of the video to be displayed and output video frame data in YUV format. The image processing unit is used to perform image transformation operations on the video frame data and output pixel data adapted to the projection lamp. The CPU is used to coordinate and control the collaborative work of various hardware units, and to execute the logical scheduling of projection frame construction, UART frame encapsulation and RGB pixel mapping. The memory is used to cache the pixel data; The VO module is used to read the pixel data from the memory and output the corresponding level signal.

[0094] This application provides a computer-readable storage medium storing a computer program / instructions thereon, which, when executed by a processor, implement the steps of any possible embodiment of the method.

[0095] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0097] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0098] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0099] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0100] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0101] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0102] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A vehicle-mounted projection system based on high-speed UART, characterized in that, The system includes: a system-on-a-chip (SOC) and a projection lamp, wherein the SOC includes a hardware acceleration module, a central processing unit (CPU), and a video output (VO) module; The hardware acceleration module is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projection lamp. The CPU is configured to construct a projection frame based on the grayscale pixels, encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data, map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values. The VO module is used to read the RGB pixels and convert the RGB pixels into corresponding level signals for output. The projection lamp is used to receive the level signal, parse the UART bit data in the level signal according to the UART frame format, restore the projection frame, and then project and display it.

2. The system according to claim 1, characterized in that, After mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the CPU is further configured to: The RGB pixels are inverted and then flushed into a frame buffer of a preset specification.

3. The system according to claim 2, characterized in that, In reading the RGB pixels and outputting the corresponding level signals of the RGB pixels, the VO module is specifically used for: Read the inverted RGB pixels in the frame buffer and automatically add blanking region data before output. The blanking region data is fixed at a low level of 0. The level signals corresponding to the inverted RGB pixels and the level signals corresponding to the blanking area data are integrated into a mixed level signal and output.

4. The system according to claim 3, characterized in that, The system also includes an inverter, which is used for: The mixed-level signal is subjected to level inversion processing, so that the inverted RGB pixels are restored to their original levels and the blanking area data is inverted from low level 0 to high level 1, so that the level of the blanking area data matches the high level of the stop bit of the UART frame; Output an inverted mixed-level signal.

5. The system according to claim 4, characterized in that, In receiving the level signal, parsing the UART bit data in the level signal according to the UART frame format, reconstructing the projection frame, and then projecting it for display, the projection lamp is specifically used for: Receive the inverted and mixed level signal; Filter the blanking region data in the inverted level signal to extract the effective level signal carrying the UART bit data; The effective level signal is parsed according to the UART frame format to obtain the UART frame; The UART frames are reassembled according to the projection frame structure to obtain the projection frame, and the projection frame is converted into a driving signal for projection display.

6. The system according to claim 5, characterized in that, Before mapping each UART bit data in the UART frame to a preset bit of an RGB pixel, the CPU is also used to: perform repeated transmission processing on each UART bit data in the UART frame, so that each UART bit data is transmitted continuously at least twice; Before parsing the RGB pixel valid level signals according to the UART frame format, the projection lamp is also used for: The UART bit data that is repeatedly transmitted in the extracted valid level signal is deduplicated and the bit data that is consistent in at least two transmissions is taken as valid UART bit data.

7. The system according to claim 1, characterized in that, When the UART bit data is not retransmitted, the base transmission baud rate of the VO module for transmitting the UART bit data is not less than 40Mbps; when the UART bit data is retransmitted, the equivalent actual transmission baud rate of the VO module for transmitting the UART bit data is determined by the base transmission baud rate and the number of retransmissions.

8. The system according to any one of claims 1-7, characterized in that, In terms of decoding and transforming the video to be displayed, and outputting grayscale pixels adapted to the projection lamp, the hardware acceleration module is specifically used for: The video to be displayed is decoded to obtain the original video frame, which is in YUV format; Extract single-frame original images of the original video frame according to the video frame rate; The original image is scaled to an effective display size that is compatible with the projection lamp; The scaled original image is converted into grayscale pixels, and the grayscale pixels correspond to the grayscale display information of the projection lamp; In constructing the projection frame based on the grayscale pixels, the CPU is specifically used for: A frame header is added at the beginning of the grayscale pixels, and a check bit and a free bit are added sequentially at the end of the grayscale pixels to obtain the complete projection frame.

9. A vehicle-mounted projection method based on high-speed UART, characterized in that, The method is applied to a system-on-a-chip (SoC) of an in-vehicle projection system, wherein the in-vehicle projection system is the system described in any one of claims 1-8, and the method comprises: The video to be displayed is decoded and transformed to output grayscale pixels adapted to the projection lamp; Construct a projection frame based on the grayscale pixels; Encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple bits of UART data; Each UART bit data in the UART frame is mapped to a preset bit of an RGB pixel, and the remaining bits of the RGB pixel are filled with invalid values; The VO module of the SOC reads the RGB pixels, converts the RGB pixels into corresponding level signals, and sends the level signals to the projection lamp. The projection lamp receives the level signals and parses the UART bit data in the level signals according to the UART frame format, restores the projection frame, and then projects and displays it.

10. A vehicle-mounted projection device based on high-speed UART, characterized in that, The device is applied to a system-on-a-chip (SoC) of an in-vehicle projection system, wherein the in-vehicle projection system is the system described in any one of claims 1-8, and the device comprises: The processing unit is used to decode and transform the video to be displayed, and output grayscale pixels adapted to the projector lamp; construct a projection frame based on the grayscale pixels; encapsulate a single grayscale pixel in the projection frame into a UART frame containing multiple UART bit data; map each UART bit data in the UART frame to a preset bit of an RGB pixel, and fill the remaining bits of the RGB pixel with invalid values; The output unit is used to read the RGB pixels through the VO module of the SOC module, convert the RGB pixels into corresponding level signals, and send the level signals to the projection lamp. The projection lamp is used to receive the level signals and parse the UART bit data in the level signals according to the UART frame format, restore the projection frame, and then project and display it.

11. A system-on-a-chip (SOC), characterized in that, The SOC is used to execute the step instructions in the method as described in claim 9. The SOC includes a hardware acceleration module, a memory, a central processing unit (CPU), a video output (VO) module, and a high-speed bus. The hardware acceleration module includes a video decoding unit and an image processing unit. The video decoding unit, the image processing unit, the CPU, the memory, and the VO module are all interconnected through the high-speed bus. The video decoding unit is used to perform hardware-accelerated decoding of the video to be displayed and output video frame data in YUV format. The image processing unit is used to perform image transformation operations on the video frame data and output pixel data adapted to the projection lamp. The CPU is used to coordinate and control the collaborative work of various hardware units, and to execute the logical scheduling of projection frame construction, UART frame encapsulation and RGB pixel mapping. The memory is used to cache the pixel data; The VO module is used to read the pixel data from the memory and output the corresponding level signal.

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