Dual-gate trench MOSFET with shielded gate electrode in stepped trench
By integrating SBR and forming HCMOSFET structure in SGT MOSFET, the problems of drain-source leakage current and breakdown voltage at high temperature are solved, resulting in lower forward voltage, reverse leakage current and switching loss, and improved device stability and on-resistance performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LINTAI SEMICONDUCTOR (QINGDAO) CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-02
AI Technical Summary
Existing SGT MOSFETs face challenges such as increased drain-source leakage current and negative temperature coefficient of breakdown voltage in high-temperature applications. Furthermore, they are prone to warping under large-diameter wafer and high breakdown voltage conditions, leading to processing difficulties and increased specific on-resistance.
An integrated SBR is used as the shielded gate structure of the MOS channel diode. By providing a shielded gate electrode in the single-stage gate trench, the parasitic diode is turned off. The second SGT MOSFET and the first SGT MOSFET are combined to form an HCMOSFET, which reduces switching losses and optimizes the specific on-resistance.
This achieves lower forward voltage and reverse leakage current in high-temperature environments, improving device stability and operational reliability under high-temperature conditions, and reducing specific on-resistance and switching losses.
Smart Images
Figure CN122138448A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a unit cell structure for a power semiconductor device. The device features a single-level gate trench with a shielded gate electrode and includes two types of gate trenches. Specifically, this invention integrates a first trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with an SBR (Super Barrier Rectifier) or with a second trench MOSFET to form an HCMOSFET (Hybrid-Channel Metal-Oxide-Semiconductor Field-Effect Transistor), thereby achieving lower on-resistance and lower switching losses. Because the top trench width of the single-level gate trench structure is smaller than its bottom trench width, the unit cell size of this novel device can be reduced. Background Technology
[0002] Compared to traditional trench MOSFETs, SGT MOSFETs (Shielded Gate Trench Metal-Oxide Semiconductor Field-Effect Transistors) offer greater application advantages because they achieve lower specific drain-source resistance (Rsp) through the oxide charge balance (OCB) region formed between adjacent deep trenches, and improve overall device efficiency in most applications without compromising shock resistance. However, as wafer diameter increases or device breakdown voltage rises, SGT MOSFETs with strip-shaped deep trenches face severe wafer warpage issues. The main reason for this problem is that as breakdown voltage and wafer diameter increase, the depth of the deep trenches and the thickness of the field oxide layer continuously increase. When wafer warpage exceeds a critical value, some process equipment may experience vacuum adsorption or wafer transport failures, preventing further wafer processing. Furthermore, the increased field oxide layer thickness occupies a significant amount of space in the cell region, leading to an increase in the device's specific on-resistance.
[0003] Meanwhile, the parasitic PIN body diode of the SGT MOSFET degrades the device's reverse recovery characteristics. Therefore, the industry typically employs various irradiation and platinum diffusion processes to shorten the reverse recovery time (Trr) of the parasitic PIN body diode. However, in high-temperature applications, this method can lead to problems such as increased drain-source leakage current and a negative temperature coefficient of breakdown voltage.
[0004] In summary, in the field of semiconductor power devices, especially in the design of SGT MOSFETs, there is still a pressing need for a new cell structure and device configuration to overcome existing design limitations and improve device performance. Summary of the Invention
[0005] This invention provides an SGT MOSFET power device comprising a shielded gate structure integrating an SBR as a MOS channel diode. The shielded gate electrode is located within the single-stage gate trench, which can turn off the parasitic diode in the SGT MOSFET, thereby reducing switching losses. The integrated SBR creates a low barrier for majority carriers in the MOS channel, the height of which can be adjusted by the gate oxide thickness, the doping concentration of the P-type body region, and the channel length. Compared to a Schottky barrier diode (SBD), the SBR in this invention exhibits lower forward voltage (Vf) and reverse leakage current (Ir), and demonstrates superior performance and higher stability at high temperatures.
[0006] According to another aspect of the invention, a second SGT MOSFET is further included, wherein its shielded gate electrode is disposed in the bottom gate trench of a single-stage gate trench and forms an HCMOSFET with the first SGT MOSFET in the unit cell to reduce the specific on-resistance of the device. By performing additional short-channel injection in the channel region of the second SGT MOSFET, the HCMOSFET forms two different threshold voltages to improve the positive temperature coefficient of the device and ensure operational reliability under high-temperature conditions.
[0007] The above and other objects and advantages of the present invention will be readily apparent to those skilled in the art upon referring to the following figures and reading the detailed description of preferred embodiments below. Attached Figure Description
[0008] Figure 1A This is a top view according to a preferred embodiment of the present invention.
[0009] Figure 1B yes Figure 1A A cross-sectional view along section A1-A1' of a preferred embodiment.
[0010] Figure 1C This is a top view according to another preferred embodiment of the present invention.
[0011] Figure 1D This is a top view according to another preferred embodiment of the present invention.
[0012] Figure 1E yes Figure 1A A cross-sectional view along section A1-A1' of another preferred embodiment.
[0013] Figure 1F yes Figure 1A A cross-sectional view along section A1-A1' of another preferred embodiment.
[0014] Figure 1G yes Figure 1AA cross-sectional view along section A1-A1' of another preferred embodiment.
[0015] Figure 2A This is a top view according to another preferred embodiment of the present invention.
[0016] Figure 2B yes Figure 2A A cross-sectional view along section A2-A2' of a preferred embodiment.
[0017] Figure 2C This is a top view according to another preferred embodiment of the present invention.
[0018] Figure 2D This is a top view according to another preferred embodiment of the present invention.
[0019] Figure 2E yes Figure 2A A cross-sectional view along section A2-A2' of another preferred embodiment.
[0020] Figure 2F yes Figure 2A A cross-sectional view along section A2-A2' of another preferred embodiment.
[0021] Figure 2G yes Figure 2A A cross-sectional view along section A2-A2' of another preferred embodiment.
[0022] Figure 2H yes Figure 2A A cross-sectional view along section A2-A2' of another preferred embodiment.
[0023] Figure 3 yes Figure 2A A cross-sectional view along section A2-A2' of another preferred embodiment.
[0024] Figure 4A This is a top view according to another preferred embodiment of the present invention.
[0025] Figure 4B yes Figure 4A A cross-sectional view along section A3-A3' of a preferred embodiment.
[0026] Figure 4C yes Figure 4A A cross-sectional view along section A3-A3' of another preferred embodiment.
[0027] Figure 4D yes Figure 4A A cross-sectional view along section A3-A3' of another preferred embodiment.
[0028] Figure 4E yes Figure 4AA cross-sectional view along section A3-A3' of another preferred embodiment.
[0029] Figure 5 yes Figure 4A A cross-sectional view along section A3-A3' of another preferred embodiment. Detailed Implementation
[0030] The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. The invention may be embodied in various ways, but should not be limited to the embodiments described herein. For example, the description herein refers more to N-channel semiconductor integrated circuits, but it will be apparent that other devices are also possible. The preferred embodiments of the invention are described in detail below with reference to the accompanying drawings. Some directional terms, such as “top,” “bottom,” “front,” “back,” “above,” “below,” etc., are used with reference to the orientation of the accompanying drawings. Since the elements in the embodiments can be placed in many different orientations, the directional terms in this invention are for descriptive purposes only and should not be considered as limiting the invention. It should be understood that various structural or logical substitutions and modifications in the embodiments should be covered within the true spirit and scope of the invention. Therefore, the following detailed description should not be considered as limiting the invention, the scope of which is defined by the appended claims. It should be understood that the inventive features of the various preferred embodiments described herein can be combined with each other, unless otherwise specified.
[0031] Figure 1A The diagram shows a top view of a trench-type semiconductor power device according to a preferred embodiment of the present invention. The device comprises multiple unit cells, each of which has two types of gate trenches. In each unit cell, a first gate trench 103 with a hexagonal structure surrounds a second gate trench 104, which also has a hexagonal structure. The second gate trench 104 surrounds a shielding gate contact trench 123. Simultaneously, a hexagonal source contact trench 113 is provided between the first gate trench 103 and the second gate trench 104, and the area between the source contact trenches 113 of adjacent unit cells constitutes a MOS unit cell region.
[0032] Figure 1B What is shown is Figure 1AA cross-sectional view along the A1-A1' direction is shown in this preferred embodiment, which employs a single-layer epitaxial layer structure. This embodiment is an N-channel SGT MOSFET, fabricated in an N-type epitaxial layer 102' located on an N+ substrate 101', the back side of which is plated with a back metal 100' as the drain metal. Each first MOSFET cell of the power device according to this embodiment has two types of gate trench structures. Within the N-type epitaxial layer 102', a plurality of first gate trenches 103' and second gate trenches 104' are formed vertically downwards from the upper surface of the N-type epitaxial layer 102', and do not extend to the common interface between the N-type epitaxial layer 102' and the N+ substrate 101', wherein the depth of the second gate trenches 104' is greater than that of the first gate trenches 103'. Each of the first gate trenches 103' has a gate electrode 105' (G, as shown in the figure) at its upper part. The bottom of the gate electrode 105' is covered by a bottom oxide layer 106', and the sidewalls are covered by a first gate oxide layer 119' (GOX1). The thickness of the bottom oxide layer 106' is greater than or equal to the thickness of the first gate oxide layer 119'. Each of the second gate trenches 104' is a single-stage gate trench structure, including a top second gate trench 1041' and a bottom second gate trench 1042', with corresponding trench depths T. 2T and T 2B The top second gate groove 1041' is located above the bottom second gate groove 1042', and its groove width W 2T The groove width W is smaller than the bottom second gate groove 1042'. 2BEach second gate trench 104' contains a shielded gate electrode 107' (SG, as shown in the figure). The bottom region of the shielded gate electrode 107' and the sidewalls of the bottom second gate trench 1042' are covered by a first insulating film 116' (FOX, as shown in the figure), and the top region of the shielded gate electrode 107' and the sidewalls of the top second gate trench 1041' are covered by a first gate oxide layer 119', wherein the thickness of the first insulating film 116' is greater than the thickness of the first gate oxide layer 119'. The first insulating film 116' is prepared by a local oxidation of silicon (LOCOS) process. During the local oxidation process, the sidewalls of the top second gate trench 1041' are covered with a silicon nitride layer or a silicon nitride-silicon dioxide double-layer stacked layer to prevent the sidewalls from being oxidized. Between the first gate trench 103' and the second gate trench 104', a first P-type body region 114' (p1, as shown) extends from the upper surface of the N-type epitaxial layer 102'. A first n+ source region 111' is provided on the first P-type body region 114', and the first P-type body region 114' surrounds the gate electrode 105' covered by the first gate oxide layer 119'. Within the first P-type body region 114', a p+ body contact region 110' is formed below the first n+ source region 111' to reduce the body contact resistance. The first channel region 140' of the first MOSFET power device is formed along the sidewall of the first gate trench 103' within the first P-type body region 114' and is connected to the first n+ source region 111'. An interlayer dielectric film 109' is stacked on top of the epitaxial layer 102', and a source metal 120' is fabricated on it. The first P-type body region 114', the first n+ source region 111', and the shielding gate electrode 107' are shorted to the source metal 120' through multiple source contact trenches 113' and shielding gate contact trenches 123', respectively. The source contact trenches 113' and the shielding gate contact trenches 123' are filled with contact metal plugs and metal barrier layers, and the heavily doped p+ body contact region 110' surrounds the bottom periphery of the source contact trenches 113' and below the first n+ source region 111'.
[0033] Figure 1C The image shown is a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention. This device comprises multiple unit cells, each of which has two types of gate trenches. The device structure of this embodiment is similar to... Figure 1A Similarly, the difference is that, in the unit cell of this embodiment, the first gate trench 103'', the second gate trench 104'', the source contact trench 113'', and the shielding gate contact trench 123'' are all square structures.
[0034] Figure 1DThe figure shows a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention. The device includes a plurality of unit cells, and each unit cell is provided with two types of gate trenches. The device structure of this embodiment is similar to that of Figure 1A , except that in the unit cell according to this embodiment, the first gate trench 103''', the second gate trench 104''', the source contact trench 113''', and the shield gate contact trench 123''' are all in strip structures.
[0035] Figure 1E The figure shows Figure 1A a cross-sectional view of another preferred embodiment along the A1-A1' direction in Figure 1B . The device adopts an improved double-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the figure. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to that of
[0036] Figure 1F The figure shows Figure 1A a cross-sectional view of another preferred embodiment along the A1-A1' direction in Figure 1E . The device adopts an improved triple-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the figure. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to that of
[0037] Figure 1G The figure shows Figure 1A a cross-sectional view of another preferred embodiment along the A1-A1' direction in Figure 1E . The device adopts an improved triple-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the figure. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to that of
[0038] Figure 2A The diagram shown is a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention. The device comprises multiple unit cells, each unit cell having two types of gate trenches. The device structure of this embodiment is similar to... Figure 1A Similarly, the difference lies in that each cell of this invention integrates a first MOSFET and a super-barrier rectifier (SBR, as shown in the figure). Within each cell, a shielding gate contact trench 223 and a second gate trench 204 are provided between two adjacent source contact trenches 213, forming a super-barrier rectifier. A first gate trench 203 is provided between the source contact trenches 213 of two adjacent cell cells, forming a first MOSFET, and the first MOSFET is arranged around the super-barrier rectifier.
[0039] Figure 2B What is shown is Figure 2A A cross-sectional view along the A2-A2' direction is shown in the figure. This preferred embodiment employs a single-layer epitaxial layer structure. The N-channel SG MOSFET of this embodiment... Figure 1B Similarly, the difference lies in the structure of the second gate trench 204', which is modified to form a super-barrier rectifier region (SBR, as shown in the figure). In this embodiment, the first MOSFET cell within each unit cell integrates a super-barrier rectifier region. This embodiment also includes a second P-type body region 224' (p2, as shown in the figure), on which a second n+ source region 221' is provided. The doping concentration of the second P-type body region 224' located at the sidewall of the top second gate trench 2041' is lower than that of the first P-type body region 214'. The second gate trench 204' penetrates the second P-type body region 224' and the second n+ source region 221', and terminates within the N-type epitaxial layer 202'. The second channel region 250' of the super-barrier rectifier region is formed within the second P-type body region 224' along the sidewall of the top second gate trench 2041' and is connected to the second n+ source region 221'. The channel length of the second channel region 250' is shorter than that of the first channel region 240'. Furthermore, by means of an arsenic or phosphorus angle implantation process, an N-type first short channel implantation region 252' (Nsci1, as shown in the figure) is formed around the second channel region 250' at the sidewall of the top second gate trench 2041', with a doping concentration higher than that of the N-type epitaxial layer 202'.
[0040] Figure 2CShown is a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention. The device includes multiple unit cells, and each unit cell is provided with two types of gate trenches. The device structure of this embodiment is similar to that in FIG. 2A, except that in the unit cells according to this embodiment, the first gate trench 203'', the second gate trench 204'', the source contact trench 213'', and the shield gate contact trench 223'' are all square structures.
[0041] Figure 2D Shown is a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention. The device includes multiple unit cells, and each unit cell is provided with two types of gate trenches. The device structure of this embodiment is similar to Figure 2A that in FIG. 2A, except that in the unit cells according to this embodiment, the first gate trench 203''', the second-type gate trench 204''', the source contact trench 213''', and the shield gate contact trench 223''' are all strip structures.
[0042] Figure 2E Shown is Figure 2A a cross-sectional view of another preferred embodiment along the A2-A2' direction in FIG. 2A. The device adopts an improved double-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the drawing. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to Figure 2B that in FIG. 2A, except that the N-type epitaxial layer in the present invention is a double-layer stepped epitaxial layer with two different doping concentrations, including a first epitaxial layer 212'''' (N1, as shown in the figure, located between the B-B and C-C lines) with a doping concentration of D1, and a second epitaxial layer 222'''' (N2, as shown in the figure, located between the A-A and B-B lines) with a doping concentration of D2, where D2 < D1, to further reduce the specific on-resistance of the device.
[0043] Figure 2F Shown is Figure 2A a cross-sectional view of another preferred embodiment along the A2-A2' direction in FIG. 2A. The device adopts an improved triple-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the drawing. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to Figure 2E that in FIG. 2A, except that there is also a buffer epitaxial layer 202'''' (NB, as shown in the figure) with a doping concentration of DB between the bottom of the shield gate electrode 207''''' (SG, as shown in the figure) and the N+ substrate 201''''' in this embodiment, and D2 < DB < D1. In addition, the bottom region of the second gate trench 204''''' is surrounded by an N-type electric field reduction region 254''''' (N , as shown in the figure), and its doping concentration is lower than the doping concentration DB of the buffer epitaxial layer 202'''''
[0044] Figure 2G What is shown is Figure 2A A cross-sectional view of another preferred embodiment along the A2-A2' direction is shown in the figure. This device employs an improved three-layer stepped epitaxial layer structure. The doping concentration variation of the epitaxial layer along the vertical direction is indicated in the figure. The N-channel trench semiconductor power device structure of this embodiment is similar to... Figure 2E Similarly, the difference lies in that, in this embodiment, a buffer epitaxial layer 202 (NB, as shown in the figure) is further provided between the bottom of the shielding gate electrode 207''''' (SG, as shown in the figure) and the N+ substrate 201''''', with a doping concentration of DB, and DB <D2<D1。
[0045] Figure 2H What is shown is Figure 2A A cross-sectional view of another preferred embodiment along the A2-A2' direction is shown in the figure. This device employs an improved three-layer stepped epitaxial layer structure. The doping concentration variation of the epitaxial layer along the vertical direction is indicated in the figure. The N-channel trench semiconductor power device structure of this embodiment is similar to... Figure 2G Similarly, the difference is that in this embodiment, the bottom region of the second gate trench 1204 is also surrounded by an N-type electric field reduction region 1254 (N As shown in the figure, its doping concentration is lower than the doping concentration DB of the buffer epitaxial layer 1202.
[0046] Figure 3 What is shown is Figure 2A A cross-sectional view of another preferred embodiment along the A2-A2' direction is shown in the figure. This device employs an improved three-layer stepped epitaxial layer structure. The doping concentration variation of the epitaxial layer along the vertical direction is indicated in the figure. The N-channel trench semiconductor power device structure of this embodiment is similar to... Figure 2G Compared to the improved first gate trench 303, in this embodiment, a second shielding gate electrode 327 is provided below the first gate electrode 305 (G, as shown in the figure) in the first gate trench 303, and the two are isolated by a first polysilicon inter-oxide layer 308.
[0047] Figure 4AThe diagram shows a top view of a trench-type semiconductor power device according to another preferred embodiment of the present invention, which employs a strip cell layout. In this device, a second MOSFET (MOS2, as shown) is integrated with a first MOSFET (MOS1, as shown) to form a hybrid channel MOSFET (HCMOSFET). According to this preferred embodiment, a first gate electrode (G1, as shown) is provided in a first gate trench 403, and a second gate electrode (G2, as shown) and a shielding gate electrode (SG, as shown) are provided in a second gate trench 404; the first gate electrode G1 in the first gate trench 403 and the second gate electrode G2 in the second gate trench 404 are shorted to the gate metal 435 through a first gate contact region 415 and a second gate contact region 425, respectively; the shielding gate electrode SG in the second gate trench 404 is shorted to the source metal 420 through a shielding gate contact trench 407. The sidewall of the second gate electrode G2 is lined with a first gate oxide layer (GOX1, as shown in the figure), which is formed on the upper part of the second gate trench 404; the sidewall of the shielding gate electrode SG is lined with a first thick oxide layer (FOX, as shown in the figure), which is formed on the lower part of the second gate trench 404, and the thickness of the first gate oxide layer is less than that of the first thick oxide layer. Furthermore, a source contact trench 413 is provided between adjacent first gate trenches 403 and second gate trenches 404.
[0048] Figure 4B What is shown is Figure 4A A cross-sectional view along the A3-A3' direction of a preferred embodiment, showing a device employing a single-layer epitaxial layer structure. The N-channel trench semiconductor power device structure according to this embodiment is... Figure 1B Compared to the improved second gate trench 404', in this embodiment, the second MOSFET (MOS2, as shown) is integrated with the first MOSFET (MOS1, as shown) to form a hybrid channel MOSFET (HCMOSFET). The second gate trench 404' extends through the second P-type body region 424' and the second n+ source region 421', and terminates in the N-type epitaxial layer 402', wherein the doping concentration of the second P-type body region 424' is the same as that of the first P-type body region 414'. In each of the second gate trenches 404' of the second MOSFET, a second gate electrode 425' (G2, as shown) is provided in the top second gate trench 4041', which is located above the shielding gate electrode 407' (SG, as shown) in the bottom second gate trench 4042', and the two are isolated by a second polysilicon inter-oxide layer 418' (IPO2). The sidewall of the second gate electrode 425' is lined with a second gate oxide layer 429' (GOX2), which is formed on the sidewall of the top second gate trench 4041' and has the same thickness as the first gate oxide layer 419'.
[0049] Figure 4C As shown Figure 4A is a cross-sectional view of another preferred embodiment along the A3 - A3' direction in Figure 4B . The device adopts an improved double-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the drawing. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to
[0050] Figure 4D As shown Figure 4A is a cross-sectional view of another preferred embodiment along the A3 - A3' direction in Figure 4C . The device adopts an improved triple-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the drawing. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to
[0051] Figure 4E As shown Figure 4A is a cross-sectional view of another preferred embodiment along the A3 - A3' direction in Figure 4C . The device adopts an improved triple-layer stepped epitaxial layer structure, and the doping concentration change of the epitaxial layer along the vertical direction is marked in the drawing. The structure of the N-channel trench-type semiconductor power device in this embodiment is similar to
[0052] Figure 5 As shown Figure 4A is a cross-sectional view of another preferred embodiment along the A3 - A3' direction in Figure 4BSimilarly, the difference lies in that this embodiment further includes a second P-type body region 524 (p2, as shown in the figure), on which a second n+ source region 521 is provided; wherein, the doping concentration of the second P-type body region 524 along the sidewall of the top second gate trench is lower than that of the first P-type body region 514. The second channel region 550 in the second MOSFET is formed within the second P-type body region 524 along the sidewall of the top second gate trench 5041 and is connected to the second n+ source region 521; the first channel region 540 in the first MOSFET is formed within the first P-type body region 514 along the sidewall of the first gate trench 503, and the channel length of the second channel region 550 is less than that of the first channel region 540. In addition, this embodiment also includes a second short channel injection region 562 (Nsci2, as shown in the figure) of the first conductivity type, which surrounds the second channel region 550 and has a higher doping concentration than that of the N-type epitaxial layer 502. This injection process enables the hybrid MOSFET, composed of the first and second MOSFETs, to form two different threshold voltages, thereby improving the positive temperature coefficient of the device and ensuring its reliability under high-temperature conditions. The threshold voltage Vth2 of the second MOSFET is lower than the threshold voltage Vth1 of the first MOSFET.
[0053] Although various embodiments have been described herein, it will be understood that various modifications can be made to the invention by means of the guidance provided in the appended claims without departing from the spirit and scope of the invention. For example, the methods of the invention can be used to form structures of various semiconductor regions having a conductivity type opposite to that described herein.
Claims
1. A power device, characterized in that, It includes multiple unit cells having two types of gate trenches, each unit cell comprising: An epitaxial layer of the first conductivity type grown on a substrate; A first body region of the second conductivity type is formed thereon, and a first source region of the first conductivity type is formed thereon; The first gate trench penetrates the first body region and the first source region, and terminates within the epitaxial layer; The first gate electrode is located in the first gate trench, and its sidewalls are lined with a first gate oxide layer; The first channel region of the first MOSFET is formed in the first body region along the sidewall of the first gate trench and is connected to the first source region; The second gate trench is located within the epitaxial layer and has a single-stage gate trench structure, including a top second gate trench located above and a bottom second gate trench located below, wherein the trench width of the top gate trench is smaller than that of the bottom second gate trench, and the trench depth of the top gate trench is smaller than that of the bottom second gate trench. A first shielding gate electrode is formed at least within the bottom second gate trench, the bottom of which and the sidewalls of the second gate trench are lined with a first insulating film, the thickness of which is greater than that of the first gate oxide layer; and The first body region, the first source region, and the first shielding gate electrode are shorted to the source metal through the source contact trench and the shielding gate contact trench, respectively.
2. The power device according to claim 1, characterized in that, The width of the first shielding gate electrode at the top of the bottom second gate trench is greater than its width in other areas of the bottom second gate trench.
3. The power device according to claim 1, characterized in that, The first insulating film is prepared by a local oxidation process of silicon. During the local oxidation process, the sidewalls of the top second gate trench are covered with a silicon nitride layer or a silicon nitride-silicon dioxide double-layer stacked layer to prevent the sidewalls of the top second gate trench from being oxidized.
4. The power device according to claim 1, characterized in that, The first shielding gate electrode is formed in both the top second gate trench and the bottom second gate trench, and its sidewall in the top second gate trench is lined with the first gate oxide layer.
5. The power device according to claim 1, characterized in that, Each cell also includes a super-barrier rectifier concentrated with the first MOSFET, further comprising: The first shielding gate electrode is simultaneously filled in the top second gate trench and the bottom second gate trench, and its sidewall in the top second gate trench is lined with a second gate oxide layer, wherein the thickness of the second gate oxide layer is less than that of the first gate oxide layer. A second body region of a second conductivity type is provided thereon, and the doping concentration of the second body region along the sidewall of the top second gate trench is lower than that of the first body region. The second gate trench penetrates the second body region and the second source region, and terminates within the epitaxial layer; The second channel region of the super-barrier rectifier is formed within the second body region along the sidewall of the top second gate trench and is connected to the second source region.
6. The power device according to claim 5, characterized in that, Also includes: A first short-channel injection region of a first conductivity type is disposed around the second channel region, wherein the first short-channel injection region is prepared at the sidewall of the top second gate trench by an arsenic or phosphorus angle implantation process, and its doping concentration is higher than that of the epitaxial layer. The channel length of the second channel area is less than that of the first channel area.
7. The power device according to claim 1, characterized in that, It also includes a second shielding gate electrode, which is formed below the first gate electrode and the two are isolated by a second polysilicon inter-oxide layer.
8. The power device according to claim 1, characterized in that, Each cell also includes a second MOSFET concentrated together with the first MOSFET, and further includes: The second gate electrode is disposed in the top second gate trench and above the first shielding gate electrode, and the two are isolated by a second polysilicon inter-oxide layer. The second gate electrode is lined with a second gate oxide layer, which is formed on the sidewall of the top second gate trench. The thickness of the second gate oxide layer is the same as that of the first gate oxide layer. A second body region of a second conductivity type is provided thereon, and a second source region of a first conductivity type is provided thereon; The second gate trench penetrates the second body region and the second source region, and terminates within the epitaxial layer; The second channel region of the second MOSFET is formed in the second body region along the sidewall of the top second gate trench and is connected to the second source region; The second MOSFET and the first MOSFET form a hybrid channel MOSFET.
9. The power device according to claim 8, characterized in that, The doping concentration of the second body region is the same as that of the first body region.
10. The power device according to claim 8, characterized in that, Also includes: A second short-channel injection region of a first conductivity type is disposed around the second channel region, and its doping concentration is higher than that of the epitaxial layer; The channel length of the second channel area is shorter than that of the first channel area; The doping concentration of the second body region along the sidewall of the top second gate trench is lower than that of the first body region.
11. The power device according to claim 1, characterized in that, The bottom of the first gate electrode is lined with the first gate oxide layer, which is formed in the bottom region of the first gate trench.
12. The power device according to claim 1, characterized in that, The bottom of the first gate electrode is lined with a second insulating film, which is formed in the bottom region of the first gate trench and has a thickness greater than that of the first gate oxide layer.
13. The power device according to claim 1, characterized in that, The epitaxial layer is a single-layer epitaxial layer with uniform doping concentration.
14. The power device according to claim 1, characterized in that, The epitaxial layer comprises at least two stepped epitaxial layers with different doping concentrations, including a first epitaxial layer with a doping concentration of D1, and a second epitaxial layer with a doping concentration of D2 disposed above the first epitaxial layer, wherein D2 <D1。 15. The power device according to claim 14, characterized in that, It also includes a buffer epitaxial layer, which is disposed between the substrate and the first epitaxial layer, and has a doping concentration of DB, wherein DB <D2<D1。 16. The power device according to claim 14, characterized in that, It also includes a buffer epitaxial layer, which is disposed between the substrate and the first epitaxial layer, and has a doping concentration of DB, wherein D2 <DB<D1。 17. The power device according to claim 1, characterized in that, It also includes an electric field reduction region of a first conductivity type, which is disposed around the bottom region of the second gate trench, and whose doping concentration is lower than that of the epitaxial layer.
18. The power device according to claim 1, characterized in that, The first and second gate trenches are square, hexagonal, or strip-shaped.
19. The power device according to claim 5, characterized in that, The super-barrier rectifier is square or hexagonal in shape and is surrounded by the first MOSFET.
20. The power device according to claim 8, characterized in that, The first and second gate trenches are strip-shaped.