An automated design and parameter optimization system for SRAM circuits in in-memory computing architectures

Abstract

An automatic design and parameter optimization system of SRAM circuit in in-memory computing architecture, first data collection and input are carried out, then simulation and model training are carried out, the artificial neural network after training convergence is used as a proxy model, and is combined with a quantum genetic algorithm optimization engine to obtain a QGA-ANN joint optimization system, the optimal design parameters of the candidate are obtained through global extreme value optimization, and after verification and evaluation, the globally optimal design parameters are output. The application is based on the high stability in-memory computing SRAM circuit and optimization system of quantum genetic algorithm and neural network, the BP proxy model with extremely low time delay is used to perfectly replace the traditional SPICE physical simulation, and the quantum genetic algorithm with the elite reservation mechanism is used to completely solve the bottleneck of local extreme value and slow convergence. The time-consuming and long analog integrated circuit "trial and error" design is converted into efficient and accurate "one-key" automatic optimization design, and the efficiency and stability of the in-memory computing macro cell reliability design are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of SRAM circuit design automation technology, and in particular to an automated design and parameter optimization system for SRAM circuits in in-memory computing architectures. Background Technology

[0002] With the explosive growth of artificial intelligence (AI) and the Internet of Things (IoT) technologies, the demand for data processing capabilities from edge computing devices is increasing exponentially. Traditional von Neumann computing architectures, due to the separation of storage and computing units, face severe bottlenecks of the "memory wall" and "power wall," making it difficult to meet the demands of high energy efficiency computing. To overcome this limitation, compute-in-memory (CIM) architecture has emerged, directly embedding processing power within the storage array, eliminating frequent data movement, and has become a hot research topic in the field of integrated circuit design.

[0003] Among numerous CIM implementation schemes, the charge domain-based CIM architecture based on SRAM (Static Random Access Memory) is highly favored due to its high compatibility with standard CMOS processes. This architecture typically adds transmission gate components to standard SRAM bit cells, utilizing the charge-sharing principle for in-situ multiplication operations. However, this architecture introduces a severe reliability challenge: during computation, the charge injection effect caused by opening the transmission gates can disturb the voltage of the memory nodes, making the stored data highly susceptible to flipping during computation operations, severely impacting chip yield and computational accuracy.

[0004] SNM (Static Noise Margin) is a crucial metric for measuring memory stability. To improve SNM, designers must meticulously optimize the transistor dimensions (channel width) of pull-up transistors (PU), pull-down transistors (ND), and access transistors (NT) in SRAM cells. Traditional analog integrated circuit design relies heavily on manual experience and repeated SPICE (simulation program) scans. This "trial and error" approach is not only time-consuming but also struggles to cover the vast design space. Although existing electronic design automation (EDA) tools have incorporated optimization techniques such as genetic algorithms (GA), ordinary genetic algorithms often suffer from drawbacks when dealing with multi-parameter, nonlinearly coupled optimization problems. These drawbacks include a high number of population iterations, slow convergence speed, and a tendency to get trapped in local optima, making it difficult to find the globally optimal transistor size combination within a limited design cycle.

[0005] Therefore, the existing charge-domain analog in-memory (CIM) architecture has serious flaws. The opening of the transmission gate switches between the storage nodes and shared capacitors within the SRAM cell generates a charge-sharing effect, severely disturbing the storage node voltage and causing a bottleneck in the reliability of SRAM data changes. Meanwhile, the traditional method of optimizing the dimensions of pull-up transistors (PU), pull-down transistors (ND), and access transistors (NT) through thousands of detailed SPICE simulations results in extremely long design cycles. Conventional genetic algorithms (GA) suffer from numerous iterations, slow convergence, and a high susceptibility to local optima. There is an urgent need for efficient and automated design methods that can replace cumbersome SPICE simulations and quickly escape local optima to achieve rapid optimization design of highly stable in-memory computing SRAM circuits. Summary of the Invention

[0006] To address the aforementioned shortcomings in existing SRAM circuit design methods, this invention provides an automated design and parameter optimization system for SRAM circuits in in-memory computing architectures.

[0007] The technical solution adopted by this invention to solve the above-mentioned technical problems is: an automated design and parameter optimization system for SRAM circuits in in-memory computing architecture. The workflow of this system includes the following steps: Step 1: Data Acquisition and Input The system collects the SRAM circuit design parameters to be optimized and performs normalization processing. Step 2: Simulation and Model Training The normalized parameters are simulated and scanned using circuit simulation tools to obtain a dataset characterizing the circuit performance. The dataset is then input into the artificial neural network to train it, enabling the network to learn and fit the nonlinear mapping relationship between parameters and circuit performance.

[0008] Step 3: Joint Modeling and Rapid Optimization The converged artificial neural network is used as a surrogate model and combined with the quantum genetic algorithm optimization engine to obtain the QGA-ANN joint optimization system, which obtains the candidate optimal design parameters through global extremum optimization. Step 4: Verification, Evaluation, and Result Output The candidate optimal design parameters are substituted into the simulator for evaluation and verification, and the verified parameters are output as the globally optimal design parameters, thereby completing the automated design and parameter optimization of the SRAM circuit.

[0009] Preferably, the workflow of the QGA-ANN joint optimization system is as follows: first, the model is loaded; then, the control parameters of the QGA algorithm are initialized; and an initial quantum state chromosome population is randomly generated; then, the main loop is entered for iterative iteration. The main loop includes the following steps: S1, Quantum Measurement and Constraint Check First, the initial quantum chromosome population is decoded into physical size parameters, and then physical constraint filtering is performed to eliminate invalid solutions that do not meet the circuit read / write constraints, thus obtaining the filtered effective parameter combinations. S2, Calculate fitness The effective parameter combination is input into the BP neural network, and the corresponding predicted SNM value is output as the fitness of the current individual. S3, Elite Retention and Recording The system records the best individual with the highest fitness in the current generation population in real time, and replaces the worst individual with the best fitness in the next generation population with the best individual. S4. Convergence Detection and Dynamic Termination The system calculates the fitness variance of the population in real time. When the fitness variance is lower than the preset convergence threshold or the preset maximum number of iterations has been reached, the main loop stops and outputs the optimal parameters. When the fitness variance is higher than the preset convergence threshold and the preset maximum number of iterations has not been reached, S5 is executed. S5, Genetic Operations and Quantum Gate Updates The system performs genetic operations on the population, then updates the current population with phase through a quantum rotation gate, and uses the generated new population as the initial population for the next round of the main cycle.

[0010] Preferably, in step S5, the genetic operation includes sequentially performing single-point crossover and adaptive mutation on individuals in the population.

[0011] Preferably, in step S5, the method for updating the quantum rotation gate is as follows: first, qubit encoding is performed, and the population is encoded using the probability amplitude of the qubits, so that each qubit... Simultaneously in status and The superposition of states, the qubit encoding satisfies the following formula: ; ; Then, the phase probability amplitude of each qubit is adjusted using a quantum rotation gate U(θ) to achieve the evolution and update of the individual states of the population. The quantum rotation gate U(θ) and the rotation angle θ satisfy the following formula: Rotation matrix definition: ; Matrix transformations: ; ; Modulus conservation: .

[0012] According to the above technical solution, the beneficial effects of the present invention are: 1. Significantly reduced design cycle: Training the BP neural network surrogate model takes only 1.51 seconds, and the mean squared error (MSE) is as low as... It accurately and efficiently replaces thousands of SPICE simulations in conventional designs. Combined with the QGA algorithm engine, the system can converge quickly in just 100 generations within the set maximum evolution number of 500 generations, greatly reducing the design cycle of analog in-memory computation macrocells.

[0013] 2. Significantly Improved Circuit Stability and Energy Efficiency: The system predicted a maximum SNM of 0.588V, which was verified by post-simulation to be 0.585V, with a prediction error of only 0.5%. Compared to the initial design's 0.524V, the optimized SRAM circuit's static noise margin (SNM) is significantly improved by 11.6%, effectively overcoming the reliability risks caused by charge sharing. Furthermore, while improving data stability, the circuit maintains the same read / write speed and further reduces overall power consumption.

[0014] 3. Overcoming the limitation of local extrema: By introducing quantum state vectors with probability amplitude characteristics and quantum logic gate update mechanisms, the diversity of the population and the search space are expanded, effectively overcoming the inherent disadvantage of traditional genetic algorithms that are prone to getting trapped in local optima, and ensuring that the global optimal solution is accurately locked in a huge number of parameter combinations. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the system workflow of the present invention; Figure 2 This is a schematic diagram of the workflow of the QGA-ANN joint optimization system; Figure 3 A scatter plot comparing the actual and predicted values ​​for the test set; Figure 4 The training error convergence curve is shown. Figure 5 A histogram of the prediction error distribution for the test set; Figure 6 A comparison chart of trajectory tracking for the test set samples; Figure 7 This is the convergence curve of the globally optimal individual. Figure 8For the convergence stability analysis curve; Figure 9 A graph showing changes in population diversity; Figure 10 To simulate and verify the butterfly curve. Detailed Implementation

[0016] This embodiment provides an automated design and parameter optimization system for SRAM circuits in an in-memory computing architecture. SRAM circuits are primarily used in power- and area-sensitive devices such as edge AI and the Internet of Things (IoT), aiming to embed processing power within the memory array. The SRAM circuit selected in this embodiment mainly consists of a standard 6T-SRAM storage structure and additional computing and transmission components.

[0017] 6T-SRAM bit cell (memory structure): This part consists of six MOS transistors used to hold single-bit data representing the synaptic weights (W) of the neural network. Specifically, it includes a first inverter consisting of a first pull-up PMOS transistor (P1) and a first pull-down NMOS transistor (N1), and a second inverter consisting of a second pull-up PMOS transistor (P2) and a second pull-down NMOS transistor (N2). These two inverters are cross-coupled to form a bistable loop, which can stably lock the voltage level of the data nodes (Q and QB). In addition, this cell also includes a first access NMOS transistor (N3) and a second access NMOS transistor (N4), which are often referred to as pass-gate transistors. Their gates are connected to the word line (WL), and their sources / drains are connected to complementary bit lines (BLB and BL), respectively, for differential data read and write operations in normal mode.

[0018] Computational Transfer Component (In-situ Multiplication Structure): To achieve "in-situ multiplication" of synaptic weights and input feature signals within the memory array, an additional CMOS transfer gate switch (SW1), controlled by an external input signal (Xin), is introduced at the internal memory node (Q) of the 6T-SRAM. The other end of this transfer gate switch is directly connected to the local shared capacitor and the shared computation line. During in-memory computation, the weights (W) stored within the 6T cell and the input signal (Xin) accumulate charge on the shared line through this switch, thus physically realizing a one-bit multiplication operation. .

[0019] Stability Challenges and Size Constraints: During in-memory computation, when the transmission gate switch (SW1) is turned on due to the input signal, the internal memory node (Q) experiences charge sharing with the shared capacitor. This charge injection can easily disturb or even flip the initial voltage of the memory node, severely reducing the circuit's static noise margin (SNM) and becoming a core bottleneck limiting the reliability of this type of CIM circuit. Therefore, the channel dimensions of the pull-up transistors (PU: P1, P2), pull-down transistors (ND: N1, N2), and access transistors (NT: N3, N4) in the circuit must be precisely designed to maximize SNM.

[0020] The workflow of the automated design and parameter optimization system for SRAM circuits in this embodiment includes the following steps: Step 1: Data Acquisition and Input Stage (Input) The system first receives the SRAM circuit design parameters to be optimized (such as transistor width-to-length ratio W / L, etc.) and uses the normalized data as the initial input source.

[0021] Step 2: Simulation and Model Training Phase The system calls circuit simulation tools such as Cadence / SPICE to perform parameter scanning on the initial input source and obtain a dataset characterizing circuit performance (such as static noise margin, SNM, etc.).

[0022] The generated dataset is then used to train the artificial neural network (BP), enabling the BP to learn and fit the nonlinear mapping relationship between parameters and circuit performance.

[0023] Step 3: Joint Modeling and Rapid Optimization Solution The converged neural network is used as a high-precision surrogate model (Model ANN) to completely replace the time-consuming SPICE simulator. This model is combined with the quantum genetic algorithm (QGA) optimization engine to obtain the QGA-ANN joint optimization system. The prediction results are used as the fitness evaluation basis to perform high-speed global extremum optimization in a huge parameter space to obtain candidate optimal design parameters.

[0024] The core algorithm of the BP neural network in step three mainly consists of two feedback loop processes: "forward propagation" of information and "backward propagation" of error. During the training phase, the input feature signal enters the network, is processed by the hidden layer neurons, and generates a network prediction output. Subsequently, the system calculates the error between this prediction output and the actual expected value, and propagates this error signal backward along the original path, iteratively adjusting and correcting the synaptic weights and biases between each neuron node. This iterative training process allows the neural network to continuously discover and learn the extremely complex implicit nonlinear mapping rules between design parameters and performance indicators (the rules are embedded in the weight matrix of the Neural Network).

[0025] This embodiment constructs a highly customized SRAM neural network surrogate model topology. The specific modeling process is as follows: 1. Determination of Input and Output Variables: Since the 6T-SRAM cell based on TSMC's 40nm process has a completely symmetrical structure in terms of physical layout and circuitry, with identical transistor sizes on both sides, the system performs variable dimensionality reduction. In the input layer, the system extracts only the size of pull-up transistor P1, the size of pull-down transistor N1, and the size of access transistor N3 as three independent input neuron variables. The output layer of the network is set as the only target performance metric to be optimized—static noise margin (SNM).

[0026] 2. Network Topology Construction: Based on the above input-output relationship, this embodiment adopts a feedforward "3-15-1" fully connected topology, which includes 3 input layer neurons, 15 neurons distributed in the hidden layers, and 1 output layer neuron. The hidden layers are connected by weight matrices (such as W1...WN) and bias vectors (such as B1...BN).

[0027] 3. Automated Dataset Acquisition and Partitioning: Before training the BP model, the system utilizes Cadence Ocean scripts for automated control, performing a wide-range parameter scan of the channel dimensions of the three key transistors P1, N1, and N3 at uniform step sizes, and calling the SPICE simulator to accurately calculate the true SNM value corresponding to each size combination. Through this process, the system quickly acquired 3150 sets of "size-SNM" data feature vectors. This large dataset was then randomly divided into two parts: 90% (2835 sets of data) was used as the training set to input into the BP neural network for supervised learning, while the remaining 10% (315 sets of data) was reserved as the test set to verify the model's generalization ability.

[0028] The workflow of the QGA-ANN joint optimization system in step three is as follows: 1. Loading neural network model & initialization: After the system starts (STAR), the high-precision BP neural network surrogate model trained in Example 2 is loaded, the control parameters of the QGA algorithm are initialized (such as setting the population size to 50 and the maximum number of generations max_gen to 500 generations), and the initial quantum state chromosome population is randomly generated.

[0029] 2. Entering the main loop (QGA): The system begins to execute the iterative main loop from generation 1 to the maximum number of generations (gen=1 to max_gen).

[0030] The main loop includes the following steps: S1. Quantum Measurement and Constraints First, the quantum chromosome in the superposition state is decoded (measured) into definite physical size parameters (i.e., the width of the pull-up transistor, access transistor, and pull-down transistor), and then physical constraint filtering is performed to eliminate invalid solutions that do not meet the circuit read and write constraints, thus obtaining the filtered effective parameter combinations.

[0031] S2. Calculate fitness SNM value When the effective parameter combination is input into the BP neural network, the neural network instantly outputs the corresponding predicted SNM value, which is then used as the "fitness" of the current individual.

[0032] S3. Elite retention and record. To ensure the monotonically increasing nature of population evolution, an elite retention mechanism is introduced. The optimal individual with the highest fitness in the current generation is recorded in real time, and this optimal individual replaces the individual with the lowest fitness in the next generation, so as to ensure that the global optimal solution is not destroyed or lost during iteration.

[0033] S4. Convergence detection and dynamic termination The system monitors the fitness variance of the population in real time. If the variance is lower than the preset convergence threshold, or if the maximum number of iterations is reached (Yes), it indicates that the population has converged near the global optimum. At this point, the system triggers an early termination mechanism, ends the loop (END), and outputs the final optimal parameters. If the convergence condition is not met (No), S5 is executed.

[0034] S5. Genetic manipulation and quantum gate update The system performs genetic manipulation on the population, specifically by sequentially performing single-point crossing and adaptive mutation on individuals in the population, in order to further enhance the desirable traits of the population.

[0035] Subsequently, the current population is phase-adjusted through quantum rotation gate update to generate a new generation of population with better potential as the initial population for the next round of main cycle.

[0036] The quantum rotation gate update method is as follows: First, quantum bit encoding is performed. Unlike the binary state determined by the classical genetic algorithm, the population is encoded using the probability amplitude of the quantum bits, so that each quantum bit... Simultaneously in status and The superposition of states, the qubit encoding satisfies the following formula: ; .

[0037] This encoding method allows a single chromosome to simultaneously express the superposition of multiple parameter combinations, greatly enriching the diversity of the population and multiplying the algorithm's search space for the optimal solution.

[0038] Then, the phase probability amplitude of each qubit is adjusted using a quantum rotation gate U(θ) to realize the evolution and update of the individual state of the population, guiding the population to evolve towards the optimal solution with extremely high efficiency.

[0039] The quantum rotation gate U(θ) and the rotation angle θ satisfy the following formula: Rotation matrix definition: ; Matrix transformations: ; ; Modulus conservation: .

[0040] Step 4: Evaluation & Output Phase After obtaining the candidate optimal design parameters, these parameters are substituted into simulators such as Cadence for final evaluation. Once the evaluation is successful, the system outputs the globally optimal design parameters (W / L), thus completing the closed loop of automated design and parameter optimization for SRAM circuits.

[0041] This embodiment performs a comprehensive multi-dimensional verification of the model training process and the prediction results on the test set. The specific technical verification details are as follows: Figure 3 The scatter plot comparing the real and predicted values ​​on the test set (Test set: real value VS predictor value) uses 10% (315 sets) of the test set samples as input into the trained model. The x-axis represents the real SNM value simulated by Cadence / SPICE, and the y-axis represents the predicted SNM value of the neural network. All the green data points in the plot are extremely closely distributed along the ideal fitting baseline, visually demonstrating the model's excellent generalization and predictive ability for new parameter combinations not used in training.

[0042] Figure 4The training error curve records the trend of the mean squared error (MSE) of the BP neural network during training with the number of iterations. The graph clearly shows that, thanks to a reasonable network layer configuration and sufficient training samples (90% of the 3150 data sets), the model's training error drops sharply within a very small number of iterations (approximately a few dozen steps), quickly approaching the baseline of zero. System test data shows that the entire high-precision training process takes only 1.51 seconds on a conventional computing platform, completely breaking through the parameter scanning time bottleneck of traditional SPICE tools, which requires hours or even days.

[0043] Figure 5 The histogram of the prediction error distribution on the test set statistically analyzed the frequency distribution of the prediction errors for 315 test samples. The results show that the prediction errors strictly follow a normal distribution centered at zero (bell curve characteristic), and the vast majority of errors are extremely compressed within the very small interval of [-0.02, +0.02], indicating that the model has no systematic bias.

[0044] Figure 6 The test set sample trajectory tracking comparison chart randomly selected dozens of test samples and compared the actual SNM value (blue solid dot line) with the network's predicted SNM value (red cross line) in the form of a line graph. The two curves achieved almost perfect overlap at various peaks, troughs, and points of sharp fluctuation, validating the comparison.

[0045] Combination Figure 3-6 The intuitive verification shows that the SRAM neural network surrogate model constructed in this invention achieves extremely high quantitative evaluation indicators on the test set: its prediction mean square error (MSE) is as low as 0.00006, the mean absolute error (MAE) is only 0.00681, and the coefficient of determination (R2, the core indicator of goodness of fit) is as high as 0.99331. This is sufficient to prove that the BP neural network surrogate model can complete the SRAM parameter fitness evaluation with an absolute advantage of almost zero latency while ensuring close to 100% physical simulation accuracy. This provides a solid and reliable data-driven foundation for the high-speed global optimization of the subsequent quantum genetic algorithm (QGA).

[0046] Figure 7The global optimal individual convergence curve records the growth trajectory of the fitness (i.e., the predicted SNM value) of the optimal individual in the population with the number of generations. The curve shows that the system achieves a very rapid leap in the early stages of optimization, and reaches a stable convergence state within the first 100 generations (the optimal solution is marked in red around generations 30-40 in the curve). The predicted maximum static noise margin (SNM) corresponding to the globally optimal individual finally locked by the system is as high as 0.588V.

[0047] Figure 8 The convergence stability analysis curve visually presents the change in the standard deviation of fitness. In the early stages of the algorithm, due to the large search space provided by the qubit encoding, the fitness standard deviation shows a significant peak, indicating that the algorithm is conducting a broad global exploration. Subsequently, this standard deviation rapidly and precipitously decreases, approaching zero. This characteristic precisely triggers the built-in variance convergence detection mechanism in the system, thereby achieving dynamic early termination and greatly saving unnecessary computation time.

[0048] Figure 9 The population diversity change curve introduces a superposition of quantum state vectors (probability amplitudes) for chromosome encoding. This curve shows that population diversity exhibits dramatic fluctuations and high activity in the initial stages, successfully overcoming the fatal flaw of traditional genetic algorithms that are prone to premature convergence and getting trapped in local optima in the early stages. With continuous directional updates and iterations of the quantum rotation gate, population diversity eventually stabilizes and converges to a constant value, indicating that all individuals have moved towards the global optimum.

[0049] Figure 10The simulation verification butterfly curve is the final closed-loop verification step of this automated design system. The system automatically rounds the optimized theoretical transistor width parameters (PU=149.578nm, NT=181.510nm, ND=219.628nm) to physical dimensions (PU=150nm, NT=180nm, ND=220nm) conforming to TSMC's 40nm foundry design rules, and then substitutes them into Cadence Virtuoso for low-level simulation verification. As shown in the butterfly curve, the measured SNM value of the side length of the inscribed MAX-Square is 0.585V. Conclusion and data analysis: The error between this measured physical value and the optimal value predicted by the BP neural network (0.588V) is only an extremely small 0.5%.

[0050] Table 1 The results of comparing this embodiment with traditional purely empirical designs (whose SNM is typically only 0.524V) are shown in Table 1. The SRAM circuit optimized by this system has a significantly improved static noise margin of 11.6%. Furthermore, due to the strict aspect ratio constraints, this optimization not only improves the charge sharing disturbance rejection capability but also fully guarantees the circuit's read and write functions, and further reduces power consumption.

[0051] In summary, this invention presents a highly stable in-memory computing SRAM circuit and optimization system based on quantum genetic algorithms and neural networks. It perfectly replaces traditional SPICE physical simulation with an extremely low-latency BP surrogate model and completely solves the bottlenecks of local extrema and slow convergence thanks to the quantum genetic algorithm with its elite retention mechanism. This system transforms the time-consuming "trial and error" design of analog integrated circuits into a highly efficient and accurate "one-click" automated optimization design, effectively improving the efficiency and stability of in-memory computing macrocell reliability design.

Claims

1. An automated design and parameter optimization system for SRAM circuits in an in-memory computing architecture, characterized in that, The system's workflow includes the following steps: Step 1: Data Acquisition and Input The system collects the SRAM circuit design parameters to be optimized and performs normalization processing. Step 2: Simulation and Model Training The normalized parameters are simulated and scanned using circuit simulation tools to obtain a dataset characterizing the circuit performance. The dataset is then input into the artificial neural network to train it, enabling the network to learn and fit the nonlinear mapping relationship between parameters and circuit performance.

2. Step 3: Joint Modeling and Rapid Optimization The converged artificial neural network is used as a surrogate model and combined with the quantum genetic algorithm optimization engine to obtain the QGA-ANN joint optimization system, which obtains the candidate optimal design parameters through global extremum optimization. Step 4: Verification, Evaluation, and Result Output The candidate optimal design parameters are substituted into the simulator for evaluation and verification, and the verified parameters are output as the globally optimal design parameters, thereby completing the automated design and parameter optimization of the SRAM circuit.

3. The automated design and parameter optimization system for SRAM circuits in an in-memory computing architecture according to claim 1, characterized in that: The workflow of the QGA-ANN joint optimization system is as follows: first, the model is loaded; then, the control parameters of the QGA algorithm are initialized; and an initial quantum state chromosome population is randomly generated. Then, the system enters the main loop for iterative iteration. The main loop includes the following steps: S1, Quantum Measurement and Constraint Check First, the initial quantum chromosome population is decoded into physical size parameters, and then physical constraint filtering is performed to eliminate invalid solutions that do not meet the circuit read / write constraints, thus obtaining the filtered effective parameter combinations. S2, Calculate fitness The effective parameter combination is input into the BP neural network, and the corresponding predicted SNM value is output as the fitness of the current individual. S3, Elite Retention and Recording The system records the best individual with the highest fitness in the current generation population in real time, and replaces the worst individual with the best fitness in the next generation population with the best individual. S4. Convergence Detection and Dynamic Termination The system calculates the fitness variance of the population in real time. When the fitness variance is lower than the preset convergence threshold or the preset maximum number of iterations has been reached, the main loop stops and outputs the optimal parameters. When the fitness variance is higher than the preset convergence threshold and the preset maximum number of iterations has not been reached, S5 is executed. S5, Genetic Operations and Quantum Gate Updates The system performs genetic operations on the population, then updates the current population with phase through a quantum rotation gate, and uses the generated new population as the initial population for the next round of the main cycle.

4. The automated design and parameter optimization system for SRAM circuits in an in-memory computing architecture according to claim 2, characterized in that: In step S5, the genetic operation includes sequentially performing single-point crossover and adaptive mutation on individuals in the population.

5. The automated design and parameter optimization system for SRAM circuits in an in-memory computing architecture according to claim 2, characterized in that: In step S5, the quantum rotation gate update method is as follows: First, qubit encoding is performed, and the population is encoded using the probability amplitude of the qubits, so that each qubit... Simultaneously in status and The superposition of states, the qubit encoding satisfies the following formula: ； ； Then, the phase probability amplitude of each qubit is adjusted using a quantum rotation gate U(θ) to achieve the evolution and update of the individual states of the population. The quantum rotation gate U(θ) and the rotation angle θ satisfy the following formula: Definition of rotation matrix: ； Matrix transformations: ； ； Modulus conservation: 。

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