Clock control topology automatic generation method and device for soc architecture

Abstract

The application provides a clock control topology graph automatic generation method and device of an SoC architecture, effectively solving the problem that existing system configuration tables of an SoC cannot be converted into a structured system architecture topology graph to meet the requirements of efficient and reliable automatic design. A system configuration table of a clock control system of an SoC architecture is obtained, and the system configuration table is processed in multiple dimensions according to the combination of peripheral main bodies and clock types to obtain a target attribute set with a hierarchical relationship. The target attribute set is subjected to dynamic resource conflict merging and bit width calculation, respectively, to obtain a corresponding multi-path selector and the minimum control signal bit width thereof. According to the feature fingerprints in the target attribute set, two-dimensional optimization matching is performed in a preset component template library to obtain an optimal basic port architecture template. The minimum control signal bit width, the optimal basic port architecture template, and multiple graph element instantiation parameters are instantiated and bound to obtain a target topology graph file.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and more specifically, to a method and apparatus for automatically generating clock control topology diagrams for SoC architecture. Background Technology

[0002] In modern SoC chip design flow, core hardware resources such as timing control and clock management are typically first organized into system configuration tables. These tables detail key information such as control register configurations, peripheral connections, clock types, bit widths, and functional constraints. To support subsequent design phases such as physical synthesis, static timing analysis, and functional verification, this table information needs to be further transformed into a structured system architecture topology diagram. This diagram then serves as input for RTL code auto-generation tools, forming an automated design toolchain from configuration table to hardware implementation.

[0003] Currently, the mainstream implementation methods mainly fall into two categories: The first is a purely manual approach, where designers manually draw modules, connections, and attributes one by one according to the configuration table. This method is inefficient, prone to problems such as missing connections, incorrect names, and mismatched bit widths, and requires a complete rework when design changes occur, severely impacting project progress. The second is a semi-automated approach based on script templates, which uses scripts such as Python to extract simple data from the configuration table and uses macro templates to replace placeholders and generate the topology structure. However, this method can only achieve static data filling and cannot adaptively handle complex scenarios such as multi-clock source drivers and irregular node logic alignment, still requiring significant manual intervention for verification. Furthermore, existing solutions lack automatic calculation of register bit widths, intelligent merging of multi-source clock conflicts, and automatic adaptation capabilities to DFT test constraints, making it difficult to guarantee consistency between the configuration table, topology diagram, and hardware code. Version synchronization issues are prominent, posing a significant risk of human error and failing to meet the requirements of rapid iteration and high reliability design for large-scale SoC architectures. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method and apparatus for automatically generating clock control topology diagrams of SoC architecture, which effectively solves the problem that existing SoC system configuration tables are difficult to convert into structured system architecture topology diagrams to meet the requirements of efficient and reliable automated design.

[0005] In a first aspect, embodiments of this application provide a method for automatically generating clock control topology diagrams for a SoC architecture, the method comprising: The system configuration table of the clock control system of the SoC architecture is obtained. Based on the combination identifier of the peripheral body and the clock type, the system configuration table is processed in multiple dimensions to obtain a set of target attributes with hierarchical relationship. The combination of target attributes includes a variety of primitive instantiation parameters. Dynamic resource conflict merging and bit width calculation are performed on the multi-source clock networks in the target attribute set to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. Based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, a two-dimensional optimization matching is performed in the preset component template library based on the feature fingerprint to obtain the optimal basic port architecture template. The minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters are instantiated and bound. After binding, they are injected into the specific coordinate anchor point of the optimal basic port architecture template to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

[0006] In conjunction with the first aspect, this application provides a first possible implementation of the first aspect, wherein performing a two-dimensional optimization matching based on the feature fingerprint in a pre-set component template library to obtain an optimal basic port architecture template includes: Extract the combined feature sequence obtained by combining the topology channel size and test constraint features from the target attribute set; The multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template.

[0007] In conjunction with the first aspect, this application provides a second possible implementation of the first aspect, wherein multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template, including: Determine whether the combined feature sequence matches a completely matching basic port architecture template in the preset component template library; If not, the priority of the topology channel size and test constraint features is dynamically adjusted to obtain the optimal basic port architecture template.

[0008] In conjunction with the first aspect, this application provides a third possible implementation of the first aspect, wherein dynamic resource conflict merging and bit width calculation are performed on the multi-source clock networks in the target attribute set to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width, including: Traverse each peripheral entity in the target attribute set and identify clock sources that belong to the same peripheral entity but have different clock types; A multi-source clock network is constructed based on the clock source, and a corresponding multiplexer is automatically created. The minimum control signal bit width of the multiplexer is calculated.

[0009] In conjunction with the first aspect, this application provides a fourth possible implementation of the first aspect, wherein calculating the minimum control signal bit width of the multiplexer includes: The number of valid input channels of the multiplexer is obtained by logarithmic processing of the number of multiple clock sources under the same peripheral device body. Based on the number of valid input channels and the rounding up mechanism, the minimum control signal bit width of the multiplexer is calculated.

[0010] In conjunction with the first aspect, this application provides a fifth possible implementation of the first aspect, wherein the system configuration table is processed in multiple dimensions based on a combination identifier of the peripheral device entity and the clock type to obtain a set of target attributes with hierarchical relationships, including: Based on the combined identifier, the system configuration table is traversed, and all configuration items belonging to the same combined identifier are grouped and merged to form a primary hierarchical tree structure. The number of all clock source entities under the primary hierarchical tree structure is counted to dynamically calculate the control signal bit width required by the multiplexer based on the count.

[0011] In conjunction with the first aspect, this application provides a sixth possible implementation of the first aspect, wherein traversing the system configuration table based on the combined identifier includes: During the traversal, it is checked whether there are any configuration items in the system configuration table that do not have a visible peripheral declaration or clock type; If so, the valid peripheral name or valid clock type obtained from the most recent successful resolution will be automatically inherited and reused.

[0012] Secondly, embodiments of this application provide an automated generation device for clock control topology graphs of a SoC architecture, the device comprising: The acquisition module is used to acquire the system configuration table of the clock control system of the SoC architecture, and to perform multi-dimensional processing on the system configuration table based on the combination identifier of the peripheral subject and the clock type to obtain a set of target attributes with hierarchical relationship; the combination of target attributes includes various primitive instantiation parameters; The merging module is used to perform dynamic resource conflict merging and bit width calculation on the multi-source clock networks in the target attribute set, respectively, to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. The module is used to perform a two-dimensional optimization matching in a pre-set component template library based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, to obtain the optimal basic port architecture template. The binding module is used to instantiate and bind the minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters. After binding, it is injected into the specific coordinate anchor point of the optimal basic port architecture template to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

[0013] Thirdly, embodiments of this application provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the clock control topology graph automatic generation method of any of the SoC architectures described in this application are performed.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the clock-controlled topology graph automatic generation method for any of the SoC architectures described in the present application.

[0015] The method for automatically generating clock control topology diagrams for SoC architecture provided in this application not only solves the technical difficulties of severe disconnect between traditional manual drawing and underlying logic data, as well as poor iteration consistency, but also addresses the risks of channel control bit width mismatch and signal truncation caused by manual input of large-scale arrays. It achieves fully automated generation from system configuration table to architecture topology diagram, significantly improving design efficiency and reducing the workload of manual drawing and verification by hundreds of times. It also effectively avoids errors such as missing connections, name confusion, and bit width truncation caused by manual operation, significantly improving the accuracy and reliability of the topology structure. Simultaneously, it achieves single data source synchronization, allowing for one-click reconstruction of the architecture diagram after configuration changes, ensuring data consistency across design stages and reducing version conflicts. This application can also automatically adapt to multiple clock sources and DFT test constraints, automatically handle floating ports, and comprehensively improve the automation level and design quality of SoC architecture design. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This paper illustrates a flowchart of an automated method for generating clock control topology diagrams for a SoC architecture, as provided in an embodiment of this application. Figure 2 This paper illustrates a flowchart of an automated method for generating clock control topology diagrams for another SoC architecture provided in an embodiment of this application. Figure 3 A schematic diagram illustrating the process of obtaining the optimal basic port architecture template provided in an embodiment of this application is shown; Figure 4 This paper shows a structural block diagram of a clock control topology graph automatic generation device for a SoC architecture provided in an embodiment of this application; Figure 5 A structural block diagram of the electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0021] In SoC design, configuration tables need to be converted into architecture topology diagrams to support subsequent synthesis, verification, and RTL generation. Existing methods mostly involve manual drawing or simple script replacement, which is inefficient, error-prone, unable to automatically adapt to multiple clock sources and register bit widths, has poor consistency, and requires a lot of manual intervention, making it difficult to meet the requirements of efficient and reliable automated design.

[0022] Based on this, embodiments of this application provide a method and apparatus for automatically generating clock control topology diagrams for SoC architectures, which are described below through embodiments.

[0023] Example 1 To facilitate understanding of this embodiment, a method for automatically generating clock control topology diagrams for a SOC architecture disclosed in this application will first be described in detail. For example... Figure 1 The diagram shows a flowchart of an automated method for generating clock control topology graphs for a SoC architecture. Figure 2 The flowchart illustrates another method for automatically generating clock control topology diagrams for a SoC architecture. This application provides a method for automatically generating clock control topology diagrams for a SoC architecture, the method comprising: S101. Obtain the system configuration table of the clock control system of the SoC architecture, and perform multi-dimensional processing on the system configuration table based on the combination identifier of peripheral main body and clock type to obtain a target attribute set with hierarchical relationship; the target attribute combination includes various primitive instantiation parameters; S102. Perform dynamic resource conflict merging and bit width calculation on the multi-source clock networks in the target attribute set respectively to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. S103. Based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, perform a two-dimensional optimization matching in the preset component template library based on the feature fingerprint to obtain the optimal basic port architecture template. S104. Instantiate and bind the minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters, and inject them into the specific coordinate anchor point of the optimal basic port architecture template after binding to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

[0024] In step S101, this application pre-sets a parsing engine for the SoC architecture. The parsing engine first obtains the system configuration table of the clock control system of the SoC architecture, which includes control register information, peripheral connection relationships, clock type, and functional constraints. The system configuration table can be in Excel format. The system configuration table is also automatically extracted. Specifically, the required information units (including peripheral identifiers, clock types, and connection sources, etc.) are extracted by indexing specific fields, and invalid characters and redundant whitespace at the edges of these information units are automatically removed to achieve the effect of format noise reduction, thereby achieving high-fidelity data point separation and standardized extraction. After automated extraction and processing, the core classification criteria are based on the combination of peripheral device entity and clock type, such as device characteristics like multiplexers (MUX) and switches (SWITCH). Functional attributes can also be used as core classification criteria to perform multi-dimensional processing on the system configuration table. This multi-dimensional processing includes parsing, classifying, and aggregating discrete data items in the system configuration table layer by layer through a parsing engine. Classification and aggregation involve merging information such as clock sources, control signals, and register configurations that belong to the same peripheral device entity and are of the same clock type to form a hierarchical data structure with nested relationships. At the same time, key parameters for primitive instantiation, such as module instance name, register bit width, port connection relationship, and test constraint features, are extracted. Finally, a target attribute set containing multiple primitive instantiation parameters and having hierarchical relationships is obtained.

[0025] This application also reduces the attributes based on specific functional areas. For example, it collects discrete control sources under the same peripheral body into functional tree branches, separates and extracts the core driver source network connection set, configures the control center register name table entries, and identifies whether they have specific test constraint features, such as DFT test insertion threshold constraints, and integrates the test constraint features into the target attribute combination. In a specific implementation of step S101, one embodiment involves: processing the system configuration table in multiple dimensions based on the combined identifier of the peripheral device and the clock type to obtain a set of target attributes with hierarchical relationships, including: S1011. Based on the combined identifier, traverse the system configuration table and merge all configuration items belonging to the same combined identifier to form a primary hierarchical tree structure. S1012. Count the number of all clock source entities under the primary hierarchical tree structure, and dynamically calculate the control signal bit width required by the multiplexer based on the number.

[0026] In steps S1011-S1012, the combination identifier obtained by combining the peripheral entity and clock type is parsed by the parsing engine through the system configuration table. All configuration items belonging to the same combination identifier are merged to form a primary hierarchical tree structure with the combination identifier as the node. Each level of the tree contains all clock source entities, control signals, and related configuration information for the corresponding peripheral. After merging, all clock source entities contained in this primary hierarchical tree structure are counted. The total number of clock channels required by the multiplexer corresponding to the peripheral entity is obtained by using the relationship that the number of clock source entities equals the number of effective input channels of the multiplexer. Based on the total number of clock channels, the required control signal bit width of the multiplexer, i.e., the control register bit width, is dynamically calculated, thereby achieving adaptive configuration of the register bit width and providing accurate parameter basis for subsequent topology instantiation.

[0027] In a specific implementation of step S1011, one embodiment is as follows: based on the combined identifier, traverse the system configuration table, including: S10111. During the traversal, check whether there are configuration items in the system configuration table that do not have a displayed peripheral declaration or clock type; S10112. If so, the valid peripheral name or valid clock type obtained from the most recent successful resolution will be automatically inherited and reused.

[0028] In steps S10111-S10112, during the traversal of the combined identifier obtained based on the combination of peripheral subject and clock type, the mechanism for identifying the same peripheral subject relies on the context state awareness of the system configuration table to achieve traversal. The system configuration table is checked in real time to see if there are configuration items without explicit peripheral declarations or clock types. If there are no explicit peripheral declarations, the relevant fields are left blank. If so, there are configuration items without explicit peripheral declarations or clock types. The system configuration table will automatically inherit and use the most recently successfully parsed valid peripheral name or valid clock type for the configuration items without explicit peripheral declarations or clock types. This ensures that all configuration items in the system configuration table have corresponding peripheral declarations or clock types, thereby automatically grouping consecutive configuration items without explicit peripheral declarations into the same peripheral subject.

[0029] In step S102, based on the obtained target attribute set, this application determines the peripheral entity and the number of clock sources under the same peripheral entity. At this time, it is necessary to manage the multiple heterogeneous clock sources under the same peripheral entity through hardware structure and control lines. Therefore, it is necessary to perform dynamic resource conflict merging and bit width calculation on the multi-source clock network composed of multiple clock sources in the target attribute set to obtain the multiplexer and its minimum control signal bit width. Before performing dynamic resource conflict merging, it is necessary to identify which peripheral entities have multi-source clock network conflicts. When it is detected that the number of clock sources under a certain peripheral entity is greater than or equal to 2 and the clock sources are heterogeneous, it is determined that the peripheral entity has multi-source clock network conflicts, and dynamic resource conflict merging and minimum control signal bit width calculation are required. If the number of clock sources is 1, it is determined that there is no conflict, and the subsequent merging and minimum control signal bit width calculation steps are not required.

[0030] In a specific implementation of step S102, one embodiment involves: performing dynamic resource conflict merging and bit width calculation on the multi-source clock networks in the target attribute set to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width, including: S1021. Traverse each peripheral entity in the target attribute set and identify clock sources that belong to the same peripheral entity but have different clock types. S1022. Construct a multi-source clock network based on the clock source, automatically create the corresponding multiplexer, and calculate the minimum control signal bit width of the multiplexer.

[0031] In steps S1021-S1022, this application traverses each peripheral entity in the target attribute set, identifies clock sources belonging to the same peripheral entity but with different clock types, and counts the number of clock sources at this time. This number is the effective input channel number of the multiplexer. If the number is greater than or equal to 2, there is a resource conflict. At this time, a multi-source clock network is constructed based on clock sources of different clock types under the same peripheral entity, and a multiplexer corresponding to the multi-source clock network is automatically created. The clock sources of different clock types under the same peripheral entity are used as the input of the multiplexer, and the outputs of multiple multiplexers are uniformly connected to the clock input port of the peripheral, thereby completely and dynamically merging resource conflicts. The minimum control signal bit width of the multiplexer is calculated. Each multi-source clock network generates a corresponding adapted multiplexer, and the control signal bit width of the multiplexer is adaptively configured, which not only ensures the stable operation of the multi-source clock network, but also provides accurate parameter support for subsequent topology instantiation and RTL code generation.

[0032] In a specific implementation of step S1022, one embodiment involves calculating the minimum control signal bit width of the multiplexer, including: S10221. The number of valid input channels of the multiplexer is obtained by logarithmic processing based on the number of multiple clock sources under the same peripheral device body. S10222. Based on the number of effective input channels and the rounding up mechanism, calculate the minimum control signal bit width of the multiplexer.

[0033] In steps S10221-S10222, this application uses the number of multiple clock sources under the same peripheral device as the number of valid input channels of the multiplexer after logarithmic processing. Based on the number of valid input channels and the rounding up mechanism, the minimum control signal bit width of the multiplexer is calculated. Specifically, this application takes the logarithm of the number of valid input channels with base 2 and rounds it up. The resulting integer result is the minimum control signal bit width required to cover all input channels of the multiplexer and achieve addressing without omissions. The calculation is performed because the number of input channels of a multiplexer is usually a power of 2, such as 2, 4, 8, 16, etc. The control port of the multiplexer is temporarily left empty, waiting to be filled with the calculated minimum control signal bit width. Subsequently, the register flag of the multiplexer is automatically rewritten with this minimum control signal bit width to ensure the safety redundancy of signal control during downstream physical mapping. The automatically calculated, absolutely safe control signal bit width is forcibly and uniquely bound to the corresponding register code definition of the multiplexer, like a label. This completely eliminates the possibility of bit width mismatch or bit width truncation caused by manual writing at the source of hardware generation.

[0034] In step S103, after calculating the minimum control signal bit width, this application uses a feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer. This feature fingerprint ensures the uniqueness and specificity of the obtained feature fingerprint. The topology channel size, after merging processing of the current multi-source clock network, corresponds to the order of magnitude range of the effective input channels of the multiplexer, directly reflecting the channel carrying capacity of the current topology. The test constraint features are specifically the physical inspection test-related constraints identified in the target attribute set. Based on the feature fingerprint, this application performs a two-dimensional optimization matching in a pre-set component template library to obtain the optimal basic port architecture template. The pre-set component template library stores various basic port architecture templates of different specifications, covering connection matrix templates with different topology densities such as 2nd, 4th, and 8th order. Each template corresponds to a unique combination of topology channel size and test constraint features, adapting to the multi-source clock network requirements in different scenarios, thereby obtaining the optimal basic port architecture template suitable for the SoC architecture.

[0035] In the specific implementation of step S103, one embodiment is as follows: Figure 3 As shown, based on the feature fingerprint, a two-dimensional optimization matching is performed in the pre-set component template library to obtain the optimal basic port architecture template, including: S1031. Extract the combined feature sequence obtained by combining the topology channel size and test constraint features from the target attribute set; S1032. Multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template.

[0036] In steps S1031-S1032, this application extracts a combined feature sequence from the target attribute set, which is a combination of topology channel size (e.g., the order of magnitude of input nodes) and test constraint features (e.g., whether a specific test network or DFT verification rule is enabled). Based on the combined feature sequence, it performs one-by-one comparison and multi-path conditional routing matching in the preset component template library, thereby prioritizing the selection of templates that fully match both the topology channel size and the test constraint features. This allows for the deduction of whether the current functional node uses a connection matrix template with a topology density of 2nd, 4th, or up to 8th order, and determines whether to bypass and load the test structure branch. This achieves highly flexible and foolproof adaptation, thereby accurately locking the optimal basic port architecture template that meets the structural function and physical compliance restrictions.

[0037] In a specific implementation of step S1032, one embodiment is as follows: multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template, including: S10321. Determine whether the combined feature sequence matches a completely matching basic port architecture template in the preset component template library; S10322. If not, dynamically adjust the priority of the topology channel size and test constraint features to obtain the optimal basic port architecture template.

[0038] In steps S10321-S10322, after comparing the combined feature sequence one by one with the preset component template library and performing multi-path conditional route matching based on the combined feature sequence, this application determines whether the combined feature sequence matches a completely matching basic port architecture template in the preset component template library. If it exists, the optimal basic port architecture template is directly obtained. If it does not exist, the optimal adaptation template that is adapted to the topology channel size and meets the minimum compliance requirements for test constraint features is selected. That is, the test constraint features are downgraded from "enabled" to "disabled" or the topology channel size is pushed up to the next higher size range (e.g., from level 2 to level 4, or from level 4 to level 8), and the matching is re-executed to obtain the optimal basic port architecture template. If a match still cannot be obtained after the above strategy, the current peripheral device is marked as "template missing anomaly", and the generation process is interrupted to output an error log, prompting the user to supplement the preset template with the corresponding topology density.

[0039] In step S104, after obtaining the optimal basic port architecture template, this application uses the optimal basic port architecture template as the basic framework and, through a parsing permutation algorithm and targeted labeling overlay technology, locates specific coordinate anchor points within the template. These specific coordinate anchor points are pre-reserved "empty slots" or "slots" with unique identifiers in the optimal basic port architecture template. They are used for targeted injection and binding of minimum control signal bit width, various primitive instantiation parameters, and clock network relationships, ensuring that the topology rendering is error-free, attribute-free, and structurally integrated. These specific coordinate anchor points include specific geometric component type markers, coordinate anchor points, and attribute fields, including entity declaration tags, control signal port anchor points, interconnection network nodes, and control register attribute bits used to carry bit width information. This application uses the minimum control signal bit width as a key control parameter and automatically overwrites the control signal bit width attribute field of the corresponding multiplexer node in the optimal basic port architecture template, ensuring that the signal addressing capability in the subsequent physical mapping stage meets safety redundancy requirements. Simultaneously, various primitive instantiation parameters are injected according to their functional attributes: the module instance name is filled into the entity declaration tag, the clock source connection network string is filled into the interconnection network anchor point, the register identifier corresponding to the multiplexer is filled into the control port attribute layer, and the DFT test constraint features are filled into the specific test rule node of the optimal basic port architecture template. This completes the instantiation binding of the minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters. It also implements spatial coordinate point matrix staking mapping rendering to accurately adapt to anchor point connections and primitive attributes. After injection, the structure of the entire optimal basic port architecture template is checked for consistency to ensure that the connection relationships, bit width configurations, and attribute values ​​between primitives match each other without overlap, misalignment, or omissions. Through this process, this application successfully transforms the abstract topology of the optimal basic port architecture template into a specific topology description containing complete instance information, and finally generates a target topology graphic file to visually describe the spatiotemporal control system of the SoC architecture. The target topology graphic file is in XML format and includes core information such as peripheral main body, multiplexer topology, clock source network connection relationship, control register bit width configuration and DFT test constraints. It can be directly used for physical synthesis, static timing analysis, RTL generation and subsequent design verification processes, realizing the standardization, automation and consistency of architecture description files.

[0040] During injection, if an input port is identified as needing to be left floating due to insufficient input resources, it can be automatically padded with a physical low-level signal (such as logic pulled low to zero potential) based on safety rules and injected into its corresponding spatial anchor point. Finally, the underlying node attribute recoding sequence is synthesized and assembled into a fully compliant, visually lossless architecture description file. For automated handling of floating ports, in addition to the default forced injection of a fixed logic "0" level as a closed-loop protection mechanism, other dynamic processing methods are also supported: for example, forcibly padding with a high effective logic "1" level based on safety state presets; using fixed constant mapping methods such as explicit tie-cell interconnection; or introducing a topology-aware pruning strategy to allow the backend to perform open-circuit floating disconnection processing, simultaneously dynamically removing associated nodes.

[0041] Example 2 This application also provides an automated generation device for clock-controlled topology graphs of a SoC architecture, such as... Figure 4 The diagram shows a block diagram of an automated clock control topology graph generation device for a SoC architecture. The functions implemented by this device correspond to the steps of executing the automated clock control topology graph generation method for a SoC architecture on a terminal device described above. This device can be understood as a server component including a processor. The automated clock control topology graph generation device for a SoC architecture described in this application includes: The acquisition module 401 is used to acquire the system configuration table of the clock control system of the SoC architecture, and to perform multi-dimensional processing on the system configuration table based on the combination identifier of the peripheral body and the clock type to obtain a set of target attributes with hierarchical relationship; the combination of target attributes includes a variety of primitive instantiation parameters; The merging module 402 is used to perform dynamic resource conflict merging and bit width calculation on the multi-source clock networks in the target attribute set respectively, to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. The constitutive module 403 is used to perform a two-dimensional optimization matching in a preset component template library based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, to obtain the optimal basic port architecture template. The binding module 404 is used to instantiate and bind the minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters. After binding, it is injected into the specific coordinate anchor point of the optimal basic port architecture template to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

[0042] In one feasible implementation, the constitutive module includes: Extract the combined feature sequence obtained by combining the topology channel size and test constraint features from the target attribute set; The multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template.

[0043] In one feasible implementation, the constitutive module further includes: Determine whether the combined feature sequence matches a completely matching basic port architecture template in the preset component template library; If not, the priority of the topology channel size and test constraint features is dynamically adjusted to obtain the optimal basic port architecture template.

[0044] In one feasible implementation, the merging module includes: Traverse each peripheral entity in the target attribute set and identify clock sources that belong to the same peripheral entity but have different clock types; A multi-source clock network is constructed based on the clock source, and a corresponding multiplexer is automatically created. The minimum control signal bit width of the multiplexer is calculated.

[0045] In one feasible implementation, the merging module further includes: The number of valid input channels of the multiplexer is obtained by logarithmic processing of the number of multiple clock sources under the same peripheral device body. Based on the number of valid input channels and the rounding up mechanism, the minimum control signal bit width of the multiplexer is calculated.

[0046] In one feasible implementation, the acquisition module includes: Based on the combined identifier, the system configuration table is traversed, and all configuration items belonging to the same combined identifier are grouped and merged to form a primary hierarchical tree structure. The number of all clock source entities under the primary hierarchical tree structure is counted to dynamically calculate the control signal bit width required by the multiplexer based on the count.

[0047] In one feasible implementation, the acquisition module further includes: During the traversal, it is checked whether there are any configuration items in the system configuration table that do not have a visible peripheral declaration or clock type; If so, the valid peripheral name or valid clock type obtained from the most recent successful resolution will be automatically inherited and reused.

[0048] Example 3 This application also provides an electronic device, such as Figure 5As shown, it includes: a processor 501, a memory 502, and a bus 503. The memory 502 stores machine-readable instructions that can be executed by the processor 501. When the electronic device is running, the processor 501 and the memory 502 communicate through the bus 503. When the machine-readable instructions are executed by the processor 501, the steps of any of the methods for automatically generating clock control topology diagrams of a SOC architecture are performed.

[0049] Example 4 This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of any of the methods for automatically generating clock-controlled topology graphs for a SOC architecture.

[0050] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0051] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0052] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0053] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a platform server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0054] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for automatically generating clock control topology diagrams for a SoC architecture, characterized in that, The method includes: The system configuration table of the clock control system of the SoC architecture is obtained. Based on the combination identifier of the peripheral body and the clock type, the system configuration table is processed in multiple dimensions to obtain a set of target attributes with hierarchical relationship. The combination of target attributes includes a variety of primitive instantiation parameters. Dynamic resource conflict merging and bit width calculation are performed on the multi-source clock networks in the target attribute set to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. Based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, a two-dimensional optimization matching is performed in the preset component template library based on the feature fingerprint to obtain the optimal basic port architecture template. The minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters are instantiated and bound. After binding, they are injected into the specific coordinate anchor point of the optimal basic port architecture template to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

2. The method according to claim 1, characterized in that, Based on the aforementioned feature fingerprint, a two-dimensional optimization matching is performed in a pre-set component template library to obtain the optimal basic port architecture template, including: Extract the combined feature sequence obtained by combining the topology channel size and test constraint features from the target attribute set; The multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template.

3. The method according to claim 2, characterized in that, Multi-path conditional routing matches the combined feature sequence with the preset component template library to obtain the optimal basic port architecture template, including: Determine whether the combined feature sequence matches a completely matching basic port architecture template in the preset component template library; If not, the priority of the topology channel size and test constraint features is dynamically adjusted to obtain the optimal basic port architecture template.

4. The method according to claim 1, characterized in that, Dynamic resource conflict merging and bit width calculation are performed on the multi-source clock networks in the target attribute set to obtain the multiplexers corresponding to the multi-source clock networks and their minimum control signal bit widths, including: Traverse each peripheral entity in the target attribute set and identify clock sources that belong to the same peripheral entity but have different clock types; A multi-source clock network is constructed based on the clock source, and a corresponding multiplexer is automatically created. The minimum control signal bit width of the multiplexer is calculated.

5. The method according to claim 4, characterized in that, Calculating the minimum control signal bit width of the multiplexer includes: The number of valid input channels of the multiplexer is obtained by logarithmic processing of the number of multiple clock sources under the same peripheral device body. Based on the number of valid input channels and the rounding up mechanism, the minimum control signal bit width of the multiplexer is calculated.

6. The method according to claim 1, characterized in that, Based on the combined identifier of peripheral device and clock type, the system configuration table is processed in multiple dimensions to obtain a hierarchical set of target attributes, including: Based on the combined identifier, the system configuration table is traversed, and all configuration items belonging to the same combined identifier are grouped and merged to form a primary hierarchical tree structure. The number of all clock source entities under the primary hierarchical tree structure is counted to dynamically calculate the control signal bit width required by the multiplexer based on the count.

7. The method according to claim 6, characterized in that, Based on the combined identifier, the system configuration table is traversed, including: During the traversal, it is checked whether there are any configuration items in the system configuration table that do not have a visible peripheral declaration or clock type; If so, the valid peripheral name or valid clock type obtained from the most recent successful resolution will be automatically inherited and reused.

8. An automated topology graph generation device for a SoC architecture, characterized in that, The device includes: The acquisition module is used to acquire the system configuration table of the clock control system of the SoC architecture, and to perform multi-dimensional processing on the system configuration table based on the combination identifier of the peripheral subject and the clock type to obtain a set of target attributes with hierarchical relationship; the combination of target attributes includes various primitive instantiation parameters; The merging module is used to perform dynamic resource conflict merging and bit width calculation on the multi-source clock networks in the target attribute set, respectively, to obtain the multiplexer corresponding to the multi-source clock network and its minimum control signal bit width. The module is used to perform a two-dimensional optimization matching in a pre-set component template library based on the feature fingerprint formed by the test constraint features in the target attribute set and the topology channel size of the multiplexer, to obtain the optimal basic port architecture template. The binding module is used to instantiate and bind the minimum control signal bit width, the optimal basic port architecture template, and various primitive instantiation parameters. After binding, it is injected into the specific coordinate anchor point of the optimal basic port architecture template to obtain the target topology graphic file, so as to visualize the spatiotemporal control system of the SoC architecture.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of an automated clock control topology graph generation method for a SoC architecture as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the method for automatically generating clock-controlled topology graphs for a SoC architecture as described in any one of claims 1 to 7.

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