Scan driver, display device including the same, and electronic device

Abstract

A scan driver, a display device including the scan driver, and an electronic device are disclosed. The scan driver includes a reference scan signal generator configured to generate a plurality of reference scan signals, a first scan signal converter configured to output an N-type scan signal for controlling a conductive state of an N-type transistor based on some of the plurality of reference scan signals, and a second scan signal converter configured to output a P-type scan signal for controlling a conductive state of a P-type transistor based on some of the plurality of reference scan signals.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0177608, filed on December 3, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a scan driver, a display device including the scan driver, and an electronic device including the display device. Background Technology

[0003] Modern display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), consist of pixel arrays, with pixels serving as the basic units for image generation. Each pixel typically includes a thin-film transistor (TFT) that regulates the drive current in response to data voltage, thereby controlling the brightness or color output of the light-emitting element. This pixel structure enables high-resolution, high-efficiency visual output with a compact form factor, making it suitable for current flat panel display and flexible display technologies.

[0004] Display devices can employ sequential emission methods (where pixels emit light row by row in a defined order) or simultaneous emission methods (where all pixels emit light simultaneously after image data is sequentially written to each row). However, these display devices typically require a separate scan driver to generate the corresponding scan signals. This dual-driver approach increases layout area, complicates wiring, and results in significant clock and control signal overhead. Furthermore, separate signal paths can introduce timing mismatches and increase power consumption due to redundant switching actions. Summary of the Invention

[0005] The embodiments provide a scan driver, a display device including the scan driver, and an electronic device including the display device. The problems to be solved by this disclosure are not limited to those mentioned above, and other problems and advantages not mentioned in this disclosure will be understood through the following description and will become more apparent through the embodiments of this disclosure. Furthermore, it will be appreciated that the problems to be solved by this disclosure can be achieved by the technical means indicated in the claims and combinations thereof.

[0006] According to an embodiment, a scan driver includes: a reference scan signal generator configured to generate a plurality of reference scan signals; a first scan signal converter configured to output an N-type scan signal for controlling the conduction state of an N-type transistor based on some of the plurality of reference scan signals; and a second scan signal converter configured to output a P-type scan signal for controlling the conduction state of a P-type transistor based on some of the plurality of reference scan signals.

[0007] In an embodiment, the first scan signal converter may include at least one NAND gate.

[0008] In an embodiment, the Nth reference scan signal and the (N+1)th reference scan signal among the plurality of reference scan signals can be applied to the input terminal of one of the NAND gates in the at least one NAND gate, and the Nth N-type scan signal can be output to the output terminal of the NAND gate, where N is a natural number greater than 0.

[0009] In an embodiment, the second scan signal converter may include at least one NOR gate and at least one inverting gate connected to the at least one NOR gate.

[0010] In an embodiment, the Nth reference scan signal and the (N+1)th reference scan signal among the plurality of reference scan signals can be applied to the input terminal of one of the at least one NOR gates, the output terminal of the NOR gate can be connected to the input terminal of one of the at least one inverter gates, the Nth P-type scan signal can be output to the output terminal of the inverter gate, and N is a natural number greater than 0.

[0011] In an embodiment, each of the plurality of reference scan signals may include a pulse, and the pulses of each of the plurality of reference scan signals may have the same width.

[0012] In an embodiment, the pulse duration of the Nth reference scan signal and the pulse duration of the (N+1)th reference scan signal among the plurality of reference scan signals may partially overlap with each other to define the overlapping pulse duration, and N is a natural number greater than 0.

[0013] In an embodiment, the pulse width of an N-type scan signal can be determined based on the pulse width of each of a plurality of reference scan signals and the width corresponding to the duration of overlapping pulses.

[0014] In an embodiment, the pulse width of the P-type scan signal can be determined based on the width corresponding to the duration of the overlapping pulses.

[0015] According to an embodiment, a display device includes: a display unit including a plurality of pixels, each pixel being connected to a corresponding scan line among a plurality of scan lines; and a scan driver configured to apply a scan signal corresponding to each of the plurality of pixels through the plurality of scan lines, wherein the scan driver includes: a reference scan signal generator configured to generate a plurality of reference scan signals; a first scan signal converter configured to output an N-type scan signal for controlling the conduction state of an N-type transistor based on some of the plurality of reference scan signals; and a second scan signal converter configured to output a P-type scan signal for controlling the conduction state of a P-type transistor based on some of the plurality of reference scan signals.

[0016] In an embodiment, the first scan signal converter may include at least one NAND gate.

[0017] In an embodiment, the Nth reference scan signal and the (N+1)th reference scan signal among the plurality of reference scan signals can be applied to the input terminal of one of the NAND gates in the at least one NAND gate, and the Nth N-type scan signal can be output to the output terminal of the NAND gate, where N is a natural number greater than 0.

[0018] In an embodiment, the second scan signal converter may include at least one NOR gate and at least one inverting gate connected to the at least one NOR gate.

[0019] In an embodiment, the Nth reference scan signal and the (N+1)th reference scan signal among the plurality of reference scan signals can be applied to the input terminal of one of the at least one NOR gates, the output terminal of the NOR gate can be connected to the input terminal of one of the at least one inverter gates, the Nth P-type scan signal can be output to the output terminal of the inverter gate, and N is a natural number greater than 0.

[0020] In an embodiment, each of the plurality of reference scan signals may include a pulse, and the pulses of each of the plurality of reference scan signals may have the same width.

[0021] In an embodiment, the pulse duration of the Nth reference scan signal and the pulse duration of the (N+1)th reference scan signal among the plurality of reference scan signals may partially overlap with each other to define the overlapping pulse duration, and N is a natural number greater than 0.

[0022] In an embodiment, the pulse width of an N-type scan signal can be determined based on the pulse width of each of a plurality of reference scan signals and the width corresponding to the duration of overlapping pulses.

[0023] In an embodiment, the pulse width of the P-type scan signal can be determined based on the width corresponding to the duration of the overlapping pulses.

[0024] According to an embodiment, an electronic device is provided, comprising a display panel and a scan driver. The display panel includes a plurality of pixels, each pixel including an N-type transistor and a P-type transistor. The scan driver is configured to provide scan signals to the plurality of pixels. The scan driver includes: a reference scan signal generator configured to generate a plurality of reference scan signals; a first scan signal converter configured to output an N-type scan signal for controlling the conduction state of an N-type transistor based on the overlap of adjacent reference scan signals among the plurality of reference scan signals; and a second scan signal converter configured to output a P-type scan signal for controlling the conduction state of a P-type transistor based on the overlap of adjacent reference scan signals among the plurality of reference scan signals.

[0025] In an embodiment, the first scan signal converter is configured to determine the pulse width of the N-type scan signal based on the pulse width of each of the plurality of reference scan signals and the time overlap between the pulse duration of the Nth reference scan signal and the pulse duration of the (N+1)th reference scan signal, where N is a natural number greater than 0.

[0026] Other aspects, features, and advantages beyond those described above will become apparent from the following drawings, claims, and detailed description of this disclosure. Attached Figure Description

[0027] The above and other aspects and features of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 This is a block diagram of a display device according to an embodiment;

[0029] Figure 2 This is a schematic diagram of the circuitry of the pixel according to a comparative embodiment;

[0030] Figure 3 This is a diagram of a scan driver according to an embodiment;

[0031] Figure 4 This is a timing diagram for explaining the N-type scan signal according to an embodiment;

[0032] Figure 5 This is a diagram illustrating the structure of the first scanning signal converter according to an embodiment;

[0033] Figure 6 This is a timing diagram for explaining the P-type scan signal according to an embodiment;

[0034] Figure 7 This is a diagram illustrating the structure of the second scanning signal converter according to an embodiment;

[0035] Figure 8 This is a diagram of a reference scan signal generator according to an embodiment;

[0036] Figure 9 A diagram of a reference scan signal generator according to another embodiment; and

[0037] Figure 10 This is a diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0038] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing them, will be apparent from the embodiments and drawings described in detail below. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0039] In the following embodiments, the terms "first" and "second," etc., are not used in a limiting sense and are used to distinguish one element from another.

[0040] The singular form used in this article is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0041] In the following embodiments, it will be understood that terms such as “comprising” or “having” are intended to indicate the presence of each feature or component disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or components may be present or added.

[0042] It will be understood that when a unit, area, or element is said to be formed on another unit, area, or element, it can be formed directly or indirectly on that other unit, area, or element. That is, for example, there can be intermediate units, areas, or elements.

[0043] In the following embodiments, unless the context clearly indicates otherwise, terms such as “connection” or “coupled” do not necessarily mean a direct and / or fixed connection or coupling between two components, and do not exclude the possibility of another component being inserted between the two components.

[0044] The present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the disclosure are illustrated. The same reference numerals in the drawings indicate the same elements, and therefore, their description will not be repeated.

[0045] Various embodiments of the present invention relate to a scan driver for a display device that uses a shared architecture to efficiently generate scan signals for both PMOS and NMOS transistors, thereby reducing layout area, minimizing signal delay, and reducing the number of clock signals required. The scan driver includes a reference scan signal generator that generates multiple reference scan signals, a first scan signal converter that uses NAND gates to generate NMOS scan signals, and a second scan signal converter that uses NOR gates and inverters to generate PMOS scan signals, instead of using separate scan drivers for PMOS and NMOS, which would increase circuit complexity and footprint. Each scan signal can be derived from an overlapping pulse segment of adjacent reference scan signals, thereby providing unified timing control and enhanced integration for high-resolution or compact display applications.

[0046] Figure 1 This is a block diagram of a display device according to an embodiment.

[0047] refer to Figure 1 The display device according to the embodiment may include a display unit 10 comprising a plurality of pixels PX11 to PXnm, a scan driver 20 (e.g., a first driver circuit), a data driver 30 (e.g., a second driver circuit), an emission control driver 40 (e.g., a third driver circuit), a power supply unit 50 (e.g., a power supply), and a controller 60 (e.g., a controller circuit).

[0048] In this embodiment, each of the plurality of pixels PX11 to PXnm can be connected to at least one corresponding scan line among the plurality of scan lines S1 to Sn connected to the display unit 10, at least one corresponding emission control line among the plurality of emission control lines EM1 to EMn, and at least one corresponding data line among the plurality of data lines D1 to Dm. Here, n and m are natural numbers greater than 0.

[0049] In an embodiment, each of the plurality of pixels PX11 to PXnm can be connected to a power line connected to the display unit 10 to receive a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage Vint.

[0050] In an embodiment, the display unit 10 may include a plurality of pixels PX11 to PXnm arranged in a specific form (e.g., matrix form).

[0051] In an embodiment, each of the plurality of pixels PX11 to PXnm can emit light at a specific brightness based on the driving current supplied to its light-emitting element, wherein the driving current is controlled according to the corresponding data voltage transmitted through the plurality of data lines D1 to Dm.

[0052] The display unit 10 can be referred to as a display panel. The display panel can be implemented as one of the following: liquid crystal display (LCD), light-emitting diode display (LED), organic LED display (OLED), active matrix OLED (AMOLED), electrochromic display (ECD), digital mirror device (DMD), actuator mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD), and can also be implemented as other types of flat panel displays or flexible displays.

[0053] In this embodiment, the scan driver 20 can generate a scan signal corresponding to a specific pixel and transmit the scan signal through multiple scan lines S1 to Sn. For example, the scan driver 20 can transmit the scan signal to each of the multiple pixels included in each row through the corresponding scan lines. For example, the scan driver 20 can generate multiple scan signals by receiving a scan drive control signal SCS from the controller 60 and sequentially apply these scan signals to the multiple scan lines S1 to Sn row by row.

[0054] In an embodiment, the scan driver 20 can generate and apply at least one type of scan signal. As a specific example, the scan driver 20 may generate and supply the required scan signal (such as a first scan signal GW, e.g., depending on the implementation of the pixels or the emission control method) depending on the pixel implementation or the emission control method. Figure 2 The first scan signal GW[N] shown in the middle figure), the second scan signal GI (or the initial scan signal) (e.g., Figure 2 The second scan signal GI[N] shown in the middle figure), the third scan signal GB (or bypass scan signal) (e.g., Figure 2 The diagram shows the third scan signal GB[N] and the fourth scan signal GC (or the compensation scan signal). Figure 2 The fourth scan signal GC[N] shown in the figure. Accordingly, the multiple scan lines S1 to Sn may include at least one type of scan line, such that the scan lines can be configured for each scan signal. In some embodiments, the first scan signal GW can be applied to each of the multiple pixels PX11 to PXnm through multiple first scan lines, the second scan signal GI can be applied to each of the multiple pixels PX11 to PXnm through multiple second scan lines, the third scan signal GB can be applied to each of the multiple pixels PX11 to PXnm through multiple third scan lines, and the fourth scan signal GC can be applied to each of the multiple pixels PX11 to PXnm through multiple fourth scan lines.

[0055] In this embodiment, the data driver 30 can transmit data signals to each pixel via multiple data lines D1 to Dm. For example, the data driver 30 can receive a data drive control signal DCS from the controller 60 and apply data signals to the multiple data lines D1 to Dm, each of which is connected to a corresponding pixel among multiple pixels PX11 to PXnm in a given row.

[0056] In an embodiment, the emission control driver 40 may be connected to multiple emission control lines EM1 to EMn connected to the display unit 10, which includes multiple pixels PX11 to PXnm arranged in a matrix. For example, multiple emission control lines EM1 to EMn extending almost parallel in the row direction to face the multiple pixels PX11 to PXnm respectively may connect each of the multiple pixels PX11 to PXnm to the emission control driver 40.

[0057] In an embodiment, the emission control driver 40 can generate an emission control signal corresponding to each pixel and transmit the emission control signal via multiple emission control lines EM1 to EMn. Each pixel receiving the emission control signal can be controlled in response to the control made by the emission control signal to emit light according to the image data signal. For example, the operation of the emission control transistor included in each pixel can be controlled in response to the emission control signal transmitted via the corresponding emission control line. As a result, the light-emitting element connected to the emission control transistor can emit light or not emit light, and when emission occurs, the brightness of the light can be determined by the drive current corresponding to the data signal.

[0058] In this embodiment, two emission control signals are applied to each pixel. For example, the emission of a pixel can be controlled based on two types of emission control signals.

[0059] In this embodiment, the power supply unit 50 can supply a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization voltage Vint, an anode initialization voltage, or a conduction bias voltage to each pixel of the display unit 10. For example, the first power supply voltage ELVDD can be a specific high-level voltage, and the second power supply voltage ELVSS can be a voltage lower than the first power supply voltage ELVDD or a ground voltage. For example, the initialization voltage Vint can be set to a value equal to or lower than the second power supply voltage ELVSS.

[0060] The voltage values ​​of the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint are not particularly limited, and can be set or adjusted under the control of the power control signal PCS transmitted from the controller 60.

[0061] In this embodiment, the controller 60 converts multiple image signals transmitted from the outside into multiple image data signals DATA, and transmits the multiple image data signals DATA to the data driver 30. Furthermore, the controller 60 can receive vertical synchronization signals, horizontal synchronization signals, and clock signals, and can generate and transmit control signals for controlling the operation of the scan driver 20, the transmit control driver 40, and the data driver 30, respectively. That is, the controller 60 can generate and transmit a scan drive control signal SCS to control the operation of the scan driver 20, a transmit drive control signal ECS to control the operation of the transmit control driver 40, and a data drive control signal DCS to control the operation of the data driver 30. The controller 60 can also generate a power control signal PCS to control the operation of the power supply unit 50, and transmit the generated power control signal PCS to the power supply unit 50.

[0062] In an embodiment, the display device may further include a reference voltage generator. For example, the reference voltage generator may generate a reference voltage based on a control signal received from the controller 60. The reference voltage generator may apply the reference voltage to the data driver 30. The reference voltage may have a value corresponding to each image data signal DATA. The reference voltage generator may be located inside the controller 60 or inside the data driver 30.

[0063] In this embodiment, the data driver 30 can receive a data drive control signal DCS from the controller 60 and a reference voltage from the reference voltage generator. The data driver 30 can use the reference voltage to convert the image data signal DATA into an analog data voltage VDATA (see [link to relevant documentation]). Figure 2 For example, data driver 30 can output the data voltage VDATA to the data line.

[0064] Figure 2 This is a schematic diagram of the circuitry of a pixel according to a comparative embodiment.

[0065] refer to Figure 2 A pixel may include a light-emitting diode, multiple transistors, and at least one capacitor. In an embodiment, the multiple transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and the at least one capacitor may include a storage capacitor Cst. A transmit control signal EM[N] may be supplied to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6.

[0066] The first transistor T1 can be referred to as a driving transistor, and can generate a driving current based on the voltage applied to the electrodes of the first transistor T1. The first electrode (e.g., the source electrode) of the first transistor T1 can be connected to a first node, the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to a second node, and the third electrode (e.g., the gate electrode) of the first transistor T1 can be connected to a third node. The first transistor T1 can generate a driving current based on the voltage difference between the third node and the first node.

[0067] A second transistor T2 can be connected between the data line transmitting the data voltage VDATA and the first node, and can be turned on based on a signal applied through the first scan line. The first electrode (e.g., the source electrode) of the second transistor T2 can be connected to the data line, the second electrode (e.g., the drain electrode) of the second transistor T2 can be connected to the first node, and the third electrode (e.g., the gate electrode) of the second transistor T2 can be connected to the first scan line. The second transistor T2 can write the data voltage VDATA to the first node in response to a first scan signal GW[N] applied through the first scan line. The second transistor T2 can be referred to as a write transistor.

[0068] A third transistor T3 can be connected between the second and third nodes and can be turned on based on a signal applied via a fourth scan line. The first electrode (e.g., drain electrode) of the third transistor T3 can be connected to the second node, the second electrode (e.g., source electrode) of the third transistor T3 can be connected to the third node, and the third electrode (e.g., gate electrode) of the third transistor T3 can be connected to the fourth scan line. The third transistor T3 can electrically connect the second and third electrodes of the first transistor T1 in response to a fourth scan signal GC[N] applied via the fourth scan line. The third transistor T3 can be referred to as a compensation transistor.

[0069] A fourth transistor T4 can be connected between the initialization line transmitting the initialization voltage VINT1 and the third node, and can be turned on based on a signal applied via the second scan line. The first electrode (e.g., drain electrode) of the fourth transistor T4 can be connected to the initialization line, the second electrode (e.g., source electrode) of the fourth transistor T4 can be connected to the third node, and the third electrode (e.g., gate electrode) of the fourth transistor T4 can be connected to the second scan line. The fourth transistor T4 can initialize the third node using the initialization voltage VINT1 in response to a second scan signal GI[N] applied via the second scan line. The fourth transistor T4 can be referred to as the driving initialization transistor.

[0070] A fifth transistor T5 may be connected between a first power line transmitting the first power supply voltage ELVDD and a first node, and may be turned on based on a signal applied via a transmit control line. The first electrode (e.g., source electrode) of the fifth transistor T5 may be connected to the first power line, the second electrode (e.g., drain electrode) of the fifth transistor T5 may be connected to the first node, and the third electrode (e.g., gate electrode) of the fifth transistor T5 may be connected to the transmit control line. The fifth transistor T5 may electrically connect the first power line and the first node in response to a transmit control signal EM[N] applied via the transmit control line.

[0071] A sixth transistor T6 can be connected between the second and fourth nodes and can be turned on based on a signal applied via the emit control line. The first electrode (e.g., the source electrode) of the sixth transistor T6 can be connected to the second node, the second electrode (e.g., the drain electrode) of the sixth transistor T6 can be connected to the fourth node, and the third electrode (e.g., the gate electrode) of the sixth transistor T6 can be connected to the emit control line. The sixth transistor T6 can electrically connect the second and fourth nodes in response to an emit control signal EM[N] applied via the emit control line. Each of the fifth transistor T5 and the sixth transistor T6 can be referred to as an emit control transistor.

[0072] The seventh transistor T7 can be connected between the initialization line transmitting the initialization voltage VINT2 and the fourth node, and can be turned on based on a signal applied via the third scan line. The first electrode (e.g., the source electrode) of the seventh transistor T7 can be connected to the initialization line, the second electrode (e.g., the drain electrode) of the seventh transistor T7 can be connected to the fourth node, and the third electrode (e.g., the gate electrode) of the seventh transistor T7 can be connected to the third scan line. The seventh transistor T7 can initialize the fourth node using the initialization voltage VINT2 in response to the third scan signal GB[N] applied via the third scan line. The seventh transistor T7 can be referred to as a diode initialization transistor.

[0073] In this embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a P-type transistor (e.g., a P-type metal-oxide-semiconductor field-effect transistor (MOSFET)), and each of the third transistor T3 and the fourth transistor T4 can be an N-type transistor (e.g., an N-type MOSFET). In this embodiment, the turn-on voltage of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a low voltage, and the turn-on voltage of each of the third transistor T3 and the fourth transistor T4 can be a high voltage.

[0074] In this way, the pixels according to the embodiment may include both P-type MOSFETs and N-type MOSFETs, and different scan signals may be required to control their switching operations. Specifically, a scan signal with a negative pulse is required to control the on / off operation of the P-type MOSFET, and a scan signal with a positive pulse is required to control the on / off operation of the N-type MOSFET.

[0075] In some embodiments, Figure 2 In the above, each of the first scan signal GW[N] and the third scan signal GB[N] can be a scan signal with a negative pulse, such as a P-type scan signal that turns the P-type transistor on and off (i.e., controls the conduction state of the P-type transistor), and each of the second scan signal GI[N] and the fourth scan signal GC[N] can be a scan signal with a positive pulse, such as an N-type scan signal that turns the N-type transistor on and off (i.e. controls the conduction state of the N-type transistor).

[0076] The scan driver according to the comparative embodiment separately includes a unit for generating a scan signal with negative pulses and a unit for generating a scan signal with positive pulses.

[0077] However, the scan driver according to embodiments of the present disclosure can generate scan signals with negative pulses and scan signals with positive pulses, without separately including units for generating scan signals with negative pulses and units for generating scan signals with positive pulses. The scan driver according to the present disclosure will be described in detail below.

[0078] Figure 3 This is a diagram of a scan driver according to an embodiment.

[0079] In an embodiment, the scan driver 20 includes a reference scan signal generator 210, a first scan signal converter 220, and a second scan signal converter 230.

[0080] In an embodiment, the reference scan signal generator 210 can generate a reference scan signal 211. The reference scan signal generator 210 can include multiple stages, and each of these stages can output a corresponding reference scan signal 211. For example, the Nth stage of the reference scan signal generator 210 can generate the Nth reference scan signal, and the (N+1)th stage can generate the (N+1)th reference scan signal. In an embodiment, the Nth stage can generate the Nth reference scan signal based on the (N-1)th reference scan signal, and the (N+1)th stage can generate the (N+1)th reference scan signal based on the Nth reference scan signal. Here, N is a natural number greater than 0.

[0081] In this embodiment, the reference scan signal 211 has a negative pulse.

[0082] In an embodiment, the reference scan signal generator 210 may include at least one P-type transistor (e.g., a P-type MOSFET) and at least one N-type transistor (e.g., an N-type MOSFET). However, this disclosure is not limited thereto, and the reference scan signal generator 210 may include only P-type transistors, or it may include only N-type transistors. (The reference...) Figure 8 and Figure 9 An embodiment of the reference scan signal generator 210 is described below.

[0083] In one embodiment, a first scan signal converter 220 receives a reference scan signal 211, generates a first converted scan signal 221 based on the received reference scan signal 211, and outputs the generated first converted scan signal 221. In another embodiment, a second scan signal converter 230 receives the reference scan signal 211, generates a second converted scan signal 231 based on the received reference scan signal 211, and outputs the generated second converted scan signal 231.

[0084] For example, the first conversion scan signal 221 can be an N-type scan signal that turns the N-type transistor on and off, and the second conversion scan signal 231 can be a P-type scan signal that turns the P-type transistor on and off.

[0085] Figure 4 This is a timing diagram for explaining the N-type scan signal according to an embodiment.

[0086] As described above, an N-type scan signal can be generated based on a reference scan signal.

[0087] Figure 4 Timing diagrams of multiple reference scan signals are shown (i.e., the Nth reference scan signal S). REF [N], N+1th reference scan signal S REF [N+1] and N+2th reference scan signal S REF (Timing diagram of [N+2]) and based on the Nth reference scan signal S REF [N], N+1th reference scan signal S REF [N+1] and N+2th reference scan signal S REF The Nth N-type scan signal S generated by [N+2] NMOS [N] and the (N+1)th N-type scan signal S NMOS Timing diagram for [N+1].

[0088] In an embodiment, the multiple reference scan signals may include pulses (e.g., negative pulses), and the pulses of the multiple reference scan signals may have the same width. Figure 4 The Nth reference scan signal S REF [N], N+1th reference scan signal SREF [N+1] and N+2th reference scan signal S REF Each of the pulses in [N+2] can have the same width PW.

[0089] refer to Figure 4 In an embodiment, when the Nth reference scan signal S REF [N] transitions from a high voltage to a low voltage, for example, when the Nth reference scan signal S... REF When the negative pulse of [N] begins, the Nth N-type scan signal S NMOS [N] can transition from a low voltage to a high voltage. Similarly, when the (N+1)th reference scan signal S... REF When [N+1] transitions from a high voltage to a low voltage, for example, when the (N+1)th reference scan signal S... REF When the negative pulse of [N+1] begins, the (N+1)th N-type scan signal S NMOS [N+1] can jump from low voltage to high voltage.

[0090] refer to Figure 4 In the embodiment, the Nth N-type scan signal S NMOS [N] can maintain a high voltage, and subsequently, at the N+1th reference scan signal S REF [N+1] When the voltage jumps from low to high, for example, at the N+1th reference scan signal S REF At the end of the [N+1]th negative pulse, the voltage can jump from high to low. Similarly, the (N+1)th N-type scan signal S NMOS [N+1] can maintain a high voltage, and subsequently, at the N+2th reference scan signal S REF [N+2] When the voltage jumps from low to high, for example, when the (N+2)th reference scan signal S REF When the negative pulse of [N+2] ends, it can jump from high voltage to low voltage.

[0091] In summary, the Nth type N scanning signal S NMOS [N] can be used in the Nth reference scan signal S REF [N] or the (N+1)th reference scan signal S REF [N+1] is a period of low voltage with high voltage, and the Nth reference scan signal S REF [N] and the (N+1)th reference scan signal S REF [N+1] Both are at low voltage during periods of high voltage.

[0092] like Figure 4 As illustrated in the figure, N-type scan signals with positive pulses can be generated based on multiple reference scan signals, each with a negative pulse.

[0093] In an embodiment, the width of the N-type scan signal is adjusted according to the scan driver of this disclosure. In an embodiment, the pulse width of the N-type scan signal is determined based on the pulse width of each of the reference scan signals and the width corresponding to the segments in which the pulse durations of the reference scan signals overlap with each other.

[0094] In this embodiment, the pulse durations of the reference scan signals partially overlap. Figure 4 The Nth reference scan signal S REF The pulse duration of [N] and the (N+1)th reference scan signal S REF The pulse durations of [N+1] can partially overlap each other, and the width corresponding to the overlapping pulse durations can be 0W. Similarly, refer to... Figure 4 The (N+1)th reference scan signal S REF The pulse duration of [N+1] and the N+2th reference scan signal S REF The pulse durations of [N+2] can partially overlap each other, and the width corresponding to the overlapping pulse durations can be 0W.

[0095] refer to Figure 4 As described above, the Nth N-type scan signal S NMOS [N] can maintain a high voltage, and at the (N+1)th reference scan signal S REF [N+1] When transitioning from a low voltage to a high voltage, it can also transition from a high voltage to a low voltage. Therefore, the pulse width of the N-type scan signal can be determined by subtracting OW (i.e., the duration of the overlapping segment between the pulse widths of the reference scan signals) from twice the pulse width of each reference scan signal. For example, the pulse width of the N-type scan signal can be calculated as 2×PW-OW.

[0096] Figure 5 This is a diagram of the structure of the first scanning signal converter according to an embodiment.

[0097] In one embodiment, the first scan signal converter 220 includes at least one NAND gate. The NAND gate may be a digital logic circuit that outputs a low voltage only when both inputs are high and otherwise outputs a high voltage.

[0098] In one embodiment, two adjacent reference scan signals can be applied to the input terminal of a NAND gate included in the first scan signal converter 220. Figure 5 The figure shows the Nth reference scan signal S. REF [N] and the (N+1)th reference scan signal S REF [N+1] is applied to the input terminal of a NAND gate, and the (N+1)th reference scan signal S REF[N+1] and N+2th reference scan signal S REF [N+2] is applied to the input terminal of another NAND gate, and the N+2th reference scan signal S REF [N+2] and N+3 reference scan signals S REF [N+3] is applied to the input terminal of yet another NAND gate.

[0099] In an embodiment, the N-type scan signal can be output to the output terminal of a NAND gate included in the first scan signal converter 220.

[0100] In the embodiment, the Nth N-type scan signal S is illustrated. NMOS [N] is output to the Nth reference scan signal S that is relative to its input. REF [N] and the (N+1)th reference scan signal S REF The output terminal of a NAND gate [N+1], the (N+1)th N-type scan signal S NMOS [N+1] is output to the (N+1)th reference scan signal S that is input to it. REF [N+1] and N+2th reference scan signal S REF The output terminal of another NAND gate of [N+2], and the N+2th N-type scan signal S NMOS [N+2] is output to the (N+2)th reference scan signal S that is input to it. REF [N+2] and N+3 reference scan signals S REF [N+3] is another output terminal of a NAND gate.

[0101] exist Figure 5 The embodiment illustrated herein shows a diagram based on the Nth reference scan signal S REF [N] and the (N+1)th reference scan signal S REF [N+1] is used to output the Nth N-type scan signal S NMOS [N], but this is provided as an example, and for signal timing control, it can be based on the Nth reference scan signal S. REF [N] and the (N+1)th reference scan signal S REF [N+1] is used to output any appropriate N-type scan signal (such as the N-2nd N-type scan signal, the N+2nd N-type scan signal, or the N+5th N-type scan signal).

[0102] In an embodiment, a NAND gate may include at least one P-type transistor (e.g., a P-type MOSFET) and at least one N-type transistor (e.g., an N-type MOSFET). However, this disclosure is not limited thereto, and NAND gates may be implemented in various ways.

[0103] Figure 6 This is a timing diagram for explaining the P-type scan signal according to an embodiment.

[0104] As described above, a P-type scan signal can be generated based on a reference scan signal.

[0105] Figure 6 Timing diagrams of multiple reference scan signals are shown (i.e., the Nth reference scan signal S). REF [N], N+1th reference scan signal S REF [N+1] and N+2th reference scan signal S REF (Timing diagram of [N+2]) and based on the Nth reference scan signal S REF [N], N+1th reference scan signal S REF [N+1] and N+2th reference scan signal S REF The Nth P-type scan signal S generated by [N+2] PMOS [N] and the (N+1)th P-type scan signal S PMOS Timing diagram for [N+1].

[0106] In an embodiment, the multiple reference scan signals may include pulses (e.g., negative pulses), and the pulses of the multiple reference scan signals may have the same width. Figure 6 The Nth reference scan signal S REF [N], N+1th reference scan signal S REF [N+1] and N+2th reference scan signal S REF Each of the pulses in [N+2] can have the same width PW.

[0107] refer to Figure 6 In the embodiment, when the (N+1)th reference scan signal S REF [N+1] The voltage jumps from high to low while the Nth reference scan signal S REF [N] When maintaining a low voltage, the Nth P-type scan signal S PMOS [N] can transition from a high voltage to a low voltage. Similarly, in the (N+2)th reference scan signal S REF [N+2] The voltage jumps from high to low while the (N+1)th reference scan signal S REF [N+1] Maintaining a low voltage, the (N+1)th P-type scan signal S PMOS [N+1] can transition from high voltage to low voltage.

[0108] In summary, the Nth reference scan signal S REF [N] and the (N+1)th reference scan signal S REF [N+1] In the segments where both have low voltage, the Nth P-type scan signal S PMOS[N] can have a low voltage.

[0109] like Figure 6 As illustrated in the figure, P-type scan signals, each with its own negative pulse, can be generated based on multiple reference scan signals, each with its own negative pulse.

[0110] In embodiments, the width of the P-type scan signal is adjusted according to the scan driver of this disclosure. In some embodiments, the pulse width of the P-type scan signal is determined based on the width corresponding to the width of segments in which the pulse durations of the reference scan signal overlap with each other.

[0111] In this embodiment, the pulse durations of the reference scan signals partially overlap. Figure 6 The Nth reference scan signal S REF The pulse duration of [N] and the (N+1)th reference scan signal S REF The pulse durations of [N+1] can partially overlap each other, and the width corresponding to the overlapping pulse durations can be 0W. Similarly, refer to... Figure 6 The (N+1)th reference scan signal S REF The pulse duration of [N+1] and the N+2th reference scan signal S REF The pulse durations of [N+2] can partially overlap each other, and the width corresponding to the overlapping pulse durations can be 0W.

[0112] As described above, in the Nth reference scan signal S REF [N] and the (N+1)th reference scan signal S REF [N+1] Both of these are during the low voltage period, the Nth P-type scan signal S PMOS [N] can have a low voltage. This period can be compared with the Nth reference scan signal S. REF The pulse duration of [N] and the (N+1)th reference scan signal S REF The [N+1] pulse durations correspond to segments where they partially overlap. Accordingly, the pulse width of the P-type scan signal can be determined as OW, which is the width corresponding to the segments where the pulse durations of the reference scan signal overlap.

[0113] Figure 7 This is a diagram of the structure of the second scanning signal converter according to an embodiment.

[0114] In an embodiment, the second scan signal converter 230 includes at least one NOR gate. The second scan signal converter 230 may further include at least one NOT gate or an inverter gate. The NOR gate may be a digital logic circuit that outputs a high voltage only when both inputs are low and otherwise outputs a low voltage. The inverter gate may be a digital logic circuit that outputs a value opposite to the input signal; for example, it may output a low voltage when the input is high and a high voltage when the input is low.

[0115] In one embodiment, two adjacent reference scan signals are applied to the input terminal of a NOR gate included in the second scan signal converter. Figure 7 The figure shows the Nth reference scan signal S. REF [N] and the (N+1)th reference scan signal S REF [N+1] is applied to the input terminal of a NOR gate, and the (N+1)th reference scan signal S REF [N+1] and N+2th reference scan signal S REF [N+2] is applied to the input terminal of another NOR gate, and the N+2th reference scan signal S REF [N+2] and N+3 reference scan signals S REF [N+3] is applied to the input terminal of yet another NOR gate.

[0116] In one embodiment, the input terminal of the inverter is connected to the output terminal of a NOR gate included in the second scan signal converter 230. In another embodiment, a P-type scan signal is output to the output terminal of the inverter.

[0117] In one embodiment, it is illustrated that the input terminal of an inverter is connected to an input with an Nth reference scan signal S. REF [N] and the (N+1)th reference scan signal S REF The output terminal of a NOR gate [N+1], the (N-7th)th P-type scan signal S PMOS [N-7] is output to the output terminal of one inverter, and the input terminal of the other inverter is connected to the (N+1)th reference scan signal S. REF [N+1] and N+2th reference scan signal S REF The output terminal of another NOR gate in [N+2], the (N-6th)th P-type scan signal S PMOS [N-6] is output to the output terminal of another inverter, and the input terminal of yet another inverter is connected to the (N+2)th reference scan signal S. REF [N+2] and N+3 reference scan signals S REF[N+3] is another NOR gate output terminal, and the (N-5)th P-type scan signal S PMOS [N-5] is output to the output terminal of another inverter gate.

[0118] exist Figure 7 The embodiment illustrated herein describes a method based on the Nth reference scan signal S REF [N] and the (N+1)th reference scan signal S REF [N+1] is used to output the N-7th P-type scan signal S. PMOS [N-7], but this is provided as an example, and for signal timing control, it can be based on the Nth reference scan signal S. REF [N] and the (N+1)th reference scan signal S REF [N+1] is used to output any appropriate P-type scan signal (such as the N-2nd P-type scan signal, the Nth P-type scan signal, or the N+1th P-type scan signal).

[0119] In an embodiment, the NOR gate includes at least one P-type transistor (e.g., a P-type MOSFET) and at least one N-type transistor (e.g., an N-type MOSFET). However, this disclosure is not limited thereto, and the NOR gate can be implemented in various ways.

[0120] Figure 8 This is a diagram of a reference scan signal generator according to an embodiment.

[0121] Figure 8 The reference scan signal generator shown can be understood as an example of the reference scan signal generator 210 described above.

[0122] refer to Figure 8 The reference scan signal generator according to an embodiment includes at least one flip-flop, at least one level shifter, at least one pulse shaping unit, and at least one NAND gate. For example, the pulse shaping unit may be a combinational logic circuit with an inverter (such as a NAND gate and / or a NOR gate). In some embodiments, an RC delay network or an edge detector may be combined with these logic circuits to fine-tune the timing.

[0123] As described above, the reference scan signal generator may include multiple stages, and each of the multiple stages may output a corresponding reference scan signal. Figure 8 The reference scan signal generator can be implemented to output reference scan signals corresponding to multiple stages respectively.

[0124] refer to Figure 8The reference scan signal generator may include multiple flip-flops arranged in a sequential chain, such as flip-flops FF1, FF2, ..., FFm and FFm+1. Each flip-flop may output a corresponding scan register signal (e.g., scan register signals SR1, SR2, ..., SRm and SRm+1), which are used as intermediate timing signals for generating the reference scan signal.

[0125] Each flip-flop can receive clock signals PCLK and / PCLK at its clock terminals clk and / clk to control timing, and the first flip-flop FF1 can receive an input pulse PSP at its input terminal in, which initializes or triggers the generation of the first scan register signal SR1. The output of the first flip-flop FF1 (i.e., the first scan register signal SR1) can be provided as an input to the second flip-flop FF2 at its output terminal out, and the output of the second flip-flop FF2 is the second scan register signal SR2. This sequential transmission can continue in the remaining flip-flops. In this way, scan register signals SR1 to SRm+1 can be generated in a time-interleaved manner based on the clock signal, thereby defining a suitable time window for pulse generation.

[0126] Scan register signals SR1 through SRm+1 can be provided to logic gates (such as NAND gates) that receive pairs of adjacent signals (e.g., SR1 and SR2, SR2 and SR3, etc.) and generate intermediate logic outputs. These outputs can be used to define overlapping pulse windows between adjacent scan register signals.

[0127] For example, such as Figure 8 As illustrated, the output signals SR1 and SR2 from the first flip-flop FF1 and the second flip-flop FF2, respectively, can be supplied as inputs to a NAND gate, which in turn supplies its output to the first PSU via the input terminal in of the first pulse shaping unit (PSU). Each PSU can receive additional control signals (such as CLIP (clamp control signal) received at its input terminal clip, VH (high voltage) received at its input terminal vh, and VL (low voltage) received at its input terminal vl), and can be configured to output shaped signals (such as selection signals (e.g., select[1], select[2], select[3], ..., select[m]) output at its output terminal sel and boost signals (e.g., boost[1], boost[2], boost[3], ..., boost[m]) output at its output terminal bst). These output signals can be used by a scan signal converter to generate a final scan signal with the desired timing and voltage characteristics.

[0128] With this structure, the reference scan signal generator can produce multiple time-shifted reference scan signals derived from the outputs of clock-controlled flip-flops and shaped by logic gates and the PSU stage. Using overlapping output ranges from adjacent flip-flops, precise pulse width control can be achieved for both N-type and P-type scan signals, while minimizing circuit complexity and layout area by reusing a shared reference signal generation chain.

[0129] Figure 9 This is a diagram of a reference scan signal generator according to another embodiment.

[0130] Figure 9 The reference scan signal generator shown can be understood as an example of the reference scan signal generator 210 described above.

[0131] refer to Figure 9 The reference scan signal generator according to the embodiment includes at least one SR latch, at least one NAND gate, and at least one inverting gate.

[0132] As described above, the reference scan signal generator may include multiple stages, and each of these stages may output a corresponding reference scan signal. Figure 9 The reference scan signal generator can be implemented to output reference scan signals corresponding to multiple stages respectively.

[0133] Figure 9 The diagram illustrates another embodiment of the reference scan signal generator, in which a series of SR stages are connected in a daisy-chained structure. The first SR stage can receive the initial input signal SSP and clock signals SFTCLK and SFTCLKB to initiate signal propagation. The output of the first SR stage can be used as input to the next SR stage, and this pattern continues sequentially through the remaining stages, with each SR stage receiving only the output of its immediate predecessor.

[0134] Each SR stage can generate a reference signal for controlling the timing of the corresponding scan signal output. For example... Figure 9 As shown, each scan signal output path may include a three-input NAND gate, a first inverter that receives the output of the NAND gate, and a second inverter that receives the output of the first inverter and generates scan signals (e.g., Scan[1], Scan[2], Scan[3], Scan[4], Scan[5], Scan[6], Scan[7], and Scan[8]). The NAND gate in each row may receive three inputs: a reference signal output from the corresponding SR stage, and two clock control signals labeled SCLK1 and SCKJ2.

[0135] In operation, the output of each SR stage, combined with clock control signals SCLK1 and SCKJ2, determines when the corresponding NAND gate will output a low-level signal. A subsequent inverter shapes this output into a scan signal with appropriate logic levels and pulse width. This configuration provides a compact and efficient method for generating multiple scan signals from a chain of SR stages, each scan signal having a scan signal timing determined by both SR signal propagation and clock control signals. Therefore, Figure 9 The structure enables precise timing control while providing a modular and scalable architecture for generating scan signals.

[0136] Apart from Figure 8 and Figure 9 In addition to the example shown in the figure, the scan driver according to this disclosure can be implemented using any suitable type of reference scan signal generator that includes multiple stages and is capable of outputting reference scan signals corresponding to each stage.

[0137] While the various embodiments of this disclosure have been described as being implemented by scanning a drive, these embodiments may also be applied to other drives.

[0138] For example, various embodiments of this disclosure can also be applied to a transmission control driver for a display device that generates multiple transmission control signals. In some embodiments, the transmission control driver may include a reference transmission control signal generator, a first transmission control signal converter, and a second transmission control signal converter.

[0139] For example, various embodiments of this disclosure can also be applied to a data driver for a display device that generates multiple data signals. In some embodiments, the data driver may include a reference data signal generator, a first data signal converter, and a second data signal converter.

[0140] According to one or more embodiments of this disclosure, it is not necessary to separately generate scan signals for controlling the on / off states of N-type and P-type transistors, thereby achieving advantages in layout.

[0141] Therefore, the pulse width of the scan signal used to control the on / off state of the N-type transistor and the pulse width of the scan signal used to control the on / off state of the P-type transistor can be easily adjusted.

[0142] In addition, the number of drivers can be reduced, thereby reducing charging and discharging and power consumption.

[0143] Figure 10 This is a diagram illustrating an electronic device according to an embodiment of the present invention. (Reference) Figure 10According to an embodiment of the present invention, the electronic device 1000 can be connected via a display module 1140 (the display module 1140 may correspond to, for example, a display module 1140 corresponding to, a display module 1140). Figure 1 The display module 1140 (as shown in the diagram) outputs various information (e.g., images, text, music, etc.). When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide the application information to the user through the display panel 1141.

[0144] In some embodiments, electronic device 1000 may be configured as a smartphone, camera, smart TV, monitor, smartwatch, tablet computer, automotive display, or AR / VR head-mounted display. For example, electronic device 1000 may be a smartphone including a touch-sensitive display area for interaction and a non-display area containing sensors and circuitry for enhanced functionality. For example, electronic device 1000 may be a television or monitor including a large display area for high-resolution video playback and a non-display area containing driving circuitry or connection modules for external input. For example, electronic device 1000 may be a smartwatch including a display area optimized for compact and high-definition visual effects and a non-display area integrating biometric sensors for health monitoring. In some cases, electronic device 1000 may be an AR / VR head-mounted display.

[0145] In some embodiments, memory 1120 may store information such as software code for operating application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may run under the control of processor 1110 and utilize the data stored in memory 1120 to provide a wide range of functions, such as productivity tools, multimedia streaming and playback, file or email delivery, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touchscreen 1142, enabling the user to launch, navigate, and utilize the program through user input (e.g., touch, tap, gesture, or voice interaction).

[0146] After a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123, retrieved from memory 1120, corresponding to the selected application, to perform the application's functions. For example, when a user selects a camera application by tapping an icon (or camera application icon) displayed on display panel 1141, processor 1110 activates the camera module. Processor 1110 can then transmit image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can then display the image corresponding to the captured image via display panel 1141.

[0147] As another example, when a user wishes to make a phone call, they tap a phone icon displayed on display module 1140, and processor 1110 can execute a phone application stored in memory 1120. A phone keypad can be displayed on display panel 1141 for the user to enter the phone number they wish to call.

[0148] As another example, the display module 1140 can be integrated into an electronic device 1000 such as a laptop computer, smart TV, or tablet computer. Users wishing to access multimedia streaming applications (e.g., watching music videos or movies) can do so by tapping the corresponding icon. This action activates the application, allowing the user to watch the streaming content.

[0149] Processor 1110 may include a main processor 1111 and an auxiliary or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU). The main processor 1111 may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0150] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. The controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specifications of the display module 1140, and output the image data. The controller 1112-1 can output various control signals to drive the display module 1140. For example, the controller 1112-1 can drive the display module 1140 to display icons suitable for user selection on the screen, thereby executing the application program 1123.

[0151] Memory 1120 may store one or more applications 1123, as well as various data used by at least one component of electronic device 1000 (e.g., processor 1110 or user interface 1161) and input or output data for associated commands. For example, camera applications, GPS applications, augmented reality and virtual reality applications, and other applications may be executed by processor 1110 after the user selects a corresponding icon presented on the display screen (or display panel 1141) via touchscreen 1142 or user interface 1161. Furthermore, various setting data corresponding to user settings may be stored in memory 1120. Memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0152] Display module 1140 can output visual information (images) to a user. Display module 1140 may include display panel 1141, gate driver, source driver, voltage generation circuitry, and touchscreen 1142. Display module 1140 may further include a window, chassis, and bracket to protect display panel 1141. Display module 1140 may include... Figure 1 At least a portion of the configuration of the display device shown.

[0153] User interface 1161 serves as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input performed by a part of the user's body (e.g., a finger) or by a stylus or mouse, and generate an electrical signal or data value corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0154] The fingerprint sensor 1162 can sense fingerprints for biometric identification of a user and can also measure one or more biometric signals (such as blood pressure, water content, or weight).

[0155] Input sensor 1163 can sense user interactions including touch, taps, gestures, motion, voice commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared photodetectors or semiconductor photodetectors. Input sensor 1163 includes audio and acoustic sensors, which can be MEMS microphones for voice recognition or voice-based interaction. The audio and acoustic sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0156] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of input made by a stylus or mouse to control the movement of the screen cursor. The digitizer 1164 can generate the amount of electromagnetic change caused by the input as a data value. The digitizer 1164 can detect input made by a passive pen, or transmit and receive data using an active pen or remote control.

[0157] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 by a process that is continuous with the process of forming the various elements (e.g., light-emitting elements and transistors) included in the display panel 1141.

[0158] Furthermore, the user interface 1161 may further include, for example, a gesture sensor, a gyroscope sensor for sensing rotational motion, an accelerometer sensor for tracking translational motion, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer sensor, and infrared emitter and camera sensor may be particularly suitable for AR / VR head-mounted display functionality.

[0159] Touchscreen 1142 includes a touch sensor embedded in a semiconductor layer of display panel 1141 to sense pressure applied to the top layer (screen) of display panel 1141. The touch sensor can be capacitive or resistive. Touchscreen 1142 can be used as a primary interface for users to select and navigate applications, control electronic device 1000, and interact with electronic device 1000.

[0160] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and there is no particular limitation on the type of display panel 1141. The display panel 1141 may be rigid or flexible and capable of being rolled or folded. The display module 1140 may further include supports, brackets, and heat dissipation components for supporting the display panel 1141. The display module 1140 can be used to implement a display device. The display panel 1141 may include... Figure 1 The display unit 10 shown is shown.

[0161] Power module 1150 can supply power to various components of electronic device 1000. Power module 1150 can be used to implement power supply. Power module 1150 may include a battery that charges with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the aforementioned components, including display module 1140.

[0162] In addition to the examples described above, various embodiments of this disclosure can be applied to constructions that require the generation of both positive and negative pulses.

[0163] Each of the embodiments described above can be implemented independently, but the structure of each embodiment can be used in combination with other embodiments.

[0164] Thus, this disclosure has been described with reference to the various embodiments illustrated in the accompanying drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and changes can be made to the embodiments.

[0165] In the description of the embodiments (particularly in the claims), the use of the term "the (described)" and similar reference terms may involve both the singular and the plural. Furthermore, when a scope is described in the embodiments, it includes the invention to which each individual value belonging to the scope is applicable (unless otherwise described to the contrary), and each individual value constituting the scope has been described in detail. Finally, unless expressly indicated herein or otherwise obviously contradictory to the context, the steps of the method according to the embodiments may be performed in any suitable order. The embodiments are not necessarily limited to the order of the steps described above. The use of any exemplary or explanatory terminology in the embodiments is solely for the purpose of describing the embodiment in detail, and the scope of the embodiment is not limited by such exemplary or explanatory terminology. Furthermore, those skilled in the art will understand that various modifications, combinations, and alterations may be made depending on design conditions and factors within the scope of the appended claims or their equivalents.

Claims

1. A scan driver, comprising: A reference scan signal generator is configured to generate multiple reference scan signals; The first scan signal converter is configured to output an N-type scan signal for controlling the conduction state of an N-type transistor based on some of the plurality of reference scan signals; as well as The second scan signal converter is configured to output a P-type scan signal for controlling the conduction state of the P-type transistor based on some of the plurality of reference scan signals.

2. The scan driver according to claim 1, wherein, The first scan signal converter includes at least one NAND gate.

3. The scan driver according to claim 2, wherein, The Nth and N+1th reference scan signals of the plurality of reference scan signals are applied to the input terminal of one of the at least one NAND gates. The Nth N-type scan signal is output to the output terminal of the NAND gate, and N is a natural number greater than 0.

4. The scan driver according to claim 1, wherein, The second scan signal converter includes at least one NOR gate and at least one inverting gate connected to the at least one NOR gate.

5. The scan driver according to claim 4, wherein, The Nth and (N+1)th reference scan signals among the plurality of reference scan signals are applied to the input terminals of one of the at least one NOR gates. The input terminal of one of the at least one inverter gate is connected to the output terminal of the NOR gate. The Nth P-type scan signal is output to the output terminal of the inverter gate, and N is a natural number greater than 0.

6. The scan driver according to claim 1, wherein, Each of the plurality of reference scan signals includes a pulse, and The pulses of each of the plurality of reference scan signals have the same width.

7. The scan driver according to claim 6, wherein, The pulse durations of the Nth reference scan signal and the (N+1)th reference scan signal partially overlap to define the overlapping pulse durations. N is a natural number greater than 0.

8. The scan driver according to claim 7, wherein, The width of the pulse of the N-type scan signal is determined based on the width of the pulse of each of the plurality of reference scan signals and the width corresponding to the duration of the overlapping pulse.

9. The scan driver according to claim 7, wherein, The pulse width of the P-type scan signal is determined based on the width corresponding to the duration of the overlapping pulses.

10. A display device, comprising: The display unit includes multiple pixels, and each pixel is connected to a corresponding scan line in multiple scan lines; as well as The scan driver according to any one of claims 1 to 9 is configured to apply a scan signal corresponding to each of the plurality of pixels via the plurality of scan lines.

11. An electronic device comprising: The display panel includes multiple pixels, each pixel including an N-type transistor and a P-type transistor; as well as A scan driver, configured to provide a scan signal to the plurality of pixels, the scan driver comprising: A reference scan signal generator is configured to generate multiple reference scan signals; A first scan signal converter is configured to output an N-type scan signal for controlling the conduction state of the N-type transistor based on the overlap of adjacent reference scan signals among the plurality of reference scan signals; and The second scan signal converter is configured to output a P-type scan signal for controlling the conduction state of the P-type transistor based on the overlapping portion of adjacent reference scan signals among the plurality of reference scan signals.

12. The electronic device according to claim 11, wherein, The first scan signal converter is configured to determine the pulse width of the N-type scan signal based on the pulse width of each of the plurality of reference scan signals and the time overlap between the pulse duration of the Nth reference scan signal and the pulse duration of the (N+1)th reference scan signal. Where N is a natural number greater than 0.

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