Satellite communication baseband processing method with flexible configuration function

Abstract

The application discloses a satellite communication baseband processing method with flexible configuration function, relates to the technical field of satellite communication, and specifically a baseband processing method process is as follows: S1, interface adaptive adaptation scheduling; S2, downlink receiving scheduling; S3, uplink sending scheduling; S4, configurable hardware acceleration scheduling.The application can greatly improve the adaptive flexibility of baseband processing and the hardware multiplexing rate by executing four-step cooperative scheduling of downlink receiving scheduling, uplink sending scheduling, configurable hardware acceleration scheduling and interface adaptive adaptation scheduling, and all signal data are uniformly stored and scheduled with the memory as the core, compared with the fixed hardware pipeline architecture in the prior art, and therefore the technical problems of the prior satellite communication baseband processing, such as the need of modifying hardware circuits when switching satellite constellations or replacing radio frequency devices, high adaptation cost and low efficiency, can be solved.

Description

Technical Field

[0001] This invention relates to the field of satellite communication technology, and in particular to a satellite communication baseband processing method with flexible configuration capabilities. Background Technology

[0002] Satellite communication baseband processing methods effectively overcome large time delays, Doppler shifts, signal fading, and noise interference in satellite-to-ground links through technologies such as coding, modulation, synchronization, channel estimation and equalization, demodulation and decoding. This enables reliable and efficient baseband signal transmission, significantly improving link spectrum utilization and power efficiency, reducing bit error rate, ensuring communication continuity and stability, and supporting multiple access, link adaptation, and anti-interference capabilities. This meets the diverse needs of satellite communication for high reliability, low latency, or long-distance coverage.

[0003] Currently, existing technologies for satellite communication baseband processing generally adopt a fixed hardware pipeline architecture. The baseband processor interface logic, data flow path, and hardware accelerator working logic are all pre-fixed, which can only adapt to a single specification of RF front-end device and a single satellite signal. When switching satellite constellations or replacing RF devices, hardware circuits need to be modified. Furthermore, the scheduling of high-throughput data flow links is lagging and the utilization rate of hardware resources is low, which affects the adaptability flexibility, hardware reuse rate, and data scheduling efficiency of baseband processing. This results in high adaptation costs, poor maintenance convenience, and an inability to meet the needs of synchronous scheduling of multiple satellite signals and diverse hardware adaptation.

[0004] Therefore, a satellite communication baseband processing method with flexible configuration is proposed to solve the above problems. Summary of the Invention

[0005] The main objective of this invention is to provide a satellite communication baseband processing method with flexible configuration capabilities to solve the problems mentioned in the background above.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is: a satellite communication baseband processing method with flexible configuration function, the specific baseband processing method process is as follows: S1. Interface adaptive adaptation scheduling: Performs adaptive adaptation on the data interaction interface between the baseband processor and the RF front end, automatically identifies the working characteristics of the access hardware and completes timing matching and data format adaptation. S2, downlink reception scheduling, performs full-process baseband data flow scheduling on the downlink signals transmitted by the satellite. During the scheduling process, the software scheduling program adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S3, Uplink transmission scheduling, performs full-process baseband data flow scheduling on the raw communication data to be transmitted. During the scheduling process, the software scheduler adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S4. Configurable hardware acceleration scheduling: Hardware acceleration scheduling is performed on high-throughput data flow links in baseband processing. The data flow path, hardware interaction logic, and timing matching method of the hardware accelerator are dynamically adjusted through processor instructions.

[0007] Preferably, in the S1 interface adaptive adaptation scheduling, the identification of device operating characteristics is completed through the hardware direct connection link between the baseband processor and the analog-to-digital conversion module and the digital-to-analog conversion module.

[0008] Preferably, in the S1 interface adaptive adaptation scheduling, the interface cache module automatically adjusts the timing matching logic and data conversion logic through pure hardware circuitry to complete the synchronous adaptation with the access hardware.

[0009] Preferably, in the S2 downlink reception scheduling, the software scheduler is a hardware scheduler implemented based on the standard hardware driver of a general-purpose baseband processor, used to set the data flow direction, hardware interaction rules and timing matching methods of each hardware module in the baseband processor.

[0010] Preferably, in the S2 downlink reception scheduling, the data flow path is configured through the bus address remapping and cross switch matrix hardware functions built into the general baseband processor.

[0011] Preferably, in the S2 downlink reception scheduling, the hardware interaction logic completes the configuration adjustment through the hardware driver register built into the general-purpose baseband processor.

[0012] Preferably, in the S2 downlink reception scheduling, the digital intermediate frequency data is filtered by pure hardware through the hardware address decoding circuit and data gating circuit built into the general baseband processor to obtain valid communication data.

[0013] Preferably, in the S3 uplink transmission scheduling, the original communication data is transformed into a digital intermediate frequency signal adapted for satellite transmission and stored in the memory after being scheduled by the baseband data flow.

[0014] Preferably, in the S4 configurable hardware acceleration scheduling, the hardware accelerator is a multi-channel DMA controller built into a general-purpose baseband processor, used to perform parallel data transmission and distribution.

[0015] Preferably, in the S4 configurable hardware acceleration scheduling, after the hardware accelerator completes data scheduling, it sends feedback to the processor through a hardware-level interrupt trigger signal.

[0016] The present invention has the following beneficial effects: 1. This invention employs a four-step collaborative scheduling approach: downlink reception scheduling, uplink transmission scheduling, configurable hardware acceleration scheduling, and interface adaptive adaptation scheduling. It utilizes a software scheduler to adapt data flow paths, hardware interaction logic, and timing matching methods. All signal data is uniformly stored and scheduled throughout the entire process, with a memory as the core. Compared to the fixed hardware pipeline architecture in existing technologies, this significantly improves the adaptability flexibility and hardware reuse rate of baseband processing. Therefore, it solves the technical problems of existing satellite communication baseband processing being limited to adapting only a single satellite signal, requiring hardware circuit modifications when switching satellite constellations or replacing RF devices, resulting in high adaptation costs and low efficiency.

[0017] 2. This invention achieves flexible configuration of data flow paths and hardware interaction logic through the built-in bus address remapping, cross-switch matrix, and hardware driver registers of a general-purpose baseband processor. Combined with a built-in multi-channel DMA controller as a hardware accelerator, it performs parallel data transmission and distribution. After completing scheduling, the hardware accelerator feeds back to the processor via hardware level signals. Compared with the fixed working logic and low data scheduling efficiency of existing hardware accelerators, this invention improves the throughput and response speed of baseband data scheduling. Therefore, it can solve the technical problems of lag in high-throughput data flow scheduling, low hardware resource utilization, and inability to meet the synchronous scheduling requirements of multiple satellite signals in existing technologies.

[0018] 3. This invention completes the identification of device operating characteristics through a direct hardware connection between the baseband processor and the analog-to-digital conversion module and the digital-to-analog conversion module. The interface cache module automatically adjusts the timing matching logic and data conversion logic through pure hardware circuitry to achieve synchronous adaptation with the access hardware. Compared with the existing technology where the baseband processor interface logic is fixed and can only adapt to a single specification of RF front-end device, this invention can improve the scalability and maintenance convenience of the hardware platform. Therefore, it can solve the technical problems of existing technologies where replacing RF front-end devices requires modification of the baseband processor hardware circuitry and interface logic, resulting in high maintenance costs and poor hardware scalability. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of the satellite communication baseband processing method of the present invention; Figure 2 This is a schematic diagram of the interface adaptive adaptation scheduling process of the present invention; Figure 3 This is a schematic diagram of the downlink reception scheduling process of the present invention. Detailed Implementation

[0020] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0021] Example 1, please refer to Figure 1As shown: A satellite communication baseband processing method with flexible configuration capabilities. The specific baseband processing process is as follows: S1. Interface adaptive adaptation scheduling: Performs adaptive adaptation on the data interaction interface between the baseband processor and the RF front end, automatically identifies the working characteristics of the access hardware and completes timing matching and data format adaptation. S2, downlink reception scheduling, performs full-process baseband data flow scheduling on the downlink signals transmitted by the satellite. During the scheduling process, the software scheduling program adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S3, Uplink transmission scheduling, performs full-process baseband data flow scheduling on the raw communication data to be transmitted. During the scheduling process, the software scheduler adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S4. Configurable hardware acceleration scheduling: Hardware acceleration scheduling is performed on high-throughput data flow links in baseband processing. The data flow path, hardware interaction logic, and timing matching method of the hardware accelerator are dynamically adjusted through processor instructions.

[0022] Furthermore, S1, interface adaptive adaptation scheduling, adaptively adapts the data interaction interface between the baseband processor and the RF front end, automatically identifies the working characteristics of the corresponding hardware of the accessed RF front end, and automatically completes timing matching and data format adaptation, greatly improving the scalability of the hardware platform.

[0023] S2, downlink reception scheduling, completes the full-process baseband data flow scheduling of the downlink signal transmitted by the satellite. The full-process baseband data scheduling is the hardware scheduling of data transmission, storage and distribution; During the scheduling process, the data flow path, hardware interaction logic, and timing matching method can all be adapted by the software scheduler. The data flow path refers to the transmission direction and hardware units through which data passes between various hardware modules of the baseband processor. It can be flexibly configured through the standard bus address remapping and cross switch matrix functions built into the general baseband processor. Hardware interaction logic refers to the data transmission and reception triggering conditions and interaction linkage rules between various hardware modules of the baseband processor, which can be flexibly adjusted through the standard hardware driver registers built into the general baseband processor. Timing matching method refers to the time synchronization rules for data transmission between various hardware modules of the baseband processor. It is used to ensure the stability of data flow and can be flexibly configured through the standard clock division and data delay adjustment hardware functions built into the general baseband processor. The software scheduler is a hardware scheduler that is common in the field of satellite communication baseband hardware and is implemented based on the standard hardware driver built into the general baseband processor. Its function is to set the data flow direction, hardware interaction rules and timing matching methods between various hardware modules in the baseband processor. S3, Uplink transmission scheduling, completes the full-process baseband data flow scheduling of the raw communication data to be transmitted. The full-process baseband data scheduling is the hardware scheduling of data transmission, storage and distribution. During the scheduling process, the data flow path, hardware interaction logic, and timing matching method can all be adapted through the software scheduling program. At the same time, all signal data are uniformly stored and scheduled throughout the entire process with the memory as the core, sharing the same hardware platform with downlink reception scheduling. S4. Configurable hardware acceleration scheduling: For high-throughput data transfer links in the baseband processing, parallel high-speed scheduling is completed through hardware accelerator. The hardware accelerator is a standard multi-channel DMA controller built into a general-purpose baseband processor. It is a pure hardware data parallel scheduling module that is common in the field and is used to complete high-speed parallel transmission and distribution of data. The data flow path, hardware interaction logic, and timing matching method of the hardware accelerator can all be dynamically adjusted through processor instructions, taking into account both the flexibility of software scheduling and the efficiency of hardware flow. Example 2, please refer to Figure 1 and Figure 2 As shown: A satellite communication baseband processing method with flexible configuration function. In the S1 interface adaptive adaptation scheduling, the device operating characteristics are identified through the hardware direct link between the baseband processor and the analog-to-digital conversion module and the digital-to-analog conversion module.

[0024] The interface caching module automatically adjusts the timing matching logic and data conversion logic through pure hardware circuitry to achieve synchronous adaptation with the access hardware.

[0025] Furthermore, the S1 interface adaptive scheduling process is as follows: After the baseband processor is powered on, the interface cache module automatically identifies the working characteristics of the connected analog-to-digital converter and digital-to-analog converter through the hardware detection link; The hardware detection link is a standard I2C interface direct connection link between the baseband processor and the analog-to-digital converter module and the digital-to-analog converter module. It completes the identification of working characteristics through the device ID reading function of the general I2C protocol, which is a conventional hardware connection method in the field of interface circuits. The specific operating characteristics are the timing rules and data format specifications of the hardware, which are general parameters that can be directly read and obtained through the device ID in the field of interface circuits; The automatic identification process is triggered once after power-on. If a device is detected to have lost power and reconnected during operation, the identification will be automatically triggered again.

[0026] The interface caching module automatically adjusts its internal timing matching logic and data conversion logic based on the identified working characteristics. The timing matching logic adjustment specifically involves automatically matching the timing rules of the corresponding hardware, adjusting the data transmission and reception time interval, and achieving time synchronization with the access hardware. This is the hardware circuit implementation of the aforementioned timing matching method. The adjustment of the data conversion logic specifically involves automatically matching the data format specifications of the corresponding hardware and adjusting the data arrangement to achieve bidirectional format compatibility with the memory and access hardware. The automatic adjustment of the timing matching logic and data conversion logic is automatically completed by the pure hardware circuit of the interface cache module without the need for software intervention. After the adjustment is completed, a status feedback signal is automatically sent to the processor. During the downlink reception scheduling process, the interface buffer module automatically converts the digital signal input from the analog-to-digital converter module into a unified data format compatible with the memory. Specifically, the automatic conversion is achieved by using the interface hardware circuit to convert digital signals with different arrangement formats into digital signals with a unified arrangement format that the memory can recognize. During the uplink transmission scheduling process, the interface buffer module automatically converts the digital signal output from the memory into a data format compatible with the digital-to-analog converter module; In existing technologies, the interface logic between the baseband processor and the RF front-end is pre-fixed by the hardware circuit, which can only adapt to a single specification of analog-to-digital converter (ADC) or digital-to-analog converter (DAC) module and cannot be compatible with other specifications of devices. When replacing the RF front-end device, the hardware circuit and interface logic of the baseband processor must be modified, resulting in extremely poor hardware scalability. However, in this invention, when the terminal replaces the ADC module, DAC module, or RF front-end, the interface buffer module automatically re-identifies the working characteristics of the corresponding hardware and updates the internal adaptation logic. Seamless adaptation to the new device can be achieved without modifying the hardware circuit and software program of the baseband processor.

[0027] Example 3, please refer to Figure 1 and Figure 3 As shown: A satellite communication baseband processing method with flexible configuration function. In the S2 downlink reception scheduling, the software scheduler is a hardware scheduler implemented based on the standard hardware driver of the general baseband processor. It is used to set the data flow direction, hardware interaction rules and timing matching method of each hardware module in the baseband processor.

[0028] The data flow path is configured through the built-in bus address remapping and crossbar switch matrix hardware functions of the general-purpose baseband processor.

[0029] The hardware interaction logic completes the configuration adjustment through the hardware driver registers built into the general-purpose baseband processor.

[0030] The digital intermediate frequency data is filtered using pure hardware through the hardware address decoding circuit and data gating circuit built into the general-purpose baseband processor to obtain valid communication data.

[0031] Furthermore, the S2 downlink reception scheduling process is as follows: The downlink radio frequency communication signal transmitted by the satellite undergoes pure hardware preprocessing operations via the antenna and radio frequency module. Specifically, the preprocessing operations are common in the field of satellite communication radio frequency, which are implemented entirely by passive / active hardware circuits, including electrical signal amplification, frequency format conversion, and noise filtering. After processing, the analog intermediate frequency signal is output to the analog-to-digital conversion module. Analog intermediate frequency (IF) signal is a common intermediate format electrical signal in the field of satellite communication, between radio frequency (RF) signals and baseband signals. It is the standard transmission signal between antennas and RF modules, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). The analog-to-digital converter module converts the input analog intermediate frequency signal into a digital intermediate frequency signal and outputs it to the interface buffer module in the baseband processor. Digital intermediate frequency (IF) signal is a common intermediate format digital electrical signal in the field of satellite communication, which is between radio frequency (RF) signals and baseband signals. It is the standard transmission signal between analog-to-digital converter (ADC), digital-to-analog converter (DAC), and baseband processor. The interface buffer module performs timing matching and format rearrangement processing on the input digital intermediate frequency signal, converts it into a unified data format compatible with the memory, stores it in the internal buffer, and then writes it to the memory through the system bus. The processor runs a software scheduler, reads digital intermediate frequency data from memory through the system bus, and completes the entire baseband data scheduling process according to the hardware interaction logic and data flow path adapted by the software scheduler based on the signal transmission characteristics of the target satellite. Finally, the processor completes the pure hardware screening and extraction of effective communication data through the standard hardware address decoding and data gating circuit built into the general-purpose baseband processor. The extraction process involves hardware distribution and filtering based on data addresses to ultimately obtain valid communication data and complete the entire process of downlink signal baseband reception scheduling. Effective communication data refers to the raw electrical signal data extracted from satellite downlink signals that is identifiable by the terminal and carries service content. It is the final output target of downlink processing of satellite communication terminals. Existing satellite communication baseband processing generally adopts a fixed hardware pipeline architecture. The downlink data flow path is fixed in advance by the hardware logic and can only flow sequentially according to the preset path. It can only adapt to the transmission requirements of a single satellite signal. However, the software scheduling program running on the processor in this invention can flexibly adjust the data flow path and hardware interaction logic of the entire process according to the signal transmission characteristics of the target satellite. It can adapt to the downlink signal transmission requirements of different satellite constellations without modifying the hardware circuit. When it is necessary to switch the access satellite constellation, only the corresponding software scheduler needs to be loaded. Loading means that the hardware scheduling rules corresponding to different satellite constellations, which are pre-stored in the general-purpose Flash storage medium built into the baseband processor, are written into the processor's hardware driver register through the standard register operation instructions of the general-purpose baseband processor. After loading is completed, the software scheduler automatically and synchronously adjusts the data flow path, hardware interaction logic and timing matching method of the entire process, and completes the complete reconstruction of the baseband scheduling process.

[0032] Example 4, please refer to Figure 1 As shown: A satellite communication baseband processing method with flexible configuration function. In the S3 uplink transmission scheduling, the original communication data is transformed into a digital intermediate frequency signal adapted to satellite transmission and stored in the memory after baseband data flow scheduling.

[0033] Furthermore, the S3 uplink transmission scheduling process is as follows: The processor acquires the raw communication data to be transmitted, runs the software scheduler, and completes the uplink baseband data scheduling process according to the hardware interaction logic and data flow path adapted by the software scheduler based on the uplink transmission characteristics of the target satellite. It generates a digital intermediate frequency signal that meets the uplink transmission requirements of the satellite. The generation process only involves hardware adaptation and adjustment of data format and transmission timing, without involving any signal content calculation or processing. The signal is written to memory through the system bus. The digital intermediate frequency signal in the memory is read into the interface buffer module through the system bus according to the timing requirements of the completed adaptation. The timing requirements of the completed adaptation, namely the time synchronization rules corresponding to the aforementioned timing matching method, the uplink transmission characteristics of the target satellite and the working characteristics of the access device, are configured by the software scheduler and then synchronously sent to the corresponding hardware modules throughout the process. The interface buffer module performs format rearrangement and timing matching processing on the input digital intermediate frequency signal, converts it into a data format compatible with the digital-to-analog converter module, stores it in the internal buffer, and then outputs it to the digital-to-analog converter module. The digital-to-analog converter module converts the input digital intermediate frequency signal into an analog intermediate frequency signal and outputs it to the antenna and radio frequency module; The antenna and RF module perform routine pure hardware preprocessing operations on the input analog intermediate frequency signal. The routine preprocessing operations are frequency format conversion, electrical signal amplification, and clutter filtering, which are common in the field of satellite communication RF and are implemented entirely by passive / active hardware circuits. There is no software / algorithm intervention. These are routine technical means that can be implemented by technical personnel in the field without creative labor. After processing, the signal is converted into radio frequency electromagnetic waves by the antenna unit and transmitted to the satellite, completing the entire process of uplink signal baseband transmission scheduling. In existing fixed hardware pipeline architectures, the uplink data flow path is also pre-fixed by hardware logic and cannot be flexibly adjusted. When adapting to different satellite signals, hardware circuits must be modified. However, the software scheduler running on the processor in this invention can flexibly adjust the data flow path and hardware interaction logic of the entire uplink signal process according to the uplink transmission characteristics of the target satellite. It can adapt to the uplink signal transmission requirements of different satellite constellations without modifying the hardware circuits.

[0034] Example 5, please refer to Figure 1 As shown: A satellite communication baseband processing method with flexible configuration. In the S4 configurable hardware acceleration scheduling, the hardware accelerator is a multi-channel DMA controller built into the general baseband processor, which is used to perform parallel data transmission and distribution.

[0035] After completing data scheduling, the hardware accelerator sends feedback to the processor via a hardware-level interrupt trigger signal.

[0036] Furthermore, the S4 configurable hardware-accelerated scheduling process is as follows: Based on the current baseband scheduling throughput requirements, the processor sends adaptation instructions to the hardware accelerator via the standard AXI protocol of the system bus to adjust the data flow path, hardware interaction logic, timing matching method and working mode of the hardware accelerator. Operating mode refers to the channel enable rules and data transmission trigger conditions of the hardware accelerator, which are common configuration items of DMA controllers in the relevant field; The processor writes the data to be scheduled from memory to the input buffer of the hardware accelerator via the system bus; The hardware accelerator performs parallel high-speed scheduling of the input data according to the adapted working mode and data flow path. The parallel high-speed scheduling is realized through the multi-channel parallel data transmission function of the general multi-channel DMA controller. After the scheduling is completed, the result data is written to the output buffer and feedback is sent to the processor through a hardware level interrupt trigger signal. The interrupt trigger signal is a hardware level trigger signal.

[0037] After receiving the interrupt trigger signal, the processor writes the result data in the hardware accelerator output buffer into the memory via the system bus for subsequent baseband scheduling process to call; In the prior art, the working logic and data flow path of the hardware accelerator are fixed in advance by the hardware logic, which can only complete a single type of data flow task and cannot be adjusted. When adapting to different data flow requirements, the hardware logic must be modified. However, in this invention, when the baseband scheduling process changes and the data flow mode needs to be adjusted, the processor can readjust the working mode and data flow path of the hardware accelerator through the adaptation instructions. Hardware accelerators can be adjusted to different working modes through processor instructions, providing parallel high-speed flow support for the scheduling process of different satellite signals, and realizing synchronous scheduling of different satellite signals.

[0038] When in use, this invention first uses interface adaptive adaptation scheduling to complete the automatic matching between the baseband processor and the RF front end, and establishes a stable data interaction link. When a terminal needs to access different satellite constellations, the processor loads a software scheduler adapted to the target satellite constellation, adjusts the data flow path, hardware interaction logic and timing matching method in the downlink and uplink scheduling process, and adjusts the working mode of the hardware accelerator to complete the complete reconstruction of the baseband scheduling process and realize the normal transmission and reception scheduling of the target satellite constellation signal. When a terminal needs to switch to access other satellite constellations, the processor only needs to load a software scheduler adapted to the new target satellite constellation, readjust the data flow path, hardware interaction logic and hardware accelerator working mode of the entire process, and complete the reconstruction of the baseband scheduling process to achieve normal transmission and reception scheduling of signals from the new satellite constellation. When the terminal needs to replace the RF front-end related components, the interface buffer module automatically identifies the working characteristics of the new components, automatically adjusts the internal adaptation logic, completes the seamless adaptation of the new components, and realizes the normal operation of the baseband scheduling process.

[0039] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A satellite communication baseband processing method with flexible configuration capabilities, characterized in that, The specific baseband processing method is as follows: S1. Interface adaptive adaptation scheduling: Performs adaptive adaptation on the data interaction interface between the baseband processor and the RF front end, automatically identifies the working characteristics of the access hardware and completes timing matching and data format adaptation. S2, downlink reception scheduling, performs full-process baseband data flow scheduling on the downlink signals transmitted by the satellite. During the scheduling process, the software scheduling program adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S3, Uplink transmission scheduling, performs full-process baseband data flow scheduling on the raw communication data to be transmitted. During the scheduling process, the software scheduler adapts the data flow path, hardware interaction logic and timing matching method. All signal data is uniformly stored and scheduled in the memory as the core. S4. Configurable hardware acceleration scheduling: Hardware acceleration scheduling is performed on high-throughput data flow links in baseband processing. The data flow path, hardware interaction logic, and timing matching method of the hardware accelerator are dynamically adjusted through processor instructions.

2. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S1 interface adaptive adaptation scheduling, the identification of device operating characteristics is completed through the hardware direct connection links between the baseband processor and the analog-to-digital conversion module and the digital-to-analog conversion module.

3. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S1 interface adaptive adaptation scheduling, the interface cache module automatically adjusts the timing matching logic and data conversion logic through pure hardware circuitry to complete the synchronous adaptation with the access hardware.

4. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S2 downlink reception scheduling, the software scheduler is a hardware scheduler implemented based on the standard hardware driver of a general-purpose baseband processor. It is used to set the data flow direction, hardware interaction rules, and timing matching methods of each hardware module in the baseband processor.

5. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S2 downlink reception scheduling, the data flow path is configured through the bus address remapping and cross switch matrix hardware functions built into the general baseband processor.

6. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S2 downlink reception scheduling, the hardware interaction logic completes the configuration adjustment through the hardware driver register built into the general-purpose baseband processor.

7. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S2 downlink reception scheduling, the digital intermediate frequency data is filtered purely by hardware through the hardware address decoding circuit and data gating circuit built into the general-purpose baseband processor to obtain valid communication data.

8. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S3 uplink transmission scheduling, the raw communication data is transformed into a digital intermediate frequency signal adapted for satellite transmission and stored in the memory after being scheduled by the baseband data flow.

9. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S4 configurable hardware acceleration scheduling, the hardware accelerator is a multi-channel DMA controller built into a general-purpose baseband processor, used to perform parallel data transmission and distribution.

10. The satellite communication baseband processing method with flexible configuration function according to claim 1, characterized in that, In the S4 configurable hardware acceleration scheduling, after the hardware accelerator completes data scheduling, it sends feedback to the processor through a hardware-level interrupt trigger signal.

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