Universal sequencer bus device without crystal oscillator and clock signal generation method

Abstract

A universal serial bus device for coupling to a universal serial bus host includes a transceiver to receive a data signal having a first frequency from the universal serial bus host, wherein the data signal includes a plurality of specific packets having a periodic characteristic; a packet detector coupled to the transceiver to receive the data signal via the transceiver to generate a reference signal based on the periodic characteristic of the plurality of specific packets; and a frequency locked loop circuit coupled to the transceiver and the packet detector to generate a clock signal having a second frequency based on the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to be close to the first frequency, and the frequency difference between the first frequency and the second frequency is less than 500 ppm.

Description

Technical Field

[0001] This application relates to a general sequence bus device and a clock signal generation method, and more particularly to a general sequence bus device and a clock signal generation method without a crystal oscillator. Background Technology

[0002] In the Universal Serial Bus (USB) protocol, hardware operates in master / slave mode, thus categorized into USB hosts and USB devices. Simply put, a USB host can connect to multiple USB devices and control their communication. USB devices can be common mobile devices such as mobile phones, external hard drives, etc. USB devices require external components (such as quartz oscillators) to generate a precise clock to achieve the clock accuracy required by the USB specification. However, these external components are not only expensive but also require additional pins to receive the clock signal provided by the external components, further increasing the cost.

[0003] If external components are removed and the clock signal is instead provided by the oscillator within the USB device, the oscillator, being an open-loop circuit, is susceptible to variations in manufacturing processes, voltage, and temperature. Consequently, the frequency error between the USB device's clock signal and the USB host's clock signal often reaches 200,000-300,000 ppm, far exceeding the 500 ppm limit specified in the USB standard. Therefore, improvements to the existing technology are necessary. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a Universal Serial Bus (USB) device and a clock signal generation method to improve the frequency error between the clock signal of the USB device and the clock signal of the USB host.

[0005] One embodiment of this application discloses a USB device for coupling to a USB host. The Universal Serial Bus (USB) device includes a transceiver that receives a data signal having a first frequency from the USB host, wherein the data signal includes a plurality of specific packets having a periodic characteristic; a packet detector coupled to the transceiver that receives the data signal through the transceiver and generates a reference signal based on the periodic characteristic of the plurality of specific packets; and a frequency-locked loop circuit coupled to the transceiver and the packet detector for generating a clock signal having a second frequency based on the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to be close to the first frequency, and the frequency difference between the first and second frequencies is less than 500 ppm.

[0006] One embodiment of this application discloses a clock signal generation method for a USB device coupled to a USB host. The clock signal generation method includes receiving a data signal having a first frequency from the USB host via a transceiver of the Universal Serial Bus (USB) device, wherein the data signal includes a plurality of specific packets having a periodic characteristic; generating a reference signal by a packet detector of the USB device based on the periodic characteristic of the plurality of specific packets; and generating a clock signal having a second frequency by a frequency-locked loop circuit of the USB device based on the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to be close to the first frequency, and the frequency difference between the first frequency and the second frequency is less than 500 ppm. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a general sequence bus system according to an embodiment of this application.

[0008] Figure 2 This is a schematic diagram of multiple SOF packets in an embodiment of this application.

[0009] Figure 3 This is a schematic diagram of a digital phase-locked loop circuit according to Embodiment 1 of this application.

[0010] Figure 4 This is a time-domain waveform diagram of a digital phase-locked loop circuit according to an embodiment of this application.

[0011] The reference numerals in the attached figures are explained as follows:

[0012] 1 USB system

[0013] 10 USB devices

[0014] 20 USB host

[0015] 101 transceiver

[0016] 102 Packet Detector

[0017] 103 Frequency Locking Loop Circuit

[0018] T is a fixed time interval.

[0019] DPLL digital phase-locked loop circuit

[0020] 1031 Phase Frequency Detector

[0021] 1032 Digital Loop Filter

[0022] 1033 Integral-Differential Modulator

[0023] 1034 Digitally Controlled Oscillator

[0024] 1035 frequency divider

[0025] FB_CLK, PFD_OUT signals

[0026] Δt phase difference Detailed Implementation

[0027] Certain terms are used in this specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that hardware manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but by differences in function. The term "comprising" throughout this specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0028] Please refer to Figure 1 . Figure 1 This is a schematic diagram of a Universal Serial Bus (USB) system 1 according to an embodiment of this application. The USB system 1 includes a USB device 10 and a USB host 20 coupled to each other. The USB device 10 can receive data signals from the USB host 20 and execute a clock signal generation method to generate a clock signal corresponding to the data signals. Specifically, the USB device 10 includes a transceiver 101, a packet detector 102, and a frequency-locked loop (FLL) circuit 103. The transceiver 101 can receive data signals with a first frequency from the USB host 20. It should be noted that the data signals transmitted by the USB host 20 may include multiple specific packets with a periodic characteristic. When the transceiver 101 receives the data signal, the packet detector 102 can receive the data signal and generate a reference signal based on the periodic characteristics of the multiple specific packets. The FLL circuit 103 then generates a clock signal with a second frequency based on the reference signal and provides the clock signal to the transceiver 101 to process the data signal. In this way, the clock signal generation method of this application can make the second frequency substantially equal to the first frequency, that is, adjust the second frequency to be close to the first frequency, and the frequency difference between the first frequency and the second frequency will be less than the 500ppm limit specified by the USB specification.

[0029] It should be noted that USB system 1 is an embodiment of this application, and those skilled in the art can derive appropriate implementations based on system conditions. For example, the USB specification defines data signals as including various packets such as start-of-frame (SOF) packets. USB devices use SOF packets to determine the start of a frame in the data signal. In other words, in this embodiment, multiple specific packets with periodic characteristics can be multiple SOF packets, but this is not a limitation. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of multiple SOF packets in an embodiment of this application. Figure 2 As shown, the data signal includes multiple SOF packets and other packets. In the data signal, an SOF packet appears once every fixed time interval T. In this way, the packet detector 102 of this application can detect whether an SOF packet appears and generate a reference signal with a period of fixed time interval T accordingly. Specifically, each SOF packet includes a SYNC field, a packet identifier (PID) field, a CRC field, and an EOP field. When the packet detector 102 detects [01011010] in the PID field, the packet detector 102 can determine that the packet is an SOF packet (that is, detect the PID field corresponding to the SOF packet) and generate a reference signal accordingly. It should be noted that the packet detector 102 can be composed of various logic gates. The working principle of logic gates is well known in the art and will not be described in detail here. Furthermore, the operating principles of SOF packets, SETUP packets, IN packets, OUT packets, and the corresponding SYNC, PID, CRC, and EOP fields are well known in the field and will not be elaborated here. For example, the packet identification code corresponding to the SETUP packet is [11010010], the packet identification code corresponding to the IN packet is [10010110], and the packet identification code corresponding to the OUT packet is [00011110].

[0030] On the other hand, the FLL circuit 103 of this application can be a phase-locked loop (PLL) circuit, a digital phase-locked loop (DPLL) circuit, or a clock and data recovery (CDR) circuit, but is not limited thereto. In one embodiment, please refer to... Figure 3 , Figure 3This is a schematic diagram of a digital phase-locked loop (DPLL) circuit according to an embodiment of this application. In this embodiment, the DPLL circuit includes a phase-frequency detector (PFD) 1031, a digital loop filter 1032, an integral-differential modulator (Sigma-Aldrich) 1033, a digital control oscillator (DCO) 1034, and a frequency divider 1035. Specifically, the phase-frequency detector 1031 is used to determine the frequency phase difference between a reference signal and a feedback signal FB_CLK. The digital loop filter 1032 is used to eliminate noise from the frequency phase difference. The integral-differential modulator 1033 is used to eliminate quantization errors in the frequency phase difference. In this way, the frequency phase difference can be used to control the digital control oscillator 1034 to generate a target clock signal. The frequency divider 1035 is used to divide the target clock signal to generate the feedback signal FB_CLK. In this embodiment, please refer to... Figure 4 , Figure 4 This is a time-domain waveform diagram of a digital phase-locked loop (DPLL) circuit according to an embodiment of this application. Figure 4 As shown, the output signal PFD_OUT of the phase frequency detector 1031 is the phase difference Δt between the reference signal and the feedback signal FB_CLK. The digital controlled oscillator 1034 generates the target clock signal in response to the phase difference Δt. In this way, the digital phase-locked loop (DPLL) circuit can continuously compare the feedback signal FB_CLK and the reference signal, aligning the phases of the feedback signal FB_CLK with the reference signal. It should be noted that when the feedback signal FB_CLK is phase-aligned with the reference signal, the target clock signal is a clock signal with a second frequency. Furthermore, the second frequency of the clock signal is essentially equal to the first frequency of the data signal; that is, the frequency difference between the first and second frequencies will be less than the 500ppm limit specified in the USB standard.

[0031] In summary, the USB device of this application can detect multiple specific packets with periodic characteristics in the data signal and generate a clock signal accordingly. Therefore, compared to existing technologies, the USB device of this application can achieve the clock accuracy required by the USB specification without using external components (such as a quartz oscillator).

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A universal sequence bus device for coupling to a universal sequence bus host, characterized in that, The universal sequence bus device includes: A transceiver receives a data signal having a first frequency from the Universal Serial Bus host, wherein the data signal comprises a plurality of specific packets having periodic characteristics; A packet detector, coupled to the transceiver, receives the data signal through the transceiver and generates a reference signal based on the periodic characteristics of the plurality of specific packets; and A frequency-locked loop circuit, coupled to the transceiver and the packet detector, is used to generate a clock signal with a second frequency based on the reference signal; The first frequency is essentially equal to the second frequency.

2. The universal sequence bus device as described in claim 1, characterized in that, These multiple specific packets are the start packets for multiple frames.

3. The universal sequence bus device as described in claim 2, characterized in that, Each of the plurality of frame start packets includes a frame start packet identifier, and the packet detector detects the time interval corresponding to two adjacent frame start packets to generate the reference signal.

4. The universal sequence bus device as described in claim 1, characterized in that, The frequency difference between the first frequency and the second frequency is less than 500 ppm.

5. The universal sequence bus device as described in claim 1, characterized in that, The frequency-locked loop circuit includes a phase-locked loop circuit or a clock data recovery circuit.

6. A clock signal generation method for a universal sequence bus device coupled to a universal sequence bus host, characterized in that, The clock signal generation method includes: The transceiver of the Universal Serial Bus device receives a data signal with a first frequency from the Universal Serial Bus host, wherein the data signal comprises a plurality of specific packets having periodic characteristics; The packet detector of the universal sequence bus device generates a reference signal based on the periodic characteristics of the plurality of specific packets; and The frequency-locked loop circuit of the general sequence bus device generates a clock signal with a second frequency based on the reference signal; The first frequency is essentially equal to the second frequency.

7. The clock signal generation method as described in claim 6, characterized in that, These multiple specific packets are the start packets for multiple frames.

8. The clock signal generation method as described in claim 7, characterized in that, Each of the plurality of frame start packets includes a frame start packet identifier, and the step of generating the reference signal based on the periodicity of the plurality of specific packets includes: detecting the time interval corresponding to two adjacent frame start packets to generate the reference signal.

9. The clock signal generation method as described in claim 6, characterized in that, The frequency difference between the first frequency and the second frequency is less than 500 ppm.

10. The clock signal generation method as described in claim 6, characterized in that, The frequency-locked loop circuit includes a phase-locked loop circuit or a clock data recovery circuit.

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