Memory control method and storage device

Abstract

This application belongs to the field of memory control, and provides a memory control method and storage device. The method includes maintaining state description information, including a dirty flag, a locking flag, and access statistics, for each mapping table in a buffer memory. In the cache replacement path, replaceable mapping tables are filtered based on the locking flag to generate a second mapping table set. A second priority coefficient is calculated based on the access statistics to select candidate replacement tables. Before replacement, the dirty flag is checked to automatically complete the persistence of dirty data. In the flush path, dirty mapping tables are filtered based on the dirty flag to generate a first mapping table set. A first priority coefficient is calculated based on the access statistics and sorted. The mapping tables are written to the memory module in sequence. The first priority coefficient is positively correlated with the write frequency and negatively correlated with the read frequency. Through the coordinated operation of the above two paths, this application reduces the write amplification effect while ensuring data consistency, thereby improving cache hit rate and system read / write performance.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] In flash memory storage devices such as general-purpose flash memory, the logical-to-physical (L2P) address mapping table is a crucial data structure used to record the mapping relationship between logical addresses and physical addresses. The mapping table (i.e., the L2P table) is typically partially cached in buffer memory to improve access speed. When the mapping table in the buffer memory is modified by writes, the modified content needs to be written back to the memory module at an appropriate time to achieve data persistence.

[0003] The common mapping table update strategy is to write all mapping tables that have been written to the memory module at once when the available space in the buffer memory is insufficient or when certain conditions are met, and then release the corresponding buffer memory space after the writing is completed.

[0004] Existing strategies may perform multiple writes to the same mapping table during execution, resulting in more data being written than actually needed. Furthermore, existing strategies do not consider the differences in access behavior among different mapping tables when selecting which to write to. Both of these factors negatively impact the overall operating efficiency and lifespan of the storage device. Summary of the Invention

[0005] In view of this, this application provides a memory control method and a storage device to solve the technical problem of poor performance in persistent writing of mapping tables in the prior art.

[0006] Embodiments of this application provide a memory control method applied to a storage device including a memory module and a memory controller. The memory controller includes a buffer memory, which stores a mapping table representing the mapping relationship between logical addresses and physical addresses. The method includes: Applied to a storage device including a memory module and a memory controller, the memory controller including a buffer memory storing a mapping table representing the mapping relationship between logical addresses and physical addresses, the method includes: Obtain the status description information of each mapping table in the buffer memory. The status description information includes: a dirty flag indicating whether the mapping table has been modified relative to the corresponding mapping table in the memory module, a locking flag indicating whether the mapping table is prohibited from being replaced or removed from the buffer memory, and access statistics of the mapping table. In response to the load instruction for loading the target mapping table, determine whether there is sufficient remaining space in the buffer memory; if not, filter out the mapping tables in the buffer memory that are in an unlocked state indicated by the lock flag, generate a second mapping table set, calculate the second priority coefficient of each mapping table in the second mapping table set based on access statistics, and select at least one candidate replacement table with the highest second priority coefficient in the second mapping table set. For each candidate replacement table, if the dirty flag indicates a dirty state, the candidate replacement table is written to the memory module and then deleted from the buffer memory; if the dirty flag indicates a non-dirty state, the candidate replacement table is directly deleted from the buffer memory. In response to a preset trigger event, the system filters out the mapping tables in a dirty state from the buffer memory according to the dirty flag, generates a first mapping table set, calculates the first priority coefficient of each mapping table in the first mapping table set according to access statistics, sorts the mapping tables in the first mapping table set based on the first priority coefficient, selects a predetermined number of mapping tables in descending order of the first priority coefficient based on the sorting result, and writes the selected mapping tables into the memory module in sequence. The first priority coefficient is configured to be positively correlated with the writing frequency of the mapping table and negatively correlated with the reading frequency of the mapping table.

[0007] Embodiments of this application also provide a storage device including a connection interface for electrically connecting to a host computer; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; and The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method described above.

[0008] Based on the above, the memory control method and storage device proposed in the embodiments of this application integrate cache replacement decisions and flushing decisions into a unified multi-dimensional information management framework by maintaining state description information including dirty flags, lock flags, and access statistics for each mapping table in the buffer memory. In the cache replacement path, the lock flag protects critical mapping tables from replacement, and the second priority coefficient is calculated using access statistics to select the optimal replacement object. Furthermore, the dirty flag is checked before replacement to automatically persist dirty data, avoiding data loss due to cache replacement. In the flushing path, by configuring the first priority coefficient to be positively correlated with the write frequency of the mapping table and negatively correlated with the read frequency, frequently written mapping tables are flushed first to ensure data safety, while frequently read mapping tables are suppressed from flushing to continue serving read requests, reducing performance jitter caused by hot mapping tables being written back prematurely and frequently reloaded. The two paths work together to effectively reduce write amplification effects and extend the lifespan of the memory module while ensuring data consistency, while simultaneously improving the cache hit rate of the buffer memory and the overall read / write response performance of the system.

[0009] To make the above-mentioned objectives, technical solutions and beneficial effects of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0011] Figure 1 This is a schematic diagram illustrating data storage according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the data structure and relationships of a three-level logic-to-entity mapping table according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating the storage of the mapping table in the buffer memory according to an embodiment of this application; Figure 6 This is a schematic diagram of the storage of the mapping table according to an embodiment of this application; Figure 7 This is a general flowchart of the memory control method provided in the embodiments of this application; Figure 8 This is a flowchart of the calculation method for the first priority coefficient provided in the embodiments of this application; Figure 9 This is a schematic flowchart of a mapping table prefetching method provided in an embodiment of this application. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0013] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host 11 and a storage device 12. The storage device 12 can be connected to the host 11 and can be used to store data from the host 11. For example, the host 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system installed in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host 11 is not limited to these. Furthermore, the storage device 12 can include a solid-state drive (SSD), universal flash storage (UFS), embedded multi-media card (eMMC), USB flash drive, memory card, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0014] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host 11. For example, the connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0015] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0016] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0017] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0018] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host 11 via the connection interface 121 for communication with the host 11. The memory interface 22 is used to connect to the memory module 122 for access to the memory module 122.

[0019] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0020] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 can be used to cache instructions from the host 11, data from the host 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0021] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0022] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0023] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0024] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0025] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0026] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0027] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0028] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0029] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0030] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0032] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0037] In one embodiment, the memory controller 123 maintains a logic-to-entity mapping table. Specifically, to support real-time acquisition and feature analysis of host I / O (Input / Output) command metadata, when the memory control circuit 23 receives a host I / O request, in addition to querying the mapping table for address translation, it simultaneously stores the logical address range and operation type flag of the I / O request in a circular buffer. This circular buffer serves as the data source for multi-dimensional feature vectors within the current time window. This allows the memory controller to perceive the address access locality and hot / cold distribution of the front-end load without increasing instruction overhead.

[0038] In another embodiment, to further reduce write amplification and improve the management efficiency of large-capacity storage devices, a three-level mapping table data structure is proposed. This adds a layer of abstraction to the two-level mapping. The three-level mapping table typically includes mappings from logical addresses to virtual addresses, mappings from virtual addresses to intermediate data packets, and mappings from intermediate data packets to physical addresses. The memory control circuit 23 writes multiple dirty-state mapping entries in batches and in an orderly manner into the three-level mapping table (L3) of the main mapping table in the memory module 122. Preferably, during mapping entry update operations, data packets with larger data volumes or older ages are prioritized for processing to maximize the efficiency of the update operation.

[0039] When the storage device 12 is a high-performance, high-capacity enterprise-grade solid-state drive, a four-level mapping table data structure is proposed in one embodiment. For example, it includes virtual channel mapping (L1), intra-channel die (wafer or bare die inside the flash memory chip) mapping (L2), die hybrid mapping (L3), and physical address mapping (L4). Specifically, virtual channel mapping breaks up consecutive LBAs and distributes them evenly across multiple virtual flash memory channels. Its main purpose is to utilize the parallelism of multiple channels within the memory module 122 to avoid a single channel becoming a performance bottleneck. Virtual channel mapping typically maintains a mapping table from LBA ranges to virtual channel IDs.

[0040] Once a virtual channel is defined, the intra-channel die mapping is responsible for scheduling multiple physical dies (chips) within that channel. This enables interleaving of operations between multiple dies within the channel. When one die is busy, operations can be routed to another idle die, thus hiding access latency. The intra-channel die mapping records the physical die ID corresponding to each virtual die address and typically integrates wear leveling operations to ensure that the same die is not frequently accessed.

[0041] Die hybrid mapping employs a hybrid mapping strategy within a single die. It divides the write operation into two parts: First, random write data is written to blocks using SLC mode, which employs page mapping, resulting in low latency and high speed. Once the SLC block is full, the memory control circuit 23 merges and organizes multiple SLC blocks, writing them into the final data block. This data block can use block mapping and page mapping, or 4K and sector mapping.

[0042] The lowest level physical address mapping records the final mapping relationship from each logical address to a physical address. When host 11 needs to read data, it locates the physical address of the data by querying this level of mapping table. Because there are many mapping relationships in L4, this level of mapping table is very large. It is usually not all resident in memory (buffer memory 24), but a caching mechanism is used to cache only the active mapping tables in memory, and the majority of the rest are stored in memory module 122. The memory control circuit 23 loads the corresponding mapping table into memory as needed.

[0043] In one embodiment, such as Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the data structure and relationships of a three-level logical-to-entity mapping table according to an embodiment of this application. This mapping structure is used to efficiently manage the mapping relationship between logical units and entity units, and is particularly suitable for industrial and automotive storage scenarios with stringent requirements for access speed, memory efficiency, and reliability.

[0044] Figure 4 In this implementation, the first-level mapping table is relatively small, maintained by the memory control circuit 23, and resides in the buffer memory 24. Each entry records the base address or index number of a second-level mapping table in the buffer memory 24, and each second-level mapping table corresponds to a contiguous range of logical addresses (called a logical segment). In this embodiment, entries in the second-level mapping table store pointers to a third-level mapping table. Each third-level mapping table manages finer-grained mapping relationships within a logical block, storing the final physical address from each logical page to an entity programmable unit (e.g., an entity page). This is crucial for achieving random writes and efficient garbage collection.

[0045] When host 11 requests data access via a logical address, memory control circuit 23 uses the most significant bit of the logical address to index the first-level mapping table and obtain the address of the template second-level mapping table. It loads (if not already in the buffer) and accesses the second-level mapping table, using the middle part of the logical address for indexing. If the entry directly points to a physical unit, the physical page offset is calculated using the low-order bits of the logical address. If the entry points to a third-level mapping table, it loads (if not already in the buffer) and accesses the third-level mapping table, using the least significant bit of the logical address for indexing to obtain the physical address of the final physical programmed unit. Memory control circuit 23 sends the corresponding read or write instruction sequence to memory module 122 via memory interface 22 to operate the physical programmed unit. Through hierarchical and on-demand loading, all mapping relationships are avoided from residing in buffer memory 24, reducing the capacity requirement of buffer memory 24 and saving hardware costs for memory controller 123. Simultaneously, the resident first-level table ensures the initial speed of mapping lookups.

[0046] It is understood that the memory control method provided in this application is not limited to... Figure 4 The specific mapping table structure is shown. In other embodiments, the storage device may also employ a three-level or four-level mapping table architecture. Regardless of the specific mapping table level used, the core concepts of mapping table status monitoring, priority sorting, and selective writing in this application remain applicable.

[0047] Based on the above Figures 1 to 4 The described storage architecture, memory controller, flash memory management mechanism, and buffer memory structure are discussed in this application. This method intelligently schedules background tasks such as garbage collection and wear leveling by real-time sensing of the dynamic characteristics of host input / output load, thereby optimizing the long-term health of the storage medium while ensuring high performance of foreground tasks. The following will combine... Figures 6 to 9 The memory control methods of various embodiments of this application will be described in detail.

[0048] The above Figures 1 to 4 The hardware architecture shown provides the operating environment for the various method embodiments of this application. Specifically, the method steps described in the various embodiments of this application can be implemented by the memory control circuit 23 executing the corresponding firmware code. The following will describe each step of the method in detail with reference to this hardware environment. Figures 5 to 9 This paper elaborates on how the memory control method provided in this application is implemented on this hardware architecture.

[0049] Specifically, the method steps described in the various embodiments of this application can be implemented by the memory control circuit 23 or the memory controller 123 executing corresponding firmware code. The following will describe each step of the method in detail with reference to this hardware environment.

[0050] Figure 7 This is a general flowchart of a memory control method shown in an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory control circuit 23 or a memory controller 123 (hereinafter the same) is configured to perform this method. The method begins at step S1.

[0051] S1. Obtain the status description information of each mapping table in the buffer memory.

[0052] Specifically, within the current monitoring period, status description information is obtained, including: a dirty flag indicating whether the mapping table has been modified relative to the corresponding mapping table in the memory module, a lock flag indicating whether the mapping table is prohibited from being replaced or removed from the buffer memory, and access statistics of the mapping table.

[0053] After the decision-making process is initiated, the first step is to retrieve the state description information of all currently cached mapping tables in the buffer memory. Each mapping table has a unique corresponding state description information. The state description information of each mapping table is read sequentially. For each mapping table, the retrieved state description information must contain at least a dirty flag.

[0054] The dirty flag is used to indicate whether the mapping table has been modified relative to the corresponding table in the memory module, that is, whether the mapping table has undergone at least one logical entry write operation since it was last written to the memory module.

[0055] The current monitoring period refers to an independent time window defined by a preset trigger time, during which the status description information of each mapping table is continuously collected. After the above method executes the write operation and completes the status reset, the written mapping table enters the next monitoring period. For mapping tables not selected in the flush operation, their status description information will be accumulated across periods, the dirty flag will remain unchanged, and the cumulative number of writes, cumulative number of reads, and cumulative residence time will continue to accumulate until they are selected for writing and reset in a subsequent trigger time.

[0056] In addition to the dirty flag, the access statistics read from the status description information may also include access statistics for the mapping table. These statistics include cumulative write counts, cumulative read counts, and cumulative residency time. The cumulative write count represents the total number of logical entries that have been written to or modified in the mapping table since it was last written to the memory module. The cumulative read count represents the total number of times the mapping table has been accessed and queried since it was loaded into the buffer. The cumulative residency time represents the duration the mapping table has resided in the buffer since it was loaded into the buffer.

[0057] See Figure 5 As shown, Figure 5This diagram illustrates an exemplary method for storing mapping tables in a buffer memory. The left column represents the mapping tables cached in the buffer memory, containing a total of six mapping tables, designated as Mapping Table 1 to Mapping Table 6. The right column represents the state description information corresponding to each mapping table, designated as State Description Information 1 to State Description Information 6.

[0058] The diagram uses different colors to identify the mapping tables. Red indicates mapping tables in a dirty state, and green indicates mapping tables in a non-dirty state. The determination of whether a mapping table is dirty or not is stored in the dirty flag field of the state description information of each mapping table.

[0059] Specifically, mapping tables 1, 3, and 6 are marked in red, indicating that the dirty flags of these three tables all indicate a dirty state. A dirty flag signifies that the mapping table has undergone at least one logical entry write modification within the current monitoring period, and the modified content has not yet been written to the memory module. In the corresponding status description information 1, 3, and 6, the dirty flag field is set to indicate a dirty state, the cumulative write count field records the cumulative number of logical entries in the mapping table that have been written and modified since the start of the current monitoring period, and the cumulative residence time field records the continuous time value since the dirty flag became dirty.

[0060] Mapping tables 2, 4, and 5 are marked in green, indicating that the dirty flag for these three tables is in a non-dirty state. A non-dirty flag means that the mapping table has not undergone any logical entry write modifications since it was last written to the memory module or loaded into the buffer memory, and its content is completely identical to the corresponding copy stored in the memory module. In the corresponding state description information 2, 4, and 5, the dirty flag field is set to indicate a non-dirty state.

[0061] S2. In response to the load instruction for loading the target mapping table, determine whether the remaining space in the buffer memory is sufficient; if not, filter out the mapping tables in the buffer memory that are in an unlocked state indicated by the lock flag, generate a second mapping table set, calculate the second priority coefficient of each mapping table in the second mapping table set according to the access statistics information, and select at least one candidate replacement table with the highest second priority coefficient in the second mapping table set.

[0062] Specifically, during the execution of data read / write tasks, when it is necessary to access a target mapping table that is not yet cached in the buffer memory, a load instruction is generated to load the target mapping table. In response to this load instruction, it is first determined whether the current remaining space in the buffer memory is sufficient to accommodate the target mapping table.

[0063] The buffer memory is divided into multiple fixed-size cache slots (Buffer / Cache, also known as cache units), each of which can hold at least one mapping table. This application also maintains a free slot counter, which records in real time the number of cache slots currently not occupied by any mapping table. When a load instruction arrives, the current value of the free slot counter is read. If the current value of the free slot counter is greater than zero, it indicates that at least one free cache slot exists in the buffer memory, and the remaining space in the buffer memory is sufficient. In this case, the target mapping table is read from the memory module and written to a free cache slot, while the corresponding status description information for the target mapping table is initialized.

[0064] If the current value of the free slot counter is zero, it indicates that all cache slots in the buffer memory are occupied, and there are no free slots available to accommodate a new mapping table. In this case, it is determined that the remaining space in the buffer memory is insufficient. Due to insufficient remaining space, the target mapping table cannot be loaded directly; a cache replacement operation must be performed first to remove an already cached mapping table from the buffer memory to free up at least one free cache slot.

[0065] When it is determined that the remaining space in the buffer memory is insufficient, a filtering operation is performed to determine the range of candidate mapping tables that can be replaced and removed. The filtering operation is based on the locking flags contained in the status description information of each mapping table.

[0066] The locking flag is a separate field in the status description information, stored in the status description information corresponding to each mapping table. The locking flag indicates whether the corresponding mapping table is currently in a protected state and is prohibited from being replaced or removed from the buffer memory. When the locking flag indicates a locked state, the mapping table cannot be replaced or removed. When the locking flag indicates an unlocked state, the mapping table can be replaced or removed. The locking flag can be set according to the operating state; for example, when the mapping table is being written to the memory module or when the mapping table is marked as critical metadata, its locking flag is set to indicate a locked state.

[0067] Iterate through the state descriptions of all currently cached mapping tables in the buffer memory, checking the state indicated by the locking flag of each table. Mapping tables whose locking flag indicates a locked state are excluded from the replacement candidate pool. Mapping tables whose locking flag indicates an unlocked state are retained.

[0068] The remaining mapping tables after the above filtering operations form the second mapping table set. Each element in the second mapping table set corresponds to a mapping table with a lock flag indicating an unlocked state and allowing it to be replaced or moved out.

[0069] The value of the second priority coefficient indicates how suitable the mapping table is to be selected as the replacement object at the current moment. The larger the value of the second priority coefficient, the more preferentially the mapping table should be replaced and removed from the buffer.

[0070] Furthermore, the access statistics also include: historical cumulative replacement count, cumulative write count, cumulative read count, and historical access pattern records; S2. Calculate the second priority coefficient of each mapping table in the second mapping table set based on the access statistics information in the status description information, including: S21. Calculate the function value of the first function, the function value of the second function, and the function value of the third function; the first function is a decreasing function with the cumulative number of reads as the independent variable, the second function is an increasing function with the historical cumulative number of replacements as the independent variable, and the third function is a function with the cumulative number of writes and the dirty flag as independent variables.

[0071] Specifically, for each mapping table in the second mapping table set, the function values ​​of the first function, the second function, and the third function are calculated based on their state description information.

[0072] The first function is a decreasing function with the cumulative number of reads as its independent variable. The cumulative number of reads is obtained from the status description information, and it represents the cumulative number of times the mapping table has been accessed since it was loaded into the buffer memory. The decreasing characteristic of the first function means that the smaller the cumulative number of reads, the larger the function value, and vice versa. Specifically, the first function can be expressed as a function value equal to a preset constant divided by the sum of the cumulative number of reads and 1. The preset constant can be an empirical value such as 100 or 200.

[0073] The second function is an increasing function with the historical cumulative replacement count as its independent variable. The historical cumulative replacement count is obtained from the state description information and represents the total number of times the mapping table has been replaced or moved out of the buffer memory since its creation. The increasing nature of the second function means that the larger the historical cumulative replacement count, the larger the function value, indicating that the mapping table has frequently undergone replacement and should be more prone to being replaced or moved out again. Specifically, the second function can be expressed as a function value equal to the historical cumulative replacement count.

[0074] The third function is a function with the cumulative write count and a dirty flag as independent variables. The cumulative write count is obtained from the status description information, and it represents the cumulative number of logical entries that have been written to or modified since the mapping table was loaded into the buffer memory. The dirty flag is also obtained from the status description information, and it indicates whether the mapping table has been modified relative to its corresponding table in the memory module. The purpose of the third function is to provide replacement protection for mapping tables in a dirty state. That is, when the mapping table is in a dirty state, the function value is positive and positively correlated with the cumulative write count, thereby producing a deduction effect when calculating the second priority coefficient, reducing the probability of it being replaced or removed. Specifically, the third function takes the form where the function value equals the cumulative write count when the dirty flag indicates a dirty state, and equals zero when the dirty flag indicates a non-dirty state.

[0075] The system sequentially reads the cumulative read count, historical cumulative replacement count, cumulative write count, and dirty flag of each mapping table in the second mapping table set, and calculates the first, second, and third function values ​​according to the function definitions described above. After calculation, each function value is associated with the identifier of the mapping table and stored in the internal working register.

[0076] S22. Obtain the fourth weight coefficient of the pre-configured first function, the fifth weight coefficient of the second function, and the sixth weight coefficient of the third function.

[0077] Specifically, before performing the calculation of the second priority coefficient, the pre-configured fourth, fifth, and sixth weight coefficients are obtained. The fourth weight coefficient corresponds to the function value of the first function, the fifth weight coefficient corresponds to the function value of the second function, and the sixth weight coefficient corresponds to the function value of the third function. All three weight coefficients are positive numbers and are pre-stored in a non-volatile configuration register.

[0078] The fourth weighting coefficient adjusts the strength of the influence of the cumulative number of reads on replacement priority. A larger fourth weighting coefficient results in a greater replacement tendency bonus for mapping tables with fewer cumulative reads. The fifth weighting coefficient adjusts the strength of the influence of the historical cumulative number of replacements on replacement priority. A larger fifth weighting coefficient results in a greater replacement tendency bonus for mapping tables that have been frequently replaced. The sixth weighting coefficient adjusts the strength of the dirty state protection mechanism's suppression of replacement priority. A larger sixth weighting coefficient results in a stronger protection effect for mapping tables in a dirty state, and a lower probability of them being replaced.

[0079] The specific values ​​of the fourth, fifth, and sixth weighting coefficients are obtained by reading the corresponding configuration registers. The values ​​of each weighting coefficient can be fixed empirical values ​​preset at the factory. For example, the fourth weighting coefficient can be set to 1, the fifth weighting coefficient to 10, and the sixth weighting coefficient to 1.

[0080] S23. Based on the preset weight coefficients and corresponding function values, calculate the second priority coefficient by weighted summation.

[0081] Specifically, after obtaining the first, second, and third function values, as well as the fourth, fifth, and sixth weighting coefficients corresponding to a single mapping table, the calculation of the second priority coefficient is performed. The calculation follows a preset weighted calculation formula.

[0082] The second priority coefficient is calculated according to the following formula: P replace =α1×f(C read )+α2×g(Eviction count )–α3×h(C update dirty flag ).

[0083] Where P replace This represents the second priority coefficient. α1 represents the fourth weight coefficient, which corresponds to the weight coefficient of the first function; this coefficient is positive. f(C) read The function α1 represents the first function, which is a decreasing function with the cumulative number of reads Cread as its independent variable. The smaller the cumulative number of reads, the larger the function value. α2 represents the fifth weighting coefficient, which corresponds to the weighting coefficient of the second function; this coefficient is positive. g(Eviction) count The second function is Eviction, which is based on the historical cumulative number of replacements. count This is an increasing function of the independent variable; the larger the cumulative number of historical replacements, the larger the function value. α3 represents the sixth weighting coefficient, which corresponds to the weighting coefficient of the third function; this coefficient is positive. h(C) update dirty flag ) represents the third function, which is based on the cumulative number of writes C. update and dirty symbol flag The third function is designed so that when the mapping table is in a dirty state, the function value is positive and positively correlated with the cumulative number of writes. Therefore, it is used as a subtraction term in the calculation formula to reduce the value of the second priority coefficient, reflecting the replacement protection for the mapping table in a dirty state.

[0084] After obtaining the second priority coefficient of each mapping table in the second mapping table set, the candidate replacement table selection operation is performed. The selection operation is based on the value of the second priority coefficient.

[0085] The search operation finds the mapping table with the largest second priority coefficient in the second mapping table set. This is done by sequentially reading the second priority coefficients of each mapping table in the set, retaining the maximum value among the currently compared values ​​and its corresponding mapping table identifier, until all mapping tables in the set have been compared. The final output mapping table identifier is the one with the largest second priority coefficient.

[0086] If multiple mapping tables in the second mapping table set have the same highest second priority coefficient value, the historical cumulative replacement counts of these multiple mapping tables are further compared, and the mapping table with the largest historical cumulative replacement count is selected as the candidate replacement table. If the historical cumulative replacement counts are still the same, the cumulative residence time is compared, and the mapping table with the longest cumulative residence time is selected as the candidate replacement table.

[0087] The selected mapping table is identified as a candidate replacement table, and its identifier is stored in an internal working register. Typically, since only one cache slot needs to be freed up when the remaining space in the buffer memory is insufficient, only one candidate replacement table is selected.

[0088] S3. For each candidate replacement table, if the dirty flag of the candidate replacement table indicates a dirty state, write the candidate replacement table to the memory module and then delete the candidate replacement table from the buffer memory; if the dirty flag indicates a non-dirty state, delete the candidate replacement table directly from the buffer memory.

[0089] Specifically, for each selected candidate replacement table, a replacement and removal operation is performed sequentially. For a single candidate replacement table, the dirty flag contained in the status description information of that candidate replacement table is read first.

[0090] If the dirty flag indicates a dirty state, it means that the candidate replacement table has undergone at least one logical entry write modification since it was last written to the memory module, and the modified content has not yet been written to the memory module. In this case, a write operation is first performed on the candidate replacement table. The write operation includes reading the physical address of the candidate replacement table in the memory module from the status description information, and simultaneously reading the dirty entry bitmap contained in the status description information. The dirty entry bitmap is used to identify which logical entries in the candidate replacement table are in a dirty state. Based on the indication of the dirty entry bitmap, the logical entries in a dirty state are determined, and only the contents of the determined logical entries in a dirty state are written to the corresponding storage location indicated by the physical address in the memory module through the memory interface. After the write operation is completed, the dirty data of the candidate replacement table has been persisted to the memory module.

[0091] Subsequently, the candidate replacement table is deleted from the buffer memory. The deletion operation includes marking the cache slot occupied by the candidate replacement table as free and incrementing the free slot counter by 1. At the same time, the historical cumulative replacement count in the status description information corresponding to the candidate replacement table is updated, and the current value of the historical cumulative replacement count is incremented by 1.

[0092] If the dirty flag indicates a non-dirty state, it means that the contents of the candidate replacement table are completely identical to the corresponding copy stored in the memory module, and there is no modified data to be persisted. In this case, no write operation is required; the candidate replacement table is directly deleted from the buffer memory, releasing the cache slot it occupies, and the value of the free slot counter is incremented by 1. Similarly, the current value of the historical cumulative replacement count in the status description information of the candidate replacement table is incremented by 1.

[0093] After the candidate replacement table is successfully deleted and the cache slot is released, the buffer memory has at least one free slot. The load instruction in step S2 is then executed to read the target mapping table from the memory module into the free slot of the buffer memory. After loading, the corresponding status description information for the target mapping table is initialized. The initialization operation includes setting the dirty flag to indicate a non-dirty state, resetting the cumulative write count to zero, resetting the cumulative read count to zero, resetting the cumulative residence time to zero, checking whether the target mapping table is a marked popular node; if so, its locking flag is set to indicate a locked state; otherwise, it is set to indicate an unlocked state, and the historical cumulative replacement count is set to the initial value of 0.

[0094] S4. In response to a preset trigger event, the mapping tables in a dirty state are filtered out in the buffer memory according to the dirty flag, a first mapping table set is generated, the first priority coefficient of each mapping table in the first mapping table set is calculated according to the access statistics information, the mapping tables in the first mapping table set are sorted according to the first priority coefficient, and a predetermined number of mapping tables are selected according to the sorting result in descending order of the first priority coefficient, and the selected mapping tables are written into the memory module in sequence.

[0095] Specifically, the first priority coefficient is configured to be positively correlated with the write frequency of the mapping table and negatively correlated with the read frequency. The filtering operation is based on the dirty flag in the status description information. It determines whether the dirty flag of each mapping table indicates a dirty state. For mapping tables with a dirty flag, their corresponding mapping table identifier and complete status description information are retained. For mapping tables with a non-dirty flag, the mapping table is removed. Triggering events can include a background timer reaching a specified period interval, the number of mapping tables in a dirty state in the buffer exceeding a preset threshold, and the available storage space in the buffer falling below a preset capacity level. When any of these triggering events occurs, the mapping table write decision process is initiated.

[0096] The remaining mapping tables after the above filtering operations constitute the first mapping table set. Each element in the first mapping table set corresponds to a mapping table that is currently in a dirty state, that is, at least one logical entry of the mapping table has been written to and modified during the current monitoring period and has not yet been written back to the non-volatile memory module. The total number of mapping tables contained in the first mapping table set is also recorded.

[0097] If, after traversal and judgment, the first mapping table set is found to contain no mapping tables (i.e., the set is empty), it indicates that there are no mapping tables in a dirty state in the current buffer memory, and no data needs to be persisted. In this case, the current write decision process is terminated, the running state is switched back to monitoring mode, and the process continues to wait for the next trigger event. This early termination mechanism helps to save computational resources and power consumption by avoiding meaningless subsequent calculations and sorting operations when there is no valid data to write. If the first mapping table set is not empty, the state description information corresponding to each mapping table in the set is kept associated, and the process proceeds to step S3 to calculate the first priority coefficient.

[0098] The first priority coefficient is a quantitative evaluation index used to indicate the suitability of each mapping table in the first mapping table set that is in a dirty state as a writing object at the current moment. It can be calculated by using a preset weighting rule based on the cumulative number of writes, cumulative number of reads and cumulative dwell time extracted from the access statistics. The first priority coefficient is configured to be positively correlated with the writing frequency of the mapping table and negatively correlated with the reading frequency of the mapping table.

[0099] The value of the first priority coefficient has a selection-guiding significance. The larger the first priority coefficient of a mapping table, the more likely the mapping table should be written to the non-volatile memory module. Conversely, the smaller the first priority coefficient, the less suitable the mapping table is to be written in this decision, and it should remain in the buffer memory to serve subsequent read and write requests.

[0100] Furthermore, the access statistics also include: the cumulative number of writes to the mapping table during the current monitoring period, the cumulative number of reads from the mapping table during the current monitoring period, and the cumulative dwell time of the mapping table during the current monitoring period.

[0101] Among them, see Figure 8 As shown, Figure 8 The flowchart of the method for calculating the first priority coefficient provided in the embodiments of this application specifically includes the following steps: S41. Obtain the cumulative number of writes, cumulative number of reads, and cumulative dwell time of the mapping table during the current monitoring period.

[0102] Specifically, after obtaining the first set of mapping tables, the status description information extraction operation is performed sequentially for each mapping table in the set. The specific objects of the extraction operation are the cumulative number of writes, cumulative number of reads, and cumulative dwell time of the mapping table within the current monitoring period. These three data items are all stored in the status description information uniquely corresponding to each mapping table. Each mapping table includes multiple logical entries. If the number of logical entries is extremely large, a compressed bitmap or range list can be used to record dirty entries to reduce storage space usage.

[0103] S42. Obtain the preset first weight coefficient for cumulative write count, the second weight coefficient for cumulative read count, and the third weight coefficient for cumulative dwell time.

[0104] Specifically, the first weighting coefficient corresponds to the cumulative number of writes, the second weighting coefficient corresponds to the cumulative number of reads, and the third weighting coefficient corresponds to the cumulative dwell time. All three weighting coefficients are positive numbers and are pre-stored in non-volatile configuration registers. This application can obtain the specific values ​​of the first, second, and third weighting coefficients by reading the corresponding configuration registers. The values ​​of each weighting coefficient can be dynamically updated during operation or can use fixed empirical values ​​preset at the device's factory. Regardless of the method used, in a single calculation of the first priority coefficient, the first, second, and third weighting coefficients are all used as known constants in the calculation.

[0105] S43. Calculate the first priority coefficient of the mapping table in the current monitoring period based on the weight coefficients and their corresponding parameter values.

[0106] Specifically, after obtaining the cumulative write count, cumulative read count, and cumulative residence time of a single mapping table, as well as the first weight coefficient, second weight coefficient, and third weight coefficient, the calculation operation of the first priority coefficient is performed. The calculation operation follows a preset weighted calculation formula.

[0107] For example, the weighted calculation formula is: P flush =(C update ×β1)+(C residency ×β3)-(C read ×β2), P flush C represents the first priority coefficient. update This represents the cumulative number of writes, β1 represents the first weighting coefficient, and C... residency Indicates the cumulative dwell time, β3 represents the third weighting coefficient, and C readThis represents the cumulative number of reads, and β2 represents the second weighting coefficient. The subtraction term represents the suppression of write priority by read frequency, because frequently read hot tables should be kept in the cache. For example, β1 and β3 can be set to 1, and β2 can be set to a value between 0.5 and 2, which can be dynamically adjusted according to the workload.

[0108] Specifically, after obtaining the first priority coefficient for each mapping table in the first mapping table set, a sorting operation is performed. The sorting operation applies to all mapping table entries in the first mapping table set, and each entry contains a mapping table identifier and its corresponding first priority coefficient. The sorting operation is based on the numerical value of the first priority coefficient, and the sorting order is descending, that is, the mapping table with the largest first priority coefficient value is placed first, and the mapping table with the smallest first priority coefficient value is placed last.

[0109] During the sorting operation, a preset sorting algorithm is used to rearrange the entries in the first mapping table set. The sorting algorithm can be any comparison sorting algorithm, such as bubble sort, quick sort, or merge sort. Internal registers or dedicated buffer units are used as the data exchange space during the sorting process. Regardless of the sorting algorithm used, it is ensured that the identifier of each mapping table and its first priority coefficient remain bound together throughout the sorting operation, without misalignment. After the sorting operation is completed, a complete sorting result is obtained, recording the sequence of the mapping tables in the first mapping table set arranged in descending order of their first priority coefficients.

[0110] Specifically, a mapping table selection operation is performed based on the sorting result generated in step S4. The sorting result records the order in which all mapping tables in the first mapping table set are arranged from high to low according to the first priority coefficient. Starting from the beginning of the sorting result, a predetermined number of mapping tables are selected sequentially as the execution objects for this write operation.

[0111] For example, the predetermined quantity is determined by rounding up to 50% of the total number of mapping tables in the first mapping table set. If the first mapping table set contains 5 mapping tables, then the predetermined quantity is 50% multiplied by 5 and rounded up, which is 3.

[0112] After selecting a mapping table, write operations are initiated sequentially according to the highest priority coefficient. For each selected mapping table, its physical address in the memory module is first read from its corresponding status description information. Subsequently, the modified logical entries of the mapping table in the buffer memory are written to the storage location indicated by that physical address in the memory module through the memory interface.

[0113] Furthermore, the mapping table includes multiple logical entries; The status description information also includes: a dirty entry bitmap, which represents the logical entries in the mapping table that are in a dirty state during the current monitoring period; The selected mapping table is written to the memory module sequentially, including: A1. For each selected mapping table, determine the logical entries in the dirty state in the mapping table according to the dirty entry bitmap of the mapping table, and write only the logical entries in the dirty state into the memory module.

[0114] Specifically, after selecting a mapping table, write operations are initiated one by one in descending order of priority coefficient. For each selected mapping table, its physical address in the memory module is first read from its corresponding status description information. Simultaneously, the dirty entry bitmap contained in the mapping table's status description information is read. A mapping table consists of multiple logical entries, and the dirty entry bitmap indicates which logical entries in the mapping table are in a dirty state during the current monitoring cycle. A dirty state refers to a logical entry whose content has been written or modified but has not yet been written back to the memory module.

[0115] Based on the obtained dirty entry bitmap, the logical entries in a dirty state are identified in the mapping table. Then, only the contents of the identified dirty logical entries are written to the corresponding storage location indicated by the physical address in the memory module via the memory interface. For the remaining logical entries that are not indicated as dirty by the dirty entry bitmap in the mapping table, no write operation is performed. This method of writing only dirty logical entries based on the dirty entry bitmap effectively reduces the total amount of data that needs to be transferred to the memory module for each write operation, thus reducing the write amplification effect.

[0116] After each successful write operation to a mapping table, a reset operation is immediately performed on the table's status description information. The reset operation includes changing the dirty flag from dirty to non-dirty, resetting all flag bits in the dirty entry bitmap to non-dirty, resetting the cumulative write count to zero, resetting the cumulative read count to zero, and resetting the cumulative residency time to zero. After the reset operation is complete, the current monitoring cycle for that mapping table ends. If the mapping table remains in the buffer memory after the write operation, it will enter a new monitoring phase in a non-dirty state until the next logical entry write operation triggers a new current monitoring cycle.

[0117] Understandably, if the number of logical entries in the mapping table is extremely large, resulting in high bitmap overhead, other methods can be used to record the range of dirty entries, such as using a list of starting offsets and lengths (dirty range list) instead of a bitmap. This application does not impose any restrictions on this.

[0118] For example, see Figure 6 As shown, Figure 6The internal logical structure of a mapping table is illustrated exemplarily. This mapping table, denoted as Mapping Table 1, contains multiple logical entries. The diagram exemplarily shows four logical entries: Logical Entry 1, Logical Entry 2, Logical Entry 3, and Logical Entry 4. Each logical entry stores the mapping relationship between a logical address and its corresponding physical address.

[0119] The diagram uses different colors to identify each logical entry. Red indicates logical entries in a dirty state, and green indicates logical entries in a non-dirty state. A dirty state means that the mapping relationship recorded by the logical entry has been written or modified but has not yet been written back to the memory module. A non-dirty state means that the mapping relationship recorded by the logical entry is completely consistent with the corresponding copy stored in the memory module.

[0120] Specifically, logical entries 1 and 4 are marked in red, indicating that these two logical entries are in a dirty state. This means that during the current monitoring period, the mapping relationships corresponding to logical entries 1 and 4 have undergone write modifications, and the modified new mapping relationships have not yet been written to the memory module. Logical entries 2 and 3 are marked in green, indicating that these two logical entries are in a non-dirty state. This means that logical entries 2 and 3 have not been modified during the current monitoring period, and their contents are consistent with the copies stored in the memory module.

[0121] The dirty and non-dirty states of each logical entry in the mapping table are recorded by the dirty entry bitmap field in the state description information. The dirty entry bitmap is a bitmap data structure, where each bit corresponds to a logical entry in the mapping table. When a bit has a specific logical value, it indicates that the corresponding logical entry is in a dirty state. When a bit has another specific logical value, it indicates that the corresponding logical entry is in a non-dirty state. Figure 6 For example, in the dirty entry bitmap corresponding to mapping table 1, the bits corresponding to logical entry 1 and logical entry 4 are set to indicate a dirty state, and the bits corresponding to logical entry 2 and logical entry 3 are set to indicate a non-dirty state.

[0122] Figure 6 The displayed dirty state flags at the logical entry level play a crucial role in implementing partial write functionality. When performing a write operation, instead of writing all logical entries of the entire mapping table to the memory module, the dirty entry bitmap is read, and only the logical entries marked as dirty are written. Figure 6Logical entries 1 and 4, marked in red, are written to the memory module. Logical entries 2 and 3, marked in green (not dirty), are not written to. This method of partial writing based on the dirty entry bitmap effectively reduces the amount of data transferred to the memory module with each write operation, lowers the write amplification factor, and reduces wear on the memory module.

[0123] Furthermore, in an optional embodiment of this application, the method further includes: D1. If the dirty flag indicates a dirty state, the function value output by the third function is the second non-zero positive value; or D2. If the dirty flag indicates a non-dirty state and the cumulative number of writes is greater than the preset update count threshold, the function value output by the third function is the first non-zero positive value, which is greater than the second non-zero positive value.

[0124] Specifically, when calculating the function value of the third function, the function output value is determined based on the dirty flag and the cumulative number of writes in the state description information. Step D1 defines the function output rules when the dirty flag indicates a dirty state.

[0125] When a mapping table's status description information indicates a dirty state with a dirty flag, it means that the mapping table has undergone at least one logical entry write modification during the current monitoring period, and the modified content has not yet been written to the memory module. In this case, the third function outputs a second non-zero positive value. This second non-zero positive value is a pre-set fixed positive number stored in the configuration register. The magnitude of the second non-zero positive value is independent of the specific number of cumulative writes; as long as the dirty flag indicates a dirty state, the third function outputs this fixed positive value. For example, the second non-zero positive value can be 10.

[0126] When calculating the function value of the third function, if the dirty flag indicates a non-dirty state, the function output value is further determined based on the relationship between the cumulative number of writes and the preset update count threshold. Step D2 defines the function output rules when the dirty flag indicates a non-dirty state.

[0127] When the dirty flag in the status description information of a mapping table indicates a non-dirty state, it means that the mapping table has not undergone any logical entry write modifications during the current monitoring period, and its content is completely consistent with the corresponding copy stored in the memory module. In this case, the current value of the cumulative write count is compared with the update count threshold pre-stored in the configuration register. The update count threshold is a preset positive number, such as 5 or 10.

[0128] If the cumulative number of writes exceeds the update count threshold, it indicates that although the mapping table is currently not dirty, it has undergone a certain amount of write modifications during the historical monitoring period, and is therefore a mapping table with a certain level of write activity. To provide appropriate replacement protection for such mapping tables, the function value of the third function is determined to be a first non-zero positive value. The first non-zero positive value is also a pre-set fixed positive number, stored in the configuration register, and the value of the first non-zero positive value is greater than the second non-zero positive value; for example, the first non-zero positive value is 15.

[0129] In an alternative embodiment of this application, see [link to application]. Figure 9 , Figure 9 This is a schematic flowchart of a mapping table prefetching method provided in an embodiment of this application, which specifically includes the following steps: S5. In response to receiving a first read request to access the first mapping table within a preset association time window, and then receiving a second read request to access the second mapping table, and the second mapping table is not hit in the buffer memory, increase the directed association strength value from the first mapping table to the second mapping table in the association metric table.

[0130] Internally, an association metric table is maintained. This table records the directed association strength values ​​between different mapping tables. Specifically, each entry in the association metric table contains three fields: the source mapping table identifier, the target mapping table identifier, and the directed association strength value from the source mapping table to the target mapping table. The directed association strength value indicates the degree of association between accessing the source mapping table and immediately following access to the target mapping table in a historical input / output request sequence. This application allows setting a maximum number of entries for the association metric table; when this maximum number of entries is exceeded, the entry with the lowest association strength is discarded.

[0131] During read request processing, the access order association between mapping tables is continuously monitored. When a read request is received and access to the first mapping table is completed, the identifier of the first mapping table is recorded, and a preset association time window timer is started. The duration of the association time window is a preset time value, such as 100 microseconds or 200 microseconds, and is stored in the configuration register. To prevent the association metric table from growing indefinitely, a maximum number of entries can be set for it. When the number of entries reaches the upper limit, the entry with the lowest directed association strength value can be discarded.

[0132] If a second read request is received within the time frame before the association time window expires, and this second read request accesses the second mapping table, it is further determined whether the second mapping table is currently cached in the buffer memory. If the second mapping table is not found in the buffer memory, i.e., the second mapping table is not currently cached, then this is considered a valid before-after association access event. In this case, the directed association strength value from the first mapping table to the second mapping table is increased.

[0133] The specific procedure for increasing the directed association strength value is as follows: using the first and second mapping table identifiers as indexes, search for the corresponding entry in the association metric table. If the entry already exists, increment the directed association strength value of that entry by a preset increment, for example, by 1. If the entry does not yet exist, create a new entry in the association metric table, set the source mapping table identifier to the first mapping table identifier, set the target mapping table identifier to the second mapping table identifier, and initialize the directed association strength value to the preset increment. The preset increment is stored in the configuration register.

[0134] It should be noted that the directed association strength increase operation is triggered only when the second mapping table is not found in the buffer. This is because if the second mapping table is already cached in the buffer, there is no need to initiate a prefetch operation for it, and the value of recording this association is relatively low. When the second mapping table is not found, it indicates that early prefetching would yield good performance benefits; therefore, strengthening this association record helps with subsequent prefetching decisions.

[0135] S6. In response to the detection that the first mapping table is accessed after the second mapping table is accessed within the preset association time window, and the first mapping table is not hit in the buffer memory, the directed association strength value from the first mapping table to the second mapping table in the association metric table is reduced.

[0136] Specifically, while performing step S5 to strengthen the positive association strength, a directional association strength attenuation operation is also performed based on the reverse access event to maintain the accuracy and timeliness of the association metric table.

[0137] When a sequential access pattern opposite to the positive association is detected within a preset association time window, the directed association strength value is reduced. Specifically, if the second mapping table is accessed first, followed by the first mapping table, and the first mapping table is not found in the buffer memory within the association time window, then the access sequence is determined to be opposite to the positive association direction of the first mapping table pointing to the second mapping table recorded in the association metric table.

[0138] In this scenario, the first mapping table identifier is used as the source mapping table identifier, and the second mapping table identifier is used as the target mapping table identifier as indexes to search for the corresponding entry in the association metric table. If the entry exists and its directed association strength value is greater than zero, the directed association strength value from the first mapping table to the second mapping table recorded for that entry is decreased by a preset decrement value, such as decreasing it by 1. If the directed association strength value drops to zero after the decrement operation, the zero-value entry can be retained or removed from the association metric table to save storage space.

[0139] Step S6 introduces a reverse inhibition mechanism. When the actual access order contradicts the recorded association direction, it indicates that the previously established association may be accidental or has become invalid due to changes in workload. By reducing the directed association strength value, the association metric can dynamically reflect the latest access pattern characteristics, preventing outdated or erroneous association information from interfering with subsequent prefetching decisions.

[0140] Furthermore, in an alternative embodiment of this application, it also includes: S7. In response to the first mapping table being loaded from the memory module into the buffer memory, the association metric table is queried to determine the third mapping table that has the highest directed association strength value with the first mapping table. Specifically, when a mapping table is loaded from the memory module to the buffer memory, a query operation in the associated prefetch decision process is triggered. The mapping table loaded into the buffer memory is denoted as the first mapping table. The first mapping table can be loaded on demand in response to a read request, or it can be loaded proactively by other cache management strategies.

[0141] Using the identifier of the first mapping table as the source mapping table identifier, the association metric table maintained internally by the memory controller is queried. The association metric table stores multiple entries, each containing the source mapping table identifier, the target mapping table identifier, and the directed association strength value from the source mapping table to the target mapping table. All entries whose source mapping table identifier is equal to the first mapping table identifier are selected from the association metric table to form a candidate prefetch target set.

[0142] If the candidate prefetch target set is empty, it indicates that there is no directed association record starting from the first mapping table in the association metric table, and the current prefetch decision process is terminated.

[0143] If the candidate prefetch target set is not empty, search for the target mapping table with the highest directed association strength value within that set. The directed association strength value of each entry is read sequentially using a comparator, retaining the currently compared maximum value and its corresponding target mapping table identifier. After comparison, the target mapping table with the highest directed association strength value is designated as the third mapping table, and the corresponding highest directed association strength value is also recorded.

[0144] S8. If the third mapping table is not currently cached in the buffer memory, and the corresponding highest directed association strength value exceeds the preset prefetch threshold, the third mapping table is prefetched from the memory module to the buffer memory.

[0145] Specifically, after determining the third mapping table and its corresponding highest directed association strength value in step S7, the prefetch condition judgment and prefetch operation are performed.

[0146] First, it is determined whether the third mapping table is currently cached in the buffer memory. The cache slot occupancy status of the buffer memory is checked to see if the third mapping table exists in any cache slot. If the third mapping table is already cached in the buffer memory, the prefetch operation is unnecessary, and the current prefetch decision process is terminated. This application can obtain the input / output load by monitoring the command queue depth or the DMA transfer busy / idle ratio.

[0147] If the third mapping table is not currently cached in the buffer memory, the highest directed association strength value obtained in step S7 is further compared with a preset prefetch threshold. The prefetch threshold is a preset positive number stored in the configuration register, for example, a value of 8 or 10. The prefetch threshold is used to filter prefetch candidates with insufficient association strength, avoiding the occupation of valuable buffer memory space and memory module read bandwidth due to weak association prefetching.

[0148] If the highest directed association strength value is greater than the prefetch threshold, it indicates that the access association between the first and third mapping tables is sufficiently strong, and prefetching the third mapping table is expected to yield high performance benefits. In this case, the prefetch operation is initiated. The prefetch operation includes obtaining the physical address of the third mapping table in the memory module from the status description information or mapping table index, reading the entire contents of the third mapping table from the memory module through the memory interface, and writing the read contents into a free slot in the prefetch isolation area of ​​the buffer memory. After the prefetch operation is completed, the corresponding status description information for the third mapping table is initialized, including setting the dirty flag to indicate a non-dirty state and resetting the cumulative write count, cumulative read count, and cumulative residence time to zero.

[0149] If the highest directed association strength value is less than or equal to the prefetch threshold, it is determined that the association is not sufficient to support the prefetch operation, the current prefetch decision process is terminated, and the third mapping table is not prefetched.

[0150] To reduce the interference of prefetching operations on normal input / output requests, prefetching operations can be scheduled to be performed during the idle period of the memory device's input / output, or prefetching requests can be marked as low-priority requests and handed over to the memory interface for scheduling.

[0151] Specifically, before performing the prefetch operation, this application can further evaluate the first priority coefficient distribution of dirty tables in the current buffer. If there are a large number of high-priority dirty tables to be written, the prefetch operation can be temporarily suppressed, and the persistence of dirty data can be processed first to avoid forcibly replacing high-value dirty tables due to the introduction of new tables, thereby further optimizing write amplification.

[0152] In an optional implementation, when calculating the first priority coefficient of each mapping table in the first mapping table set, an additional forced priority determination is performed for mapping tables with a cumulative write count of zero. The first mapping table set is traversed; if a mapping table is detected to have a cumulative write count of zero in the current monitoring period, the cumulative residence time of that mapping table in the current monitoring period is further obtained. This cumulative residence time is compared with a preset first duration threshold. The first duration threshold is stored in a configuration register, for example, with a value of 500 milliseconds.

[0153] If the cumulative residence time exceeds the first duration threshold, it indicates that although the mapping table has not undergone any write modifications, it is in a dirty state and has remained in the buffer memory for an excessively long time. This may be because the mapping table was marked as dirty at an earlier time, and the cumulative write count was cleared to zero due to partial execution of the flush operation or other reasons, but the dirty flag has not been cleared. To prevent such mapping tables from occupying cache space for extended periods without being processed, the first priority coefficient of the mapping table is directly set to the highest priority value. The highest priority value is a preset special value that is greater than any first priority coefficient value that could be obtained using a conventional weighted calculation formula; for example, it can be set to a preset maximum integer value.

[0154] During the sorting operation, the mapping table with the highest priority value will naturally be placed at the beginning of the sorting result, thus being selected first and written to the memory module. This forces the completion of the write process for the mapping table, clearing its dirty flag and reducing its accumulated residence time to zero.

[0155] In an optional implementation, when performing cache replacement decisions and calculating the second priority coefficients for each mapping table in the second mapping table set, the current command queue depth of the memory controller is first obtained. Command queue depth refers to the total number of read / write commands that have not yet been processed in the command queue of the buffer memory.

[0156] The command queue depth obtained from the read operation is compared with a preset depth threshold. The depth threshold can be stored in a configuration register, for example, with a value of 5. If the command queue depth exceeds the depth threshold, the storage device is determined to be under high load.

[0157] After determining that the storage device is under high load, a pre-configured dynamic adjustment value for the sixth weighting coefficient is obtained. This dynamic adjustment value is a preset value chosen such that when a substitute for the original sixth weighting coefficient is used in the weighted summation calculation, the influence of the third function's value on the second priority coefficient is weakened compared to using the sixth weighting coefficient, while the influence of the first function's value on the second priority coefficient is strengthened. For example, if the original sixth weighting coefficient is 1, the dynamic adjustment value can be set to 0.3 or 0. The dynamic adjustment value is then used to replace the original sixth weighting coefficient and substituted into the calculation formula for the second priority coefficient shown above.

[0158] Because the dynamic adjustment reduces the contribution of the third function's value to the second priority coefficient, the replacement protection obtained by mapping tables in a dirty state or with high write activity is correspondingly weakened. Meanwhile, the contribution of the first function's value to the second priority coefficient is relatively strengthened. This adjustment makes it more inclined to select replacement objects based on the infrequency of cumulative read counts and the jitter of historical cumulative replacement counts under high load conditions, thus accelerating cache space turnover efficiency and alleviating system pressure caused by command queue backlog.

[0159] If the command queue depth does not exceed the depth threshold, the original sixth weight coefficient will continue to be used in the calculation of the second priority coefficient (see the formula for the second priority coefficient above).

[0160] In an optional implementation, when performing the directed association strength increment operation, the logical address interval between the logical address accessed by the first read request and the logical address accessed by the second read request is first obtained. Both the first and second read requests are read requests, wherein the first read request accesses a first mapping table, and the second read request accesses a second mapping table, and the second mapping table is not found in the buffer memory. The logical address interval represents the absolute value of the difference between the logical address accessed by the first read request and the logical address accessed by the second read request.

[0161] An attenuation factor is determined based on the logical address interval. The attenuation factor is a value less than 1, and it is inversely proportional to the logical address interval; that is, the larger the logical address interval, the smaller the attenuation factor, and vice versa. One specific method for determining the attenuation factor is to divide a preset constant by the sum of the logical address interval and the preset constant. For example, when the preset constant is 1, the attenuation factor is equal to 1 divided by the sum of the logical address interval and 1.

[0162] The purpose of introducing the attenuation factor is to ensure that read requests with a small logical address interval have a stronger correlation and should receive a higher correlation strength gain. Conversely, read requests with a large logical address interval may have a random correlation and should receive a lower correlation strength gain.

[0163] The calculated attenuation factor is multiplied by the preset association strength increment to obtain the weighted increment. The preset association strength increment is stored in the configuration register, for example, with a value of 1. The weighted increment is the actual increase in the directed association strength value for this time.

[0164] Using the identifiers of the first and second mapping tables as indexes, find the corresponding entry in the correlation metric table, add the existing directed correlation strength value of the entry to the weighted increment, obtain the updated directed correlation strength value, and write it back to the correlation metric table.

[0165] In one optional implementation, access statistics include cumulative write counts, cumulative read counts, and cumulative dwell time.

[0166] An average access depth record is maintained for each mapping table in the buffer memory. Whenever a mapping table is accessed during the current monitoring period, the command queue depth of the memory controller at that moment is read, and this depth value is used as the cumulative access depth for that mapping table. The command queue depth refers to the total number of unprocessed read / write commands in the command queue. At the end of the current monitoring period, the command queue depth values ​​for each access to the mapping table are summed, and then divided by the number of accesses. The result is the average access depth of the mapping table during the current monitoring period.

[0167] When calculating the first priority coefficient of each mapping table in the first mapping table set, the average access depth corresponding to that mapping table is obtained. The average access depth is then compared with a preset depth threshold. The depth threshold is stored in a configuration register, for example, with a value of 4.

[0168] If the average access depth is greater than the depth threshold, it indicates that the storage device is in a command busy state every time the mapping table is accessed, and the access request for the mapping table experiences a high latency. Therefore, the mapping table is determined to belong to the high latency access mode.

[0169] For mapping tables operating under high-latency access mode, the weight of the cumulative write count is increased when calculating the first priority coefficient. Specifically, the first weight coefficient β1 corresponding to the cumulative write count is multiplied by a preset increase factor, for example, by 2. Let's say the original first weight coefficient β1 was 1, and it becomes 2 after the increase. The first priority coefficient still uses the calculation formula shown above, but β1 has been replaced with the increased value. Because the weight of the cumulative write count is increased, the first priority coefficient of this mapping table will increase accordingly, thus occupying a higher position in the sorting and being written to the memory module more preferentially. This allows mapping tables that are frequently modified in high-latency access mode to be processed promptly, reducing the time dirty data remains and mitigating the risk of subsequent access latency being exacerbated by non-persistent data.

[0170] If the average access depth is not greater than the depth threshold, the memory controller uses the original weighting coefficients to calculate the first priority coefficient.

[0171] In an optional embodiment, after generating the second set of mapping tables, it is detected whether the target mapping table has a sequential access attribute. The sequential access attribute refers to the sequential read / write characteristics of the logical address range corresponding to the mapping table during historical access. One detection method is to read the historical access pattern records contained in the access statistics information of the target mapping table. If the historical access pattern records indicate that the mapping table has been accessed sequentially more frequently than a preset proportion over a period of time, then the target mapping table is determined to have a sequential access attribute.

[0172] If the target mapping table has a sequential access attribute, further filtering is performed on the second mapping table set to find mapping tables that also have a sequential access attribute. The filtering method involves checking the access statistics of each mapping table in the second mapping table set, reading its historical access pattern records, and retaining only mapping tables that are also marked as having a sequential access attribute. The filtering results constitute a sequential elimination candidate subset.

[0173] Subsequently, when selecting a candidate replacement table, priority is given to selection from the sequential elimination candidate subset. Specifically, this priority selection involves first searching the sequential elimination candidate subset for the mapping table with the largest second priority coefficient. If at least one mapping table exists in the sequential elimination candidate subset, it is selected as the candidate replacement table. Only when the sequential elimination candidate subset is empty are selections made from the remaining mapping tables in the second mapping table set.

[0174] The purpose of this priority-based eviction mechanism is that sequential access attributes mean that mapping tables typically experience a concentrated period of access after being loaded, followed by a relatively long period of inactivity, and when their data is reused, it is usually replaced entirely. Prioritizing mapping tables with the same sequential access attributes as replacement targets can improve cache space turnover efficiency and reduce the risk of cache thrashing caused by replacing mapping tables with random access attributes.

[0175] In an optional implementation, when processing a directed association strength value increment operation, the initiator identifiers of the first read request and the second read request are first obtained. The initiator identifiers are used to distinguish read / write requests from different sources, such as identifiers of different processor cores, different virtual machines, or different applications. The initiator identifiers can be extracted from the command header or request attribute fields of the read request.

[0176] The initiator identifier of the first read request is compared with the initiator identifier of the second read request. If the two initiator identifiers are the same, it indicates that the first and second read requests were issued by the same initiator, and there is an application-level correlation in addition to spatial locality. This kind of continuous access to the first and second mapping tables by the same initiator has stronger predictability of correlation and higher expected benefits.

[0177] In this case, a preset homology association strength increment is added. The homology association strength increment is a preset positive number stored in the configuration register, for example, a value of 0.5 or 1. The addition method is to add the current directed association strength value to the homology association strength increment to obtain the updated directed association strength value and write it back to the association metric table.

[0178] If the initiator identifiers of the first read request and the second read request are different, then only the basic increment operation is performed according to the rules described above, and no additional homo-origin association strength increment is added.

[0179] In one optional implementation, during the maintenance of the correlation metric table, the in-degree of each mapping table in the correlation metric table is periodically counted. In-degree refers to the number of entries in the correlation metric table that use a given mapping table as their target mapping table; that is, how many other mapping tables have directed association records pointing to that mapping table. By traversing all entries in the correlation metric table, using the target mapping table identifier of each entry as an index, the number of times each mapping table is pointed to is accumulated, thus obtaining the in-degree value of each mapping table.

[0180] The in-degree of each mapping table obtained from the statistics is compared with a preset popularity threshold. The popularity threshold is stored in the configuration register, for example, with a value of 3. If the in-degree of a mapping table exceeds the popularity threshold, it indicates that multiple different other mapping tables in the association metric have directed associations with this mapping table. This mapping table frequently appears as a subsequent access object in the access sequence and has high global association value. This mapping table is then marked as a popular node.

[0181] For a mapping table marked as a popular node, the lock flag in its state description information is set to indicate a locked state in the buffer. After the lock flag indicates a locked state, the mapping table will be excluded from the replacement candidate range during the filtering operation, will not be added to the second mapping table set, and therefore cannot become a candidate replacement table to be removed from the buffer.

[0182] By locking popular nodes in a buffer, it ensures that frequently accessed mapping tables reside in the buffer for an extended period, preventing them from being repeatedly swapped in and out due to cache replacement. This helps improve the overall cache hit rate of the mapping table and reduces cascading misses caused by missing popular mapping tables.

[0183] In an optional implementation, the step of acquiring the state description information of each mapping table in the buffer memory within the current monitoring period in response to a preset trigger event, and the step of selecting a predetermined number of mapping tables in descending order of priority based on the sorting result and writing them sequentially into the memory module, are executed in parallel in two independent processing contexts. The processing context refers to a concurrently running task execution environment within the memory controller, such as independent hardware threads, firmware tasks, or state machine instances.

[0184] The first processing context is specifically responsible for collecting state description information and generating the first mapping table set. When a preset trigger event occurs, the first processing context traverses all cached mapping tables in the buffer memory, reads the dirty flag, cumulative write count, cumulative read count, and cumulative residence time from the state description information of each mapping table, filters mapping tables whose dirty flags indicate a dirty state, and generates the first mapping table set. Then, it calculates the first priority coefficient of each mapping table in the first mapping table set, completes the sorting, and generates the sorting result. The sorting result is stored in a memory area shared by the two processing contexts.

[0185] The second processing context is specifically responsible for executing write operations. The second processing context continuously monitors the shared memory region for newly generated sorting results from the first processing context. Once a valid sorting result is detected, the second processing context immediately reads the sorting order from the sorting result, selects a predetermined number of mapping tables in descending order of the first priority coefficient, and sequentially executes the write operation to the memory module.

[0186] The two processing contexts exchange data via a shared memory area and synchronize using flags or semaphores. The first processing context sets a data-ready flag before writing a new sorting result, and the second processing context clears the flag after reading the sorting result. While the second processing context is performing a write operation, the first processing context can simultaneously handle the collection and sorting of status description information for the next monitoring cycle, without blocking each other.

[0187] By separating information collection sorting and writing operations into independent parallel processing contexts, it helps to avoid the problem of information collection delay caused by long writing operation time when executed serially in a single thread, thereby improving the overall response speed and system throughput of the brush decision process.

[0188] In one optional implementation, the buffer memory is divided into two logical regions: a normal buffer and a prefetch isolation region. The normal buffer stores mapping tables obtained through on-demand loading or prefetch operations that have been verified as valid. The prefetch isolation region stores mapping tables loaded by prefetch operations but not yet accessed and verified. The size ratio of the two regions can be set by a configuration register; for example, the normal buffer may occupy 80% of the total buffer memory capacity, and the prefetch isolation region may occupy 20%.

[0189] When the third mapping table needs to be prefetched into the buffer memory, it is not written directly to the normal buffer, but rather to a free slot in the prefetch isolation area. After writing, the state description information for the third mapping table is initialized, and a preset verification cycle timer is started. The duration of the verification cycle is stored in the configuration register, for example, with a value of 100 milliseconds.

[0190] If a read request to access the third mapping table is received during the verification period, it indicates that the prefetch operation successfully predicted future access demands, and the third mapping table has caching value. The third mapping table is then promoted from the prefetch isolation area to the normal cache area, the cumulative read count in its status description is incremented by 1, and the verification period timer is cleared.

[0191] If the verification period timer times out, and the third mapping table is not accessed by any read requests during that verification period, it indicates that the prefetch operation has failed to generate any real benefit. Continuing to occupy cache space with the third mapping table will cause cache pollution. The third mapping table should be directly removed from the prefetch isolation area to release the slots it occupies, and it should not be promoted to the normal cache area.

[0192] By combining the prefetch isolation zone with the verification cycle, the actual value of prefetch operations can be effectively determined, valuable prefetch results can be retained, and invalid prefetches can be cleared in a timely manner. This improves the cache hit rate while avoiding the waste of limited cache space caused by prefetching.

[0193] In one optional implementation, each time a mapping table is loaded or updated in the buffer memory, the logical address range covered by that mapping table within the current monitoring cycle is recorded. The logical address range is defined by a start logical address and an end logical address. The logical address range information of each mapping table is stored in its corresponding status description information.

[0194] At a predetermined statistical time, all currently cached mapping tables in the buffer memory are sorted according to the logical address range they cover. The sorting is based on the starting logical address of each mapping table, and the sorting direction is ascending. After sorting, the logical address interval between each pair of adjacent mapping tables in the sorted sequence is calculated. The logical address interval is equal to the difference between the starting logical address of the next mapping table and the ending logical address of the previous mapping table.

[0195] The calculated logical address interval between each adjacent mapping table is compared with a preset interval threshold. The interval threshold is stored in a configuration register, and its value is, for example, 0 or a small positive integer. If the logical address interval between two adjacent mapping tables is less than the interval threshold, it indicates that the logical address ranges covered by the two mapping tables are closely adjacent and have a strong spatial correlation. The two adjacent mapping tables are then marked as a spatially correlated pair.

[0196] After generating the first set of mapping tables, check whether each mapping table in the first set belongs to a certain spatial association pair. If a mapping table belongs to a spatial association pair, further check whether the other mapping table in that spatial association pair also exists in the first set of mapping tables. If both mapping tables are in a dirty state, set the first priority coefficient of these two mapping tables to the same value. This same value is taken from the higher of the original first priority coefficients of the two tables, or set to the preset highest priority value.

[0197] During the sorting operation, the two mapping tables are arranged in adjacent positions because they have the same first priority coefficient and adjacent logical addresses, thus being selected consecutively and written to the memory module in sequence. Writing spatially associated mapping tables consecutively helps reduce the write addressing overhead of the memory module and improves write efficiency.

[0198] In an optional implementation, after obtaining the sorting results and selecting a predetermined number of mapping tables, the size of each selected mapping table is obtained. The size of the mapping table can be read from its status description information or calculated based on the logical address range covered by the mapping table and the size of each logical entry.

[0199] The memory module maintains a currently active write block, which is a physical memory block within the memory module currently designated to receive write data. This physical memory block has a fixed number of programmable pages. The memory controller internally maintains a remaining programmable page counter to record the number of pages in the currently active write block that have not yet been programmed.

[0200] When writing the selected mapping tables to the memory module in sequence, the memory controller does not strictly follow the fixed order of the first priority coefficient from high to low, but adjusts the writing order according to the matching relationship between the size of each mapping table and the number of remaining programmable pages.

[0201] Specifically, among the selected mapping tables, priority is given to searching for mapping tables whose size is less than or equal to the number of remaining programmable pages in the currently active write block. If a mapping table that meets this condition is found, it is written to the currently active write block. After the write is complete, the value of the remaining programmable page counter is updated. If the number of remaining programmable pages in the currently active write block is exactly zero, the currently active write block is closed, and a new physical storage block is opened as the new currently active write block.

[0202] By prioritizing the writing of mapping tables whose size matches the remaining space, the currently active write block can be naturally filled with valid data from the mapping table without having to write filler data into the unfilled remaining space. This helps improve the storage space utilization of the memory module and reduces the additional write overhead caused by filler data.

[0203] In an optional implementation, a list of blocks awaiting reclamation is maintained in the memory module. This list records physical blocks that have been marked as awaiting reclamation. A physical block is marked as awaiting reclamation if all valid data in that physical block has been moved to another physical block, or if the proportion of invalid data pages in that physical block exceeds a preset garbage collection threshold. Each entry in the list contains an identifier for the corresponding physical block and its erase count. The erase count records the cumulative number of times the physical block has been erased since it was put into use.

[0204] When performing a write operation, if the number of remaining programmable pages in the currently active write block is less than the size of the smallest pending write table in the first set of mapping tables, it indicates that the remaining space in the currently active write block is insufficient to accommodate any pending write tables. In this case, write operations to the currently active write block are paused, and the list of blocks to be reclaimed is checked instead.

[0205] The process iterates through each entry in the list of blocks to be reclaimed, compares the number of erases for each physical block, and selects the physical block with the fewest erases. Selecting the physical block with the fewest erases helps to achieve wear leveling among the physical blocks of the memory module, extending the overall lifespan of the memory module.

[0206] An erase operation is performed on the selected physical block, restoring all its memory cells to a programmable state. After erasure, the physical block is designated as the new currently active write block. The mapping table to be written is written to this new currently active write block, and the value of the remaining programmable page counter is updated.

[0207] Simultaneously, the previously active write block is closed. Remaining pages in the previously active write block that have not yet been programmed are marked as skipped pages. The location information of the skipped pages, including their starting page number and quantity, is recorded in the metadata area of ​​the physical block. This skipped page record information will be read during subsequent garbage collection operations so that the garbage collection task can correctly skip these unused pages when moving valid data from the physical block, thus improving garbage collection efficiency.

[0208] In one embodiment, a prefetching and load / dirty table suppression scheme based on the aforementioned correlation metric table is also proposed, wherein the memory controller 123 performs active and correlation-based prefetching operations according to the aforementioned correlation metric table.

[0209] Specifically, when any mapping table (e.g., the first mapping table) is loaded from the memory module 122 to the buffer memory 24 due to a missing read request, the memory controller 123 will use the newly loaded table as the triggering reference to start the prefetch evaluation.

[0210] In detail, the association metric table is queried to find the third mapping table with the highest directed association strength value with the first mapping table. This third mapping table is the one that the memory controller 123 predicts is most likely to be accessed next. If the check finds that the third mapping table is not currently cached in the buffer memory 24, and its highest directed association strength value with the first mapping table exceeds a preset prefetch threshold, then the prefetch condition is met. The memory controller 123 then proactively prefetches the third mapping table from the memory module 122 into the buffer memory 24.

[0211] However, blind prefetching may compete with the core data protection processes of storage device 12 (such as dirty data write-back) for the resources of memory controller 123, and may even interfere with the foreground load. Therefore, in one embodiment, multiple safeguards and constraints are designed for prefetching operations.

[0212] First, there are input / output limitations. Before actually prefetching the third mapping table from memory module 122 to buffer memory 24, memory controller 123 monitors the input / output load of storage device 12. This load can be measured by metrics such as the total number of I / O requests processed over a period of time and the average queue depth. The prefetching operation is only allowed when the input / output load is determined to be below a preset load threshold, i.e., when storage device 12 is relatively idle. This ensures that prefetching does not occur when storage device 12 is busy, thereby preventing contention for resources of memory controller 123.

[0213] Secondly, there is the issue of dirty mapping table count suppression. If there is an excessive backlog of dirty mapping tables, it indicates a significant risk of power failure for storage device 12. In this case, all backend / background write resources are prioritized for urgent write-back operations. Before performing prefetching, the number of mapping tables currently in a dirty state in buffer memory 24 is obtained. If this number exceeds a preset dirty mapping table suppression threshold, the primary issue is determined to be data consistency, and therefore prefetching is temporarily suspended. However, to avoid missing this opportunity, the identifier of the third mapping table is temporarily recorded in a prefetch queue. Subsequently, when the number of dirty mapping tables falls below the preset dirty mapping table suppression threshold, it indicates a data pressure phase, and prefetch requests in the prefetch queue are processed sequentially. Considering the timeliness of prefetch information, if the waiting time for a prefetch request in the prefetch queue is too long, its value will decrease or even become invalid. Therefore, if the waiting time for a prefetch request in the prefetch queue exceeds a preset prefetch validity period threshold, the prefetch request is removed from the prefetch queue and no longer executed.

[0214] Next, the prefetch data is isolated and verified. To prevent inaccurate prefetching from occupying the cache space of the buffer memory 24, in one embodiment, the buffer memory 24 is logically divided into two regions: a normal cache area and a prefetch isolation area. All third mapping tables obtained based on association prediction are written to the prefetch isolation area during initial loading, instead of being directly placed in the normal cache area. Furthermore, the memory controller 123 sets a preset verification period for the prefetch table. During this verification period, if the third mapping table in the prefetch isolation area is accessed and hit by the host system 11, it indicates that the prediction was successful. At this time, the memory controller 123 will move this third mapping table from the prefetch isolation area to the normal cache area, giving it the same buffer memory 24 space usage / residency rights as other hot tables. Conversely, if it is not accessed during the entire verification period, it indicates that the prefetch is invalid, and the memory controller 123 will directly delete this third mapping table from the prefetch isolation area, and the space it occupies will be quickly reclaimed.

[0215] Furthermore, to prevent recently evicted mapping tables from being immediately prefetched, a recent evicting record table is introduced in one embodiment. This table uses a sliding time window to record the identification information of all mapping tables that have been replaced or removed from the buffer memory 24 within a recent period. Before performing the prefetch operation of the third mapping table, the memory controller 123 first queries the recent evicting record table. If the identifier of the third mapping table is detected in the recent evicting record table, it means that it has just been determined to be of low value and evicted. Prefetching it immediately at this time would lead to a waste of resources. Therefore, the memory controller 123 will not perform the prefetch and will mark the third mapping table as a prefetch pending state. Only when the sliding time window slides out and the evicting record expires and disappears will the memory controller 123 re-evaluate whether it meets the prefetch conditions.

[0216] Finally, the prefetch threshold itself is not static. The memory controller 123 needs to dynamically adjust its sensitivity based on the prefetch results. The memory controller 123 continuously monitors the cache hit rate and average read request latency. If these metrics deteriorate, it indicates that the buffer memory 24 has failed to prepare the required data in advance. In this case, the prefetch threshold will be lowered to make associative prefetching easier to trigger, thereby more aggressively performing data prefetching to proactively improve the hit rate and latency. Conversely, if the cache hit rate is already high (above the preset fifth threshold), it indicates that prefetching is already sufficient or even potentially excessive. To conserve resources, the memory controller 123 will appropriately increase the prefetch threshold, raising the prefetch threshold and reducing unnecessary prefetch operations.

[0217] Figures 6 to 9 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 6 to 9 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 6 to 9 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0218] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized in that, Applied to a storage device including a memory module and a memory controller, the memory controller including a buffer memory storing a mapping table representing the mapping relationship between logical addresses and physical addresses, the method includes: Obtain the status description information of each mapping table in the buffer memory. The status description information includes: a dirty flag indicating whether the mapping table has been modified relative to the corresponding mapping table in the memory module, a locking flag indicating whether the mapping table is prohibited from being replaced or removed from the buffer memory, and access statistics of the mapping table. In response to the load instruction for loading the target mapping table, determine whether there is sufficient remaining space in the buffer memory; if not, filter out the mapping tables in the buffer memory that are in an unlocked state indicated by the lock flag, generate a second mapping table set, calculate the second priority coefficient of each mapping table in the second mapping table set based on access statistics, and select at least one candidate replacement table with the highest second priority coefficient in the second mapping table set. For each candidate replacement table, if the dirty flag indicates a dirty state, the candidate replacement table is written to the memory module and then deleted from the buffer memory; if the dirty flag indicates a non-dirty state, the candidate replacement table is directly deleted from the buffer memory. In response to a preset trigger event, the system filters out the mapping tables in a dirty state from the buffer memory according to the dirty flag, generates a first mapping table set, calculates the first priority coefficient of each mapping table in the first mapping table set according to access statistics, sorts the mapping tables in the first mapping table set based on the first priority coefficient, selects a predetermined number of mapping tables in descending order of the first priority coefficient based on the sorting result, and writes the selected mapping tables into the memory module in sequence. The first priority coefficient is configured to be positively correlated with the writing frequency of the mapping table and negatively correlated with the reading frequency of the mapping table.

2. The method according to claim 1, characterized in that, The mapping table includes multiple logical entries; The status description information also includes: a dirty entry bitmap, which represents logical entries in the mapping table that are in a dirty state during the current monitoring period, where the current monitoring period is an independent time window defined by a preset trigger time; The step of sequentially writing the selected mapping table into the memory module includes: For each selected mapping table, based on the dirty entry bitmap of the mapping table, the logical entries in the dirty state are determined in the mapping table, and only the logical entries in the dirty state are written into the memory module.

3. The method according to claim 1, characterized in that, The access statistics also include: historical cumulative replacement count, cumulative write count, and cumulative read count; The step of calculating the second priority coefficient of each mapping table in the second mapping table set based on the access statistics information in the status description information includes: Calculate the function values ​​of the first function, the second function, and the third function; The first function is a decreasing function with the cumulative number of reads as the independent variable, the second function is an increasing function with the historical cumulative number of replacements as the independent variable, and the third function is a function with the cumulative number of writes and the dirty flag as independent variables. Obtain the pre-configured fourth weight coefficient of the first function, the fifth weight coefficient of the second function, and the sixth weight coefficient of the third function; The second priority coefficient is calculated by weighted summation based on the preset weight coefficients and corresponding function values.

4. The method according to claim 3, characterized in that, If the dirty flag indicates a dirty state, the function value output by the third function is a second non-zero positive value; or If the dirty flag indicates a non-dirty state and the cumulative number of writes is greater than the preset update count threshold, the function value output by the third function is a first non-zero positive value, which is greater than the second non-zero positive value.

5. The method according to claim 1, characterized in that, The memory controller maintains an association metric table, which records the directed association strength values ​​between the first mapping table and the second mapping table. The method further includes: In response to receiving a first read request to access the first mapping table within a preset association time window, and then receiving a second read request to access the second mapping table, and the second mapping table is not found in the buffer memory, the directed association strength value from the first mapping table to the second mapping table in the association metric table is increased; or In response to the first mapping table being accessed after the second mapping table is accessed within a preset association time window, and the first mapping table not being hit in the buffer memory, the directed association strength value from the first mapping table to the second mapping table in the association metric table is reduced.

6. The method according to claim 5, characterized in that, The method further includes: In response to the first mapping table being loaded from the memory module into the buffer memory, the association metric table is queried to determine a third mapping table that has the highest directed association strength value with the first mapping table; If the third mapping table is not currently cached in the buffer memory, and the corresponding highest directed association strength value exceeds a preset prefetch threshold, the third mapping table is prefetched from the memory module to the buffer memory.

7. The method according to claim 3, characterized in that, The calculation of the second priority coefficient of each mapping table in the second mapping table set further includes: Obtain the command queue depth of the memory controller; If the depth of the command queue exceeds a preset depth threshold, the storage device is determined to be in a high-load state. Under the high load condition, the pre-configured dynamic adjustment value of the sixth weighting coefficient is obtained and used to replace the original sixth weighting coefficient in the calculation; The dynamic adjustment value makes the influence of the function value of the third function on the second priority coefficient weaker than when the sixth weight coefficient is used, and the influence of the function value of the first function on the second priority coefficient is enhanced.

8. The method according to claim 5, characterized in that, Increasing the directed association strength value from the first mapping table to the second mapping table in the association metric table specifically includes: Obtain the logical address interval between the second read request and the first read request; Based on the logical address interval, an attenuation factor less than 1 is determined, wherein the attenuation factor is inversely proportional to the logical address interval; The attenuation factor is multiplied by a preset correlation strength increment to obtain a weighted increment, and the directed correlation strength value is updated with the weighted increment.

9. The method according to claim 1, characterized in that, The access statistics include: cumulative write count, cumulative read count, and cumulative dwell time; The calculation of the first priority coefficient for each mapping table in the first mapping table set further includes: The average access depth of the memory controller is obtained when the mapping table is accessed during the current monitoring period. If the average access depth is greater than a preset depth threshold, the mapping table is determined to belong to a high-latency access mode. For mapping tables that belong to the high-latency access mode, when calculating the first priority coefficient, the weight of the cumulative write count in the calculation of the first priority coefficient is increased.

10. The method according to claim 9, characterized in that, The first priority coefficient is further configured as follows: If, during the current monitoring period, any mapping table is not written to and the cumulative residence time of the mapping table in the buffer memory exceeds a preset first duration threshold, the first priority coefficient of the mapping table is set to the highest priority value to force it to be written to the memory module first.

11. The method according to claim 1, characterized in that, After generating the second mapping table set, the process further includes: Detect whether the target mapping table has a sequential access attribute; If so, then in the second set of mapping tables, select mapping tables that also have the sequential access attribute and generate a sequential elimination candidate subset; The step of selecting at least one candidate replacement table with the highest second priority coefficient in the second mapping table set includes: Prioritize selection from the candidate subset eliminated in the aforementioned order.

12. The method according to claim 5, characterized in that, The method of increasing the directed correlation strength value also includes: Distinguish the initiator identifiers of the first read request and the second read request; If the first read request and the second read request have the same initiator identifier, then a preset homogeneous association strength increment is added to the increased directed association strength value.

13. The method according to claim 5, characterized in that, The method further includes: In the correlation metric table, each mapping table is considered as the in-degree of the node to which it is pointed, and the in-degree represents how many other mapping tables point to that mapping table. Maps with in-degrees exceeding a preset popularity threshold are marked as popular nodes; For a mapping table marked as a popular node, set the lock flag in its state description information to indicate a locked state to prevent it from being eliminated as a candidate replacement table.

14. The method according to claim 1, characterized in that, The steps of selecting a predetermined number of mapping tables based on the sorting results and in descending order of the first priority coefficient, and writing the selected mapping tables sequentially into the memory module, and the step of obtaining the state description information of each mapping table in the buffer memory, are executed in parallel in their respective independent processing contexts.

15. The method according to claim 6, characterized in that, The method further includes: The buffer memory is divided into a normal buffer area and a prefetch isolation area; Write the prefetched third mapping table into the prefetch isolation area; If the third mapping table in the prefetch isolation area is accessed within the preset verification period, it is promoted to the normal cache area. If the third mapping table is not accessed within the verification period, it is directly deleted from the prefetch isolation area.

16. The method according to claim 1, characterized in that, The method further includes: Within the current monitoring period, record the logical address range covered by each mapping table; Sort each mapping table according to the logical address range it covers, and calculate the logical address interval between adjacent mapping tables; If the logical address interval between adjacent mapping tables is less than a preset interval threshold, then the two adjacent mapping tables are marked as a spatial association pair. After filtering out the mapping tables in a dirty state from the buffer memory according to the dirty flag and generating the first mapping table set, the method further includes: If any dirty mapping table in the first mapping table set belongs to a certain spatial association pair, and another mapping table in that spatial association pair is also in a dirty state, then the first priority coefficient of these two mapping tables is set to the same value so that they are written to the memory module consecutively.

17. The method according to claim 1, characterized in that, The step of writing the selected mapping table into the memory module sequentially further includes: Get the size of each selected mapping table; In the memory module, a currently active write block is maintained, and the currently active write block has a number of remaining programmable pages; When writing the selected mapping tables sequentially, mapping tables with a size less than or equal to the number of remaining programmable pages are preferentially selected for writing, so that the currently active write block is filled without needing to be filled with data.

18. The method according to claim 17, characterized in that, The method further includes: The memory module maintains a list of blocks to be reclaimed, which records the physical blocks that have been marked as pending reclamation. If the number of remaining programmable pages of the currently active write block is less than the size of the smallest write mapping table in the first mapping table set, then check the list of blocks to be reclaimed. Select the physical block with the fewest erase counts from the list of blocks to be reclaimed, and use it as the new currently active write block. Then, write the mapping table to be written into the new currently active write block. At the same time, the remaining pages in the currently active write block that have not yet been programmed are marked as skipped pages, and the skipped page positions are recorded in the metadata of the block for reference during subsequent garbage collection.

19. The method according to claim 6, characterized in that, The method further includes: Before performing the prefetch operation, obtain the number of mapping tables in the buffer memory that are currently processing dirty states; If the number of dirty mapping tables exceeds a preset dirty mapping table suppression threshold, the operation of prefetching the third mapping table into the buffer memory will not be performed for the time being. Instead, the identifier of the third mapping table will be recorded in a prefetch queue. When the number of dirty mapping tables is detected to fall below the preset dirty mapping table suppression threshold, the prefetch requests in the prefetch queue are processed sequentially. If the waiting time of a prefetch request in the prefetch queue exceeds a preset prefetch validity period threshold, then the prefetch request is removed from the prefetch queue.

20. A storage device, characterized in that, include: A connection interface for electrically connecting to a host computer; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 19.

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