Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes a first type of gate driving circuit and a pixel circuit. The pixel circuit includes a target pixel circuit, and the target pixel circuit and the first type of gate driving circuit are arranged in a first direction. The target pixel circuit is electrically connected to a target data line, and the first type of gate driving circuit is electrically connected to a first type of clock line. Both the target data line and the first type of clock line extend along the first direction. In a second direction, the target data line is located on one side of the target pixel circuit, and at least one first type of clock line electrically connected to the first type of gate driving circuit is located on the other side of the target pixel circuit. The first direction and the second direction intersect. According to the embodiments of this application, the wiring design in the display panel can be optimized.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and users are demanding more and more display quality from display panels.

[0003] The display panel includes micro LED (micro light-emitting diode) or OLED (organic light-emitting diode) type display panels. To meet the driving requirements of the display panel, it is equipped with pixel circuits and gate driving circuits. The gate driving circuit provides gate driving signals to the pixel circuit, which drives the light-emitting elements to emit light. The gate driving circuit is electrically connected to the clock line, and the pixel circuit is electrically connected to the data line.

[0004] In related technologies, there are parasitic capacitances between clock lines and data lines. How to optimize the routing design in the display panel is a technical problem faced by those skilled in the art. Summary of the Invention

[0005] This application provides a display panel and display device that can optimize the wiring design in the display panel.

[0006] In a first aspect, embodiments of this application provide a display panel, including a first type of gate driving circuit and a pixel circuit. The pixel circuit includes a target pixel circuit, and the target pixel circuit and the first type of gate driving circuit are arranged in a first direction. The target pixel circuit is electrically connected to a target data line, and the first type of gate driving circuit is electrically connected to a first type of clock line. Both the target data line and the first type of clock line extend along the first direction. In a second direction, the target data line is located on one side of the target pixel circuit, and at least one first type of clock line electrically connected to the first type of gate driving circuit is located on the other side of the target pixel circuit. The first direction and the second direction intersect.

[0007] In some possible implementations of the first aspect, the pixel circuit includes a data writing module and a driving module. A first end of the data writing module is electrically connected to a data line, a second end of the data writing module is electrically connected to the driving module, and the output end of the first type of gate driving circuit is electrically connected to the control end of the data writing module.

[0008] In some possible implementations of the first aspect, the pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, the first type of gate driving circuit includes a first gate driving circuit and a second gate driving circuit, the signal output by the first gate driving circuit is used to control the writing of the data signal of the amplitude modulation sub-circuit, the signal output by the second gate driving circuit is used to control the writing of the data signal of the pulse width modulation sub-circuit, and the target pixel circuit includes a first target pixel circuit and a second target pixel circuit, the first target pixel circuit and the first gate driving circuit are arranged in a first direction, and the second target pixel circuit and the second gate driving circuit are arranged in a first direction; The first type of clock line includes a first clock line and a second clock line. The first gate driving circuit is electrically connected to the first clock line, and the second gate driving circuit is electrically connected to the second clock line. The target data line includes a first target data line and a second target data line. The first target data line is electrically connected to the amplitude modulation sub-circuit, and the second target data line is electrically connected to the pulse width modulation sub-circuit. In the second direction, the first target data line is located on one side of the first target pixel circuit, and at least one first clock line electrically connected to the first gate driving circuit is located on the other side of the first target pixel circuit; and / or, in the second direction, the second target data line is located on one side of the second target pixel circuit, and at least one second clock line electrically connected to the second gate driving circuit is located on the other side of the second target pixel circuit.

[0009] In some possible implementations of the first aspect, in the second direction, the first target data line and the second target data line are located on both sides of the target pixel circuit, respectively.

[0010] In some possible implementations of the first aspect, in the second direction, the first target data line is located on one side of the first target pixel circuit, and at least two [L3.1] first clock lines electrically connected to the first gate drive circuit are located on the other side of the first target pixel circuit; and / or, the second target data line is located on one side of the second target pixel circuit, and at least two [L4.1] second clock lines electrically connected to the second gate drive circuit are located on the other side of the second target pixel circuit.

[0011] In some possible implementations of the first aspect, the second target data line electrically connected to the first target pixel circuit is located on the same side of the first target pixel circuit; and / or, the first target data line electrically connected to the second target pixel circuit is located on the same side of the second target pixel circuit.

[0012] In some possible implementations of the first aspect, the display panel includes a center line extending along a first direction, and a first area and a second area on either side of the center line along a second direction. The distance between the first gate driving circuit of the first region and the center line is equal to the distance between the first gate driving circuit of the second region and the center line. And / or, the distance between the second gate drive circuit of the first region and the center line is equal to the distance between the second gate drive circuit of the second region and the center line.

[0013] In some possible implementations of the first aspect, for the pixel circuits of the first and second regions, the data lines electrically connected to the amplitude modulation sub-circuit are located on the first side of the pixel circuit, and the data lines electrically connected to the pulse width modulation sub-circuit are located on the second side of the pixel circuit.

[0014] In some possible implementations of the first aspect, the first clock line in the first region is located on the side of the first gate drive circuit away from the center line, and the first clock line in the second region is located on the side of the first gate drive circuit closer to the center line. And / or, the second clock line in the first region is located on the side of the second gate drive circuit closer to the center line, and the second clock line in the second region is located on the side of the second gate drive circuit farther from the center line.

[0015] In some possible implementations of the first aspect, for the pixel circuit in the first region, the data line electrically connected to the amplitude modulation sub-circuit is located on the first side of the pixel circuit, and the data line electrically connected to the pulse width modulation sub-circuit is located on the second side of the pixel circuit. For the pixel circuit in the second region, the data lines electrically connected to the amplitude modulation sub-circuit are located on the second side of the pixel circuit, and the data lines electrically connected to the pulse width modulation sub-circuit are located on the first side of the pixel circuit.

[0016] In some possible implementations of the first aspect, the first clock line in the first region is located on the side of the first gate drive circuit away from the center line, and the first clock line in the second region is located on the side of the first gate drive circuit away from the center line. And / or, the second clock line in the first region is located on the side of the second gate drive circuit closer to the center line, and the second clock line in the second region is located on the side of the second gate drive circuit closer to the center line.

[0017] In some possible implementations of the first aspect, the display panel includes a first region and a second region arranged along a second direction, wherein, in the second direction, a second gate driving circuit in the first region is located between the first gate driving circuit in the first region and the second region, and a first gate driving circuit in the second region is located between the second gate driving circuit in the second region and the first region.

[0018] In some possible implementations of the first aspect, the first target data line and the second target data line electrically connected to the first target pixel circuit are located on one side of the first target pixel circuit, and the first clock line electrically connected to the first gate drive circuit is located on the other side of the first target pixel circuit. And / or, the first target data line and the second target data line electrically connected to the pixel circuit of the second mu are located on one side of the second target pixel circuit, and the second clock line electrically connected to the second gate drive circuit is located on the other side of the second target pixel circuit.

[0019] In some possible implementations of the first aspect, the display panel includes a center line extending along a first direction, and a first area and a second area on either side of the center line along a second direction. The distance between the first gate driving circuit of the first region and the center line is equal to the distance between the first gate driving circuit of the second region and the center line. And / or, the distance between the second gate drive circuit of the first region and the center line is equal to the distance between the second gate drive circuit of the second region and the center line.

[0020] In some possible implementations of the first aspect, in the second direction, the first target data line electrically connected to the first target pixel circuit and at least one first clock line electrically connected to the first gate drive circuit are located on the same side of the first target pixel circuit; and / or, the second target data line electrically connected to the second target pixel circuit and at least one second clock line electrically connected to the second gate drive circuit are located on the same side of the second target pixel circuit.

[0021] In some possible implementations of the first aspect, the first clock line is electrically connected to the input terminal of the output module in the first gate drive circuit, or the first clock line is electrically connected to the control terminal of the input module in the first gate drive circuit, and the first clock line transmits a first clock signal. The second clock line is electrically connected to the input terminal of the output module in the second gate drive circuit, or the second clock line is electrically connected to the control terminal of the input module in the second gate drive circuit, and the second clock signal line transmits the second clock signal. The rising edges of the first clock signal and the second clock signal are staggered.

[0022] In some possible implementations of the first aspect, the rising edges of the first clock signal and the second clock signal are staggered by at least 0.5µs.

[0023] In some possible implementations of the first aspect, the display panel further includes a second type of gate driving circuit, wherein the rising edge of the clock signal received by the second type of gate driving circuit is staggered from the rising edge of the first clock signal and the rising edge of the second clock signal.

[0024] In some possible implementations of the first aspect, the display panel further includes a second type of gate driving circuit, the target pixel circuit includes a third target pixel circuit, the third target pixel circuit and the second type of gate driving circuit are arranged in a first direction, and the second type of gate driving circuit is electrically connected to a second type of clock line. In the second direction, the data line electrically connected to the third target pixel circuit is located on one side of the third target pixel circuit, and at least one second-type clock line electrically connected to the second-type gate drive circuit is located on the other side of the third target pixel circuit.

[0025] In some possible implementations of the first aspect, the display panel further includes a second type of gate driving circuit, and the target pixel circuit includes a third target pixel circuit, with the third target pixel circuit and the second type of gate driving circuit arranged in a first direction. In the second direction, the second type of clock line electrically connected to the second type of gate drive circuit is located on the side of the third target pixel circuit away from the center line of the display panel.

[0026] In some possible implementations of the first aspect, along the second direction, the two sides of the center line are respectively the first region and the second region; the second type of clock line of the first region is located on the side of the second type of gate drive circuit away from the center line, and the second type of clock line of the second region is located on the side of the second type of gate drive circuit away from the center line.

[0027] In some possible implementations of the first aspect, the first type of gate drive circuit is electrically connected to the first type of clock line via a first type of connection line; The first type of connection cable and the target data cable are located on different metal layers.

[0028] In some possible implementations of the first aspect, at least one metal layer is included between the first type of connecting line and the target data line in the thickness direction of the display panel.

[0029] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0030] According to the display panel and display device provided in the embodiments of this application, since at least one first-type clock line electrically connected to the first-type gate driving circuit and the target data line are located on different sides of the target pixel circuit, at least one first-type connection line electrically connected to the first-type gate driving circuit and the target data line are also located on different sides of the target pixel circuit. This can reduce the interference of the clock signal of the first-type clock line on the data signal on the target data line, thereby reducing the brightness difference between the target area and the non-target area and improving the problem of uneven display. Attached Figure Description

[0031] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0032] Figure 1This is a top view of a partial area of ​​a display panel provided in an embodiment of this application. Figure 2 This invention provides a schematic diagram of another top view of a partial area of ​​a display panel according to an embodiment of the present application. Figure 3 This illustration shows another top view of a partial area of ​​the display panel provided in an embodiment of this application. Figure 4 This illustration shows a schematic diagram of a module structure of a pixel circuit provided in an embodiment of this application; Figure 5 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 6 This illustration shows another modular structure diagram of the pixel circuit provided in an embodiment of this application; Figure 7 This illustration shows another structural diagram of the pixel circuit provided in an embodiment of this application; Figure 8 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 9 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 10 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 11 This illustration shows another top view of a partial area of ​​the display panel provided in an embodiment of this application. Figure 12 This illustration shows another top view of a partial area of ​​the display panel provided in an embodiment of this application. Figure 13 This illustration shows a top view of a display panel provided in an embodiment of this application. Figure 14 This diagram illustrates another top view of the display panel provided in an embodiment of this application. Figure 15 This diagram shows another top view of the display panel provided in an embodiment of this application; Figure 16 This diagram shows another top view of the display panel provided in an embodiment of this application; Figure 17 This diagram shows another top view of the display panel provided in an embodiment of this application; Figure 18 This illustration shows a schematic diagram of a first shift register provided in an embodiment of this application; Figure 19 This illustration shows a schematic diagram of a second shift register provided in an embodiment of this application; Figure 20 This illustration shows a timing diagram of a clock signal provided in an embodiment of this application; Figure 21 This illustration shows another timing diagram of the clock signal provided in an embodiment of this application; Figure 22 This illustration shows another top view of a partial area of ​​the display panel provided in an embodiment of this application. Figure 23 This diagram shows another top view of the display panel provided in an embodiment of this application; Figure 24 Show Figure 3 A schematic diagram of a cross-sectional structure along the C1-C2 direction; Figure 25 This diagram shows another top view of the display panel provided in an embodiment of this application; Figure 26 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0033] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0035] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0036] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0037] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0038] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0039] like Figure 1 As shown, in order to achieve a narrow bezel or even a bezel-less design, the gate driving circuit 10' can be built into the display area AA of the display panel. The gate driving circuit 10' includes multiple cascaded shift registers VSR'. In the target area A1', multiple shift registers VSR' and multiple pixel circuits 20' are arranged in the first direction X. In the non-target area A2', pixel circuits 20' are arranged but there is no gate driving circuit 10'.

[0040] The shift register VSR' is connected to clock lines CK' and XCK', and the pixel circuit 20' is connected to the data line Data. Clock lines CK' and XCK' and the data line Data extend along the second direction Y. The shift register VSR' is connected to the clock lines CK' and XCK' via connecting line 40'. Research revealed that within the target area, clock lines CK' and XCK' and the data line Data are located on the same side of the shift register VSR', and connecting line 40' overlaps with the data line Data. This results in a relatively large parasitic capacitance between connecting line 40' and the data line Data. Consequently, the clock signal interferes with the data signal on the data line, affecting the display effect.

[0041] The non-target area A2' does not have a gate drive circuit 10', while the target area A1' has a gate drive circuit 10'. This will eventually result in a difference in brightness between the area with the gate drive circuit 10' and the area without the gate drive circuit 10', causing uneven display (mura).

[0042] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0043] like Figure 2 or Figure 3 As shown, the display panel 100 includes pixel circuits 20 and a first type of gate driving circuit 11. Multiple pixel circuits 20 are arrayed along a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. The first type of gate driving circuit 11 includes multiple cascaded first type shift registers VSR1. Both the pixel circuits 20 and the first type of gate driving circuit 11 are located in the display area AA. That is, by embedding the first type of gate driving circuit 11 within the display area AA, a narrow bezel or even bezel-less design can be achieved.

[0044] The output of the first type of gate driving circuit 11 can be electrically connected to the pixel circuit 20 through a gate trace (not shown in the figure). The first type of gate driving circuit 11 outputs a gate driving signal to drive the pixel circuit 20 to work and generate a driving current, thereby driving the light-emitting element to emit light.

[0045] The display area AA includes a target area A1 and a non-target area A2. The pixel circuit 20 in the target area A1 is the target pixel circuit 21, and the pixel circuit 20 in the non-target area A2 is the non-target pixel circuit 22. The pixel circuits 20 are electrically connected to the data line 50. The data line 50 to which the target pixel circuit 21 is electrically connected is the target data line 51, and the data line 50 to which the non-target pixel circuit 22 is electrically connected is the non-target data line 52. The pixel circuit 20 may include the pixel circuit corresponding to the red sub-pixel, the pixel circuit corresponding to the green sub-pixel, and the pixel circuit corresponding to the blue sub-pixel. Correspondingly, the data line 50 may include the data line Data(R) corresponding to the red sub-pixel, the data line Data(G) corresponding to the green sub-pixel, and the data line Data(B) corresponding to the blue sub-pixel.

[0046] Within the target region A1, the first type of gate driving circuit 11 and the target pixel circuit 21 are arranged in the first direction X. The non-target region A2 does not include the gate driving circuit.

[0047] For example, within the target region A1, the first type shift register VSR1 and the target pixel circuit 21 are arranged alternately in the first direction X, which can be the column direction.

[0048] For example, the width of the first type shift register VSR1 in the second direction Y can be greater than the width of one pixel circuit 20 in the second direction Y, and the width of the first type shift register VSR1 in the second direction Y is less than or equal to the sum of the widths of three pixel circuits 20 in the second direction Y. In the first direction X, three target pixel circuits 21 can be arranged between the two first type shift registers VSR1, and the three target pixel circuits 21 are the pixel circuits corresponding to the red light-emitting element, the green light-emitting element, and the blue light-emitting element, respectively. In other words, three columns of target pixel circuits 21 can be provided in the target area A1.

[0049] The first type of gate driving circuit 11 is electrically connected to the first type of clock line 31, and both the first type of clock line 31 and the data line 50 extend along the first direction X. Specifically, the first type of gate driving circuit 11 is electrically connected to the first type of clock line 31 through a first type of connection line 41, and the first type of connection line 41 extends along the second direction Y.

[0050] In the second direction Y, the target data line 51 is located on one side of the target pixel circuit 21, and at least one first-type clock line 31 electrically connected to the first-type gate drive circuit 11 is located on the other side of the target pixel circuit 21. That is, at least one first-type clock line 31 and the target data line 51 are located on different sides of the target pixel circuit 21.

[0051] As an example, such as Figure 2 As shown, the multiple first-type clock lines 31 electrically connected to the first-type gate drive circuit 11 are all located on different sides of the target pixel circuit 21 from the target data line 51.

[0052] As another example, such as Figure 3 As shown, at least one first-type clock line 31 and the target data line 51 electrically connected to the first-type gate driving circuit 11 are located on different sides of the target pixel circuit 21, and at least one first-type clock line 31 and the target data line 51 are located on the same side of the target pixel circuit 21.

[0053] For example, please refer to the reference. Figure 2 and Figure 18The first type shift register VSR1 includes a first clock terminal CK and a second clock terminal XCK. In this case, the first type gate drive circuit 11 can be electrically connected to two clock lines. Specifically, the first clock terminal CK of the odd-level first type shift register VSR1 is electrically connected to the first type clock line 31 for transmitting clock signal ck, and the second clock terminal XCK of the odd-level first type shift register VSR1 is electrically connected to the first type clock line 31 for transmitting clock signal xck. The first clock terminal CK of the even-level first type shift register VSR1 is electrically connected to the first type clock line 31 for transmitting clock signal xck, and the second clock terminal XCK of the even-level first type shift register VSR1 is electrically connected to the first type clock line 31 for transmitting clock signal ck.

[0054] The positional relationship between the first type of gate driving circuit 11 and its electrically connected clock line includes: the first type of clock line 31 transmitting the clock signal ck is closer to the first type of gate driving circuit 11, or the first type of clock line 31 transmitting the clock signal xck is closer to the first type of gate driving circuit 11.

[0055] Taking the first type of clock line 31 for transmitting the clock signal ck and the target data line 51 as being located on different sides of the target pixel circuit 21 as an example, the first type of connection line 41 for transmitting the clock signal ck and the target data line 51 are also located on different sides of the target pixel circuit 21. In this way, the first type of connection line 41 for transmitting the clock signal ck and the target data line 51 will not cross, which can reduce the parasitic capacitance between the first type of connection line 41 for transmitting the clock signal ck and the target data line 51, thereby reducing the interference of the clock signal ck on the target data line 51.

[0056] According to the display panel provided in the embodiments of this application, since at least one first-type clock line 31 electrically connected to the first-type gate driving circuit 11 and the target data line 51 are located on different sides of the target pixel circuit 21, at least one first-type connection line 41 electrically connected to the first-type gate driving circuit 11 and the target data line 51 are also located on different sides of the target pixel circuit 21. This can reduce the interference of the clock signal of the first-type clock line 31 on the data signal on the target data line 51, thereby reducing the brightness difference between the target area A1 and the non-target area A2 and improving the problem of uneven display.

[0057] In some embodiments, such as Figure 4As shown, the pixel circuit 20 includes a driving module 201 and a data writing module 202. The driving module 201 and the light-emitting element D are connected in series between the first power line PVDD and the second power line PVEE. The first end of the data writing module 202 is electrically connected to the data line 50, the second end of the data writing module 202 is electrically connected to the driving module 201, and the control end of the data writing module 202 is electrically connected to the output end of the first type of gate driving circuit 11. The gate driving signal output by the first type of gate driving circuit 11 is used to control the writing of the data signal.

[0058] As an example, such as Figure 5 As shown, the driving module includes transistor T11, the data writing module includes transistor T15, and the gate of transistor T15 is connected to the gate driving signal S2, which comes from the output terminal of the first type of gate driving circuit 11.

[0059] The gate driving signal output by the first type of gate driving circuit 11 is used to control the writing of data signals into the driving module. Therefore, the first type of gate driving circuit 11 has the most direct impact on the data signal. In this embodiment, for the first type of gate driving circuit 11 that controls the writing of data signals, at least one first type of clock line 31 electrically connected to it is located on a different side of the target pixel circuit 21 from the target data line 51. This can better reduce the interference of the clock signal on the data signal on the target data line 51, thereby better reducing the brightness difference between the target area A1 and the non-target area A2 and improving the problem of uneven display.

[0060] In some embodiments, the pixel circuit 20 includes an amplitude modulation sub-circuit (PAM) and a pulse width modulation sub-circuit (PWM), which generate a drive current under the control of the PAM and PWM. The PAM can be used to control the amplitude of the drive current, and the PWM can be used to adjust the pulse width of the voltage applied to the first electrode of the light-emitting element D.

[0061] The pulse width modulation (PWM) sub-circuit adjusts the pulse width of the voltage applied to the first electrode of the light-emitting element (LED) D. In other words, the PWM sub-circuit adjusts the actual emission period of the drive current applied to the LED D. Simultaneously, it maintains the drive current applied to the LED at a constant level to adjust the grayscale or brightness of the LED display, rather than simply adjusting the magnitude of the drive current applied to the LED. Therefore, the amplitude modulation (PAM) sub-circuit can provide drive current to the LED so that it is driven with optimal luminous efficiency, and adjust the LED's emission duty cycle (i.e., the emission period of the LED) through the PWM sub-circuit to adjust the grayscale or brightness of the LED display.

[0062] When the pixel circuit 20 includes an amplitude modulation sub-circuit (PAM) and a pulse width modulation sub-circuit (PWM), the structure of the pixel circuit 20 can be as follows: Figures 7 to 10 As shown in any one of them, Figure 7 In the structure shown, the output terminal of the pulse width modulation sub-circuit PWM is directly electrically connected to the gate of the driving transistor T11 in the amplitude modulation sub-circuit PAM. Figure 8 In the structure shown, the output terminal of the pulse width modulation sub-circuit PWM is directly electrically connected to the gate of the control transistor T29 in the amplitude modulation sub-circuit PAM. Figure 9 In the structure shown, the output terminal of the pulse width modulation sub-circuit PWM is coupled to the gate of the driving transistor T11 in the amplitude modulation sub-circuit PAM through the first capacitor C1. Figure 8 In the structure shown, the output terminal of the pulse width modulation sub-circuit PWM is coupled to the gate of the control transistor T29 in the amplitude modulation sub-circuit PAM through the second capacitor C2.

[0063] It should be noted that regardless of the specific structure of the amplitude modulation module and pulse width modulation module in the pixel circuit, both typically require a gate driving circuit for operation. Therefore, the design concept regarding the gate driving circuit and wiring in this application can also be applied to... Figures 7 to 10 Pixel circuits with other structural forms besides the circuit structure shown.

[0064] like Figure 11 As shown, the first type of gate driving circuit 11 includes a first gate driving circuit 11a and a second gate driving circuit 11b. The signal output by the first gate driving circuit 11a is used to control the writing of the data signal of the amplitude modulation sub-circuit PAM, and the signal output by the second gate driving circuit 11b is used to control the writing of the data signal of the pulse width modulation sub-circuit PWM. For example, referring to the reference... Figure 11 as well as Figures 7 to 10 In any of the accompanying drawings, the first gate drive circuit 11a outputs the gate drive signal PAM_S2, and the second gate drive circuit 11b outputs the gate drive signal PWM_S2.

[0065] The target pixel circuit 21 includes a first target pixel circuit 21a and a second target pixel circuit 21b. The first target pixel circuit 21a and the first gate driving circuit 11a are arranged in a first direction X, and the second target pixel circuit 21b and the second gate driving circuit 11b are also arranged in the first direction X. The data line connected to the amplitude modulation sub-circuit of the first target pixel circuit 21a and the second target pixel circuit 21b is the first target data line 51a, and the data line connected to the pulse width modulation sub-circuit of the first target pixel circuit 21a and the second target pixel circuit 21b is the second target data line 51b.

[0066] When the pixel circuit 20 includes an amplitude modulation sub-circuit PAM and a pulse width modulation sub-circuit PWM, the pixel circuit may include a pixel circuit corresponding to the red light-emitting element, a pixel circuit corresponding to the green light-emitting element, and a pixel circuit corresponding to the blue light-emitting element. Correspondingly, the data line 50 may include the data line PAM_Data(R) corresponding to the amplitude modulation sub-circuit PAM of the red light-emitting element, the data line PAM_Data(G) corresponding to the amplitude modulation sub-circuit PAM of the green light-emitting element, the data line PAM_Data(B) corresponding to the amplitude modulation sub-circuit PAM of the blue light-emitting element, the data line PWM_Data(R) corresponding to the pulse width modulation sub-circuit PWM of the red light-emitting element, the data line PWM_Data(G) corresponding to the pulse width modulation sub-circuit PWM of the green light-emitting element, and the data line PWM_Data(B) corresponding to the pulse width modulation sub-circuit PWM of the blue light-emitting element.

[0067] For example, the target region includes a first target region A1a and a second target region A1b. The first gate driving circuit 11a includes a plurality of cascaded first shift registers VSR1a, and the second gate driving circuit 11b includes a plurality of cascaded second shift registers VSR1b; in the first target region A1a, the first shift registers VSR1a and the first target pixel circuit 21a are alternately arranged in the first direction X; in the second target region A1b, the second shift registers VSR1b and the second target pixel circuit 21b are alternately arranged in the first direction X.

[0068] For example, in the first direction X, three first target pixel circuits 21a can be arranged between the two first shift registers VSR1a, and the three first target pixel circuits 21a are respectively the pixel circuits corresponding to the red light-emitting element, the green light-emitting element, and the blue light-emitting element; in other words, three columns of first target pixel circuits 21a can be set in the first target area A1a. Similarly, in the first direction X, three second target pixel circuits 21b can be arranged between the two second shift registers VSR1b, and the three second target pixel circuits 21b are respectively the pixel circuits corresponding to the red light-emitting element, the green light-emitting element, and the blue light-emitting element; in other words, three columns of second target pixel circuits 21b can be set in the second target area A1b.

[0069] The first type of clock line 31 includes a first clock line 31a and a second clock line 31b. The first type of connection line 41 includes a first connection line 41a and a second connection line 41b. The first gate drive circuit 11a is electrically connected to the first clock line 31a through the first connection line 41a, and the second gate drive circuit 11b is electrically connected to the second clock line 31b through the second connection line 41b.

[0070] like Figure 11 or Figure 12As shown, in the second direction Y, the first target data line 51a is located on one side of the first target pixel circuit 21a, and at least one first clock line 31a electrically connected to the first gate driving circuit 11a is located on the other side of the first target pixel circuit 21a; and / or, in the second direction Y, the second target data line 51b is located on one side of the second target pixel circuit 21b, and at least one second clock line 31b electrically connected to the second gate driving circuit 11b is located on the other side of the second target pixel circuit 21b.

[0071] As an example, in the second direction Y, the first target data line 51a is located on one side of the first target pixel circuit 21a, and at least one first clock line 31a electrically connected to the first gate driving circuit 11a is located on the other side of the first target pixel circuit 21a; and, in the second direction Y, the second target data line 51b is located on one side of the second target pixel circuit 21b, and at least one second clock line 31b electrically connected to the second gate driving circuit 11b is located on the other side of the second target pixel circuit 21b.

[0072] As another example, in the second direction Y, the first target data line 51a is located on one side of the first target pixel circuit 21a, and at least one first clock line 31a electrically connected to the first gate driving circuit 11a is located on the other side of the first target pixel circuit 21a; and, in the second direction Y, the second target data line 51b and the second clock line 31b electrically connected to the second gate driving circuit 11b are located on the same side of the second target pixel circuit 21b.

[0073] As another example, in the second direction Y, the first target data line 51a and the first clock line 31a electrically connected to the first gate driving circuit 11a are located on the same side of the first target pixel circuit 21a; and in the second direction Y, the second target data line 51b is located on one side of the second target pixel circuit 21b, and at least one second clock line 31b electrically connected to the second gate driving circuit 11b is located on the other side of the second target pixel circuit 21b.

[0074] The first gate driving circuit 11a is used to control the data signal on the first target data line 51a to be written into the amplitude modulation sub-circuit of the first target pixel circuit 21a. Therefore, the clock signal connected to the first gate driving circuit 11a has a direct effect on the data signal being written into the amplitude modulation sub-circuit. In this embodiment, at least one first clock line 31a electrically connected to the first gate driving circuit 11a is also located on a different side of the first target pixel circuit 21a from the first target data line 51a. This can reduce the interference of the clock signal of the first clock line 31a on the data signal on the first target data line 51a, thereby reducing the brightness difference between the first target area A1a and the non-target area A2 and improving the problem of uneven display.

[0075] And / or, the second gate driving circuit 11b is used to control the data signal on the second target data line 51b to be written into the pulse width modulation sub-circuit. Therefore, the clock signal connected to the second gate driving circuit 11b has a direct effect on the data signal being written into the pulse width modulation sub-circuit. In this embodiment, at least one second clock line 31b electrically connected to the second gate driving circuit 11b is located on a different side of the first target pixel circuit 21a from the second target data line 51b. This can reduce the interference of the clock signal of the second clock line 31b on the data signal on the second target data line 51b, thereby reducing the brightness difference between the second target area A1b and the non-target area A2 and improving the problem of uneven display.

[0076] In some embodiments, such as Figure 11 or Figure 12 As shown, in the second direction Y, the first target data line 51a and the second target data line 51b are located on both sides of the target pixel circuit 21, respectively.

[0077] For each pixel circuit 20, the amplitude modulation sub-circuit PAM and the pulse width modulation sub-circuit PWM of the pixel circuit 20 are each connected to a data line, and in the second direction Y, the data line connected to the amplitude modulation sub-circuit PAM and the data line connected to the pulse width modulation sub-circuit PWM are located on both sides of the pixel circuit 20.

[0078] For example, the amplitude modulation sub-circuit PAM of the first target pixel circuit 21a is electrically connected to the first target data line 51a, and the pulse width modulation sub-circuit PWM of the first target pixel circuit 21a is electrically connected to the second target data line 51b. For the first target pixel circuit 21a, in the second direction Y, the first target data line 51a and the second target data line 51b that are electrically connected are located on both sides of the first target pixel circuit 21a.

[0079] The amplitude modulation sub-circuit PAM of the second target pixel circuit 21b is electrically connected to the first target data line 51a, and the pulse width modulation sub-circuit PWM of the second target pixel circuit 21b is electrically connected to the second target data line 51b. For the second target pixel circuit 21b, in the second direction Y, the first target data line 51a and the second target data line 51b that are electrically connected are located on both sides of the second target pixel circuit 21b.

[0080] Furthermore, for the non-target pixel circuit 22, in the second direction Y, the data lines connected to its amplitude modulation sub-circuit PAM and pulse width modulation sub-circuit PWM are located on both sides of the non-target pixel circuit 22.

[0081] In this embodiment, the data lines connected to the amplitude modulation sub-circuit PAM and the data lines connected to the pulse width modulation sub-circuit PWM are located on both sides of the pixel circuit 20, which can reduce the possibility of crossover between the data lines connected to the amplitude modulation sub-circuit PAM and the data lines connected to the pulse width modulation sub-circuit PWM, thereby reducing interference between the two types of data lines and improving the display effect.

[0082] In some embodiments, such as Figure 11 As shown, in the second direction Y, the first target data line 51a is located on one side of the first target pixel circuit 21a, and at least two first clock lines 31a electrically connected to the first gate driving circuit 11a are located on the other side of the first target pixel circuit 21a; and / or, the second target data line 51b is located on one side of the second target pixel circuit 21b, and at least two second clock lines 31b electrically connected to the second gate driving circuit 11b are located on the other side of the second target pixel circuit 21b.

[0083] For example, any first clock line 31a electrically connected to the first gate driving circuit 11a is located on a different side of the first target pixel circuit 21a from the first target data line 51a. In this way, any first connection line 41a will not form a cross capacitance with the first target data line 51a, which can better reduce the interference of the clock signal connected to the first gate driving circuit 11a on the data signal on the first target data line 51a, thereby better reducing the brightness difference between the first target area A1a and the non-target area A2 and improving the problem of uneven display.

[0084] For example, any two second clock lines 31b and the second target data line 51b electrically connected to the second gate driving circuit 11b are located on different sides of the second target pixel circuit 21b. In this way, any second connection line 41b will not form a cross capacitance with the second target data line 51b, which can better reduce the interference of the clock signal connected to the second gate driving circuit 11b on the data signal on the second target data line 51b, thereby better reducing the brightness difference between the second target area A1b and the non-target area A2 and improving the problem of uneven display.

[0085] In some embodiments, such as Figure 11 As shown, the second target data line 51b, which is electrically connected to the first clock line 31a and the first target pixel circuit 21a, is located on the same side of the first target pixel circuit 21a; and / or, the first target data line 51a, which is electrically connected to the second clock line 31b and the second target pixel circuit 21b, is located on the same side of the second target pixel circuit 21b.

[0086] The first clock line 31a is electrically connected to the first gate driving circuit 11a. The first gate driving circuit 11a is not used to control whether the data signal on the second target data line 51b is written into the first target pixel circuit 21a. Therefore, even if the first clock line 31a and the second target data line 51b are located on the same side of the first target pixel circuit 21a, it will not have a serious impact on the writing of the data signal on the second target data line 51b.

[0087] The second clock line 31b is electrically connected to the second gate driving circuit 11b. The second gate driving circuit 11b is not used to control whether the data signal on the first target data line 51a is written to the second target pixel circuit 21b. Therefore, even if the second clock line 31b and the first target data line 51a are located on the same side of the second target pixel circuit 21b, it will not have a serious impact on the writing of the data signal on the first target data line 51a.

[0088] In some embodiments, such as Figure 13 or Figure 14 As shown, the display panel 100 includes a center line L extending along a first direction X, and a first region Q1 and a second region Q2 on either side of the center line L along a second direction Y; along the second direction Y, the distance between the first gate driving circuit 11a of the first region Q1 and the center line L is d11, and the distance between the first gate driving circuit 11a of the second region Q2 and the center line L is d12, d11=d12; and / or, along the second direction Y, the distance between the second gate driving circuit 11b of the first region Q1 and the center line L is d21, and the distance between the second gate driving circuit 11b of the second region Q2 and the center line L is d22, d21=d22.

[0089] In this article, the distance between the gate drive circuit and the neutral line L can refer to the distance between the side of the gate drive circuit closest to the neutral line L and the neutral line L, or the distance between the center of the gate drive circuit and the neutral line L.

[0090] In the above embodiments, d11=d12, which allows for a certain degree of error. For example, the difference between d11 and d12 within 5% can be considered as equal. Similarly, d21=d22, which also allows for a certain degree of error. For example, the difference between d21 and d22 within 5% can be considered as equal.

[0091] Zones Q1 and Q2 represent the left and right halves of the display panel, respectively. A first gate driving circuit 11a is provided in both the left and right halves. The signal (PAM_S2) output by both first gate driving circuits 11a is used to control the writing of data signals to the amplitude modulation sub-circuit. The two first gate driving circuits 11a are equidistant from the center line L, thus making them approximately symmetrical with respect to the center line L. The loads on the two first gate driving circuits 11a are essentially the same, improving display uniformity. Alternatively, a second gate driving circuit 11b is provided in both the left and right halves. The signal (PWM_S2) output by both second gate driving circuits 11b is used to control the writing of data signals to the pulse width modulation sub-circuit. The two second gate driving circuits 11b are equidistant from the center line L, thus making them approximately symmetrical with respect to the center line L. The loads on the two second gate driving circuits 11b are essentially the same, improving display uniformity.

[0092] In some embodiments, such as Figure 14 As shown, for the pixel circuits 20 in the first region Q1 and the second region Q2, the data line PAM_Data electrically connected to the amplitude modulation sub-circuit is located on the first side of the pixel circuit 20, and the data line PWM_Data electrically connected to the pulse width modulation sub-circuit is located on the second side of the pixel circuit 20.

[0093] For example, the amplitude modulation sub-circuit corresponding to the red light-emitting element is electrically connected to the data line PAM_Data(R), the amplitude modulation sub-circuit corresponding to the green light-emitting element is electrically connected to the data line PAM_Data(G), and the amplitude modulation sub-circuit corresponding to the blue light-emitting element is electrically connected to the data line PAM_Data(B). Similarly, the pulse width modulation sub-circuit corresponding to the red light-emitting element is electrically connected to the data line PWM_Data(R), the pulse width modulation sub-circuit corresponding to the green light-emitting element is electrically connected to the data line PWM_Data(G), and the pulse width modulation sub-circuit corresponding to the blue light-emitting element is electrically connected to the data line PWM_Data(B).

[0094] In terms of the entire display panel, the data line PAM_Data, which is electrically connected to the amplitude modulation sub-circuit, is located on one side of the pixel circuit 20 to which it is electrically connected, and the data line PWM_Data, which is electrically connected to the pulse width modulation sub-circuit, is located on the other side of the pixel circuit 20 to which it is electrically connected. Overall, the arrangement of the two types of data lines is periodic, which facilitates the wiring design and can improve the uniformity of the display.

[0095] In some embodiments, such as Figure 14As shown, in the first region Q1, the first clock line 31a is located on the side of the first gate driving circuit 11a away from the center line L, and in the second region Q2, the first clock line 31a is located on the side of the first gate driving circuit 11a close to the center line; and / or, in the first region Q1, the second clock line 31b is located on the side of the second gate driving circuit 11b close to the center line, and in the second region Q2, the second clock line 31b is located on the side of the second gate driving circuit 11b away from the center line.

[0096] For example, Figure 14 In the first region Q1, the first clock line 31a is located to the left of the first gate driving circuit 11a, and in the second region Q2, the first clock line 31a is located to the left of the first gate driving circuit 11a. That is to say, the relative positional relationship between the first clock line 31a and the first gate driving circuit 11a in the first region Q1 is the same as that between the first clock line 31a and the first gate driving circuit 11a in the second region Q2, so that the first connection line 41a connected to the first clock line 31a in the two regions does not intersect with the second target data line 51b.

[0097] For example, Figure 14 In the first region Q1, the second clock line 31b is located to the right of the second gate drive circuit 11b, and the second clock line 31b in the second region Q2 is also located to the right of the second gate drive circuit 11b. That is to say, the relative positional relationship between the second clock line 31b and the second gate drive circuit 11b in the first region Q1 is the same as that between the second clock line 31b and the second gate drive circuit 11b in the second region Q2, so that the second connection line 41b connected to the second clock line 31b in the two regions does not intersect with the first target data line 51a.

[0098] Figure 14 The example shown illustrates that, across the entire screen, the positional relationship between the data lines PAM_Data and PWM_Data electrically connected to the amplitude modulation sub-circuit and the pixel circuit 20 is consistent. In other embodiments, the positional relationship between the data lines PAM_Data and PWM_Data electrically connected to the amplitude modulation sub-circuit and the pixel circuit 20 may differ in different regions.

[0099] For example, such as Figure 13As shown, for the pixel circuit 20 in the first region Q1, the data line PAM_Data electrically connected to the amplitude modulation sub-circuit is located on the first side of the pixel circuit 20, and the data line PWM_Data electrically connected to the pulse width modulation sub-circuit is located on the second side of the pixel circuit 20; for the pixel circuit 20 in the second region Q2, the data line PAM_Data electrically connected to the amplitude modulation sub-circuit is located on the second side of the pixel circuit 20, and the data line PWM_Data electrically connected to the pulse width modulation sub-circuit is located on the first side of the pixel circuit 20.

[0100] For example, the data line PAM_Data electrically connected to the amplitude modulation sub-circuit in the first region Q1 is located to the right of the pixel circuit 20 to which it is electrically connected, and the data line PAM_Data electrically connected to the amplitude modulation sub-circuit in the second region Q2 is located to the left of the pixel circuit 20 to which it is electrically connected; the data line PWM_Data electrically connected to the pulse width modulation sub-circuit in the first region Q1 is located to the left of the pixel circuit 20 to which it is electrically connected, and the data line PWM_Data electrically connected to the pulse width modulation sub-circuit in the second region Q2 is located to the right of the pixel circuit 20 to which it is electrically connected; the data lines PAM_Data electrically connected to the amplitude modulation sub-circuit in the first region Q1 and the second region Q2 are relative to their electrically connected... The pixel circuits 20 are positioned differently, and the data lines PWM_Data electrically connected to the pulse width modulation sub-circuits of the first region Q1 and the second region Q2 are positioned differently relative to the pixel circuits 20 they are electrically connected to. However, the data lines PAM_Data of the first region Q1 and the second region Q2 are symmetrical about the center line L, and the data lines PWM_Data of the first region Q1 and the second region Q2 are symmetrical about the center line L. This makes it easier to design the first gate driving circuit 11a and the second gate driving circuit 11b in both the left and right halves of the screen to be symmetrical about the center line L, so as to improve the consistency of the gate driving circuits in the left and right halves of the screen.

[0101] Please continue to refer to this. Figure 13 In the first region Q1, the first clock line 31a is located on the side of the first gate drive circuit 11a away from the center line L, and the first clock line of the second region Q2 is located on the side of the first gate drive circuit 11a away from the center line L; and / or, the second clock line 31b in the first region Q1 is located on the side of the second gate drive circuit 11b close to the center line L, and the second clock line 31b in the second region Q2 is located on the side of the second gate drive circuit 11b close to the center line L.

[0102] For example, Figure 13In the first region Q1, the first clock line 31a is located to the left of the first gate driving circuit 11a, and in the second region Q2, the first clock line 31a is located to the right of the first gate driving circuit 11a, so that the first gate driving circuits 11a in the two regions can be symmetrical about the center line L, and the first clock lines 31a in the two regions can also be symmetrical about the center line L, so as to improve the consistency of the driving performance of the first gate driving circuits 11a in the left and right halves of the screen.

[0103] For example, Figure 13 In the first region Q1, the second clock line 31b is located to the right of the second gate driving circuit 11b, and in the second region Q2, the second clock line 31b is located to the left of the second gate driving circuit 11b. This allows the second gate driving circuits 11b in the two regions to be symmetrical about the center line L, and the second clock lines 31b in the two regions to also be symmetrical about the center line L, thereby improving the consistency of the driving performance of the second gate driving circuits 11b in the left and right halves of the screen.

[0104] In some embodiments, such as Figure 15 As shown, in the second direction Y, the first target data line 51a and at least one first clock line 31a are located on different sides of the first target pixel circuit 21a, and the first target data line 51a and at least one first clock line 31a are located on the same side of the first target pixel circuit 21a. And / or, the second target data line 51b and at least one second clock line 31b are located on different sides of the second target pixel circuit 21b, and the second target data line 51b and at least one second clock line 31b are located on the same side of the second target pixel circuit 21b.

[0105] In this embodiment, the interference of the clock signal of at least one first clock line 31a to the first target data line 51a can be reduced, and / or, the interference of the clock signal of at least one second clock line 31b to the second target data line 51b can be reduced.

[0106] Figure 13 , Figure 14 and Figure 15 In the example shown, the distances between the two first gate driving circuits 11a of the left and right halves of the screen and the center line L are equal, and the distances between the two second gate driving circuits 11b of the left and right halves of the screen and the center line L are equal; in other embodiments, the distances between the two first gate driving circuits 11a of the left and right halves of the screen and the center line L may be unequal, and / or, the distances between the two second gate driving circuits 11b of the left and right halves of the screen and the center line L may be unequal.

[0107] For example, such as Figure 16As shown, the display panel 100 includes a first region Q1 and a second region Q2 arranged along the second direction Y. In the second direction Y, the second gate driving circuit 11b in the first region Q1 is located between the first gate driving circuit 11a in the first region Q1 and the second region Q2, and the first gate driving circuit 11a in the second region Q2 is located between the second gate driving circuit 11b in the second region Q2 and the first region Q1.

[0108] In other words, for the first region Q1, the second gate drive circuit 11b is closer to the center line L; for the second region Q2, the first gate drive circuit 11a is closer to the center line L.

[0109] For example, the distance between the first gate driving circuit 11a in the first region Q1 and the center line L is d13, and the distance between the first gate driving circuit 11a in the second region Q2 and the center line L is d14, where d13 ≠ d14, for example, d13 > d14.

[0110] The distance between the second gate driving circuit 11b in the first region Q1 and the center line L is d23, and the distance between the second gate driving circuit 11b in the second region Q2 and the center line L is d24, where d23 ≠ d24, for example, d23 < d24.

[0111] Although the gate driving circuits of the left and right halves of the screen cannot be symmetrical about the center line L in this embodiment, the arrangement of the data lines can be consistent for the whole screen, and the original design of the data lines does not need to be changed.

[0112] The above describes how the data lines PAM_Data and PWM_Data are located on opposite sides of the pixel circuit.

[0113] In some embodiments, such as Figure 7 As shown, the first target data line 51a and the second target data line 51b electrically connected to the first target pixel circuit 21a are located on one side of the first target pixel circuit 21a, and the first clock line 31a electrically connected to the first gate driving circuit 11a is located on the other side of the first target pixel circuit 21a; and / or, the first target data line 51a and the second target data line 51b electrically connected to the second target pixel circuit 21b are located on one side of the second target pixel circuit 21b, and the second clock line 31b electrically connected to the second gate driving circuit 11b is located on the other side of the second target pixel circuit 21b.

[0114] The first gate driving circuit 11a is electrically connected to the first clock line 31a via a first connection line 41a. The first connection line 41a does not cross any of the first target data lines 51a and 51b, thus better reducing the interference of the clock signal of the first gate driving circuit 11a on the data signals on the data lines and improving display uniformity. And / or, the second gate driving circuit 11b is electrically connected to the second clock line 31b via a second connection line 41b. The second connection line 41b does not cross any of the first target data lines 51a and 51b, thus better reducing the interference of the clock signal of the second gate driving circuit 11b on the data signals on the data lines and improving display uniformity.

[0115] For example, for any pixel circuit 20 on the entire screen, the data lines PAM_Data of the amplitude modulation sub-circuit and PWM_Data of the pulse width modulation sub-circuit are both located on the left side of the pixel circuit 20; or, the data lines PAM_Data of the amplitude modulation sub-circuit and PWM_Data of the pulse width modulation sub-circuit are both located on the right side of the pixel circuit 20. In this way, the data lines of the entire screen are arranged uniformly, which can better improve the uniformity of the display.

[0116] Please continue to refer to this. Figure 17 The display panel 100 includes a center line L extending along a first direction X and a second direction Y, with a first area Q1 and a second area Q2 on both sides of the center line L. Along the second direction Y, the distance between the first gate driving circuit 11a of the first region Q1 and the center line L is d15, and the distance between the first gate driving circuit 11a of the second region Q2 and the center line L is d16, d15=d16; and / or, along the second direction Y, the distance between the second gate driving circuit 11b of the first region Q1 and the center line L is d25, and the distance between the second gate driving circuit 11b of the second region Q2 and the center line L is d26, d25=d26.

[0117] In this embodiment, the distance between the gate driving circuit and the center line L can refer to the distance between the side of the gate driving circuit closest to the center line L and the center line L, or the distance between the center of the gate driving circuit and the center line L.

[0118] In the above embodiments, d15=d16, which allows for a certain degree of error. For example, the difference between d15 and d16 within 5% can be considered equal. Similarly, d25=d26, which also allows for a certain degree of error. For example, the difference between d25 and d26 within 5% can be considered equal.

[0119] Zones Q1 and Q2 represent the left and right halves of the display panel, respectively. A first gate driving circuit 11a is provided in both the left and right halves. The signal (PAM_S2) output by both first gate driving circuits 11a is used to control the writing of data signals to the amplitude modulation sub-circuit. The two first gate driving circuits 11a are equidistant from the center line L, thus making them approximately symmetrical with respect to the center line L. The loads on the two first gate driving circuits 11a are essentially the same, improving display uniformity. Alternatively, a second gate driving circuit 11b is provided in both the left and right halves. The signal (PWM_S2) output by both second gate driving circuits 11b is used to control the writing of data signals to the pulse width modulation sub-circuit. The two second gate driving circuits 11b are equidistant from the center line L, thus making them approximately symmetrical with respect to the center line L. The loads on the two second gate driving circuits 11b are essentially the same, improving display uniformity.

[0120] In some embodiments, with Figure 17 and Figure 18 For example, the first gate driving circuit 11a includes an output module 101a and an input module 102a. The input module 102a receives the input signal PAM_IN, and the output terminal PAM_OUT of the output module 101a outputs the gate driving signal (e.g., PAM_S2). For example, one of the first clock lines 31a is electrically connected to the input terminal of the output module 101a in the first gate driving circuit 11a, and the other first clock line 31a is electrically connected to the control terminal of the input module 102a in the first gate driving circuit 11a. The first clock signals transmitted by the two first clock lines 31a are PAM_xck and PAM_ck, respectively. The first clock signal PAM_xck can be output through the output module 101a. The first clock signal PAM_ck controls the state of the input module 102a, thereby controlling the writing status of the input signal PAM_IN. It can be understood that the first clock signal PAM_xck and the first clock signal PAM_ck can affect the signal waveform output by the first gate driving circuit 11a.

[0121] by Figure 17 and Figure 19For example, the second gate drive circuit 11b includes an output module 101b and an input module 102b. The input module 102b is connected to the input signal PWM_IN, and the output terminal PWM_OUT of the output module 101b outputs the gate drive signal (e.g., PWM_S2). For example, one of the second clock lines 31b is electrically connected to the input terminal of the output module 101b in the second gate drive circuit 11b, and the other second clock line 31b is electrically connected to the control terminal of the input module 102b in the second gate drive circuit 11b. The second clock signals transmitted by the two second clock lines 31b are PWM_xck and PWM_ck, respectively. The second clock signal PWM_xck can be output through the output module 101b. The second clock signal PWM_ck controls the state of the input module 102b, thereby controlling the writing status of the input signal PWM_IN. It can be understood that the second clock signal PWM_xck and the second clock signal PWM_ck can affect the signal waveform output by the second gate drive circuit 11b.

[0122] The rising edges of the first clock signal and the second clock signal are staggered.

[0123] For example, such as Figure 20 As shown, the rising edges of the first clock signal PAM_ck and the second clock signal PWM_ck are staggered; the rising edges of the first clock signal PAM_xck and the second clock signal PWM_xck are staggered.

[0124] The first clock signal affects the signal waveform output by the first gate driving circuit 11a. The first gate driving circuit 11a is used to control the writing of the data signal of the amplitude modulation sub-circuit. When the rising edge of the first clock signal and the rising edge of the second clock signal are staggered, the transition of the second clock signal will be staggered with the transition of the output signal of the first gate driving circuit 11a. In this way, even if there is parasitic capacitance between the second clock signal and the data line of the amplitude modulation sub-circuit, the interference of the second clock signal on the process of writing the data signal into the amplitude modulation sub-circuit can be reduced.

[0125] Similarly, the second clock signal affects the signal waveform output by the second gate drive circuit 11b. The second gate drive circuit 11b is used to control the writing of the data signal of the pulse width modulation sub-circuit. When the rising edge of the first clock signal and the rising edge of the second clock signal are staggered, the transition of the first clock signal will be staggered with the transition of the output signal of the second gate drive circuit 11b. In this way, even if there is parasitic capacitance between the first clock signal and the data line of the pulse width modulation sub-circuit, the interference of the first clock signal on the process of writing the data signal into the pulse width modulation sub-circuit can be reduced.

[0126] Through extensive experimental research, the inventors discovered that when the rising edges of the first clock signal and the second clock signal are staggered by at least 0.5µs, the problem of uneven display can be improved more effectively.

[0127] It should be noted that, Figure 18 and Figure 19 The structure shown is merely an example and is not intended to limit this application. The technical concept of this application can also be applied to gate drive circuits with other structural forms.

[0128] In some embodiments, the display panel may further include a second type of gate driving circuit, wherein the rising edge of the clock signal received by the second type of gate driving circuit is staggered from the rising edge of the first clock signal and the rising edge of the second clock signal.

[0129] The first type of gate drive circuit is used to control the writing of data signals, while the second type of gate drive circuit and the first type of gate drive circuit are used to drive different transistors in the pixel circuit.

[0130] For example, such as Figure 5 As shown, the first type of gate drive circuit outputs gate drive signal S2, and the second type of gate drive circuit outputs gate drive signal S1 or EM.

[0131] For example, such as Figures 7 to 10 In any of the following, the first type of gate drive circuit outputs a gate drive signal PAM_S2 or PWM_S2, the second type of gate drive circuit outputs a gate drive signal PAM_S1 or PWM_S1 or PAM_EM or PWM_EM, or the second type of gate drive circuit outputs a sweep frequency signal SWEEP.

[0132] like Figure 21 As shown, ck(11) and xck(11) represent the clock signals received by the first type of gate driving circuit, and ck(12) and xck(12) represent the clock signals received by the second type of gate driving circuit. The rising edge of the clock signal ck(12) received by the second type of gate driving circuit is offset from the rising edge of the clock signal ck(11) received by the first type of gate driving circuit; the rising edge of the clock signal xck(12) received by the second type of gate driving circuit is offset from the rising edge of the clock signal xck(11) received by the first type of gate driving circuit.

[0133] In this embodiment, the clock signal of the first type of gate driving circuit 11 affects the output signal waveform. The first type of gate driving circuit 11 is used to control the writing of data signals. If the rising edge of the clock signal of the second type of gate driving circuit is different from the rising edge of the clock signal of the first type of gate driving circuit 11, the transition of the clock signal of the second type of gate driving circuit will be different from the transition of the output signal of the first type of gate driving circuit 11. In this way, even if there is parasitic capacitance between the clock signal of the second type of gate driving circuit and the data line, the interference of the clock signal of the second type of gate driving circuit on the process of writing data signals into the pixel circuit can be reduced.

[0134] The following are some examples of the second type of gate drive circuit and the clock lines to which they are connected.

[0135] In some embodiments, such as Figure 22 As shown, the display panel 100 also includes a second type of gate driving circuit 12, and the target pixel circuit includes a third target pixel circuit 23. In the third target region A3, the third target pixel circuit 23 and the second type of gate driving circuit 12 are arranged in the first direction X.

[0136] For example, the second type of gate driving circuit 12 includes multiple cascaded second type shift registers VSR2. Within the third target region A3, the second type of shift registers VSR2 and the third target pixel circuits 23 are arranged in the first direction X. In the first direction X, three third target pixel circuits 23 can be arranged between two second type of shift registers VSR2, and these three third target pixel circuits 23 are respectively the pixel circuits corresponding to the red, green, and blue light-emitting elements. In other words, three columns of target pixel circuits 21 can be provided within the target region A1.

[0137] The second type of gate driving circuit 12 is electrically connected to the second type of clock line 32, and both the second type of clock line 32 and the data line 50 extend along the first direction X. Specifically, the second type of gate driving circuit 12 is electrically connected to the second type of clock line 32 through a second type of connection line 42, which extends along the second direction Y.

[0138] In the second direction Y, the third target pixel circuit 23 is electrically connected to a third target data line 53 located on one side of the third target pixel circuit 23, and the second type gate drive circuit 12 is electrically connected to at least one second type clock line 32 located on the other side of the third target pixel circuit 23. That is, at least one second type clock line 32 and the third target data line 53 are located on different sides of the third target pixel circuit 23.

[0139] Taking the second type clock line 32 and the third target data line 53, which transmit the clock signal ck, as being located on different sides of the third target pixel circuit 23, as an example, the second type connection line 42 and the third target data line 53, which transmit the clock signal ck, are also located on different sides of the third target pixel circuit 23. In this way, the second type connection line 42 and the third target data line 53, which transmit the clock signal ck, will not cross, which can reduce the parasitic capacitance between the second type connection line 42 and the third target data line 53, thereby reducing the interference of the clock signal ck on the third target data line 53.

[0140] In other embodiments, such as Figure 23 As shown, the display panel 100 also includes a second type of gate driving circuit 12, and the target pixel circuit includes a third target pixel circuit 23. The third target pixel circuit 23 and the second type of gate driving circuit 12 are arranged in a first direction X; in the second direction Y, the second type of clock line 32 electrically connected to the second type of gate driving circuit 12 is located on the side of the third target pixel circuit 23 away from the center line L of the display panel. In this way, space can be reserved for the side of the second type of clock line 32 closer to the center line L to facilitate the arrangement of other structures.

[0141] like Figures 7 to 10 In any of the following, the first type of gate drive circuit outputs a gate drive signal PAM_S2 or PWM_S2, the second type of gate drive circuit outputs a gate drive signal PAM_S1 or PWM_S1 or PAM_EM or PWM_EM, or the second type of gate drive circuit outputs a sweep frequency signal SWEEP.

[0142] As an example, such as Figure 23 As shown, along the second direction Y, the two sides of the center line L are the first region Q1 and the second region Q2, respectively; the second type clock line 32 of the first region Q1 is located on the side of the second type gate drive circuit 12 away from the center line L, and the second type clock line 32 of the second region Q2 is located on the side of the second type gate drive circuit 12 away from the center line L.

[0143] In this embodiment, both the first region Q1 and the second region Q2 are provided with a second type of gate driving circuit 12, which can realize dual-end driving and reduce signal delay. In addition, the second clock lines of the two regions are located outside the second type of gate driving circuit, which facilitates the symmetrical arrangement of the second clock lines of the two regions and improves the consistency of the driving performance of the two second type of gate driving circuits 12.

[0144] For example, such as Figure 23 As shown, the distance between the second type gate driving circuit 12 in the first region Q1 and the center line L is d31, and the distance between the second type gate driving circuit 12 in the second region Q2 and the center line L is d32, where d31 = d32.

[0145] In the above embodiments, d31=d32, which allows for a certain error. For example, the difference between d31 and d32 can be considered equal if it is within 5%.

[0146] The first zone Q1 and the second zone Q2 are the left and right halves of the display panel, respectively. A second type of gate driving circuit 12 is provided in both the left and right halves of the screen. The distance between the two second type of gate driving circuits 12 and the center line L is equal. In this way, the two second type of gate driving circuits 12 are roughly symmetrical with respect to the center line L, and the load of the two second type of gate driving circuits 12 is basically the same, which can improve the uniformity of the display.

[0147] certainly, Figure 22 and Figure 23 These are merely examples of the second type of gate drive circuit 12 and the second type of clock line connected thereto, and are not intended to limit this application. The second type of gate drive circuit 12 and the second type of clock line connected thereto may also be configured in other ways.

[0148] In some embodiments, such as Figure 3 and Figure 24 As shown, the first type of gate drive circuit 11 is electrically connected to the first type of clock line 31 through the first type of connection line 41; the first type of connection line 41 and the target data line 51 are located on different metal layers.

[0149] For example, at least one first-type clock line 31 is located on the side of the target data line 51 away from the first-type gate drive circuit 11. In this way, in the thickness direction of the display panel, the first-type connection line 41 needs to cross with the target data line 51. The first-type connection line 41 and the target data line 51 are located in different metal layers, which can avoid signal crosstalk between the two types of traces.

[0150] For example, in the thickness direction Z of the display panel, at least one metal layer SD is included between the first type of connection line 41 and the target data line 51. In this embodiment, even though the first type of connection line 41 and the target data line 51 intersect in the thickness direction of the display panel, there is still at least one metal layer between them in the thickness direction. The distance between them is relatively large, which can reduce the parasitic capacitance between them, thereby reducing the interference of the clock signal on the data signal.

[0151] It should be noted that, for the target data line 51 and the first type of clock line 31 on the same side of the target pixel circuit 21, the above embodiments (for example, refer to...) Figure 11 Taking the first type of clock line 31 located on the side of the target data line 51 away from the target pixel circuit 21 as an example, this is not intended to limit the present application. In other embodiments, for the target data line 51 and the first type of clock line 31 on the same side of the target pixel circuit 21, for example, referring to... Figure 25The first type of clock line 31 can be located on the side of the target data line 51 closer to the target pixel circuit 21. Specifically, Figure 25 In the first clock line 31a, the second target data line 51b is located on the side of the first target pixel circuit 21a closer to the second target pixel circuit 21b, and the second clock line 31b is located on the side of the first target data line 51a closer to the second target pixel circuit 21b.

[0152] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 26 , Figure 26 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 26 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 26 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0153] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, It includes a first type of gate driving circuit and a pixel circuit, wherein the pixel circuit includes a target pixel circuit, and the target pixel circuit and the first type of gate driving circuit are arranged in a first direction; The target pixel circuit is electrically connected to the target data line, and the first type of gate driving circuit is electrically connected to the first type of clock line. Both the target data line and the first type of clock line extend along the first direction. In the second direction, the target data line is located on one side of the target pixel circuit, and at least one first-type clock line electrically connected to the first-type gate drive circuit is located on the other side of the target pixel circuit, and the first direction and the second direction intersect.

2. The display panel according to claim 1, characterized in that, The pixel circuit includes a data writing module and a driving module. The first end of the data writing module is electrically connected to a data line, the second end of the data writing module is electrically connected to the driving module, and the output end of the first type of gate driving circuit is electrically connected to the control end of the data writing module.

3. The display panel according to claim 1, characterized in that, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit. The first type of gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The signal output by the first gate driving circuit is used to control the writing of the data signal of the amplitude modulation sub-circuit, and the signal output by the second gate driving circuit is used to control the writing of the data signal of the pulse width modulation sub-circuit. The target pixel circuit includes a first target pixel circuit and a second target pixel circuit. The first target pixel circuit and the first gate driving circuit are arranged in the first direction, and the second target pixel circuit and the second gate driving circuit are arranged in the first direction. The first type of clock line includes a first clock line and a second clock line. The first gate driving circuit is electrically connected to the first clock line, and the second gate driving circuit is electrically connected to the second clock line. The target data line includes a first target data line and a second target data line. The first target data line is electrically connected to the amplitude modulation sub-circuit, and the second target data line is electrically connected to the pulse width modulation sub-circuit. In the second direction, the first target data line is located on one side of the first target pixel circuit, and at least one of the first clock lines electrically connected to the first gate driving circuit is located on the other side of the first target pixel circuit; and / or, in the second direction, the second target data line is located on one side of the second target pixel circuit, and at least one of the second clock lines electrically connected to the second gate driving circuit is located on the other side of the second target pixel circuit.

4. The display panel according to claim 3, characterized in that, In the second direction, the first target data line and the second target data line are located on both sides of the target pixel circuit.

5. The display panel according to claim 4, characterized in that, In the second direction, the first target data line is located on one side of the first target pixel circuit, and at least two first clock lines electrically connected to the first gate driving circuit are located on the other side of the first target pixel circuit; and / or, the second target data line is located on one side of the second target pixel circuit, and at least two second clock lines electrically connected to the second gate driving circuit are located on the other side of the second target pixel circuit.

6. The display panel according to claim 4, characterized in that, The first clock line and the second target data line electrically connected to the first target pixel circuit are located on the same side of the first target pixel circuit; and / or, the second clock line and the first target data line electrically connected to the second target pixel circuit are located on the same side of the second target pixel circuit.

7. The display panel according to claim 4, characterized in that, The display panel includes a center line extending along a first direction, and a first area and a second area on both sides of the center line along a second direction. The distance between the first gate driving circuit in the first region and the center line is equal to the distance between the first gate driving circuit in the second region and the center line. And / or, the distance between the second gate driving circuit in the first region and the center line is equal to the distance between the second gate driving circuit in the second region and the center line.

8. The display panel according to claim 7, characterized in that, For the pixel circuits in the first region and the second region, the data lines electrically connected to the amplitude modulation sub-circuit are located on the first side of the pixel circuit, and the data lines electrically connected to the pulse width modulation sub-circuit are located on the second side of the pixel circuit.

9. The display panel according to claim 8, characterized in that, The first clock line in the first region is located on the side of the first gate driving circuit away from the center line, and the first clock line in the second region is located on the side of the first gate driving circuit closer to the center line. And / or, the second clock line in the first region is located on the side of the second gate drive circuit closer to the center line, and the second clock line in the second region is located on the side of the second gate drive circuit farther from the center line.

10. The display panel according to claim 7, characterized in that, For the pixel circuit in the first region, the data line electrically connected to the amplitude modulation sub-circuit is located on the first side of the pixel circuit, and the data line electrically connected to the pulse width modulation sub-circuit is located on the second side of the pixel circuit; For the pixel circuit in the second region, the data line electrically connected to the amplitude modulation sub-circuit is located on the second side of the pixel circuit, and the data line electrically connected to the pulse width modulation sub-circuit is located on the first side of the pixel circuit.

11. The display panel according to claim 10, characterized in that, The first clock line in the first region is located on the side of the first gate driving circuit away from the center line, and the first clock line in the second region is located on the side of the first gate driving circuit away from the center line. And / or, the second clock line in the first region is located on the side of the second gate drive circuit closer to the center line, and the second clock line in the second region is located on the side of the second gate drive circuit closer to the center line.

12. The display panel according to claim 3, characterized in that, The display panel includes a first area and a second area arranged along the second direction. In the second direction, the second gate driving circuit in the first area is located between the first gate driving circuit in the first area and the second area, and the first gate driving circuit in the second area is located between the second gate driving circuit in the second area and the first area.

13. The display panel according to claim 3, characterized in that, The first target data line and the second target data line electrically connected to the first target pixel circuit are located on one side of the first target pixel circuit, and the first clock line electrically connected to the first gate drive circuit is located on the other side of the first target pixel circuit. And / or, the first target data line and the second target data line electrically connected to the pixel circuit of the second mu are located on one side of the second target pixel circuit, and the second clock line electrically connected to the second gate drive circuit is located on the other side of the second target pixel circuit.

14. The display panel according to claim 13, characterized in that, The display panel includes a center line extending along a first direction, and a first area and a second area on both sides of the center line along a second direction. The distance between the first gate driving circuit in the first region and the center line is equal to the distance between the first gate driving circuit in the second region and the center line. And / or, the distance between the second gate driving circuit in the first region and the center line is equal to the distance between the second gate driving circuit in the second region and the center line.

15. The display panel according to claim 3, characterized in that, In the second direction, the first target data line electrically connected to the first target pixel circuit and at least one first clock line electrically connected to the first gate drive circuit are located on the same side of the first target pixel circuit; and / or, the second target data line electrically connected to the second target pixel circuit and at least one second clock line electrically connected to the second gate drive circuit are located on the same side of the second target pixel circuit.

16. The display panel according to claim 3, characterized in that, The first clock line is electrically connected to the input terminal of the output module in the first gate driving circuit, or the first clock line is electrically connected to the control terminal of the input module in the first gate driving circuit, and the first clock line transmits the first clock signal. The second clock line is electrically connected to the input terminal of the output module in the second gate drive circuit, or the second clock line is electrically connected to the control terminal of the input module in the second gate drive circuit, and the second clock line transmits the second clock signal; The rising edges of the first clock signal and the rising edges of the second clock signal are staggered.

17. The display panel according to claim 16, characterized in that, The rising edges of the first clock signal and the rising edges of the second clock signal are staggered by at least 0.5µs.

18. The display panel according to claim 16, characterized in that, The display panel further includes a second type of gate driving circuit, wherein the rising edge of the clock signal received by the second type of gate driving circuit is staggered from the rising edge of the first clock signal and the rising edge of the second clock signal.

19. The display panel according to claim 1, characterized in that, The display panel further includes a second type of gate driving circuit, the target pixel circuit includes a third target pixel circuit, the third target pixel circuit and the second type of gate driving circuit are arranged in a first direction, and the second type of gate driving circuit is electrically connected to a second type of clock line. In the second direction, the data line electrically connected to the third target pixel circuit is located on one side of the third target pixel circuit, and at least one second type clock line electrically connected to the second type gate drive circuit is located on the other side of the third target pixel circuit.

20. The display panel according to claim 1, characterized in that, The display panel further includes a second type of gate driving circuit, and the target pixel circuit includes a third target pixel circuit. The third target pixel circuit and the second type of gate driving circuit are arranged in a first direction. In the second direction, the second type of clock line electrically connected to the second type of gate drive circuit is located on the side of the third target pixel circuit away from the center line of the display panel.

21. The display panel according to claim 20, characterized in that, Along the second direction, the two sides of the center line are a first region and a second region, respectively; the second type of clock line in the first region is located on the side of the second type of gate driving circuit away from the center line, and the second type of clock line in the second region is located on the side of the second type of gate driving circuit away from the center line.

22. The display panel according to claim 1, characterized in that, The first type of gate drive circuit is electrically connected to the first type of clock line through the first type of connection line; The first type of connecting line and the target data line are located in different metal layers.

23. The display panel according to claim 22, characterized in that, In the thickness direction of the display panel, at least one metal layer is included between the first type of connecting line and the target data line.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-23.

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