Intelligent configuration management system of switch cabinet electrical interlocking box

Abstract

This invention discloses an intelligent configuration management system for electrical interlock boxes in switchgear. This invention relates to the field of switchgear configuration technology and solves the technical problems of low design efficiency, reliance on manual experience, high debugging risks, and lack of verification methods. Through a pre-built electrical component library, each component contains a three-layer data structure: a view layer, an attribute layer, and a rule layer. When a user drags and drops to draw a main wiring diagram, the system can automatically identify and highlight legitimate ports based on the rule layer, displaying a red prohibition symbol and rejecting illegal connections, thus eliminating topology connection errors at the source. By sending device discovery broadcast packets through a communication gateway, a physical device resource pool is automatically constructed. A mapping recommendation engine is used to automatically retrieve candidate channels that meet conditions such as type matching, rule library matching, and priority within the same cabinet based on topology semantic tags, pre-filling the optimal channel into the configuration items, improving configuration efficiency and eliminating human error.

Description

Technical Field

[0001] This invention relates to the field of switchgear configuration technology, specifically to an intelligent configuration management system for switchgear electrical interlock boxes. Background Technology

[0002] As a critical power distribution device in the power system, the operational safety of switchgear is of paramount importance. The electrical interlock box is the core safety control unit of the switchgear, used to achieve logical interlocking between primary equipment such as circuit breakers, disconnectors, and grounding switches, strictly adhering to the five safety requirements of the power system.

[0003] Currently, traditional switchgear electrical interlocking systems mainly adopt the following technical solutions: The first is the hard-wired relay interlocking method. This method achieves logical interlocking through the physical connection of intermediate relays, auxiliary contacts, and secondary cables. Designers manually calculate the number of contacts based on the electrical schematic diagram and connect the auxiliary contacts of different devices in series or parallel through wires to form a logic circuit that meets the five protection requirements; The second method is the Programmable Logic Controller (PLC) method. This method uses a general-purpose PLC as the core of logic processing, implements interlocking logic through ladder diagram programming, and connects input / output modules to the auxiliary contacts and actuators of field devices.

[0004] However, the aforementioned existing technologies have the following drawbacks in practical applications: First, hard-wiring relies entirely on manually drawing secondary circuit diagrams. For complex main wiring methods, this results in a large design workload, a long cycle, and poor drawing reusability. Although PLC methods enable software programming, ladder diagrams still need to be written manually, the logical expression is not intuitive, and there is a lack of design integration with the primary main wiring. Secondly, logic verification can only be performed after equipment installation and during on-site power-on testing. It is impossible to conduct comprehensive simulation testing of complex interlocking logic offline. Once a logic error is discovered, on-site modifications are very reactive, severely impacting project progress and even threatening personal and equipment safety. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an intelligent configuration management system for electrical interlocking boxes in switchgear, which solves the problems of low design efficiency, reliance on manual experience, high debugging risks, and lack of verification methods.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an intelligent configuration management system for electrical interlock boxes in switchgear, comprising: The topology model building module is used to load a pre-built electrical component library, receive drag-and-drop instructions in the graphical editing interface to draw a main wiring diagram, identify legal ports according to the rule layer and guide the connection, generate unique logical IDs and device IDs based on the drawn topology path using a hierarchical coding method, and build a topology link matrix. It discovers online smart interlocking boxes through the communication gateway and parses their hardware self-description information to build a physical device resource pool. When a graphical icon is selected, its topology semantic label is extracted, and the mapping recommendation engine is called to search for matching candidate channels in the resource pool. The mapping relationship between logical devices and hardware IO points is established and an IO point table is generated. The logic analysis and generation module is used to automatically generate basic logic, receive the operation object and the set of anti-misoperation rules, load the corresponding abstract logic constraint meta-model, execute the graph traversal algorithm based on the topology link matrix, identify the key control points that affect the safety of operation, map the abstract logic constraints to the key control points, generate the initial logic tree in combination with the operation mode flag, and arbitrate the logic conflict according to the safety priority matrix. The offline simulation verification module is used to automatically create a virtual switchgear operating environment isolated from the physical world, read all configuration information in the current project database, perform forward logic verification and reverse logic verification, and generate a simulation report; The configuration distribution and verification module is used to generate a patch package based on the simulation results using a differential algorithm, and distribute it to the backup storage area of ​​the target interlock box via encrypted communication. After verification, an atomic switch is performed, and the hardware-in-the-loop verification process is triggered.

[0007] As a further aspect of the present invention, the specific process of identifying legitimate ports and initiating connection guidance based on the rule layer is as follows: When a graphical icon is detected to be close to another icon port, the adjacency matrix constraint table in the rule layer is queried; If the current port combination matches the preset definition of a valid connection pair, the target port will be highlighted and the connection will be allowed. If the current port combination does not conform to the preset definition of a valid connection pair, a forbidden symbol will be displayed and the connection request will be rejected.

[0008] As a further aspect of the present invention, the specific process of calling the mapping recommendation engine to retrieve matching candidate channels in the resource pool includes: The first step is to filter out idle channels in the physical device resource pool whose channel type matches the logic signal type; The second step is to consult the preset standard wiring rule library and assign a first weight value to channels that conform to the recommended wiring specifications. The third step is to calculate the distance between the physical interlock box to which the candidate channel belongs and the cabinet where the current logic device is located, and assign a second weight value to the channels in the same or adjacent cabinets. The fourth step is to select the channel with the highest total weight as the optimal candidate channel and pre-populate it into the configuration items.

[0009] As a further aspect of the present invention, the specific process of the graph traversal algorithm based on the topology link matrix is ​​as follows: Starting from or ending at the object being operated on, a bidirectional breadth-first search is performed on the electrical connectivity graph constructed by the topology link matrix. Traversing to the power supply side, all circuit breakers and handcart contacts connected in series along the path are recorded; traversing to the load side and the grounding end, all grounding switches that may form an electrical loop are identified. Mark all device nodes on the search path as critical control points and record their electrical distances and connections.

[0010] As a further aspect of the present invention, the specific process of arbitrating logical conflicts based on the security priority matrix is ​​as follows: When mutually exclusive sub-logic expressions generated by different rules are detected, a priority directed acyclic graph is constructed to automatically prune logic branches with lower priorities, or to generate a forced unlocking composite logic branch that requires additional authorization authentication.

[0011] As a further aspect of the present invention, the specific process of the reverse logic verification is as follows: In the virtual switchgear operating environment, the device state combination that violates the anti-misoperation rules is forcibly set; when the simulation engine detects a violation state, the highest priority interrupt is triggered to execute a logic clamping operation, and regardless of the result of the user-defined logic calculation, the virtual output signal of the corresponding operation is forcibly set to the disabled state. Simultaneously, a safety violation event record is generated, and the corresponding indicator light is driven to provide alarm visual feedback in the simulation interface; if the verification fails, a simulation report containing hyperlinks is generated.

[0012] As a further aspect of the present invention, the specific process of generating the patch package using the differential algorithm is as follows: By comparing the binary streams of the new local configuration file and the current version file of the interlocking box, a minimal differential patch package is generated using the BSDiff algorithm. Based on the national cryptographic SM2 algorithm, two-way authentication is performed with the target interlocking box. A session key is negotiated to establish an encrypted communication tunnel. The differential patch package is divided into several independently signed data fragments for transmission. If the transmission is interrupted, the index of the received fragments is recorded. After the connection is restored, only the missing fragments are requested.

[0013] As a further aspect of the present invention, the specific process of performing atomic switching and hardware-in-the-loop verification is as follows: The target interlocking box restores the received differential patch to the complete configuration file in the spare storage area. It performs a local CRC check for each data block written, and then uses the built-in public key to verify the digital signature and version compatibility. After successful verification, an atomic flag is written to the secure boot sector, indicating that the backup storage sector will be loaded on the next boot and triggering a soft reboot; After the new configuration starts, if initialization is not completed or a heartbeat signal is not sent within the preset watchdog time window, the hardware watchdog will be forcibly reset and the startup flag will be automatically rolled back to point to the original running memory area. After the verification is passed, the host computer sends a simulated signal command to simulate the real physical waveform and contact jitter, collects the actual output action waveform of the interlock box, compares the action delay and debouncing effect, and if it exceeds the tolerance range, the verification is judged to have failed and a rollback is triggered.

[0014] As a further aspect of the present invention, a configuration management information output module is also included, which is used to display the acquired configuration success log to the corresponding administrator.

[0015] This invention provides an intelligent configuration management system for electrical interlock boxes in switchgear. Compared with existing technologies, it has the following advantages: This invention utilizes a pre-built electrical component library, where each component contains a three-layer data structure: a view layer, an attribute layer, and a rule layer. When a user drags and drops to draw a main wiring diagram, the system can automatically identify and highlight legitimate ports based on the rule layer, while displaying a red prohibition symbol and rejecting illegal connections, thus eliminating topology connection errors at the source.

[0016] This invention sends device discovery broadcast packets through a communication gateway, automatically builds a physical device resource pool, and uses a mapping recommendation engine to automatically retrieve candidate channels that meet conditions such as type matching, rule base matching, and priority for channels in the same cabinet based on topological semantic tags. The optimal channel is pre-populated into the configuration items, which improves configuration efficiency and eliminates human error.

[0017] This invention constructs an electrical connectivity graph using a topology link matrix and automatically identifies key control points through a graph traversal algorithm. It maps abstract anti-misoperation rules into specific logical expressions and merges them to generate an initial logic tree. For example, when a user selects an anti-misoperation rule for circuit breaker closing, the system automatically traverses the states of associated disconnectors, grounding switches, and other equipment to generate a complete logical expression containing conditions such as disconnector closing, grounding switch opening, and trolley operating position, thus achieving automation and intelligence in logic design.

[0018] This invention creates a virtual switchgear operating environment isolated from the physical world, simultaneously performing forward and reverse logic verification. In particular, the reverse logic verification can simulate dangerous operating conditions such as attempting to operate a disconnecting switch while the circuit breaker is closed. The simulation engine detects violations in real time and forces a virtual output flashing alarm, generating a simulation report containing hyperlinks to the error locations. Compared with existing technologies that can only discover logic vulnerabilities during on-site live commissioning, this invention moves safety verification to the design stage, eliminates personal safety risks during commissioning, and achieves exhaustive testing of dangerous operating conditions. Attached Figure Description

[0019] Figure 1 This is a block diagram of the intelligent configuration management system for the electrical interlocking box of the switchgear of the present invention; Figure 2 This is an implementation flowchart of the intelligent configuration management system for the electrical interlocking box of the switchgear of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] First Embodiment Please see Figure 1 This application provides an intelligent configuration management system for electrical interlock boxes in switchgear, including a topology model construction module, a logic analysis generation module, an offline simulation verification module, a configuration distribution and verification module, and a configuration management information output module, and combined with... Figure 1 It can be seen that the information between the above functional modules is transmitted in one direction only.

[0022] The topology model construction module is used to build the system's topology model. Specifically, the system loads a pre-set electrical component library. Each component object in the library contains a three-layer data structure: a view layer, an attribute layer, and a rule layer. In the graphical editing interface, users drag and drop graphical icons from the pre-set device component library. These icons include circuit breakers, disconnectors, grounding switches, handcarts, and busbars to draw the primary main wiring diagram of the target switchgear. The system automatically identifies and highlights valid ports based on the rule layer. If a port is near an invalid port, a red prohibition symbol is displayed, and the connection is rejected. Based on the currently drawn topology path, the system uses a hierarchical coding method to generate unique logical IDs. The specific method for generating unique logical IDs is as follows: starting from the parent node, the ID is dynamically generated according to the format of busbar ID - segment ID - device type - index number, ensuring that the ID remains fixed with the topology structure and does not change due to the addition or deletion of irrelevant nodes. Simultaneously with generating logical IDs, the system generates a unique device ID for each icon and automatically constructs a topology link matrix based on the relationships between icons. Next, each icon is bound to a physical device and a communication address. The system sends device discovery broadcast packets to the LAN / bus via a communication gateway, receives responses from online smart interlocking boxes, parses their hardware self-description information, and constructs a physical device resource pool. This resource pool includes a unique device identifier, communication protocol type, IP / station number, IO module type, current status of each channel, and channel electrical characteristics. When a graphical icon is selected and its properties window is opened, the system extracts the icon's topological semantic tag and simultaneously calls the mapping recommendation engine to search the physical device resource pool for candidate channels that meet the following conditions: Type matching where the physical channel type matches the logical signal type; Prioritize matching the recommended channels defined in the preset standard wiring rule library; Priority should be given to aisles that are located on the same physical interlock box as other equipment in the same cabinet; Next, the optimal candidate channels are pre-populated into the configuration items, a one-to-one mapping relationship is established between the graphical logic devices and the hardware I / O points in the physical world, an I / O point table is generated, and the generated mapping table is transmitted to the logic analysis generation module.

[0023] The logic analysis and generation module is used to call the rule base and automatically generate basic logic. The specific processing is as follows: it receives the selected operation object and the checked anti-misoperation rule set, loads the corresponding logic meta-model from the rule base, and each meta-model is defined as an abstract logical constraint. It calls the generated topology link matrix to construct the electrical connectivity diagram of the current switchgear system. Taking the operation object as the start / end point, it executes the graph traversal algorithm to search from the power supply side to the operation object, identifies all series disconnect switches and handcart contacts, marks all equipment nodes on the search path that affect the operation safety as key control points, and records their current electrical distance and connection relationship. Next, the abstract logical constraints are mapped to key control points. Simultaneously, the system's current operating mode flag is read, dynamic variables are substituted into the logical expressions, and all rule-generated sub-logical expressions are merged into an initial logic tree. If a conflict is found, low-priority branches are automatically pruned according to a preset security priority matrix, or a composite logic with mandatory unlocking permissions is generated. A conflict analysis report is also generated. The specific process of arbitrating logical conflicts based on the security priority matrix is ​​as follows: When it is detected that there is mutual exclusion between the sub-logical expressions generated by different rules, a priority directed acyclic graph is constructed to automatically prune the logical branches with lower priority, or to generate a forced unlocking compound logical branch that requires additional authorization authentication. For example, when selecting the circuit breaker closing error prevention rule, the system automatically traverses the status of devices such as disconnecting switches and grounding switches associated with the circuit breaker in the topology link matrix, takes the conditions such as the disconnecting switch being in the closed position, the grounding switch being in the open position, and the trolley being turned to the working position as logical premises, and generates the basic logical expression that allows the circuit breaker to close by combining the built-in logical operators (AND, OR, NOT) (disconnecting switch closing signal AND grounding switch opening signal AND trolley working position signal).

[0024] For complex scenarios, users can manually adjust the automatically generated basic logic through a visual logic editor. Custom conditions can be added or logical relationships modified. During editing, the system performs real-time syntax checking; if a logical conflict occurs, a prompt will immediately appear and the conflicting node will be highlighted. After completing the logic configuration, the system compiles the final logical expression into machine language instructions supported by the target interlocking box and generates a logic configuration file. This file contains information such as the logic ID, associated device ID, condition set, action output channel, and execution priority.

[0025] Second Embodiment As a second embodiment of the present invention, it is implemented based on the first embodiment, and the difference from the first embodiment is as follows: The offline simulation verification module is used to perform simulation verification based on the completed interlocking logic design. First, it automatically creates a virtual switch cabinet operating environment isolated from the physical world and reads all configuration information in the current project database, including the primary equipment list, the topological connection relationship between each device, the designed interlocking logic rules, and the virtual model of the smart interlocking box. Next, perform forward logic verification. First, click the circuit breaker QF1 button on the console to set it to the open state. Then, pay attention to the output point that allows closing QS1 on the logic editing diagram, or check whether the operation permission indicator light corresponding to QS1 is lit on the simulation console. Since the interlocking logic of QS1 is that the circuit breaker QF1 is opened and the grounding switch ES1 is opened, when QF1 is opened, if ES1 was originally opened, the system should immediately drive the virtual output to light up the virtual indicator light of QS1 that allows operation to green. If the indicator light is lit, it means that the path logic is correct. If it is not lit, the logic or the status of ES1 needs to be checked. Simultaneously, reverse logic verification is performed. First, circuit breaker QF1 is set to the closed state on the console. Observe or try to trigger the conditions that allow operation of disconnector QS1. The simulation engine detects that QF1 is in the closed state, which violates the rule of preventing disconnector from being opened or closed under load. Therefore, regardless of other conditions, the system forcibly allows the virtual output flashing light of QS1 to be closed, and generates a simulation report. If there are errors, the report will directly hyperlink to the corresponding error component in the logic diagram. Only after the simulation report shows that all logic verifications have passed will the system allow the execution of subsequent steps and transmit them to the configuration management output module.

[0026] The configuration distribution and verification module is used to securely distribute the generated configuration file to the target electrical interlock box based on the simulation results, and to verify the validity of the configuration. The specific implementation method is as follows: The system compares the locally generated new configuration file with the current version of the interlocking box, uses the BSDiff algorithm to generate a minimized differential patch package, and the system and the target interlocking box perform two-way authentication based on the national cryptographic SM2 algorithm, negotiate the session key, establish an encrypted communication tunnel, and divide the differential packet into several independently signed data fragments. If the transmission is interrupted, the system records the index of the received fragments. After the connection is restored, it only requests the missing fragments and does not need to retransmit them. The interlocking box receives the master control command, identifies the current running area, automatically selects the backup area as the writing target, restores the decrypted differential patch to the complete configuration file in the backup area, performs local CRC check immediately after writing each data block, and after the file is written, the interlocking box uses the built-in public key to verify the digital signature and version compatibility of the file. If the verification fails, the backup area data is directly discarded, the current running area is kept running, and an invalid signature error is reported. After the verification is passed, an atomic flag is written to the secure boot area to indicate that the backup storage area will be loaded on the next boot and trigger a soft reboot. After the new configuration is started, if initialization is not completed or a heartbeat signal is not sent within the preset watchdog time window, the hardware watchdog will be forcibly reset and the start flag will be automatically rolled back to the original running memory area. After the verification is passed, the host computer sends an analog signal command to simulate the real physical waveform and contact jitter, collects the actual output action waveform of the interlock box, and compares the action delay and debouncing effect. If it exceeds the tolerance range, the verification is judged to have failed and the rollback is triggered. After the configuration is distributed, the system automatically triggers the verification process, sends simulated signal commands to the interlocking boxes, simulates the input states under various combinations of logical conditions, collects the output action feedback of the interlocking boxes in real time, compares the actual output results with the expected logic, generates a verification report, if there are any mismatches, the system locates the specific logical node and prompts the possible causes of the fault, and supports one-click rollback to the historical configuration version; if the verification passes, a configuration success log is generated and the system configuration ledger is updated, and it is also transmitted to the configuration management information output module.

[0027] The configuration management information output module is used to display the successfully acquired configuration logs to the corresponding administrators.

[0028] Third Embodiment As a third embodiment of the present invention, the focus is on combining the implementation processes of the first and second embodiments.

[0029] Some of the data in the above formulas are numerical calculations with dimensions removed, and the contents not described in detail in this specification are all prior art known to those skilled in the art.

[0030] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. An intelligent configuration management system for electrical interlock boxes in switchgear, characterized in that, include: The topology model building module is used to load a pre-built electrical component library, receive drag-and-drop instructions in the graphical editing interface to draw a main wiring diagram, identify legal ports according to the rule layer and guide the connection, generate unique logical IDs and device IDs based on the drawn topology path using a hierarchical coding method, and build a topology link matrix. It discovers online smart interlocking boxes through the communication gateway and parses their hardware self-description information to build a physical device resource pool. When a graphical icon is selected, its topology semantic label is extracted, and the mapping recommendation engine is called to search for matching candidate channels in the resource pool. The mapping relationship between logical devices and hardware IO points is established and an IO point table is generated. The logic analysis and generation module is used to automatically generate basic logic, receive the operation object and the set of anti-misoperation rules, load the corresponding abstract logic constraint meta-model, execute the graph traversal algorithm based on the topology link matrix, identify the key control points that affect the safety of operation, map the abstract logic constraints to the key control points, generate the initial logic tree in combination with the operation mode flag, and arbitrate the logic conflict according to the safety priority matrix. The offline simulation verification module is used to automatically create a virtual switchgear operating environment isolated from the physical world, read all configuration information in the current project database, perform forward logic verification and reverse logic verification, and generate a simulation report; The configuration distribution and verification module is used to generate a patch package based on the simulation results using a differential algorithm, and distribute it to the backup storage area of ​​the target interlock box via encrypted communication. After verification, an atomic switch is performed, and the hardware-in-the-loop verification process is triggered.

2. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of identifying legitimate ports and initiating connection guidance based on the rule layer is as follows: When a graphical icon is detected to be close to another icon port, the adjacency matrix constraint table in the rule layer is queried; If the current port combination matches the preset definition of a valid connection pair, the target port will be highlighted and the connection will be allowed. If the current port combination does not conform to the preset definition of a valid connection pair, a forbidden symbol will be displayed and the connection request will be rejected.

3. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of calling the mapping recommendation engine to retrieve matching candidate channels in the resource pool includes: The first step is to filter out idle channels in the physical device resource pool whose channel type matches the logic signal type; The second step is to consult the preset standard wiring rule library and assign a first weight value to channels that conform to the recommended wiring specifications. The third step is to calculate the distance between the physical interlock box to which the candidate channel belongs and the cabinet where the current logic device is located, and assign a second weight value to the channels in the same or adjacent cabinets. The fourth step is to select the channel with the highest total weight as the optimal candidate channel and pre-populate it into the configuration items.

4. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of the graph traversal algorithm based on the topological link matrix is ​​as follows: Starting from or ending at the object being operated on, a bidirectional breadth-first search is performed on the electrical connectivity graph constructed by the topology link matrix. Traversing to the power supply side, all circuit breakers and handcart contacts connected in series along the path are recorded; traversing to the load side and the grounding end, all grounding switches that may form an electrical loop are identified. Mark all device nodes on the search path as critical control points and record their electrical distances and connections.

5. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process for arbitrating logical conflicts based on the security priority matrix is ​​as follows: When mutually exclusive sub-logic expressions generated by different rules are detected, a priority directed acyclic graph is constructed to automatically prune logic branches with lower priorities, or to generate a forced unlocking composite logic branch that requires additional authorization authentication.

6. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of the reverse logic verification is as follows: In the virtual switchgear operating environment, the device state combination that violates the anti-misoperation rules is forcibly set; when the simulation engine detects a violation state, the highest priority interrupt is triggered to execute a logic clamping operation, and regardless of the result of the user-defined logic calculation, the virtual output signal of the corresponding operation is forcibly set to the disabled state. Simultaneously, a record of safety violation events is generated, and the corresponding indicator lights are driven in the simulation interface to provide alarm visual feedback. If the verification fails, a simulation report containing hyperlinks will be generated.

7. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of generating the patch package using the differential algorithm is as follows: By comparing the binary streams of the new local configuration file and the current version file of the interlocking box, a minimal differential patch package is generated using the BSDiff algorithm. Based on the national cryptographic SM2 algorithm, two-way authentication is performed with the target interlocking box. A session key is negotiated to establish an encrypted communication tunnel. The differential patch package is divided into several independently signed data fragments for transmission. If the transmission is interrupted, the index of the received fragments is recorded. After the connection is restored, only the missing fragments are requested.

8. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, The specific process of performing atomic switching and hardware-in-the-loop verification is as follows: The target interlocking box restores the received differential patch to the complete configuration file in the spare storage area. It performs a local CRC check for each data block written, and then uses the built-in public key to verify the digital signature and version compatibility. After successful verification, an atomic flag is written to the secure boot sector, indicating that the backup storage sector will be loaded on the next boot and triggering a soft reboot; After the new configuration starts, if initialization is not completed or a heartbeat signal is not sent within the preset watchdog time window, the hardware watchdog will be forcibly reset and the startup flag will be automatically rolled back to point to the original running memory area. After the verification is passed, the host computer sends a simulated signal command to simulate the real physical waveform and contact jitter, collects the actual output action waveform of the interlock box, compares the action delay and debouncing effect, and if it exceeds the tolerance range, the verification is judged to have failed and a rollback is triggered.

9. The intelligent configuration management system for a switchgear electrical interlock box according to claim 1, characterized in that, It also includes a configuration management information output module, which is used to display the obtained configuration success logs to the corresponding administrators.

Images