A phased array hierarchical multi-step delay distribution method, system and medium based on peak comparison strategy

Abstract

This invention discloses a phased array hierarchical multi-step delay allocation method, system, and medium based on a peak comparison strategy, relating to the field of broadband phased array beam control. The method is applied to a phased array system employing a two-stage cascaded architecture of first-stage and second-stage delayers. The method includes: acquiring beam control information to calculate the basic delay and acquiring delay compensation data; determining the target quadrant and the coordinates of the maximum delay element based on the beam angle polarity, and calculating the peak delay across the entire array surface; executing a peak comparison strategy, comparing the peak delay with the total delay of the first stage; when the peak delay exceeds the total delay of the first stage, introducing a second-stage delayer and accumulating it step-by-step according to a step value until the peak delay is covered, thereby determining the configured delay; finally, calculating the target delay of each element and decomposing it into two levels of control codes. This invention effectively achieves high-precision, large-angle broadband beam control through a dynamically configured hierarchical delay strategy.

Description

Technical Field

[0001] This invention relates to the field of broadband phased array beam control, and more specifically to a phased array hierarchical multi-step delay allocation method based on a peak comparison strategy. Background Technology

[0002] The statements in this section are provided only as background information in connection with this disclosure and may not constitute prior art.

[0003] A broadband phased array system consists of a large number of array element channels. Each channel integrates a power amplifier, a low-noise amplifier, a delay unit, a phase shifter, and control circuitry. These devices form the transmit / receive (TR) component. By precisely controlling the amplitude and phase (or delay) characteristics of each TR component within the array, the system can achieve superior performance such as large-angle beam scanning, high pointing accuracy, and large instantaneous bandwidth under broadband signals.

[0004] The TR component adjusts the transmission time of the signal to different array elements by using built-in delayers or phase shifters to form the required beam shape and direction, thereby achieving beam control. This technology has been widely used in broadband transceiver systems. In broadband operating scenarios, the fixed phase shift introduced by the phase shifter causes its equivalent delay to vary with frequency, i.e., frequency dispersion, which ultimately affects the accuracy of beam pointing and limits the instantaneous bandwidth of the system. Therefore, for broadband phased arrays, the use of a True Time Delay (TTD) can provide a frequency-independent constant group delay, ensuring that different frequency components in the signal remain synchronized in the target direction, thereby effectively overcoming frequency dispersion and achieving high-precision broadband beam control.

[0005] In currently used subarray delay systems, single-level subarray architecture and multi-level subarray hierarchical delay architecture are commonly used for subarray design. Compared with single-level subarray architecture, multi-level subarray hierarchical delay technology has become one of the key methods to improve the performance of broadband phased array systems. The application of hierarchical multi-step delayers can significantly improve beam pointing accuracy, effectively extend the array scanning range, and optimize antenna radiation performance.

[0006] While hierarchical multi-step delay units can effectively improve beam pointing accuracy and scanning range, their implementation requires complex combination logic of multi-level delay units to complete the inter-channel delay allocation. As the array element size increases, the number of beam control code combinations required by the traditional lookup table method grows exponentially, leading to a surge in storage resource overhead. Once the array scanning angle range or scanning accuracy changes, the code table must be reconfigured, resulting in low flexibility. On the other hand, the hierarchical calculation method faces challenges of global optimization and insufficient real-time performance due to the coupling of multi-level delay quantities, making it difficult to achieve effective combination of global multi-level delays. Summary of the Invention

[0007] The purpose of this invention is to address the problems of high resource consumption and low flexibility in traditional lookup table methods, and the difficulty in global optimization and poor real-time performance in hierarchical calculation methods. This invention proposes a phased array hierarchical multi-step delay allocation method, system, and medium based on a peak comparison strategy, achieving fast and high-precision beam control. FPGA (Field-Programmable Gate Array), as a commonly used logic device, has advantages such as strong parallel processing capability, low latency, low power consumption, and strong real-time performance. This method is used to classify and combine hierarchical multi-step delays for multiple channels of a phased array. Two-level delay weights are dynamically configured based on the peak delay of each channel, achieving the globally optimal classification and combination of delays between channels. Relying on the FPGA pipeline computing architecture, it supports reconfiguration of the entire array's hierarchical delay codes within 1µs, meeting the rapid switching requirements of beam pointing in highly dynamic scenarios.

[0008] The technical solution of the present invention is as follows: A phased array hierarchical multi-step delay allocation method based on a peak comparison strategy is applied to a phased array system containing multiple array elements. The delay channels of the array elements adopt a two-stage cascaded architecture of a first-stage delayer and a second-stage delayer. The method includes the following steps: Acquire the control information of the target beam, and parse the control information to obtain the azimuth angle of the target beam. and pitch angle And according to the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay And obtain pre-stored delay compensation data. ; According to the azimuth angle and pitch angle The polarity determines the target quadrant, and based on the target quadrant, the coordinates of the maximum delay element in the array face requiring the maximum delay are determined, combined with the azimuth-based delay. Pitch foundation delay and the delay compensation data Calculate the peak delay across the entire array. ; Execute peak comparison strategy: compare the peak delay amount The total delay provided by the first stage delay unit Compare; if If so, it is determined that only the first-level delay unit will be used for allocation; if Then a second-stage delay unit is introduced, and the delay values ​​of the second-stage delay unit are gradually increased until the total delay value of the first stage is reached. The sum of the accumulated second-level delay amounts covers the peak delay amount. This determines the configuration delay amount of the second-stage delay unit; Based on the determined strategy, the target delay amount of each array element is calculated, and the target delay amount is decomposed into control codes corresponding to the first-level delayer and the second-level delayer, and then sent to each array element.

[0009] Furthermore, based on the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay The specific calculation formula is as follows:

[0010]

[0011] in: The azimuth spacing of the array elements; The pitch spacing of the array elements.

[0012] Furthermore, based on the azimuth angle and pitch angle The polarity determines the target quadrant, and based on the target quadrant, the coordinates of the maximum delay element in the array surface requiring the maximum delay are determined, including the following steps: like and It is determined to be in the first quadrant, and the coordinates of the maximum delay element are: ; like and It is determined to be in the second quadrant, and the coordinates of the maximum delay element are: ; like and It is determined to be in the third quadrant, and the coordinates of the maximum delay element are: ; like It is determined to be in the fourth quadrant, and the coordinates of the maximum delay element are: ; in: This represents the total number of array elements in the X direction of the array surface; This represents the total number of array elements in the Y direction of the array face.

[0013] Furthermore, the delay amounts of the second-stage delay units are progressively increased, specifically including: Let the number of bits in the second-stage delay be... The corresponding delay amounts are respectively ,in, ; judge Is this condition met? If so, determine the configuration delay amount of the second-stage delay unit. ; If not, continue the evaluation. Is it valid? And so on, until the condition is met. Then the configuration delay amount of the second-stage delay unit is determined as follows: ,in This is the currently accumulated ladder index.

[0014] Furthermore, the target delay of each array element is calculated, specifically including: Based on the array element coordinates Calculate the target delay of the array element according to the following formula. :

[0015] in: These are the coordinates of the array element's orientation. The elevation coordinates of the array element.

[0016] Furthermore, the following constraints must be met to ensure delay continuity:

[0017] in: This represents the minimum element delay across the entire array.

[0018] Furthermore, the first-stage delay is a small-step delay with a step accuracy in the ps range, and is independently arranged in each array element channel; the second-stage delay is a large-step delay with a step accuracy in the ns range, and is arranged in the common channel of the subarray composed of multiple array elements.

[0019] This invention also proposes a phased array hierarchical multi-step delay allocation system based on a peak comparison strategy, comprising: The basic delay calculation module is used to obtain the control information of the target beam, parse the azimuth and elevation angles, calculate the basic azimuth delay and elevation delay, and obtain the pre-stored delay compensation data. The target quadrant selection module is used to determine the target quadrant and the corresponding maximum delay array element coordinates based on the polarity of the azimuth and elevation angles, and to calculate the peak delay of the entire array surface in combination with the delay compensation data. The hierarchical allocation module is used to compare the peak delay with the total delay of the first-level delay unit. When the peak delay exceeds the total delay of the first-level delay unit, the delay of the second-level delay unit is accumulated from small to large until it covers the peak delay, thereby determining the delay hierarchical strategy. The delay accumulation module is used to calculate the target delay of each array element based on the coordinate position of each array element, the azimuth base delay, and the elevation base delay. The delay control module is used to decompose the target delay amount into control codes and send them to the corresponding first-level delay and second-level delay.

[0020] Furthermore, the system is implemented based on a field-programmable gate array (FPGA), which employs a pipelined computing architecture. The delay control module sends control codes to each array element via the SPI protocol.

[0021] The present invention also proposes a computer-readable storage medium for storing instructions that, when executed, cause the method described above to be implemented.

[0022] Compared with existing technologies, the advantages of this invention are: 1. This invention constructs a collaborative architecture of "small step precision control - large step angle expansion," and based on a dynamic decomposition strategy of peak delay, accurately allocates global requirements to subarray-level large step segments and cell-level small step segments, dividing the delay into... In a 24-element delay system example, this algorithm was applied for beam control, and the delay calculation and hierarchical multi-step delay allocation can be completed within 1µs, with a calculation error of no more than ±12.5ps (<1 / 2 LSB). In the anechoic chamber, the beam angle error of the array system was within 3° during radiation pattern testing, and it also supports a large dynamic delay range of 5075ps, providing experimental support for large-scale arrays.

[0023] 2. This invention is applied to broadband phased array beam control systems, which can quickly achieve efficient delay allocation and ensure high-precision, large-angle beam control, providing an engineerable beam control solution for next-generation phased array systems. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0025] Figure 1 This is a diagram showing the array surface distribution of a planar phased array. Figure 2 This is a schematic diagram of the two-stage delay circuit. Figure 3 Flowchart for delay allocation; Figure 4 Block diagram for FPGA delay allocation algorithm implementation; Figure 5 This is a simulation diagram of the time delay calculation for Example 2, with an azimuth angle of 40° and an elevation angle of 0°. Figure 6 This is a test pattern of the 24-element array (left is 30°, right is 40°). Detailed Implementation

[0026] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0028] Example 1 This embodiment provides a phased array hierarchical multi-step delay allocation method based on peak comparison strategy. This method is applied to a broadband phased array beam control system and aims to solve the problems of high resource consumption and difficulty in global optimization of traditional table lookup method and hierarchical calculation method.

[0029] Please see Figure 1 The application scenario in this embodiment is a planar phased array. Assuming the horizontal direction is the X direction and the elevation direction is the Y direction, the array surface includes... There are array elements, that is, there are in the X direction. There are array elements, with one in the Y direction. Each array element. The azimuth spacing between array elements is... The pitch spacing of the array elements is The coordinates of the origin point of the reference element of the array are: The coordinates of any array element within the array are ,in .

[0030] The array element delay channel of this system adopts a two-stage serial architecture of "small step control accuracy - large step topology angle" (see [link]). Figure 2 The first-stage delay unit is a small-step delay unit with a step accuracy in the ps range (e.g., 25 ps step), independently arranged in each array element channel, used for fine-tuning the delay between channels; the second-stage delay unit is a large-step delay unit with a step accuracy in the ns range (e.g., 500 ps step), arranged in the common channel of the subarray composed of multiple array elements, used for supplementing the delay between subarrays. This architecture can effectively improve the single-beam pointing accuracy while expanding the beam pointing range of the array.

[0031] Assuming the first-stage delay has p bits, the corresponding delay values ​​are as follows: The second-stage delay has a bit depth of q, and the corresponding delay values ​​are as follows: The total delays for the first and second stages are as follows:

[0032]

[0033] in: This indicates the total delay that the first-stage delay unit can provide. This indicates the total delay provided by the second-stage delay unit. , .

[0034] Specifically, this embodiment proposes a phased array hierarchical multi-step delay allocation method based on a peak comparison strategy, which includes the following steps: Step S1: Obtain the control information of the target beam and parse the control information to obtain the azimuth angle of the target beam. (Theoretical scope is) ) and pitch angle And according to the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay And obtain pre-stored delay compensation data. (This data is usually related to specific hardware channel differences); In this embodiment, specifically, according to the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay The specific calculation formula is as follows:

[0035]

[0036] in: The azimuth spacing of the array elements; The pitch spacing of the array elements.

[0037] In this embodiment, it should be noted that the azimuth base delay amount Pitch base delay These represent the delay increments required by adjacent array elements in the X and Y directions when the beam is pointed at a specific angle.

[0038] Step S2: Based on the azimuth angle and pitch angle The polarity determines the target quadrant, and based on the target quadrant, the coordinates of the maximum delay element in the array face requiring the maximum delay are determined, combined with the azimuth-based delay. Pitch foundation delay and the delay compensation data Calculate the peak delay across the entire array. ; In this embodiment, it should be noted that, as shown in Table 1, for a two-dimensional planar phased array, the delay must be a positive value. To calculate the delay budget required for the entire array, it is necessary to determine which array element has the largest delay requirement. This is based on the azimuth angle. and pitch angle The polarity of the beam can divide the target beam direction into four quadrants, and the coordinates of the maximum delay element (i.e., the element farthest from the beam wavefront) are different in different quadrants: like and It is determined to be in the first quadrant (beam pointing to the upper right, maximum delay occurs in the lower left corner), and the coordinates of the maximum delay element are: ; like and It is determined to be in the second quadrant (beam pointing to the upper left, maximum delay occurs in the lower right corner), and the coordinates of the maximum delay element are: ; like and It is determined to be in the third quadrant (beam pointing to the lower right, maximum delay occurs in the upper left corner), and the coordinates of the maximum delay element are: ; like It is determined to be in the fourth quadrant (beam pointing to the lower left, maximum delay occurs in the upper right corner), and the coordinates of the maximum delay element are: ; Determine the coordinates of the maximum delay array element Then, combined with delay compensation data Calculate the peak delay across the entire array. (Right now ):

[0039] Table 1 Calculation of Delay in Different Quadrants

[0040] That is, step S3: execute the peak comparison strategy; it should be noted that the total delay provided by the two-stage delay unit and the peak delay required by the array should satisfy the relationship shown in the equation:

[0041] When allocating delay amounts, in order to improve beam pointing accuracy, small step delay units should be used first. Only when small step delay units cannot provide sufficient delay should large step delay units be used. Therefore, the peak comparison strategy is as follows: The peak delay The total delay provided by the first stage delay unit Compare; if If so, it is determined that only the first-level delay unit will be used for allocation; if Then a second-stage delay unit is introduced, and the delay values ​​of the second-stage delay unit are gradually increased until the total delay value of the first stage is reached. The sum of the accumulated second-level delay amounts covers the peak delay amount. This determines the configuration delay amount of the second-stage delay unit; In this embodiment, specifically, the delay amount of the second-stage delay unit is accumulated step by step from small to large, including: Let the number of bits in the second-stage delay be... The corresponding delay amounts are respectively ,in, ; judge Is this condition met? If so, determine the configuration delay amount of the second-stage delay unit. ; If not, continue the evaluation. Is it valid? And so on, until the condition is met. Then the configuration delay amount of the second-stage delay unit is determined as follows: ,in This is the currently accumulated ladder index.

[0042] That is, the system pre-sets the total delay amount of the first stage of the first-stage delay unit. (For example, obtained by accumulating p-bit small-step delay units). The calculated... and Comparisons are made to dynamically determine the delay allocation strategy.

[0043] In this embodiment, it should be noted that for an M×N planar phased array, the coordinates of the maximum delay element and the corresponding peak delay are... As shown in Table 2.

[0044] Table 2 Calculation of Maximum Delay in the Array

[0045] right Perform successive comparisons; if the total delay of the first stage... It can cover peak latency. All delays are provided by the first-level delay unit; if the first-level delay unit cannot cover the delay... A second-stage delay unit needs to be introduced. The delay is compared step-by-step, starting from the minimum delay value of the second-stage delay unit. The specific delay allocation process is as follows: Figure 3 As shown.

[0046] according to Figure 3 The process shown divides the delay amount into categories based on the range of peak delay. This is one scenario. To ensure that the calculated delay covers the target delay as much as possible, the maximum element delay is [value missing] at any beam angle. and minimum array element delay The difference between the second-level minimum delay and the second-level minimum delay The following conditions must be met:

[0047] in: This represents the minimum element delay across the entire array. This constraint ensures that, regardless of where the beam is pointed, the maximum delay difference within the array will not exceed the minimum resolution of the second-stage delay unit, thus guaranteeing the integrity of beamforming.

[0048] Step S4: Based on the determined strategy, calculate the target delay amount for each array element, and decompose the target delay amount into control codes corresponding to the first-level delayer and the second-level delayer, and send them to each array element.

[0049] In this embodiment, specifically, calculating the target delay of each array element includes: Based on the array element coordinates Calculate the target delay of the array element according to the following formula. :

[0050] in: These are the coordinates of the array element's orientation. The elevation coordinates of the array element.

[0051] Subsequently, the delay control module in the system decomposes the target delay into two parts: A portion corresponds to the configuration delay amount of the second-level delay unit (this may be common or regional). The remaining portion is handled by independent first-stage delay units for each channel. The system converts the decomposed data into control codes and sends them to the TR components of each array element via the SPI protocol.

[0052] Please see Figure 4 Based on the same inventive concept, this embodiment also proposes a phased array hierarchical multi-step delay allocation system based on a peak comparison strategy, comprising: The basic delay calculation module is used to obtain the control information of the target beam, parse the azimuth and elevation angles, calculate the basic azimuth delay and elevation delay, and obtain the pre-stored delay compensation data. The target quadrant selection module is used to determine the target quadrant and the corresponding maximum delay array element coordinates based on the polarity of the azimuth and elevation angles, and to calculate the peak delay of the entire array surface in combination with the delay compensation data. The hierarchical allocation module is used to compare the peak delay with the total delay of the first-level delay unit. When the peak delay exceeds the total delay of the first-level delay unit, the delay of the second-level delay unit is accumulated from small to large until it covers the peak delay, thereby determining the delay hierarchical strategy. The delay accumulation module is used to calculate the target delay of each array element based on the coordinate position of each array element, the azimuth base delay, and the elevation base delay. The delay control module is used to decompose the target delay amount into control codes and send them to the corresponding first-level delay and second-level delay.

[0053] In this embodiment, the system is specifically implemented based on a field-programmable gate array (FPGA). The FPGA adopts a pipelined computing architecture, and the delay control module sends control codes to each array element via the SPI protocol.

[0054] That is, the method in this embodiment can be implemented using an FPGA (Field-Programmable Gate Array). The FPGA employs a pipelined computing architecture, including a basic delay calculation module, a target quadrant selection module, a delay accumulation module, a hierarchical allocation module, and a delay control module. Benefiting from the parallel processing capabilities of the FPGA, this method can be implemented... The entire array can be reconfigured with a delay within the time frame to meet the requirements of fast beam switching in high dynamic scenarios.

[0055] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to execute a phased array hierarchical multi-step delay allocation method based on a peak comparison strategy, as described above.

[0056] In some alternative embodiments, the present invention also provides a method for hierarchical multi-step delay allocation of a phased array based on a peak comparison strategy, which can also be implemented as a program product including program code. When the program product is run on a device, the program code is used to cause the control device to perform the steps in the method for hierarchical multi-step delay allocation of a phased array based on a peak comparison strategy according to various exemplary embodiments of the present invention as described above.

[0057] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operation of the method of the invention is described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0058] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can be implemented in one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs) containing computer-usable program code. The form of a computer program product implemented on ROM, optical memory, etc.

[0059] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] Program code for performing the operations of this invention can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0061] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0062] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0063] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0064] Example 2 This embodiment selects a TR component delay system containing 24 array elements as a specific object to verify the effectiveness and accuracy of the method described in Embodiment 1.

[0065] In this verification system, the delay architecture adopts a combination of "cell-level fine-tuning + subarray-level coarse-tuning", and the specific hardware parameters are configured as follows: The first-stage delay unit (fine-tuning stage) is independently arranged in each channel of the 24 array elements across the entire array. This stage uses a 6-bit digital delay unit with a minimum step size (LSB) set to 25ps, thus providing a total delay of 1575ps.

[0066] The second-stage delay unit (coarse adjustment stage) is located in the common channel of each subarray consisting of six array elements. This stage uses 3-bit large-step delay units, namely 500ps, 1000ps, and 2000ps, to cover delay requirements exceeding the range of the first stage.

[0067] Under the aforementioned hardware conditions, the target beam control information is set as follows: azimuth 40°, elevation 0°. Applying the peak comparison strategy and hierarchical allocation method of this invention, the theoretical target delay for each array element is calculated. It is then decomposed into control codes for two-stage delay units to obtain the actual configured delay amount. The calculation and allocation results of some typical array element coordinates are compared. The specific data is shown in the table below: Table 3. Comparison of Theoretical and Actual Delays for 24 Array Elements

[0068] The above table will and By comparison, the error value is obtained. The calculation results show that the error is less than half of the minimum step delay, that is:

[0069] The algorithm was simulated in the software with a master clock frequency of 100MHz. The simulation results are as follows. Figure 5 As shown in the figure. According to the simulation results, the FPGA delay allocation algorithm has a calculation time of 0.72us. That is, this algorithm can complete the delay calculation and hierarchical multi-step delay allocation within 1us.

[0070] System radiation pattern tests were conducted in both a darkroom and an outdoor environment, with tests performed at target azimuth angles of 30° and 40°, respectively. The radiation pattern test results are as follows: Figure 6 As shown, the red curve represents the darkroom environment, the blue curve represents the outdoor environment, and the error between the test angle and the target angle of the radiation pattern is less than 3°.

[0071] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

[0072] This background section is provided to generally present the context of the invention. The work of the currently named inventors, the work to the extent described in this background section, and aspects described in this section that did not constitute prior art at the time of application are neither expressly nor impliedly acknowledged as prior art to the invention.

Claims

1. A phased array hierarchical multi-step delay allocation method based on a peak comparison strategy, applied to a phased array system containing multiple array elements, wherein the delay channel of the array elements adopts a two-stage cascaded architecture of a first-stage delayer and a second-stage delayer, characterized in that, The method includes the following steps: Acquire the control information of the target beam, and parse the control information to obtain the azimuth angle of the target beam. and pitch angle And according to the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay And obtain pre-stored delay compensation data. ; According to the azimuth angle and pitch angle The polarity determines the target quadrant, and based on the target quadrant, the coordinates of the maximum delay element in the array face requiring the maximum delay are determined, combined with the azimuth-based delay. Pitch foundation delay and the delay compensation data Calculate the peak delay across the entire array. ; Execute peak comparison strategy: compare the peak delay amount The total delay provided by the first stage delay unit Compare; if If so, it is determined that only the first-level delay unit will be used for allocation; if Then a second-stage delay unit is introduced, and the delay values ​​of the second-stage delay unit are gradually increased until the total delay value of the first stage is reached. The sum of the accumulated second-level delay amounts covers the peak delay amount. This determines the configuration delay amount of the second-stage delay unit; Based on the determined strategy, the target delay amount of each array element is calculated, and the target delay amount is decomposed into control codes corresponding to the first-level delayer and the second-level delayer, and then sent to each array element.

2. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 1, characterized in that, According to the azimuth angle and the pitch angle Calculate the azimuth base delay Pitch base delay The specific calculation formula is as follows: in: The azimuth spacing of the array elements; The pitch spacing of the array elements.

3. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 2, characterized in that, According to the azimuth angle and pitch angle The polarity determines the target quadrant, and based on the target quadrant, the coordinates of the maximum delay element in the array surface requiring the maximum delay are determined, including the following steps: like and It is determined to be in the first quadrant, and the coordinates of the maximum delay element are: ; like and It is determined to be in the second quadrant, and the coordinates of the maximum delay element are: ; like and It is determined to be in the third quadrant, and the coordinates of the maximum delay element are: ; like It is determined to be in the fourth quadrant, and the coordinates of the maximum delay element are: ; in: This represents the total number of array elements in the X direction of the array surface; This represents the total number of array elements in the Y direction of the array face.

4. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 1, characterized in that, The delay values ​​of the second-stage delay units are accumulated progressively from small to large, specifically including: Let the number of bits in the second-stage delay be... The corresponding delay amounts are respectively ,in, ; judge Is this condition met? If so, determine the configuration delay amount of the second-stage delay unit. ; If not, continue the evaluation. Is it valid? And so on, until the condition is met. Then the configuration delay amount of the second-stage delay unit is determined as follows: ,in This is the currently accumulated ladder index.

5. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 1, characterized in that, Calculate the target delay for each array element, specifically including: According to the array element coordinates Calculate the target delay of the array element according to the following formula. : in: These are the coordinates of the array element's orientation. The elevation coordinates of the array element.

6. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 1, characterized in that, The following constraints must also be met to ensure delay continuity: in: This represents the minimum element delay across the entire array.

7. The phased array hierarchical multi-step delay allocation method based on peak comparison strategy according to claim 1, characterized in that, The first-stage delay is a small-step delay with a step accuracy in the ps range, and is independently arranged in each array element channel; the second-stage delay is a large-step delay with a step accuracy in the ns range, and is arranged in the common channel of a subarray composed of multiple array elements.

8. A phased array hierarchical multi-step delay allocation system based on a peak comparison strategy, characterized in that, include: The basic delay calculation module is used to obtain the control information of the target beam, parse the azimuth and elevation angles, calculate the basic azimuth delay and elevation delay, and obtain the pre-stored delay compensation data. The target quadrant selection module is used to determine the target quadrant and the corresponding maximum delay array element coordinates based on the polarity of the azimuth and elevation angles, and to calculate the peak delay of the entire array surface in combination with the delay compensation data. The hierarchical allocation module is used to compare the peak delay with the total delay of the first-level delay unit. When the peak delay exceeds the total delay of the first-level delay unit, the delay of the second-level delay unit is accumulated from small to large until it covers the peak delay, thereby determining the delay hierarchical strategy. The delay accumulation module is used to calculate the target delay of each array element based on the coordinate position of each array element, the azimuth base delay, and the elevation base delay. The delay control module is used to decompose the target delay amount into control codes and send them to the corresponding first-level delay and second-level delay.

9. A phased array hierarchical multi-step delay allocation system based on a peak comparison strategy according to claim 8, characterized in that, The system is implemented based on a field-programmable gate array (FPGA). The FPGA adopts a pipelined computing architecture, and the delay control module sends control codes to each array element via the SPI protocol.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 1-7 to be implemented.

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