Non-return-to-zero code based on adjacent symbol difference decision for cable receiver

Abstract

A non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision includes: a feedforward enhanced continuous-time linear equalizer, four parallel time-interleaved sample-and-hold circuits, an adjacent symbol differential decision comparator with embedded positive feedback, and deserialization circuits connected to the four adjacent symbol differential decision comparators respectively. This invention employs a feedforward enhanced continuous-time linear equalizer and an adjacent symbol differential decision comparator with embedded positive feedback. The adjacent symbol differential decision technology avoids the need for high-amplitude equalization of the input signal, significantly reducing system power consumption while suppressing common-mode noise. By introducing feedforward technology into the continuous-time linear equalizer, its equalization strength is improved without significantly increasing power consumption. By introducing positive feedback technology into the comparator, the comparator delay is reduced, enabling NRZ reception at a data transmission rate of 64Gb / s, effectively equalizing 12dB of channel attenuation, while the total power consumption is only 70.4mW.

Description

Technical Field

[0001] This invention relates to a technology in the field of communication systems, specifically a non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision. Background Technology

[0002] In high-speed serial wired interface communication, the receiver needs to make correct decisions on the received signal. However, the existing receivers require excessive equalization strength, resulting in high power consumption. The continuous-time linear equalizer has low transconductance efficiency, and the comparator has a large delay. Summary of the Invention

[0003] This invention addresses the problems of high equalization power consumption, weak common-mode noise suppression, low transconductance efficiency of continuous-time linear equalizers, and large comparator delays in existing high-speed serial wired receivers when dealing with high-loss channels. It proposes a non-return-to-zero (NRZ) code wired receiver based on adjacent symbol differential decision. This receiver employs a feedforward enhanced continuous-time linear equalizer and an adjacent symbol differential decision comparator with embedded positive feedback. The adjacent symbol differential decision technique avoids the need for high-amplitude equalization of the input signal, significantly reducing system power consumption while suppressing common-mode noise. By introducing feedforward technology into the continuous-time linear equalizer, its equalization strength is improved without significantly increasing power consumption. Furthermore, by introducing positive feedback technology into the comparator, comparator delay is reduced, enabling NRZ code reception at a data transmission rate of 64Gb / s. This effectively equalizes 12dB of channel attenuation, while the total power consumption is only 70.4mW.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision, comprising: a feedforward enhanced continuous-time linear equalizer, four parallel time-interleaved sample-and-hold circuits, an embedded positive feedback adjacent symbol differential decision comparator, and deserialization circuits connected to the four adjacent symbol differential decision comparators respectively. Specifically: the feedforward enhanced continuous-time linear equalizer performs equalization processing on the input differential voltage signal to compensate for channel loss and eliminate long-tailed inter-symbol interference; the four time-interleaved sample-and-hold circuits sample and hold the data and output them to two adjacent symbol differential decision comparators respectively; the embedded positive feedback adjacent symbol differential decision comparators compare the input data symbols from different time-interleaved sample-and-hold circuits and determine the result; the deserialization circuit deserializes the decision result into low-speed data and performs bit error rate detection.

[0006] Technical effect

[0007] This invention performs differential decision-making between the sampled data of the current symbol and the sampled data of the previous symbol interval. A capacitively coupled input signal feedforward path is introduced at the gate of the current source transconductance transistor in the continuous-time linear equalizer. A pair of cross-coupled transistors are connected in parallel at the output node of the comparator's pre-amplification stage to form a local positive feedback loop. Compared with existing technologies, this invention eliminates the need to equalize signals passing through high-loss channels to a higher DC level, significantly reducing the performance requirements of the front-end equalizer and saving power. Furthermore, differential decision-making naturally suppresses common-mode noise on the signal path, improving the system's anti-interference capability. The introduction of the feedforward capacitor effectively increases the equivalent transconductance of the continuous-time linear equalizer, enhancing its compensation capability for high-frequency components without significantly increasing power consumption. This better opens the signal eye diagram, providing a higher-quality signal for subsequent decision circuits, effectively improving the overall gain and response sensitivity of the comparator, and reducing the probability of misjudgment. Introducing positive feedback within the adjacent symbol differential decision comparator rapidly amplifies the output voltage swing of the pre-amplification stage, accelerating the comparator's comparison speed. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of the present invention;

[0009] Figure 2 This is a schematic diagram of a feedforward enhanced continuous-time equalizer.

[0010] Figure 3 This is a schematic diagram of an adjacent symbol differential decision comparator with embedded positive feedback.

[0011] Figure 4 This is a schematic diagram of a serial deserialization circuit. Detailed Implementation

[0012] like Figure 1 As shown in the figure, this embodiment relates to a non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision, including: a feedforward enhanced continuous-time linear equalizer, four parallel time-interleaved sample-and-hold circuits, an embedded positive feedback adjacent symbol differential decision comparator, and a deserialization circuit connected to the four adjacent symbol differential decision comparators respectively.

[0013] like Figure 2 As shown, the feedforward enhanced continuous-time linear equalizer adopts a transconductance-transimpedance cascaded structure, including: a transconductance stage circuit and a transimpedance stage circuit connected thereto, wherein: the transconductance stage circuit converts the input differential voltage signal into a current signal; the transimpedance stage circuit converts the current signal after transconductance stage equalization back into a voltage signal and outputs it to four parallel time-interleaved sample-and-hold circuits respectively.

[0014] The transconductance stage circuit adopts a source degradation structure, including: a pair of input transconductance transistors, a pair of current source transconductance transistors, a pair of feedforward capacitors, a source degradation network, and a pair of current sources. The positive and negative terminals of the input differential voltage signal are respectively connected to the gates of the pair of input transconductance transistors, and respectively connected to the gates of the corresponding current source transconductance transistors through the feedforward capacitors to improve the equivalent transconductance of the continuous-time linear equalizer. The drains of the input transconductance transistors and the current source transconductance transistors are connected. The sources of the pair of input transconductance transistors are respectively connected to the corresponding current sources. The source degradation network is disposed between the pair of current sources.

[0015] This embodiment enhances the compensation capability for high-frequency components without increasing the quiescent current by introducing an input signal feedforward path formed by a coupling capacitor at the gate of the current source transconductance transistor.

[0016] The transconductance stage circuit includes: a pair of p-type input transistors, a pair of n-type input transistors, an adjustable resistor, an inductor, and a current source. The output of the transconductance stage circuit is connected to the gates of the p-type and n-type input transistors. The source of the n-type input transistor is grounded, and the source of the p-type input transistor is connected to the current source. The output of the transconductance stage circuit is connected to the drains of the p-type and n-type input transistors via the adjustable resistor and inductor, and then connected to the subsequent time-interleaved sample-and-hold circuit.

[0017] The time-interleaved sample-and-hold circuit employs a clock-controlled sampling switch, wherein: the input of the sampling switch is connected to the output of a feedforward enhanced continuous-time linear equalizer, and the output is connected to a subsequent adjacent symbol differential decision comparator with embedded positive feedback. When the sampling clock is low, the sampling switch samples the output of the feedforward enhanced continuous-time linear equalizer. When the sampling clock is high, the sampling switch holds the output.

[0018] like Figure 3 As shown, the embedded positive feedback adjacent symbol differential decision comparator includes: a pre-amplifier stage circuit and a latch stage circuit connected thereto, wherein: the input of the pre-amplifier stage circuit is connected to the output of the sample-and-hold circuit, the output of the pre-amplifier stage circuit is connected to the input of the latch stage circuit, and the output of the latch stage circuit is connected to the deserialization circuit.

[0019] The pre-amplification stage circuit includes: an input transistor pair, a positive feedback transistor pair, and a clocked current source. The corresponding drains of the input transistor pair and the positive feedback transistor pair are connected in parallel and connected to the drain of the clocked current source, and are also connected to the input of the latch stage. The gates of the input transistor pair are connected to the outputs of sample-and-hold circuits with different time intervals to receive and decide on adjacent sampled data symbols. The positive feedback transistor pair with connected drains forms a local positive feedback loop. When a small differential voltage exists at the input of the pre-amplification stage circuit, the output voltage swing of the pre-amplification stage is rapidly amplified. The larger output swing of the pre-amplification stage circuit also significantly reduces the feedback time of the latch stage, effectively improving the speed and sensitivity of the comparator and reducing the probability of misjudgment.

[0020] The latch stage circuit includes: an input transistor pair, a p-type cross-coupled transistor pair, an n-type cross-coupled transistor pair, and a clocked current source, wherein: the input is connected to the gate of the input transistor, the source of the input transistor pair and the n-type cross-coupled transistor pair are grounded, the source of the p-type cross-coupled transistor pair is connected to the drain of the clocked current source, and the drain of the input transistor and the drains of the p-type and n-type cross-coupled transistor pairs are connected to the subsequent deserialization circuit.

[0021] like Figure 4 As shown, the deserialization circuit includes three D flip-flops, wherein: the output of the adjacent symbol differential decision comparator with embedded positive feedback is connected to the input of the first-stage D flip-flop and the lower D flip-flop of the second stage; the output of the first-stage D flip-flop is connected to the upper D flip-flop of the second stage; and the second-stage D flip-flop outputs low-speed deserialized data.

[0022] Through simulation software, the input signal was set to a pseudo-random code sequence with a common-mode voltage of 500mV and an amplitude of 400mVpp in Virtuoso. The input signal, obtained through an S-parameter model obtained from actual channel testing, passed through a 500nF AC decoupling capacitor and a 1nH parasitic inductance introduced by wire bonding before entering the non-return-to-zero (NRZ) wired receiver of this invention based on adjacent symbol differential decision. When a feedforward capacitor was added to the continuous-time linear equalizer, the peak gain at the Nyquist frequency increased from 7.8dB to 10.4dB. Without increasing power consumption, the feedforward-enhanced continuous-time linear equalizer achieved a peak gain improvement of 2.6dB. In a channel with 12dB attenuation at the same Nyquist frequency, using the adjacent symbol differential decision technique reduced system power consumption from 181.2mW to 70.4mW because it was not necessary to equalize the signal to the threshold level. By introducing positive feedback technology into the comparator, the comparator delay is reduced from 35.9ps to 26.6ps under the same input signal swing and power consumption, significantly speeding up the comparison.

[0023] Compared with existing technologies, this invention achieves low-power symbol decision without the need for strong equalization, effectively suppressing common-mode noise and improving the overall energy efficiency and reliability of the system. By employing adjacent symbol differential decision technology, this invention avoids the traditional method of directly comparing the input signal with a fixed decision threshold. For high-loss channels, there is no need to equalize the signal to a high DC level, thus significantly reducing power consumption. Simultaneously, differential decision has a natural suppression effect on common-mode noise along the signal path. By introducing feedforward enhancement into the continuous-time linear equalizer, its ability to compensate for high-frequency components near the Nyquist frequency is enhanced without significantly increasing power consumption. For the adjacent symbol differential decision comparator with embedded positive feedback, the output voltage swing of the first stage can be rapidly amplified when a small differential voltage exists at the comparator input, thereby improving the comparator's comparison speed.

[0024] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision, characterized in that, include: The system comprises a feedforward enhanced continuous-time linear equalizer, four parallel time-interleaved sample-and-hold circuits, an adjacent symbol differential decision comparator with embedded positive feedback, and a deserialization circuit connected to each of the four adjacent symbol differential decision comparators. Specifically: the feedforward enhanced continuous-time linear equalizer performs equalization processing on the input differential voltage signal to compensate for channel loss and eliminate long-tailed inter-symbol interference; the four time-interleaved sample-and-hold circuits sample and hold the data and output it to two adjacent symbol differential decision comparators respectively; the adjacent symbol differential decision comparators with embedded positive feedback compare the input data symbols from different time-interleaved sample-and-hold circuits and determine the result; and the deserialization circuit deserializes the decision result into low-speed data and performs bit error rate detection.

2. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 1, characterized in that, The feedforward enhanced continuous-time linear equalizer adopts a transconductance-transimpedance cascaded structure, including: a transconductance stage circuit and a transimpedance stage circuit connected thereto, wherein: the transconductance stage circuit converts the input differential voltage signal into a current signal; the transimpedance stage circuit converts the current signal after transconductance stage equalization back into a voltage signal and outputs it to four parallel time-interleaved sample-and-hold circuits respectively.

3. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 2, characterized in that, The transconductance stage circuit adopts a source degradation structure, including: a pair of input transconductance transistors, a pair of current source transconductance transistors, a pair of feedforward capacitors, a source degradation network, and a pair of current sources. The positive and negative terminals of the input differential voltage signal are respectively connected to the gates of the pair of input transconductance transistors, and respectively connected to the gates of the corresponding current source transconductance transistors through the feedforward capacitors to improve the equivalent transconductance of the continuous-time linear equalizer. The drains of the input transconductance transistors and the current source transconductance transistors are connected. The sources of the pair of input transconductance transistors are respectively connected to the corresponding current sources. The source degradation network is disposed between the pair of current sources.

4. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 2, characterized in that, The transconductance stage circuit includes: a pair of p-type input transistors, a pair of n-type input transistors, an adjustable resistor, an inductor, and a current source. The output of the transconductance stage circuit is connected to the gates of the p-type and n-type input transistors. The source of the n-type input transistor is grounded, and the source of the p-type input transistor is connected to the current source. The output of the transconductance stage circuit is connected to the drains of the p-type and n-type input transistors via the adjustable resistor and inductor, and then connected to the subsequent time-interleaved sample-and-hold circuit.

5. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to any one of claims 1-4, characterized in that, The time-interleaved sample-and-hold circuit uses a clock-controlled sampling switch, wherein: the input of the sampling switch is connected to the output of the feedforward enhanced continuous-time linear equalizer, and the output is connected to the subsequent embedded positive feedback adjacent symbol differential decision comparator. When the sampling clock is low, the sampling switch samples the output of the feedforward enhanced continuous-time linear equalizer; when the sampling clock is high, the sampling switch holds it.

6. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 1, characterized in that, The embedded positive feedback adjacent symbol differential decision comparator includes a pre-amplifier stage circuit and a latch stage circuit connected thereto, wherein: the input of the pre-amplifier stage circuit is connected to the output of the sample-and-hold circuit, the output of the pre-amplifier stage circuit is connected to the input of the latch stage circuit, and the output of the latch stage circuit is connected to the deserialization circuit.

7. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 6, characterized in that, The pre-amplification stage circuit includes: an input transistor pair, a positive feedback transistor pair, and a clocked current source. The corresponding drains of the input transistor pair and the positive feedback transistor pair are connected in parallel and connected to the drain of the clocked current source, and are also connected to the input of the latch stage. The gates of the input transistor pair are connected to the outputs of different time-interleaved sample-and-hold circuits to receive and decide on adjacent sampled data symbols. The positive feedback transistor pair with connected drains forms a local positive feedback loop. When a small differential voltage exists at the input of the pre-amplification stage circuit, the output voltage swing of the pre-amplification stage is rapidly amplified. The larger output swing of the pre-amplification stage circuit also significantly reduces the feedback time of the latch stage, effectively improving the speed and sensitivity of the comparator and reducing the probability of misjudgment.

8. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to claim 6, characterized in that, The latch stage circuit includes: an input transistor pair, a p-type cross-coupled transistor pair, an n-type cross-coupled transistor pair, and a clocked current source, wherein: the input is connected to the gate of the input transistor, the source of the input transistor pair and the n-type cross-coupled transistor pair are grounded, the source of the p-type cross-coupled transistor pair is connected to the drain of the clocked current source, and the drain of the input transistor and the drains of the p-type and n-type cross-coupled transistor pairs are connected to the subsequent deserialization circuit.

9. The non-return-to-zero (NRZ) wired receiver based on adjacent symbol differential decision according to any one of claims 1 or 6-8, characterized in that, The deserialization circuit includes three D-type flip-flops, wherein: the output of the adjacent symbol differential decision comparator with embedded positive feedback is connected to the input of the first-stage D-type flip-flop, the output of the first-stage D-type flip-flop is connected in parallel to two second-stage D-type flip-flops, and the second-stage D-type flip-flops output low-speed deserialized data.

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