Digital proportional valve constant current control fault detection circuit and method

Abstract

The application discloses a kind of digital proportional valve constant current control fault detection circuit and method, including microcontroller MCU, external nonvolatile memory EEPROM, gate drive chip U0, power NMOS tube Q0, sampling resistance R0, operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U4, comparator U5, comparator U6, double-channel constant current source U7, inverter U8, high-side power switch U9, controlled MOS switch K1, double-channel analog switch K2, external load proportional solenoid valve L0 and its freewheeling diode D0, voltage dividing resistance R1, voltage dividing resistance R2 and voltage dividing resistance R6, voltage dividing resistance R7, current-limiting protection resistance R3, current-limiting protection resistance R4, current-limiting protection resistance R5 and current-limiting protection resistance R8.The fault detection method of detection circuit is disclosed.The application is detected to different faults, and different faults are quickly identified and alarmed, so as to improve the integrity and real-time performance of fault detection.

Description

Technical Field

[0001] This invention belongs to the field of proportional valve fault detection technology, and relates to a digital proportional valve constant current control fault detection circuit and method. Background Technology

[0002] Proportional solenoid valves, as core control components in hydraulic transmission and industrial automation systems, achieve linear matching between valve core displacement and fluid parameters through precise control of coil current. They are widely used in critical fields such as engineering machinery, metallurgical equipment, and aerospace. Constant current control is the core technology ensuring the control accuracy and dynamic response performance of proportional solenoid valves. Essentially, it uses closed-loop regulation to stably track the target value of the coil current, offsetting the effects of power fluctuations, coil parameter drift, and load disturbances.

[0003] Existing proportional solenoid valve constant current control schemes are mainly divided into three categories: analog circuit type, microcontroller integrated type, and microcontroller discrete type. Analog circuit type schemes rely on a large number of discrete electronic components to construct current amplification and drive logic. The power amplifier transistors typically operate in the linear region, resulting in inherent defects such as complex circuit structure, large size, high power consumption, and significant temperature rise. Furthermore, control accuracy is easily affected by component parameter dispersion and ambient temperature changes, leading to poor reliability. Microcontroller integrated type schemes introduce digital control technology to optimize power consumption and adjustment flexibility, but at a higher cost. Microcontroller discrete type schemes have advantages such as low hardware cost, flexible circuit debugging, and strong power drive capability, making them widely applicable in low- to mid-range industrial control scenarios. However, existing microcontroller schemes generally lack systematic fault detection design: on the one hand, the discrete nature of discrete components and the harshness of the operating environment, such as high temperature, vibration, and strong electromagnetic interference, result in a relatively high failure rate; on the other hand, the lack of real-time detection and anomaly judgment logic for current sampling accuracy, power device operating status, and coil electrical parameters prevents early warning and accurate fault location, leading to increased system maintenance costs and extended downtime. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a digital proportional valve constant current control fault detection circuit and method, which effectively solves the problems in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A fault detection circuit for a digital proportional valve constant current control includes:

[0007] The microcontroller (MCU) includes a gate driver chip U0, a power NMOS transistor Q0, operational amplifiers U1, U2, U3 and U4, comparators U5 and U6, a dual-channel constant current source U7, an inverter U8, a high-side power switch U9, and an external load proportional solenoid valve L0. The MCU is connected to an external non-volatile memory (EEPROM), and the MCU has peripheral pins GPIO1, GPIO2, GPIO3, GPIO4, ADC1, ADC2, TIM1, and TIM2.

[0008] TIM1, GPIO1 and GPIO2 are respectively connected to current-limiting protection resistors R3, R4 and R5;

[0009] TIM2 is connected to U0, U0 is connected to the gate of Q0, and R3, R4 and R5 are connected to the end away from the MCU and then connected to voltage divider resistors R1 and R2. The other end of R1 is connected to the gate of Q0, and the other end of R2 is connected to the drain of Q0 and grounded.

[0010] The ADC1 is connected to the output terminal of U2 and the inverting input terminal. The positive input terminal of U2 is connected to the output terminal of U1. The inverting input terminal of U1 is connected to the positive input terminal and the sampling resistor R0 is connected in parallel. The inverting input terminal of U1 is connected to the source of Q0.

[0011] The ADC2 is connected to a current-limiting protection resistor R8. R8 is connected to the output terminal and the inverting input terminal of U3. The positive input terminal of U3 is connected to voltage divider resistors R6 and R7. The other end of R6 is connected to the positive input terminal of U1, and R7 is grounded.

[0012] GPIO3 and GPIO4 are connected to the output terminals of U5 and U6 respectively. The inverting input terminals of U5 and U6 are connected to the output terminal of U4. The output terminal of U4 is connected to a dual-channel analog switch K2 and a controlled MOS switch K1. The output terminal of U4 is connected to the inverting input terminal. The other end of K1 is connected to R6. K1 is connected to the output terminal of U8.

[0013] K2 is used to switch the connection between the pull-up path and the pull-down path of U7. U9 is connected to L0. The other end of L0 is connected to R6. A freewheeling diode D0 is connected in parallel across both ends of L0.

[0014] U5, U6 and U4 are each input with a reference voltage.

[0015] A method, the method being the fault detection method for a digital proportional valve constant current control fault detection circuit as described above, includes:

[0016] The MCU's timer peripheral TIM2 executes constant current control algorithm instructions, outputting a PWM signal with a variable duty cycle. This PWM signal drives Q0 via U0, and the signal input to the gate of Q0 is V. G The signal S is obtained after VG is divided by R1 and R2.G It is then sent back to the MCU;

[0017] S G After passing through R3, the signal is input to the MCU's peripheral TIM1. TIM1 captures frequency and duty cycle information, verifies the output of TIM2, and detects input faults in the power drive module.

[0018] The current flowing through load L0 is converted into a voltage signal by sampling resistor R0. After passing through U1 and U2, it is input to the MCU's peripheral ADC1, which provides real-time feedback of the control current to the internal constant current control unit. The voltage across R0 is denoted as V. RH and V RL ;

[0019] S G After passing through resistors R4 and R5, the inputs are respectively sent to the MCU's peripheral GPIO1 and GPIO2. GPIO1 detects S. G The rising edge triggers fault detection when Q0 is turned on, and GPIO2 detects S. G The falling edge of the signal triggers fault detection when Q0 is turned off;

[0020] The non-inverting input of U4 is connected to the reference voltage V. rf0 This generates a reference voltage, which is connected to the negative input terminals of U5 and U6;

[0021] The non-inverting input of U5 is connected to the reference voltage V. rf1 The non-inverting input of U6 is connected to the reference voltage V. rf2 GPIO2 detection S G When the falling edge interrupts, the MCU's peripheral GPIO3 and GPIO4 are checked for high and low levels, respectively to detect and determine whether the drive unit has a short circuit to ground fault or an open circuit fault in the load coil.

[0022] V RH After being divided by R6 and R7, the voltage is transmitted to the MCU's peripheral ADC2 via U3, and GPIO1 detects S. G When the rising edge of the interrupt occurs, the current and voltage of the MCU's peripheral ADC1 and ADC2 are detected to detect power supply short circuit faults, drive unit open circuit faults, and ground short circuit faults.

[0023] Among them, V G After U8 controls the opening and closing of K1, when V G When Q0 is low, K1 is closed when Q0 is off, and vice versa. When K1 is closed, U7 enters fault detection. Q0 is off by default during system power-on initialization.

[0024] Optionally, after the system is powered on, U9 is in the off state by default. Before the MCU outputs the PWM control signal, it performs a power-on self-test. The power-on self-test includes detection of short circuit to ground fault, open circuit fault of load, and abnormal fault of sampling circuit when Q0 is turned off.

[0025] Optionally, the input fault detection of the power drive module includes:

[0026] Check if the PWM signal output by the MCU's peripheral TIM2 is normal;

[0027] When the MCU's peripheral TIM2 outputs a normal PWM signal, but the MCU's peripheral TIM1 cannot capture the feedback signal S... G If so, it is determined that there is a PWM signal transmission failure;

[0028] When the MCU's peripheral TIM1 can normally capture the return signal S G The system calculates the frequency and duty cycle information of the captured signal and compares it with the set value. If the values ​​are outside the range, the system determines that the PWM frequency and PWM duty cycle are abnormal.

[0029] Optionally, S G The fault detection during Q0 shutdown, triggered by a falling edge interrupt, includes:

[0030] With U9 in the drive system off, a short-circuit fault to ground is detected. K2 is initially connected to the pull-up path of U7 by default. If the drive system is normal and has no short circuit to ground, then after current injection, V... RH Voltage equals reference voltage V rf0 The positive threshold V of U5 is higher than that of U5. rf1 U5 output remains low. If there is a short circuit to ground in the drive system, V RH The voltage is pulled down to near ground potential, below the positive terminal threshold V of U5. rf1 When the output level of U5 flips, it triggers a short-circuit-to-ground fault alarm.

[0031] When the system detects a ground fault, it opens U9 of the drive system and switches the pull-down path of K2 to U7. If the load coil is normal and has no open circuit, after current is drawn, node V... RH The voltage is still equal to the high-side power supply voltage V of U9. power ±0.1V, higher than the positive threshold V of U6. rf2 The output of U6 remains low. If the load coil is open, the current will be drawn from node V. RH The voltage is lower than the positive terminal threshold V of U6 rf2 When the output level of U6 flips, it triggers a load open circuit fault alarm.

[0032] Optionally, the fault detection of the sampling circuit includes:

[0033] For the detection of zero-current calibration, the normal drift range of the sampling circuit within the system design temperature range is used as the threshold. If the output value of the sampling circuit read during the system power-on initialization phase exceeds the threshold, then U1 and U2 are determined to be abnormally drifting.

[0034] During the operation of the sampling system, the range and rate of change of the sampling current are periodically detected. Based on the rated parameters of the proportional valve, the threshold of the sampling current is set. If the sampling value continues to exceed the threshold, after ruling out power device faults, the sampling circuit is determined to be abnormal. If the current control command input by the system does not issue the specified action, but the rate of change of the sampling current exceeds the normal range, the sampling circuit is determined to be interfered with or the wiring is loose.

[0035] Optionally, the EEPROM stores historical control and current sampling data. Each time the system is initially powered on, the zero point is calibrated. If the deviation between the sampled reference value and the previous reference value is within the set accuracy range, the sampling circuit is working normally and the current reference value is stored in a rolling manner. If the deviation is large, the sampling circuit is judged to be abnormal.

[0036] When U1 and U2 drift normally, the variance index of the stored zero-bias data is calculated to assess the volatility of the current zero-bias data. If the volatility is extremely high, it is determined that the sampling circuit wiring is loose or has poor contact.

[0037] Optionally, for application scenarios with a limited number of specific operating conditions, the control values ​​and standard values ​​of current sampling for each operating condition are written into the EEPROM. During system operation, the control values ​​and standard values ​​of current sampling for each operating condition are compared.

[0038] Optionally, S G The fault detection when Q0 is turned on includes the following: (The following text appears to be unrelated and possibly from a different source: "Rising edge interruption, fault detection when Q0 is turned on includes:")

[0039] If the MCU detects that the voltage of node VRH is 0±0.1V through ADC2, but the sampling current detected by the MCU through ADC1 is also 0±0.01A, and the duty cycle of the PWM signal output by the MCU exceeds the limit and remains at 100%, it indicates that the load coil in the drive unit has an open circuit fault.

[0040] If the MCU detects that the voltage of node VRH through ADC2 is equal to the power supply voltage ±0.1V, and the sampling current detected by the MCU through ADC1 is equal to 0 ±0.01A, and the duty cycle of the PWM signal output by the MCU exceeds the limit and remains at 100% all the time, it indicates that Q0 in the drive unit has an open circuit fault.

[0041] If the MCU detects that the voltage at node VRH is equal to the power supply voltage ±0.1V via ADC2, and the sampling current value detected by the MCU via ADC1 surges, it indicates that the load has experienced a short circuit to the power supply.

[0042] Optionally, during the system power-on self-test, if a fault occurs when Q0 is turned off, a retest is performed after waiting for 255 PWM cycles, and the number of retests is set. If the fault is not eliminated after reaching the upper limit of the number of retests, the self-test fails and the response to subsequent constant current control function modules is prohibited.

[0043] Compared with the prior art, the present invention has the following beneficial effects: by setting up detection for different faults, different faults can be quickly identified and alarmed, improving the integrity and real-time performance of the microcontroller discrete constant current control technology in fault detection, and by simplifying the detection circuit, it is easy to achieve domestic substitution, reduce the cost of use, and improve economic efficiency. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the circuit system according to an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Please see Figure 1 The present invention discloses a digital proportional valve constant current control fault detection circuit, comprising:

[0047] The microcontroller (MCU) consists of a gate driver chip U0, a power NMOS transistor Q0, operational amplifiers U1, U2, U3 and U4, comparators U5 and U6, a dual-channel constant current source U7, an inverter U8, a high-side power switch U9, and an external load proportional solenoid valve L0. The MCU is connected to an external non-volatile memory (EEPROM), and the MCU has peripheral pins GPIO1, GPIO2, GPIO3, GPIO4, ADC1, ADC2, TIM1, and TIM2.

[0048] TIM1, GPIO1 and GPIO2 are connected to current limiting protection resistors R3, R4 and R5 respectively;

[0049] TIM2 is connected to U0, U0 is connected to the gate of Q0, R3, R4 and R5 are connected to the end away from the MCU and then connected to the voltage divider resistors R1 and R2. The other end of R1 is connected to the gate of Q0, and the other end of R2 is connected to the drain of Q0 and grounded.

[0050] ADC1 is connected to the output and inverting input of U2. The non-inverting input of U2 is connected to the output of U1. The inverting input and the non-inverting input of U1 are connected in parallel with a sampling resistor R0. The inverting input of U1 is connected to the source of Q0.

[0051] ADC2 is connected to a current-limiting protection resistor R8. R8 is connected to the output terminal and the inverting input terminal of U3. The positive input terminal of U3 is connected to voltage divider resistors R6 and R7. The other end of R6 is connected to the positive input terminal of U1, and R7 is grounded.

[0052] GPIO3 and GPIO4 are connected to the output terminals of U5 and U6 respectively. The inverting input terminals of U5 and U6 are connected to the output terminal of U4. The output terminal of U4 is connected to a dual-channel analog switch K2 and a controlled MOS switch K1. The output terminal of U4 is connected to the inverting input terminal. The other end of K1 is connected to R6. K1 is connected to the output terminal of U8.

[0053] K2 is used to switch the pull-up path and pull-down path of U7. U9 is connected to L0. The other end of L0 is connected to R6. A freewheeling diode D0 is connected in parallel across L0.

[0054] U5, U6 and U4 are each input with a reference voltage.

[0055] In some feasible configurations, the reference voltages for U5, U6, and U4 are 2V, 3V, and 2.5V, respectively.

[0056] To facilitate understanding of the fault detection circuit for a digital proportional valve constant current control according to this application, this application also discloses a method, including...

[0057] The microcontroller's timer peripheral TIM2 executes constant current control algorithm instructions, outputting a PWM signal with a variable duty cycle according to the configured frequency. The PWM signal drives the power NMOS transistor Q0 through the gate driver chip U0, and the signal input to the gate of the power NMOS transistor Q0 is V. G V G The signal S is obtained after voltage division by voltage divider resistors R1 and R2. G It is then sent back to the microcontroller MCU;

[0058] Return signal S G After passing through the current-limiting protection resistor R3, the signal is input to the peripheral TIM1 of the microcontroller MCU. TIM1 captures the feedback signal S. G The frequency and duty cycle information is used to verify the output of TIM2 and detect input faults in the power drive module.

[0059] The external load L0 current is converted into a voltage signal through sampling resistor RO. After passing through operational amplifiers U1 and U2, it is input to the MCU's peripheral ADC1 to provide real-time feedback of the control current to the internal constant current control unit. The voltage across RO is denoted as V. RH and V RL ;

[0060] Return signal S G After passing through current-limiting protection resistors R4 and R5, the signals are input to the microcontroller's peripherals GPIO1 and GPIO2, respectively. GPIO1 detects the feedback signal S. G The rising edge triggers fault detection when the power NMOS transistor Q0 is turned on, and GPIO2 detects the feedback signal S. G The falling edge of the signal triggers fault detection when the power NMOS transistor Q0 is turned off.

[0061] The non-inverting input of operational amplifier U4 is connected to the reference voltage V. rf0 This generates a reference voltage, which is connected to the negative input terminals of U5 and U6. When different faults occur in the system, the reference voltage changes, which will trigger the output changes of comparators U5 and U6. Setting the reference voltage can avoid interference from power supply ripple and circuit noise, ensuring that the subsequent comparators' judgment of fault signals is not interfered with, and improving detection accuracy.

[0062] The non-inverting input of comparator U5 is connected to the reference voltage V. rf1， The non-inverting input of comparator U6 is connected to the reference voltage V. rf2， Microcontroller MCU peripheral GPIO2 detection S G When the falling edge interrupts, the MCU's peripheral GPIO3 and GPIO4 are checked for high and low levels, respectively to detect and determine whether the drive unit has a short circuit to ground fault or an open circuit fault in the load coil.

[0063] V RH After being divided by voltage divider resistors R6 and R7, the voltage is transmitted to the MCU's peripheral ADC2 via operational amplifier U3. The microcontroller's peripheral GPIO1 detects S. G When the rising edge of the interrupt occurs, the current and voltage of the MCU's peripheral ADC1 and ADC2 are detected to detect power supply short circuit faults, drive unit open circuit faults, and ground short circuit faults.

[0064] Among them, the gate signal V of the power NMOS transistor Q0 G After passing through inverter U8, K1 is controlled to open and close. When V GWhen the voltage level is low, K1 closes when the power NMOS transistor Q0 is turned off, and vice versa. When K1 is closed, the constant current source U7 enters fault detection. When the system is powered on and initialized, the power NMOS transistor Q0 is turned off by default.

[0065] In this way, by setting up detection for different faults, different faults can be quickly identified and alarmed, improving the completeness and real-time performance of the microcontroller discrete constant current control technology solution in fault detection. Furthermore, by simplifying the detection circuit, it is easier to achieve domestic substitution, reduce usage costs, and improve economic efficiency.

[0066] In this embodiment, V rf0 2.5V, V rf1 For 2V, V rf2 The voltage is 3V. To facilitate circuit protection, when a major system fault is detected, the MCU controls U9 to cut off the system power supply through a control signal.

[0067] In some feasible approaches, input fault detection of power devices includes PWM amplitude detection, PWM frequency detection, and PWM duty cycle detection, determining the period and frequency of the previous complete PWM wave signal when the rising edge of the next PWM wave arrives.

[0068] Specifically, for input fault detection of power devices, the first step is to check the signal source, namely whether the PWM signal output by the TIM2 of the microcontroller MCU is normal. Since the rated current of the load coil is usually much smaller than the direct current connected to the power supply (PWM duty cycle is 100%), there is an upper limit to the PWM duty cycle. In a constant current control closed-loop system, if the feedback current is lower than the given current, the controller will automatically increase the PWM duty cycle to increase the output current. Therefore, if the duty cycle of the PWM signal output by the microcontroller continuously exceeds the limit, it indicates that there may be an external open-circuit fault in the system, and other signals need to be considered to determine the specific fault.

[0069] When the microcontroller MCU's TIM2 outputs a PWM signal with a duty cycle lower than the preset upper limit, this signal passes through the gate driver chip U0 and then outputs the actual gate drive signal V of the power device. G V G After voltage division, the return signal S is obtained. G By setting the ratio of the voltage divider resistors, V G The voltage fluctuation limit is within the upper limit tolerated by the microcontroller's (MCU) I / O port, V G The voltage fluctuation lower limit is above the logic high level standard. When the microcontroller MCU's TIM2 outputs a normal PWM signal, but TIM1 fails to capture the feedback signal S... G，Then determine the PWM signal transmission fault (gate driver chip U0 fault or gate resistor open circuit fault). If TIM1 can normally capture the return signal S G， The frequency and duty cycle information of the captured signal are calculated and compared with the set value. If they are outside the range, the PWM frequency and PWM duty cycle are determined to be abnormal.

[0070] In some feasible ways, the return signal S G The fault detection when the power NMOS transistor Q0 is turned off during a falling edge interruption includes:

[0071] When the high-side power switch U9 of the drive system is turned off, a ground short-circuit fault detection is performed. The analog switch K2 is initially connected to the pull-up path (terminal b2) of the constant current source U7 by default. The constant current source U7 provides a stable pull-up current for "load open-circuit fault" detection. If the drive system is normal and there is no ground short circuit, after current injection, V... RH The voltage is equal to the reference voltage and higher than the positive threshold voltage V of comparator U5. rf1 The comparator U5 output remains low. If there is a short circuit to ground in the drive system, V RH The voltage is pulled down to near ground potential, below the positive threshold voltage V of comparator U5. rf1 When the output level of comparator U5 flips, it triggers a short-circuit fault alarm to ground.

[0072] When the system detects a no-to-ground short-circuit fault, it opens the high-side power switch U9 of the drive system, switching analog switch K2 to the pull-down path (terminal b1) of U7. The constant current source U7 provides a stable pull-down current for the "load open-circuit fault" detection. If the load coil is normal and has no open circuit, after the current is drawn, node V... RH The voltage is still equal to the high-side power supply voltage V of U9. power ±0.1V, higher than the positive threshold V of comparator U6. rf2 The comparator U6 output remains low. If the load coil is open, the current will be drawn from node V. RH The voltage is lower than the positive threshold V of comparator U6 rf2 When the output level of comparator U6 flips, it triggers a load open circuit fault alarm.

[0073] Therefore, when the output level of comparator U5 or comparator U6 flips, the fault condition is determined by detecting the high or low level of GPIO3 or GPIO4. When a short-circuit fault to ground exists in the drive unit, it is necessary to further check whether the sampling current over-limit fault alarm is triggered synchronously to determine whether the load coil is short-circuited to ground or the power MOSFET is short-circuited to ground. If the sampling current is normal, it is determined that the load coil is short-circuited to ground; if the sampling current is abnormal, it is determined that the power MOSFET is short-circuited to ground. This situation is very likely to burn out the load coil, so the high-side switch U9 must be turned off immediately to cut off the power supply. At the same time, usually after the system is powered on and initialized, there is no rising or falling edge signal at this time, and the power NMOS transistor Q0 is turned off by default. After the initialization and power-on self-test are completed, the system outputs the PWM control signal normally, and then the corresponding fault diagnosis process is triggered with the rising or falling edge of the signal. Since short-circuit faults to ground pose the greatest threat to the system and may burn out the load coil or circuit board, the high-side power switch U9 of the drive system is turned off by default after power-on. The system prioritizes detecting short-circuit faults to ground and turns on the high-side power switch U9 only after ensuring that there are no dangerous faults.

[0074] Furthermore, it also includes sampling circuit fault detection, which includes two parts: zero-current calibration during the system power-on initialization phase and periodic (period Ts) detection of the sampling current range and rate of change during the operation of the sampling system. Specific fault situations include: zero bias sampling value exceeding the limit, large fluctuation of zero bias sampling value, sampling current exceeding the limit, operating current deviating from the empirical value, and abnormal changes in sampling current.

[0075] The detection of zero-current calibration is mainly to eliminate zero-point drift issues of U1 and U2 caused by temperature changes. Within the system's designed temperature range, the zero point of the sampling circuit has a normal drift range. A judgment threshold (such as twice the normal drift range) is set based on this normal range. Using the normal drift range of the sampling circuit's zero point within the system's designed temperature range as the threshold, if the output value of the sampling circuit read during the system's power-on initialization phase exceeds the threshold, then U1 and U2 are determined to be abnormally drifting.

[0076] During operation, the sampling system diagnoses the rationality of the sampled values ​​at a period of Ts. Based on the rated parameters of the proportional valve, a threshold for the sampling current is set. If the sampled value consistently exceeds the threshold, after ruling out power device faults, the sampling circuit is determined to be malfunctioning. If the system input current control command fails to issue the specified action, but the rate of change of the sampling current exceeds the normal range, the sampling circuit is determined to be experiencing interference or loose wiring.

[0077] Furthermore, the EEPROM stores historical control and current sampling data. Each time the system initially powers on, it calibrates the zero point. If the deviation between the acquired reference value and the previous reference value is within the set accuracy range, the sampling circuit is considered to be working normally, and the current reference value is stored on a rolling basis. If the deviation is large, the sampling circuit is considered faulty. When U1 and U2 drift normally, the variance index of multiple zero-bias data is calculated to assess the volatility of the current zero-bias data. If the volatility is extremely high, the sampling circuit wiring is considered loose or has poor contact. For application scenarios with a limited number of specific operating conditions, the control values ​​and standard values ​​of current sampling for each operating condition are written into the EEPROM. During system operation, the control values ​​and standard values ​​of current sampling for each operating condition are compared.

[0078] Furthermore, during the system's power-on self-test, if a fault occurs when Q0 is turned off, a retest is performed after waiting for 255 PWM cycles. The number of retests is set; if the fault is not eliminated after reaching the maximum number of retests, the self-test fails, and subsequent responses from constant current control modules are prohibited. Faults include short circuits to ground, open circuits, and zero-bias anomalies in the sampling circuit.

[0079] In some feasible ways, S G The fault detection when the power NMOS transistor Q0 is turned on, which is interrupted on the rising edge, includes:

[0080] If the microcontroller MCU detects node V via ADC2 RH The voltage is equal to 0±0.1V, but the sampling current detected by the microcontroller MCU through ADC1 is also equal to 0±0.01A, and the duty cycle of the PWM signal output by the microcontroller MCU exceeds the limit and remains at 100% all the time, which indicates that the load coil in the drive unit has an open circuit fault.

[0081] If the microcontroller MCU detects node V via ADC2 RH If the voltage is equal to the power supply voltage ±0.1V, and the sampling current detected by the microcontroller MCU through ADC1 is equal to 0 ±0.01A, and the duty cycle of the PWM signal output by the microcontroller MCU exceeds the limit and remains at 100% all the time, then it indicates that the power NMOS transistor Q0 in the drive unit has an open circuit fault.

[0082] If the microcontroller MCU detects node V via ADC2 RH If the voltage is equal to the power supply voltage ±0.1V, and the sampling current value detected by the microcontroller MCU through ADC1 surges, it indicates that the load has a short circuit fault to the power supply.

[0083] Specifically, when the return signal S GWhen the rising edge of the signal triggers an input interrupt for the microcontroller, it indicates that the power MOSFET Q0 is in the on state. Under normal circumstances, the microcontroller MCU can detect the normal sampling current through ADC1, and node V... RH The theoretical voltage should be equal to 0±0.1V. At the same time, in the input fault detection of power devices, the duty cycle of the PWM signal output by the microcontroller should not exceed the limit, but the above-mentioned different situations will occur under fault conditions.

[0084] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fault detection circuit for a digital proportional valve constant current control, characterized in that, include The microcontroller (MCU) includes a gate driver chip U0, a power NMOS transistor Q0, operational amplifiers U1, U2, U3 and U4, comparators U5 and U6, a dual-channel constant current source U7, an inverter U8, a high-side power switch U9, and an external load proportional solenoid valve L0. The MCU is connected to an external non-volatile memory (EEPROM), and the MCU has peripheral pins GPIO1, GPIO2, GPIO3, GPIO4, ADC1, ADC2, TIM1, and TIM2. TIM1, GPIO1 and GPIO2 are respectively connected to current-limiting protection resistors R3, R4 and R5; TIM2 is connected to U0, U0 is connected to the gate of Q0, and R3, R4 and R5 are connected to the end away from the MCU and then connected to voltage divider resistors R1 and R2. The other end of R1 is connected to the gate of Q0, and the other end of R2 is connected to the drain of Q0 and grounded. The ADC1 is connected to the output terminal of U2 and the inverting input terminal. The positive input terminal of U2 is connected to the output terminal of U1. The inverting input terminal of U1 is connected to the positive input terminal and the sampling resistor R0 is connected in parallel. The inverting input terminal of U1 is connected to the source of Q0. The ADC2 is connected to a current-limiting protection resistor R8. R8 is connected to the output terminal and the inverting input terminal of U3. The positive input terminal of U3 is connected to voltage divider resistors R6 and R7. The other end of R6 is connected to the positive input terminal of U1, and R7 is grounded. GPIO3 and GPIO4 are connected to the output terminals of U5 and U6 respectively. The inverting input terminals of U5 and U6 are connected to the output terminal of U4. The output terminal of U4 is connected to a dual-channel analog switch K2 and a controlled MOS switch K1. The output terminal of U4 is connected to the inverting input terminal. The other end of K1 is connected to R6. K1 is connected to the output terminal of U8. K2 is used to switch the connection between the pull-up path and the pull-down path of U7. U9 is connected to L0. The other end of L0 is connected to R6. A freewheeling diode D0 is connected in parallel across both ends of L0. U5, U6 and U4 are each input with a reference voltage.

2. A method, the method being a fault detection method based on the digital proportional valve constant current control fault detection circuit of claim 1, comprising: The MCU's timer peripheral TIM2 executes constant current control algorithm instructions, outputting a PWM signal with a variable duty cycle. This PWM signal drives Q0 via U0, and the signal input to the gate of Q0 is V. G V G Signal S is obtained after voltage division by R1 and R2. G It is then sent back to the MCU; S G After passing through R3, the signal is input to the MCU's peripheral TIM1. TIM1 captures frequency and duty cycle information, verifies the output of TIM2, and detects input faults in the power drive module. The current flowing through load L0 is converted into a voltage signal by sampling resistor R0. After passing through U1 and U2, it is input to the MCU's peripheral ADC1, which provides real-time feedback of the control current to the internal constant current control unit. The voltage across R0 is denoted as V. RH and V RL ; S G After passing through resistors R4 and R5, the inputs are respectively sent to the MCU's peripheral GPIO1 and GPIO2. GPIO1 detects S. G The rising edge triggers fault detection when Q0 is turned on, and GPIO2 detects S. G The falling edge of the signal triggers fault detection when Q0 is turned off; The non-inverting input of U4 is connected to the reference voltage V. rf0 This generates a reference voltage, which is connected to the negative input terminals of U5 and U6; The non-inverting input of U5 is connected to the reference voltage V. rf1 The non-inverting input of U6 is connected to the reference voltage V. rf2 GPIO2 detection S G When the falling edge interrupts, the MCU's peripheral GPIO3 and GPIO4 are checked for high and low levels, respectively to detect and determine whether the drive unit has a short circuit to ground fault or an open circuit fault in the load coil. V RH After being divided by R6 and R7, the voltage is transmitted to the MCU's peripheral ADC2 via U3, and GPIO1 detects S. G When the rising edge of the interrupt occurs, the current and voltage of the MCU's peripheral ADC1 and ADC2 are detected to detect power supply short circuit faults, drive unit open circuit faults, and ground short circuit faults. Among them, V G After U8 controls the opening and closing of K1, when V G When Q0 is low, K1 is closed when Q0 is off, and vice versa. When K1 is closed, U7 enters fault detection. Q0 is off by default during system power-on initialization.

3. A method according to claim 2, characterized in that: After the system is powered on, U9 is in the off state by default. Before the MCU outputs the PWM control signal, it performs a power-on self-test. The power-on self-test includes detection of short circuit to ground fault, open circuit fault of load and abnormal fault of sampling circuit when Q0 is turned off.

4. The method according to claim 2, characterized in that: The input faults of the power drive module include: Check if the PWM signal output by the MCU's peripheral TIM2 is normal; When the MCU's peripheral TIM2 outputs a normal PWM signal, but the MCU's peripheral TIM1 cannot capture the feedback signal S... G， Then the PWM signal transmission is determined to be faulty; When the MCU's peripheral TIM1 can normally capture the return signal S G， The frequency and duty cycle information of the captured signal are calculated and compared with the set value. If they are outside the range, the PWM frequency and PWM duty cycle are determined to be abnormal.

5. A method according to claim 3, characterized in that: S G The fault detection during Q0 shutdown, triggered by a falling edge interrupt, includes: With U9 in the drive system off, a short-circuit fault to ground is detected. K2 is initially connected to the pull-up path of U7 by default. If the drive system is normal and has no short circuit to ground, then after current injection, V... RH Voltage equals reference voltage V rf0 The positive threshold V of U5 is higher than that of U5. rf1 U5 output remains low. If there is a short circuit to ground in the drive system, V RH The voltage is pulled down to near ground potential, below the positive terminal threshold V of U5. rf1 When the output level of U5 flips, it triggers a short-circuit-to-ground fault alarm. When the system detects a ground fault, it opens U9 of the drive system and switches the pull-down path of K2 to U7. If the load coil is normal and has no open circuit, after current is drawn, node V... RH The voltage is still equal to the high-side power supply voltage V of U9. power ±0.1V, higher than the positive threshold V of U6. rf2 The output of U6 remains low. If the load coil is open, the current will be drawn from node V. RH The voltage is lower than the positive terminal threshold V of U6 rf2 When the output level of U6 flips, it triggers a load open circuit fault alarm.

6. A method according to claim 3, characterized in that: The fault detection of the sampling circuit includes: For the detection of zero-current calibration, the normal drift range of the sampling circuit within the system design temperature range is used as the threshold. If the output value of the sampling circuit read during the system power-on initialization phase exceeds the threshold, then U1 and U2 are determined to be abnormally drifting. During the operation of the sampling system, the range and rate of change of the sampling current are periodically detected. Based on the rated parameters of the proportional valve, the threshold of the sampling current is set. If the sampling value continues to exceed the threshold, after ruling out power device faults, the sampling circuit is determined to be abnormal. If the current control command input by the system does not issue the specified action, but the rate of change of the sampling current exceeds the normal range, the sampling circuit is determined to be interfered with or the wiring is loose.

7. A method according to claim 6, characterized in that: The EEPROM stores historical control and current sampling data. Each time the system is initially powered on, the zero point is calibrated. If the deviation between the sampled reference value and the previous reference value is within the set accuracy range, the sampling circuit is working normally and the current reference value is stored in a rolling manner. If the deviation is large, the sampling circuit is judged to be abnormal. When U1 and U2 drift normally, the variance index of the stored zero-bias data is calculated to assess the volatility of the current zero-bias data. If the volatility is extremely high, it is determined that the sampling circuit wiring is loose or has poor contact.

8. A method according to claim 7, characterized in that: For application scenarios with a limited number of specific operating conditions, the control values ​​and standard values ​​of current sampling for each operating condition are written into the EEPROM. During system operation, the control values ​​and standard values ​​of current sampling for each operating condition are compared.

9. A method according to claim 2, characterized in that: S G The fault detection when Q0 is turned on includes the following: (The following text appears to be unrelated and possibly from a different source: "Rising edge interruption, fault detection when Q0 is turned on includes:") If the MCU detects node V via ADC2 RH The voltage is equal to 0±0.1V, but the sampling current detected by the MCU through ADC1 is also equal to 0±0.01A, and the duty cycle of the PWM signal output by the MCU exceeds the limit and remains at 100% all the time, which indicates that the load coil in the drive unit has an open circuit fault. If the MCU detects node V via ADC2 RH If the voltage is equal to the power supply voltage ±0.1V, and the sampling current detected by the MCU through ADC1 is equal to 0 ±0.01A, and the duty cycle of the PWM signal output by the MCU exceeds the limit and remains at 100% all the time, then it indicates that Q0 in the drive unit has an open circuit fault. If the MCU detects node V via ADC2 RH If the voltage is equal to the power supply voltage ±0.1V, and the sampling current value detected by the MCU through ADC1 surges, it indicates that the load has a short circuit fault to the power supply.

10. A method according to claim 3, characterized in that: During the system power-on self-test, if a fault occurs when Q0 is turned off, a retest will be performed after waiting for 255 PWM cycles. The number of retests is set. If the fault is not eliminated after reaching the maximum number of retests, the self-test will fail and subsequent constant current control function modules will be prohibited from responding.

Images