Dynamic recalibration of voltage regulators

Abstract

The present disclosure relates to dynamic recalibration of voltage regulators. Embodiments herein relate to a voltage regulator (VR) that includes a measurement circuit to perform periodic recalibration that accounts for temperature effects. The measurement circuit compares an output voltage Vout to a working point (WP) or target voltage. Based on the comparison, inputs to a summing circuit are adjusted. The measurement circuit can include a finite state machine (FSM) that operates at a clock frequency that is significantly lower than the clock frequency of the main control loop of the VR. The FSM can increment or decrement inputs to a multiplier when WP > Vout or WP < Vout, respectively. The WP is modified by the multiplier before being input to the VR.

Description

Technical Field

[0001] This disclosure relates to the dynamic recalibration of voltage regulators. Background Technology

[0002] Computing devices typically rely on voltage regulators to power their components. For example, a voltage regulator can down-convert the computing device's main supply voltage (e.g., 12 V) to lower voltages (e.g., 5 V, 3.3 V, or 1.8 V). These lower voltages can be used by various components within the computing device, such as Universal Serial Bus (USB) interfaces, memory (e.g., dynamic random access memory, DRAM), and processing resources (e.g., central processing unit, CPU). However, designing voltage regulators presents various challenges. Summary of the Invention

[0003] According to one embodiment of this disclosure, an apparatus is provided, comprising: a voltage regulator having an input node and an output node; a voltage shaping circuit coupled to the input node, wherein the voltage shaping circuit includes a summing circuit; and a measurement circuit coupled to the output node and the summing circuit.

[0004] According to one embodiment of this disclosure, an apparatus is provided, comprising: a voltage regulator (VR) having an input node and an output node, the input node being configured to receive an operating point voltage, wherein the voltage regulator is configured to implement a first feedback loop to control the voltage at the output node in response to the operating point voltage; a voltage shaping circuit coupled to the input node; and a measurement circuit coupled to the output node and the voltage shaping circuit, wherein the measurement circuit is configured to implement a second feedback loop to control the operating point voltage.

[0005] According to one embodiment of this disclosure, a system is provided, comprising: a processor; a voltage regulator coupled to the processor, wherein the voltage regulator is configured to control an output voltage in response to an operating point voltage; and one or more circuits coupled to the voltage regulator, wherein the one or more circuits are configured to control the operating point voltage.

[0006] According to one embodiment of this disclosure, a method is provided, comprising: implementing a first feedback loop at a voltage regulator (VR), the VR having an input node and an output node, the input node being for receiving an operating point voltage, wherein the first feedback loop is configured to control a voltage at the output node in response to the operating point voltage; and implementing a second feedback loop using measurement circuitry and voltage shaping circuitry to control the operating point voltage. Attached Figure Description

[0007] The embodiments of this disclosure will be more fully understood through the accompanying drawings, which are given below with reference to the specific embodiments and various examples of this disclosure. However, these drawings should not be construed as limiting this disclosure to the particular embodiments, but are for explanation and understanding only.

[0008] Figure 1 An example analog voltage regulator (VR) 100 according to various embodiments is depicted.

[0009] Figure 2 An example digital linear voltage regulator (DLVR) 200 according to various embodiments is depicted.

[0010] Figure 3 An example VR circuit 300 according to various embodiments is depicted, which includes a DLVR 310 having an operating point pre-shaping circuit 320.

[0011] Figure 4 Depicting various embodiments of the relationship with Figure 3 Example graph of consistent output voltage Vout relative to operating point voltage (WP).

[0012] Figure 5 An example VR circuit 500 according to various embodiments is depicted, the example VR circuit 500 including Figure 3 The operating point pre-shaping circuit 320 and DLVR 310, as well as the measurement circuit 510.

[0013] Figure 6 Another example VR circuit 600 according to various embodiments is depicted, the example VR circuit 600 including Figure 3 The operating point pre-shaping circuit 320 and VR 310, as well as the measurement circuit 610.

[0014] Figure 7 Depicting various embodiments Figure 6 Example implementation of measurement circuit 610.

[0015] Figure 8Depicting various embodiments of the relationship with Figures 4-7 A flowchart of a consistent example process.

[0016] Figure 9 Examples of components that may exist in the computing system 950 for implementing the techniques (e.g., operations, processes, methods, and methodologies) described herein are shown. Detailed Implementation

[0017] As mentioned at the beginning, various challenges arise when designing voltage regulators.

[0018] The high-level behavior of a voltage regulator (VR) typically follows this process: First, the VR receives a digital word representing the desired output voltage value or operating point (WP) and converts it to an analog value. Second, the VR compares the actual value of the output voltage (Vout(t)) using an analog-to-digital converter (ADC). Third, the measured error (WP - Vout(t)) is used by a compensator (CPS) unit to calculate the desired change in the relevant power stage characteristics (e.g., resistance). In some architectures, previous error values ​​and / or previous CPS output values ​​are also taken into account. Steps two and three are repeated until the error becomes below the resolution of the VR.

[0019] However, due to factors such as process and layout defects, as well as parasitic effects, the ideal process described above cannot provide optimal performance. To ensure that the VR output voltage meets the desired quality standards, a separate calibration procedure is typically required for each VR. For example, if a classic flash ADC is used in the design, the offset of the comparator forming the ADC needs to be calibrated.

[0020] One of the challenges associated with calibration is that circuit performance is somewhat temperature-dependent. Therefore, it's ideal to perform the calibration process at several temperature points and use this data to adjust the VR's tuning based on the actual temperature. However, this approach significantly increases testing time and complexity, and is therefore costly, at least for cost-sensitive products. In many cases, calibration is done at a single temperature point, the effect of temperature drift in the output voltage is assessed empirically, and the resulting positioning inaccuracies are considered as a protection factor, which negatively impacts the VR's performance metrics.

[0021] One approach to mitigating the temperature dependence of VR output voltage is to use design techniques that are less sensitive to temperature changes. However, design methods that reduce the temperature dependence of the circuit are often complex and lead to increased circuit area and power consumption. Furthermore, these techniques often exhibit high sensitivity to analog parameters at the technology node, such as diode ideality factors.

[0022] Another approach is to calibrate at multiple (at least two) temperature points, provided the additional testing costs are acceptable. However, this does increase product costs.

[0023] The solution presented in this paper addresses the aforementioned and other issues. In one aspect, a VR circuit is provided that automatically and in real-time performs in-situ, periodic recalibration throughout the VR's entire lifespan. In an example implementation, the autonomous calibration mechanism uses a single comparator for decision-making and can be designed to avoid or minimize temperature dependence and aging effects. Calibration can be performed relative to a "golden" reference voltage, such as Vbgr, provided by a bandgap reference circuit that may already exist in the VR. Vbgr can be considered substantially temperature-independent. The periodicity of the recalibration can be aligned with the thermal time constant, allowing the VR output to tune and track and mitigate the effects of temperature variations over time.

[0024] This solution offers numerous advantages, including the ability to reduce the Vmin guard band and thus improve product power performance metrics without impacting test time. Furthermore, because dynamic recalibration can be performed throughout the product's lifespan, aging-related VR performance degradation is mitigated. This enables further reductions in the guard band and / or more cost-effective designs, as it relaxes requirements on the "natural" temperature and aging recovery capabilities of the VR.

[0025] This solution is applicable to most types of VR topologies, including analog VR (e.g., buck VR) and digital VR (e.g., digital linear voltage regulators (DLVR)). It is also suitable for integrated voltage regulators (IVR), i.e., VR contained within a single integrated circuit (IC) package or chip.

[0026] These and other features will become more apparent in light of the following discussion.

[0027] Figure 1An example analog voltage regulator (VR) 100 according to various embodiments is depicted. The VR includes an amplifier 101 that receives an operating point (WP) or reference voltage at its non-inverting input and a feedback voltage Vout at its inverting input. The amplifier's output Vg is provided to the control gate of an n-type transistor 102 (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)). This transistor receives Vin at its source and provides Vout at its drain at an output node 103. In this example, a resistive load Rload is coupled to the output node. The VR also includes an output capacitor Cout coupled between the output node and ground.

[0028] VR regulates the output voltage Vout by adjusting Vg as Vout changes. For example, if Vout > Vref, then Vg < 0, causing transistor 102 to remain off to decrease Vout. If Vout < Vref, then Vg > 0, causing the transistor to turn on to increase Vout. VR has a negative feedback loop.

[0029] Figure 2 An example digital linear voltage regulator (DLVR) 200 according to various embodiments is depicted. The DLVR includes control circuitry 202 that controls the resistance or output of power stage 203 based on a digital value from an ADC 201. The ADC, in turn, provides this digital value based on an analog value of WP and Vout at output node 204. Power stage 203 may include a plurality of p-type MOSFETs, for example, whose control gates are coupled to control circuitry 202. Control circuitry may output a bit as a control voltage for turning each transistor in the power stage on or off, and thus modulate Vout. These transistors are coupled in parallel between the power supply node Vin and the output node 204.

[0030] Figure 3 An example VR circuit 300 according to various embodiments is depicted, which includes a DLVR 310 with an operating point pre-shaping circuit 320. A DVLR is depicted in some examples, but as previously stated, this solution is generally applicable to any type of VR. The operating point pre-shaping circuit 320 (or voltage pre-shaping, shaping, or regulating circuit) utilizes a multiplier 321 and a summing circuit 323 to adjust WP. The operating point pre-shaping circuit 320 has an input node 320a and an output node 320b. The multiplier receives a value A, and the output WP*A on path 322 is added to the value B at the summing circuit 323 to provide a modified value of WP, WPmod = WP*A + B, at the input node 310a of VR 310. See the xy-axis graph of Vout versus WP (see...). Figure 4In this equation, A is the slope, and B is the y-axis offset. Values ​​A and B can be set during manufacturing as part of the calibration process. In the initial configuration, for example, A=1 and B=0.

[0031] WPmod is provided to the VR control circuit 311 as the requested operating point or target voltage. VR 310 has an input node 310a and an output node 310b. VR outputs a corresponding control signal to the power stage 315, which in turn outputs a voltage Vout to the load 330 via the output node 310b. VR control circuit 311 also receives Vout via feedback path 312 and compares it with WPmod to determine whether to adjust the control signal for the power stage. VR responds to a first clock 325, which controls VR to update the frequency of the power stage.

[0032] Figure 4 Depicting various embodiments of the relationship with Figure 3 A sample graph of consistent output voltage Vout versus operating point voltage (WP). This graph can be obtained by setting different levels of WP and measuring Vout at each level. In this simplified example, each black circle represents a measurement point. In one approach, the graph is obtained with A=1 and B=0.

[0033] In some cases, due to factors such as process variations, layout defects, and parasitic effects, the output voltage level may not match the desired operating point value. A calibration process can be performed to eliminate or reduce the error. In the first step, for example during the VR manufacturing process, the actual value of Vout is measured under different WP settings. In this step, the original value of WP is not modified (i.e., A=1 and B=0) and appears in its original form at the input of the VR control circuit (also known as the compensator block). Therefore, the correlation between Vout and the target voltage Vtgt (==WP) represents the aberration introduced by the compensator (i.e., the analog part of the compensator). The dependency between WP and Vout is approximated by a linear function: Vout_fit = γ*WP + ε, with a certain scattering δVout_i. Line 400 represents the best linear fit to the data, where γ (gamma) is the slope of the line, ε (epsilon) is the y-intercept, and the equation of the line is of the form y=mx+b. For the i-th data point 410 in the example, the output voltage is Vout_i, which represents the error δVout_i relative to the corresponding voltage Vout_fit_i on the line. It can be observed that Vout_i = γ * WPmod + ε + δVout_i. When A = 1 / γ and B = -ε / γ, WPmod = WP * 1 / γ - ε / γ.

[0034] Please note that for a well-designed VR, the slope (γ) of the Vout_fit = f(WP) function is typically very close to 1, while the offset (ε) is the main source of inaccuracy and varies depending on the component.

[0035] The numerical representations of (γ, ε) are fed into the operating point pre-shaping circuit 320, and the VR uses the modified value of the operating point. As a result, the output voltage approximates its target value: Vout_fit = γ*WPmod + ε = γ*(1 / γ*WP - ε / γ) + ε = WP. To avoid any ambiguity, the offset value obtained during the calibration process is represented as ε(cal). Then, the actual value of Vout at any point is: Vout_i = Vout_fit + δVout_i = WP + δVout_i. The difference between WP and Vout_i is called the DC error of the DLVR.

[0036] One drawback of this approach is its accuracy at the temperature at which calibration is performed. Typically, the slope is very weakly dependent on temperature, while the offset can vary significantly with temperature. As mentioned earlier, to address this drawback, one could either: (a) incur design complexity, resulting in area and power losses and process sensitivity, or (b) perform multi-temperature (at least two-point) calibration and have the power management recalculate the offset, leading to increased test time / cost and software complexity.

[0037] The solution presented in this paper addresses the aforementioned issues by providing VR with a measurement circuit capable of autonomously adjusting its offset in real time. Figure 5 An example is provided.

[0038] Figure 5 An example VR circuit 500 according to various embodiments is depicted, the example VR circuit 500 including Figure 3The system includes an operating point pre-shaping circuit 320, a DLVR 310, and a measurement circuit 510. A multiplier 321 receives WP via path 511 and input node 320a, and receives the slope correction term 1 / γ via path 512. This is the initial or unmodified value of WP. A summing circuit 323 receives the output of the multiplier via path 514, and receives the offset correction term -ε / γ -ε(T) / γ via path 513, and provides WPmod to output node 320b and VR input node 310a. In VR 310, feedback path 312 is part of a first feedback loop used to adjust the output of VR 310, and the measurement circuit 510 is part of a second feedback loop used to adjust -ε(T) / γ and the input of the summing circuit 323. The first feedback loop operates at a first frequency, and the second feedback loop operates at a second frequency lower than the first frequency.

[0039] In the example implementation, VR implements a first feedback loop to control the voltage at the output node in response to the operating point voltage, and the measurement circuit implements a second feedback loop to control the operating point voltage.

[0040] In addition, the voltage shaping circuit receives the initial value of the operating point voltage and outputs the modified value of the operating point voltage to the input node of VR.

[0041] Measurement circuit 510 includes comparator 520, which is coupled to WP via path 515 at input node 520a and to Vout via path 516 at input node 520b. The measurement circuit also includes a low-pass filter (LPF) 530 and an ADC 525. The ADC outputs a low-pass filtered digital version of Vout, Vout_lpf. Comparator 520 provides an output at its output node 520c representing the difference between WP and Vout_lpf, which leads to a finite state machine (FSM) 540, the rate of which is determined by clock 535. Clock 535 (the second clock) can operate at a slower rate than clock 325 (the first clock) (e.g., 1 / 2). N The rate is times that of N (where N≥7). Each clock cycle, the FSM provides a time-varying output to the summing circuit 545 via switch S1 and input node 545b. ε(T) / γ. The summing circuit 545 has input nodes 545a and 545b and an output node 545c. The output node 545c is coupled to the input node 323a of the summing circuit 323.

[0042] Input node 545a provides an additional fixed input -ε / γ to the summing circuit. -ε / γ - ε(T) / γ is the output of the summing circuit at output node 545c. T represents the sampling time of the FSM output.

[0043] In the example implementation, if WP > Vout_lpf, the FSM output includes a positive increment; if WP < Vout_lpf, the FSM output includes a negative increment; or if WP ≈ Vout_lpf, there is no change.

[0044] The measurement circuit provides an additional control loop independent of the main feedback loop. This control mechanism periodically compares the actual output voltage (Vout_lpf) with its target value (WP) and adjusts Vout so that the remaining DC error is limited by the accuracy of the measurement system. The difference in adjustment bandwidth between the two loops can exceed two orders of magnitude, thus posing no stability issues or challenges. That is, the frequency of the first clock 325 can be 10-100 times higher than the frequency of the second clock 535. VR operates according to the first clock, and the measurement circuit operates according to the second clock.

[0045] Figure 6 Another example VR circuit 600 according to various embodiments is depicted, which includes... Figure 3 The operating point pre-shaping circuit 320 and VR 310, as well as the measurement circuit 610, are repeated. Figure 5 The circuit comprises an LPF 530, an ADC 525, a comparator 520, a clock 535, and an FSM 540. An analog multiplexer 615 passes the digital output Vout of the ADC 525 or a reference voltage Vref = k*Vbgr to the inverting input of the comparator based on a calibration / measurement signal from path 616 of the FSM. In calibration mode, Vref is passed; and in measurement mode, Vout is passed. The non-inverting input of the comparator receives a voltage from multiplexer 619 or a selector, which is then coupled to a resistor ladder 625. A bandgap reference circuit 630 outputs a reference bandgap voltage Vbgr to the power supply voltage node 631 of the resistor ladder. Based on a signal from path 623 of the up / down counter 635, multiplexer 619 passes the voltage at output node 621 to the comparator. Comparator 520 provides an output to FSM 540 on path 622 based on the relative value of its input.

[0046] In one approach, the FSM can be a digital circuit that receives digital inputs and provides digital outputs. The FSM signals the input to the up / down counter 635 to trigger an up or down change in the signal on path 623. The FSM receives other inputs, including -ε / γ on path 636, power management (PM) status / updates (from power management circuitry) on path 637, and an instability regulation alarm (a regulation stability indicator provided by VR) on path 638. The up / down counter 635 and the resistor ladder 625 are part of a digital-to-analog converter (DAC) 620 that provides an analog voltage at output node 621. This analog voltage is obtained from or generated by Vbgr.

[0047] In the example implementation, there is no need to compensate for temperature variations in the analog reference voltage at output node 621, because this voltage is based on the output Vbgr of the bandgap (BG) reference circuit 630. The voltage generated by the BG reference circuit is largely independent of temperature fluctuations.

[0048] As previously mentioned, the measurement circuit 610 operates at a slower cycle compared to the main feedback loop of the VR. The aim is to achieve slow-loop operation under stable regulation conditions. In other words, temperature compensation can be disabled during power management events (e.g., WP changes) or regulation mode changes (e.g., transitions in VR power state and / or operating mode). This decision is made by the FSM, taking into account power management status and data, as well as regulation stability indicators. If regulation is stable, the temperature compensation loop of the measurement circuit 610 is activated.

[0049] In measurement circuit 610, an up / down counter 635 can be used to scan the output voltage of DAC 620. The DAC output and the measured signal (Vout) are connected to a low-offset comparator 520. As the DAC output is scanned, the code of the change in the comparator output indicates a digital representation of the analog value of the measured signal. For example, as counter 635 counts up from the minimum voltage, a series of increasing voltages are output at output node 621, and the comparator indicates a first voltage exceeding Vout. As counter 635 counts down from the maximum voltage, a series of decreasing voltages are output at output node 621, and the comparator indicates a first voltage below Vout. The FSM then knows that Vout is limited by these first voltages and can accordingly decide whether to set a non-zero value for -ε(T) / γ.

[0050] To reduce noise, quantization, and other effects, measurements can be performed multiple times in both the up and down directions. The result is the average of the codes obtained from all measurements. To reduce uncorrelated high-frequency variations of the measured signal (i.e., above the bandwidth of interest), the measured signal is passed through the LPF 530 before being fed into comparator 520. For example, the LPF can have a time constant on the order of tens of microseconds. This time constant can be configured post-silicon (e.g., after the die containing VR is manufactured). The range of this time constant is consistent with the value of the relevant temperature time constant. Analog multiplexer 615 enables the measurement of different signals using the same circuit. Preferably, the measurement system of the slow compensation loop does not have significant temperature dependence because the goal of the control mechanism is to compensate for slow temperature changes (relative to the main control loop). Therefore, the measurement / decision system can be recalibrated each time the output voltage offset is readjusted without sacrificing the effectiveness of temperature compensation. For this purpose, the voltage on output node 621 (which is proportional to Vbgr) is used as a voltage reference (adjustable voltage).

[0051] The measurement circuitry can be advantageously implemented at a relatively low cost, while providing significant performance advantages to VR by essentially eliminating the temperature dependence of its output.

[0052] Further details regarding the example implementation of measurement circuit 610 will be discussed below. Please note that this is only one possible implementation, as alternative designs are also possible.

[0053] Figure 7 Depicting various embodiments Figure 6An example implementation of the measurement circuit 610 is shown below. Circles represent states the FSM can enter, one state at a time. For example, the FSM can initially be in idle state 701 and then transition to measurement configuration state 702. The FSM transitions to measure-up state 703, in which the output of DAC 620 increases from minimum to maximum during a scan, e.g., while comparator 520 compares the DAC output with Vout. Once complete, a wait is executed, and then the measurement reset state 704 is reached. The FSM then transitions to measure-down state 705, in which the output of DAC 620 decreases from maximum to minimum during a scan, e.g., while comparator 520 compares the DAC output with Vout. States 702-705 can be repeated iteratively (Max_iter) if needed. Once complete, a wait is executed. State 706 indicates that the measurement is complete and a value representing Vout is obtained, e.g., meas_code[7:0], an eight-bit value. Multiple measurements are provided to adder 715, which provides the sum of the measurements, such as sum_meas_code[11:0], a twelve-bit value.

[0054] When the FSM reaches measurement completion state 706, shift circuit 710 outputs the average value of Vout, av_meas_code[7:0], to decision block 720. The decision block also receives WP. The decision block provides its output to block 721, indicating whether WP is greater than av_meas_code[7:0]. Based on the decision block, block 721 increments or decrements offset_count (by 1 or -1), or leaves it unchanged (0). Block 722 clips offset_count to the maximum offset_shift code to ensure that offset_count is not too large. The output of block 722... ε(T) / γ is provided to the summing circuit 545. The summing circuit 545 also receives -ε / γ from the initial slope / offset calibration circuit 723. The output of the summing circuit is -ε / γ. ε(T) / γ is provided to block 724, which limits this value to the maximum offset code to provide an adjusted offset code. For example, this code is provided to Figure 6 The summing circuit 323.

[0055] Figure 8 Depicting various embodiments of the relationship with Figures 4-7Flowchart of a consistent example process. Block 800 includes High-Volume Manufacturing Test (HVM), where ref_hvm_code is determined, for example, a code representing an analog value of a voltage reference, Vref = k*Vbgr, where 0 < k < 1. This code is characterized and recorded using the described measurement system. During the Vmin search, the control loop of the measurement circuit is enabled. This loop ensures that the post-LPF mode related distortion of the output voltage is accounted for in the resulting voltage-frequency (V / F) curve. Additionally, this loop ensures that the difference between the actual VR output voltage and the desired WP equivalent value is limited by the resolution of the measurement system.

[0056] Block 801 relates to the first stage of Vout adjustment. This includes determining the calibration offset MS(T)] = Vref(T) - ref_hvm_code. In the first stage, the measurement system is recalibrated. The current value of the digital code representing Vref(T) is recorded and compared with ref_hvm_code. This difference is defined as the measurement system (MS) calibration offset MS(T)].

[0057] Block 802 relates to the second stage of Vout adjustment. This involves measuring Vout_actual_code = Vout_lpf(T) and determining ε(T) = Vout_actual_code - (WP + εcal). In the second stage, the current value of Vout_lpf(T) is measured using the measurement system described in Block 801. Its digital representation is denoted as Vout_actual_code. The effective temperature-dependent DAC offset ε(T) is the difference between Vout_actual_code and WP + εcal.

[0058] [[ID=!17]]Block 803 includes calculating the offset readjustment based on the results of Block 802 and the HVM calibration (T) = cal - (T) + MS(T)]. If ε(T) > 1, then Block 804 is reached, where the offset correction can be enabled in a single code step corresponding to a voltage step. Alternatively, the offset correction / compensation can be proportional to ε(T). If ε(T) < 0, then Block 805 is reached, where the offset is reset to its calibration value εcal. If 0 < Note: There seems to be an error in the original text where "Block 803 includes calculating the offset readjustment based on the results of Block 802 and the HVM calibration" is not fully formatted in the original. I've tried to make sense of it in the translation as best as possible. If there are any specific clarifications, please let me know. Also, it's not clear what the specific meaning of some of the variables like "WP", "εcal", etc. are in the context of the patent, but I've translated them as they are presented.​​If ε(T) < 1, then block 806 is reached, where no offset correction is provided.

[0059] Please note that offset correction will not occur when the measurement circuit loop is disabled.

[0060] The above process can be performed periodically while the VR is in adjustment mode. The time between two consecutive measurements can be configured via a fuse.

[0061] In summary, this solution provides a way to mitigate / eliminate slow variations in VR output voltage (primarily due to temperature and aging) by adding measurement circuitry with a dedicated slow feedback loop. This solution offers the opportunity to reduce the guard band and allows for a reduction in VR controller area and / or quiescent power consumption. Furthermore, since the bandwidth difference between the main feedback loop and the slow feedback loop exceeds, for example, two orders of magnitude, this solution does not introduce any instability risks. The introduction of the slow feedback loop is transparent to the HVM Vmin process and system verification process.

[0062] Figure 9 Examples of components that may exist in computing system 950 for implementing the techniques described herein (e.g., operations, processes, methods, and methodologies) are shown.

[0063] The computing system 950 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof adapted into the computing system 950, or as components otherwise included within the chassis of a larger system. In the example implementation, the aforementioned voltage regulator and associated measurement circuitry are represented by voltage regulator 900.

[0064] In one approach, all or part of the computing system 950 is provided in the form of a SoP, a System in Package (SiP), or a System on Chip (SoC).

[0065] A voltage regulator may provide a voltage Vout to one or more components of the computing system 950. Furthermore, the computing system 950 may include one or more voltage regulators. Memory circuitry 954 may store instructions, and processor circuitry 952 may execute these instructions to perform the functions described herein.

[0066] System 950 includes processor circuitry in the form of one or more processors 952. Processor circuitry 952 includes, but is not limited to, circuitry such as (but not limited to): one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C, or general-purpose programmable serial interface circuitry, real-time clock (RTC), timer-counters including interval and watchdog timers, general-purpose I / O, memory card controller such as secure digital / multi-media card (SD / MMC) or similar interfaces, mobile industrial processor interface (MIPI) interface, and Joint Test Access Group (JTAG) test access port. In some implementations, processor circuitry 952 may include one or more hardware accelerators (e.g., the same as or similar to accelerator circuitry 964), which may be microprocessors, programmable processing devices (e.g., FPGAs, ASICs, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, processor circuitry 952 may include on-chip memory circuitry, which may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0067] Processor circuitry 952 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing element, or any suitable combination thereof. Processor (or core) 952 may be coupled to or may include a memory / storage device and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on platform 950. Processor (or core) 952 is configured to operate application software to provide specific services to users of platform 950. In some embodiments, processor(s) 952 may be one or more dedicated processors / controllers configured (or configurable to) operate according to various embodiments herein.

[0068] As an example, processor(s) 952 may include Intel® Core™ architecture-based processors, such as i3, i5, i7, i9-based processors; Intel® microcontroller-based processors, such as Quark™, ​​Atom™, or other MCU-based processors; (one or more) Pentium® processors, (one or more) Xeon® processors, or other such processors available from Intel® Inc., Santa Clara, California. However, any number of other processors may also be used, such as one or more of the following: Zen® architecture from Advanced Micro Devices (AMD), such as one or more Ryzen® or EPYC® processors, Accelerated Processing Units (APUs), MxGPUs, one or more Epyc® processors, etc.; one or more A5-A12 and / or S1-S4 processors from Apple®, one or more Snapdragon™ or Centriq™ processors from Qualcomm® Technologies, one or more Open Multimedia Applications Platform (OMAP)™ processors from Texas Instruments, Inc.; MIPS-based designs from MIPS Technologies, such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; ThunderX2® from Cavium™, etc. In some implementations, the processor(s) 952 may be part of a system-on-a-chip (SoC), a system-in-package (SiP), a multi-chip package (MCP), etc., where the processor(s) 952 and other components are formed as a single integrated circuit or a single package, such as an Edison™ or Galileo™ SoC board from Intel®. Other examples of the processor(s) 952 are mentioned elsewhere in this disclosure.

[0069] System 950 may include or be coupled to acceleration circuitry 964, which may be implemented by one or more AI / ML accelerators, neural computation sticks, neuromorphic hardware, FPGAs, GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, application-specific integrated circuits (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other specialized processors or circuits designed to perform one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, and so on. In an FPGA-based implementation, acceleration circuitry 964 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and so on of the various embodiments discussed herein. In such an implementation, the acceleration circuit 964 may also include memory cells (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.)) for storing logic blocks, logic architectures, data, etc. in LUTs, etc.

[0070] In some implementations, processor circuitry 952 and / or acceleration circuitry 964 may include hardware elements specifically tailored for machine learning and / or artificial intelligence (AI) functions. In these implementations, processor circuitry 952 and / or acceleration circuitry 964 may be or may include an AI engine chip, which, once loaded with appropriately weighted and trained code, can run many different kinds of AI instruction sets. Additionally or alternatively, processor circuitry 952 and / or acceleration circuitry 964 may be or may include one or more AI accelerators, which may be one or more of the aforementioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators could be clusters of the following: artificial intelligence (AI) GPUs, tensor processing units (TPUs) developed by Google®, Real AI Processors (RAP™) provided by AlphaICs®, Neural Network Processors (NNPs) provided by Intel®, Vision Processing Units (VPUs) provided by Intel® Movidius™ Myriad™ X, GPUs based on NVIDIA® PX™, NM500 chips provided by General Vision®, Hardware 3 provided by Tesla®, Epiphany™-based processors provided by Adapteva®, and so on. In some embodiments, the processor circuitry 952 and / or the acceleration circuitry 964 and / or the hardware accelerator circuitry can be implemented as one or more AI acceleration coprocessors, such as the Hexagon 685 DSP from Qualcomm®, the PowerVR2NX Neural Net Accelerator (NNA) from Imagination Technologies Limited®, the Neural Engine core within the Apple® A11 or A12 Bionic SoC, the Neural Processing Unit (NPU) within the HiSilicon Kirin from Huawei®, and so on. In some hardware-based implementations, individual subsystems of the system 950 can be operated by various AI acceleration coprocessors, AI GPUs, TPUs, or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., configured with appropriate logic blocks, bitstreams, etc., to perform their respective functions.

[0071] System 950 also includes system memory circuitry 954. Any number of memory devices can be used to provide a fixed amount of system memory. As an example, memory circuitry 954 may be or may include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other desired type of volatile memory device. Additionally or alternatively, memory circuitry 954 may be or may include non-volatile memory, such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable (EEPROM), flash memory, non-volatile RAM, ferroelectric RAM, phase-change memory (PCM), and / or any other desired type of non-volatile memory device. Access to memory circuitry 954 is controlled by a memory controller. Individual memory devices can have any number of different package types, such as single die package (SDP), dual die package (DDP), or quad die package (Q17P). Any number of other memory implementations can be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0072] Storage circuitry 958 provides persistent storage for information such as data, applications, operating systems, and so on. In one example, storage circuitry 958 can be implemented via a solid-state disk drive (SSDD) and / or high-speed electrically erasable memory (often referred to as "flash memory"). Other devices that can be used with storage circuitry 958 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and so on, as well as USB flash drives. In one example, the memory device may be or may include memory devices using chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) incorporating memristor technology, phase change RAM (PRAM), resistive memory including metal oxide substrates, oxygen vacancy substrates, and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, devices based on spintronic magnetic junction memory, devices based on magnetic tunneling junction (MTJ), devices based on domain wall (DW) and spin orbit transfer (SOT), memory devices based on semiconductor thyristors, and hard disk drives. The memory circuitry 954 and / or memory circuitry 958 may also contain three-dimensional (3D) crosspoint (XPOINT) memory from Intel® and Micron®.

[0073] Memory circuitry 954 and / or storage circuitry 958 are configured to store computational logic 983 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. Computational logic 983 may be used to store working copies and / or permanent copies of programming instructions, or data for creating programming instructions, for use by various components of operating system 950 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of system 950, one or more applications, and / or for implementing the embodiments discussed herein. Computational logic 983 may be stored or loaded into memory circuitry 954 as instructions 982 or data for creating instructions 982, and then accessed by processor circuitry 952 for execution to implement the functions described herein. Processor circuitry 952 and / or acceleration circuitry 964 access memory circuitry 954 and / or storage circuitry 958 via interconnect (IX) 956. Instructions 982 instruct processor circuitry 952 to perform specific sequences of actions or processes, for example, as described with reference to one or more flowcharts and block diagrams of operation and function previously depicted. Various elements can be implemented using assembly instructions or high-level languages ​​supported by processor circuitry 952. These instructions can be compiled into instructions 988, or used to create data for instructions 988, so that they can be executed by processor circuitry 952. A permanent copy of the programming instructions can be placed into the persistent storage device of the storage circuitry 958 at the factory or in the field via, for example, a distribution medium (not shown), a communication interface (e.g., from a distribution server (not shown)), over-the-air (OTA), or any combination thereof.

[0074] IX 956 couples processor 952 to communication circuitry 966 for communication with other devices, such as remote servers (not shown), etc. Communication circuitry 966 is a hardware element, or a collection of hardware elements, for communicating via one or more networks 963 and / or with other devices. In one example, communication circuitry 966 is or includes transceiver circuitry configured to implement wireless communication using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or variations thereof), IEEE 802.23.4, Bluetooth® and / or Bluetooth® Low Energy (BLE), ZigBee®, LoRaWAN™ (Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 966 is or includes one or more network interface controllers (NICs) to enable wired communication using, for example, the following: Ethernet connection, Controller Area Network (CAN), Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0075] The IX 956 also couples a processor 952 to an interface circuit 970, which connects the system 950 to one or more external devices 972. External devices 972 may include, for example, sensors, actuators, positioning circuitry (e.g., global navigation satellite system (GNSS) / Global Positioning System (GPS) circuitry), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., integrated circuits (ICs) of optical neural networks (ONNs), and / or other similar devices.

[0076] In some optional examples, various input / output (I / O) devices may be present within or connected to system 950, referred to as input circuitry 986 and output circuitry 984. Input circuitry 986 and output circuitry 984 include one or more user interfaces designed to enable user interaction with platform 950, and / or peripheral component interfaces designed to enable peripheral components to interact with platform 950. Input circuitry 986 may include any physical or virtual device for accepting input, particularly including one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphone, scanner, headset, etc. Output circuitry 984 may be included to display or otherwise convey information, such as sensor readings, actuator(s) position, or other similar information. Data and / or graphics may be displayed on one or more user interface components of output circuitry 984. The output circuitry 984 may include any number and / or combination of audio or visual displays, particularly including one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light-emitting diodes, LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., liquid crystal displays). Displays (LCDs), LED displays, quantum dot displays, projectors, etc.), where the output of characters, graphics, multimedia objects, etc., is generated or produced from the operation of platform 950. Output circuitry 984 may also include speakers and / or other audio emitting devices, one or more printers, etc. Additionally or alternatively, one or more sensors may be used as output circuitry 984 (e.g., image capture devices, motion capture devices, etc.) and one or more actuators may be used as output device circuitry 984 (e.g., actuators to provide haptic feedback, etc.). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power supply interfaces, etc. In some embodiments, within the context of this system, display or console hardware may be used to provide output and receive input from the edge computing system; manage components or services of the edge computing system; identify the status of edge computing components or services; or perform any other number of management or administrative functions or service use cases.

[0077] Components of the System 950 can communicate via the IX 956. The IX 956 can include any number of technologies, including ISA, Extended ISA, I2C, SPI, Point-to-Point Interface, Power Management Bus (PMBus), PCI, PCIe, PCIx, Intel® UPI, Intel® Accelerator Link, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, UPI, Intel® OPA IX, RapidIO™ System IX, CCIX, Gen-Z Alliance IX, HyperTransport Interconnect, NVLink provided by NVIDIA®, Time-Trigger Protocol (TTP) System, FlexRay System, PROFIBUS, and / or any number of other IX technologies. The IX 956 can be a proprietary bus, for example, used in SoC-based systems.

[0078] The number, capabilities, and / or capacity of the elements of system 950 may vary depending on whether computing system 950 is used as a fixed computing device (e.g., a server computer, workstation, desktop computer, etc. in a data center) or a mobile computing device (e.g., a smartphone, tablet computing device, laptop computer, game console, IoT device, etc.). In various implementations, computing device system 950 may include one or more components of a data center, a desktop computer, workstation, laptop computer, smartphone, tablet device, digital camera, smart home appliance, smart home hub, network appliance, and / or any other device / system that processes data.

[0079] The techniques described herein can be executed, in whole or in part, by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions for implementing any other processes discussed herein). Instructions associated with and executed to implement embodiments of the disclosed subject matter can be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of instructions.

[0080] Storage media can be tangible, non-transitory, machine-readable media, such as read-only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., compact disk read-only memory (CD ROMs), digital versatile disks (DVDs)), and so on.

[0081] Storage media can be included in, for example, communication devices, computing devices, network devices, personal digital assistants, manufacturing tools, mobile communication devices, cellular phones, laptops, tablets, game consoles, set-top boxes, embedded systems, TVs, or personal desktop computers.

[0082] The following are some non-limiting examples of various embodiments.

[0083] Example 1 includes an apparatus comprising: a voltage regulator having an input node and an output node; a voltage shaping circuit coupled to the input node, wherein the voltage shaping circuit includes a summing circuit; and a measurement circuit coupled to the output node and the summing circuit.

[0084] Example 2 includes the apparatus of Example 1, wherein the voltage shaping circuit includes an input node configured to receive the operating point voltage of VR.

[0085] Example 3 includes the apparatus of Example 2, wherein the input node of the voltage shaping circuit is coupled to the summing circuit via a multiplier.

[0086] Example 4 includes the apparatus of any one of Examples 1-3, wherein the VR operates according to a first clock, and the measurement circuit operates according to a second clock, wherein the frequency of the first clock is at least 10-100 times higher than the frequency of the second clock.

[0087] Example 5 includes an apparatus of any of Examples 1-4, wherein the measurement circuit includes a comparator whose input node is coupled to the output node of VR and the input node of the voltage shaping circuit.

[0088] Example 6 includes an apparatus of any one of Examples 1-5, wherein the measurement circuit includes a comparator, a finite state machine (FSM), and a summing circuit, the comparator having an input node coupled to the output node of the VR, the FSM being coupled to the output node of the comparator, and the summing circuit of the measurement circuit having an input node coupled to the FSM and an output node coupled to the voltage shaping circuit.

[0089] Example 7 includes an apparatus from any of Examples 1-6, wherein the measurement circuitry includes a comparator whose input node is coupled to the output node of the VR and the output node of a digital-to-analog converter (DAC), and the DAC includes a resistor ladder coupled to the DAC output node via a multiplexer.

[0090] Example 8 includes the apparatus of Example 7, wherein the resistive ladder includes a power supply voltage node coupled to a bandgap reference circuit.

[0091] Example 9 includes the apparatus of Example 7 or 8, and further includes: an up / down counter coupled to a multiplexer and a finite state machine (FSM) coupled to the up / down counter, wherein the multiplexer is configured to pass a series of incrementing voltages and a series of decrementing voltages to the output node of the DAC.

[0092] Example 10 includes an apparatus of any one of Examples 1-9, wherein the apparatus is provided in at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device.

[0093] Example 11 includes an apparatus comprising: a voltage regulator (VR) having an input node and an output node, the input node being for receiving an operating point voltage, wherein the VR is configured to implement a first feedback loop to control the voltage at the output node in response to the operating point voltage; a voltage shaping circuit coupled to the input node; and a measurement circuit coupled to the output node and the voltage shaping circuit, wherein the measurement circuit is configured to implement a second feedback loop to control the operating point voltage.

[0094] Example 12 includes the apparatus of Example 11, wherein a first feedback loop is configured to operate at a first frequency, and a second feedback loop is configured to operate at a second frequency lower than the first frequency.

[0095] Example 13 includes the apparatus of Example 11 or 12, wherein the voltage shaping circuit is configured to receive an initial value of the operating point voltage and output a modified value of the operating point voltage to the input node of the VR.

[0096] Example 14 includes the apparatus of Example 13, wherein the voltage shaping circuit includes a summing circuit configured to provide a modified value of the operating point voltage, and the summing circuit is coupled to the measurement circuit.

[0097] Example 15 includes the apparatus of Example 14, wherein the voltage shaping circuitry includes a multiplier configured to provide a modified value of the operating point voltage, and a summing circuitry is coupled to the multiplier.

[0098] Example 16 includes a system comprising: a processor; a voltage regulator (VR) coupled to the processor, wherein the VR is configured to control an output voltage in response to an operating point voltage; and one or more circuits coupled to the VR, wherein the one or more circuits are configured to control the operating point voltage.

[0099] Example 17 includes the system of Example 16, wherein the one or more circuits include a bandgap reference circuit configured to generate a bandgap reference voltage, and a comparator configured to compare an output voltage with a voltage obtained from the bandgap reference voltage.

[0100] Example 18 includes the system of Example 17, wherein the one or more circuits include a finite state machine (FSM) configured to operate in an up-measurement state and a down-measurement state, wherein in the up-measurement state the voltage obtained from the bandgap reference voltage increases in sequence, and in the down-measurement state the voltage obtained from the bandgap reference voltage decreases in sequence.

[0101] Example 19 includes the system of Example 17 or 18, wherein the one or more circuits further include a finite state machine (FSM) coupled to the output node of the comparator, and the FSM is configured to increment or decrement the operating point voltage based on the value received at the comparator output node.

[0102] Example 20 includes a system of any of Examples 17-19, wherein the one or more circuits are configured to determine, in a given clock cycle of the one or more circuits, whether to increment, decrement, or not change the operating point voltage based on the output of the comparator.

[0103] Example 21 includes a method comprising: implementing a first feedback loop at a voltage regulator (VR) having an input node and an output node, the input node being for receiving an operating point voltage, wherein the first feedback loop is used to control the voltage at the output node in response to the operating point voltage; and implementing a second feedback loop using measurement circuitry and voltage shaping circuitry to control the operating point voltage.

[0104] Example 22 includes the method of Example 21, further comprising: operating the first feedback loop at a first frequency and operating the second feedback loop at a second frequency lower than the first frequency.

[0105] Example 23 includes the method of Example 21 or 22, further comprising: at a voltage shaping circuit, receiving an initial value of the operating point voltage and outputting a modified value of the operating point voltage to the input node of VR.

[0106] Example 24 includes the method of any one of Examples 21-23, and further includes providing a modified value of the operating point voltage at the summing circuit of the voltage shaping circuit.

[0107] Example 25 includes the method of any of Examples 21-24, and further includes: providing a modified value of the operating point voltage at the multiplier of the voltage shaping circuit.

[0108] Example 26 includes an apparatus comprising means for performing the method according to any one of Examples 21-25.

[0109] Example 27 includes a machine-readable storage medium comprising machine-readable instructions that, when executed, cause a computer to perform the method according to any one of Examples 21-25.

[0110] Example 28 includes a computer program containing instructions that, when executed by a computer, cause the computer to perform the method according to any one of Examples 21-25.

[0111] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from that described in the embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0112] The terms “basically,” “near,” “roughly,” “approximately,” and “about” generally refer to within + / - 10% of the target value. Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third,” etc., to describe common objects merely indicates that different instances of similar objects are being referenced, and is not intended to imply that the objects described in this way must be in a given sequence in time, space, ranking, or any other way.

[0113] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0114] The description may use the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in connection with embodiments of this disclosure are synonymous.

[0115] As used herein, the term "circuit" can refer to, is part of, or includes: an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or grouped), combinational logic circuitry, and / or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" can refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0116] This document uses the terms “coupling,” “communicationally coupled,” and their derivatives. The term “coupling” can mean two or more elements in direct physical or electrical contact with each other, can mean two or more elements in indirect contact with each other but still cooperating or interacting with each other, and / or can mean one or more other elements coupled or connected between the elements allegedly coupled to each other. The term “direct coupling” can mean two or more elements in direct contact with each other. The term “communicationally coupled” can mean two or more elements in contact with each other through communication means, including through wires or other interconnections, through wireless communication channels or links, etc.

[0117] Furthermore, specific features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment wherever specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0118] While this disclosure has been described in conjunction with specific embodiments thereof, those skilled in the art will recognize from the foregoing description many alternatives, modifications, and variations of such embodiments. The embodiments of this disclosure are intended to encompass all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0119] Furthermore, for the sake of simplicity in illustration and discussion, and to avoid obscuring this disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the accompanying drawings. Additionally, arrangements may be shown in block diagram form to avoid obscuring this disclosure, also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which this disclosure is to be implemented (i.e., such specific details should be entirely within the view of someone skilled in the art). In the context of setting forth specific details (e.g., circuits) to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that this disclosure can be implemented without these specific details, or using variations thereof. Therefore, this specification should be considered illustrative rather than restrictive.

[0120] An abstract is provided to allow the reader to determine the nature and spirit of this technical disclosure. The abstract is submitted with the understanding that it is not intended to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim serving as an independent, separate embodiment.

Claims

1. An apparatus comprising: A voltage regulator with input and output nodes; A voltage shaping circuit is coupled to the input node, wherein the voltage shaping circuit includes a summing circuit; as well as The measurement circuit is coupled to the output node and the summing circuit.

2. The apparatus according to claim 1, wherein, The voltage shaping circuit includes an input node configured to receive the operating point voltage of the voltage regulator.

3. The apparatus according to claim 2, wherein, The input node of the voltage shaping circuit is coupled to the summing circuit via a multiplier.

4. The apparatus according to claim 1 or 2, wherein, The voltage regulator operates according to a first clock, and the measurement circuit operates according to a second clock, wherein the frequency of the first clock is at least 10-100 times higher than the frequency of the second clock.

5. The apparatus according to claim 1 or 2, wherein, The measurement circuit includes a comparator, the input node of which is coupled to the output node of the voltage regulator and the input node of the voltage shaping circuit.

6. The apparatus according to claim 1 or 2, wherein, The measurement circuit includes a comparator, a finite state machine (FSM), and a summing circuit. The comparator has an input node coupled to the output node of the voltage regulator, the FSM is coupled to the output node of the comparator, and the summing circuit of the measurement circuit has an input node coupled to the FSM and an output node coupled to the summing circuit of the voltage shaping circuit.

7. The apparatus according to claim 1 or 2, wherein, The measurement circuit includes a comparator whose input node is coupled to the output node of the voltage regulator and the output node of the digital-to-analog converter (DAC), and the DAC includes a resistor ladder coupled to the output node of the DAC via a multiplexer.

8. The apparatus according to claim 7, wherein, The resistive ladder includes a power supply voltage node coupled to a bandgap reference circuit.

9. The apparatus according to claim 7, further comprising: An up / down counter coupled to the multiplexer and a finite state machine coupled to the up / down counter, wherein the multiplexer is configured to pass a series of incrementing voltages and a series of decrementing voltages to the output node of the DAC.

10. The apparatus according to claim 1 or 2, wherein, The device is provided in at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device.

11. An apparatus comprising: A voltage regulator (VR) has an input node and an output node, the input node being used to receive an operating point voltage, wherein the voltage regulator is configured to implement a first feedback loop to control the voltage at the output node in response to the operating point voltage; Voltage shaping circuitry, coupled to the input node; and A measurement circuit is coupled to the output node and the voltage shaping circuit, wherein the measurement circuit is configured to implement a second feedback loop to control the operating point voltage.

12. The apparatus according to claim 11, wherein, The first feedback loop is configured to operate at a first frequency, and the second feedback loop is configured to operate at a second frequency lower than the first frequency.

13. The apparatus according to claim 11 or 12, wherein, The voltage shaping circuit is configured to receive the initial value of the operating point voltage and output the modified value of the operating point voltage to the input node of the voltage regulator.

14. The apparatus according to claim 13, wherein, The voltage shaping circuit includes a summing circuit configured to provide a modified value of the operating point voltage, and the summing circuit is coupled to the measurement circuit.

15. The apparatus according to claim 14, wherein, The voltage shaping circuit includes a multiplier configured to provide a modified value of the operating point voltage, and the summing circuit is coupled to the multiplier.

16. A system comprising: processor; A voltage regulator, coupled to the processor, wherein the voltage regulator is configured to control the output voltage in response to the operating point voltage; and One or more circuits are coupled to the voltage regulator, wherein the one or more circuits are configured to control the operating point voltage.

17. The system according to claim 16, wherein, The one or more circuits include a bandgap reference circuit and a comparator, the bandgap reference circuit being configured to generate a bandgap reference voltage, and the comparator being configured to compare the output voltage with a voltage obtained from the bandgap reference voltage.

18. The system according to claim 17, wherein, The one or more circuits include a finite state machine (FSM) configured to operate in an up-measurement state and a down-measurement state, wherein in the up-measurement state the voltage obtained from the bandgap reference voltage increases in sequence, and in the down-measurement state the voltage obtained from the bandgap reference voltage decreases in sequence.

19. The system according to claim 17 or 18, wherein, The one or more circuits also include a finite state machine (FSM) coupled to the output node of the comparator, and the FSM is configured to increment or decrement the operating point voltage based on a value received at the output node of the comparator.

20. The system according to claim 17, wherein, The one or more circuits are configured to determine, based on the output of the comparator, whether to increment, decrement, or not change the operating point voltage during the corresponding clock cycle of the one or more circuits.

21. A method comprising: A first feedback loop is implemented at a voltage regulator (VR), the VR having an input node and an output node, the input node for receiving an operating point voltage, wherein the first feedback loop is used to control the voltage at the output node in response to the operating point voltage; and A second feedback loop is implemented using a measurement circuit and a voltage shaping circuit to control the operating point voltage.

22. The method of claim 21, further comprising: The first feedback loop is operated at a first frequency, and the second feedback loop is operated at a second frequency lower than the first frequency.

23. An apparatus comprising means for performing the method according to claim 21 or 22.

24. A machine-readable storage medium comprising machine-readable instructions that, when executed, cause a computer to perform the method according to claim 21 or 22.

25. A computer program comprising instructions that, when executed by a computer, cause the computer to perform the method according to claim 21 or 22.

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