Hybrid digital signal generation method, system, storage medium and program product

Abstract

The embodiment of the present disclosure discloses a hybrid digital signal generation method, system, storage medium and program product. The method comprises the following steps: obtaining a signal generation task and a corresponding target signal type in real time by analyzing a signal event description word stream; when the target signal type is a self-contained signal, distributing the signal generation task to a heterogeneous processing pipeline resource pool, and generating a self-contained IQ signal stream according to the configuration parameters of the signal generation task by the internally matched pipeline; when the target signal type is a dependent signal, distributing the signal generation task to an adaptive digital echo coprocessor, and generating a dependent IQ signal stream by performing digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task; and merging the two types of IQ signal streams in parallel to generate a composite IQ signal stream. The method can realize the cooperative generation of high-density self-contained signals and high-fidelity dependent signals in a single chip, and improve the utilization rate of hardware resources.

Description

Technical Field

[0001] This disclosure relates to the field of digital signal processing technology, and in particular to a method, system, storage medium, and program product for generating mixed digital signals. Background Technology

[0002] In modern electronic warfare, radar testing, and complex electromagnetic environment simulation applications, it is often necessary to synthesize mixed waveforms of multiple signal types in real time within the same physical channel. These signals can be divided into two categories: self-contained signals and dependent signals. Self-contained signals include radar pulses, communication signals, noise, and jamming, which are numerous, simple in structure, and can be parameterized. Dependent signals, typically represented by radar target echoes, depend on the transmitted signal and require complex operations such as convolution, time delay, Doppler shift, and attenuation to simulate channel and target characteristics, resulting in high computational load and complex processing logic. Existing FPGA signal synthesis schemes are mainly divided into two paradigms: homogeneous parallel architecture and dedicated processor architecture. The former uses a large number of identical simple signal generation cores to work in parallel, while the latter relies on a dedicated processor to achieve high-precision correlation signal operations.

[0003] In traditional single-architecture signal generation methods, while homogeneous parallel architectures can efficiently generate a large number of independent signals, they struggle to efficiently perform complex operations such as convolution, failing to meet the requirements for high-fidelity dependent signal generation. Dedicated processor architectures, while capable of high-precision echo simulation, are unable to generate a large number of simple signals in parallel, resulting in low hardware resource utilization. Therefore, current technologies cannot simultaneously achieve high-density self-contained signal generation and high-fidelity dependent signal synthesis within a single chip, making them unsuitable for the practical needs of modern complex electromagnetic environment simulations requiring mixed signal generation. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a hybrid digital signal generation method, system, storage medium, and program product that can simultaneously achieve the collaborative generation of high-density self-contained signals and high-fidelity dependent signals within a single chip, effectively solving the problems of traditional architectures being unable to simultaneously generate both types of signals and having low hardware resource utilization.

[0005] In a first aspect, embodiments of this disclosure provide a method for generating hybrid digital signals, employing the following technical solution: Receive signal event description word stream, parse the signal event description word stream in frames as the smallest unit, obtain the signal generation task in real time, and identify the target signal type corresponding to the signal generation task; When the target signal type is a self-contained signal, the signal generation task is assigned to the heterogeneous processing pipeline resource pool, and the pipeline matched in the heterogeneous processing pipeline resource pool generates a self-contained IQ signal stream according to the configuration parameters of the signal generation task. When the target signal type is a dependent signal, the signal generation task is assigned to an appropriate digital echo coprocessor. The digital echo coprocessor performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate a dependent IQ signal stream. The parallel self-contained IQ signal stream and the dependent IQ signal stream are digitally combined to generate a composite IQ signal stream.

[0006] Optionally, the received signal event description stream is parsed frame by frame to extract the signal generation task in real time and identify the target signal type corresponding to the signal generation task, including: The header frame and member frames that have control and constraint relationships with the header frame are received sequentially from the signal event description word stream. Based on the group header frame and the member frames that have control and constraint relationships with the group header frame, a corresponding signal generation task is constructed and the configuration parameters of the signal generation task are extracted. The signal generation type is parsed from the member frame and used as the target signal type for the signal generation task.

[0007] Optionally, the step of allocating the signal generation task to a heterogeneous processing pipeline resource pool, and having a matching pipeline within the heterogeneous processing pipeline resource pool generate a self-contained IQ signal stream according to the configuration parameters of the signal generation task, includes: Analyze the signal generation task to obtain the corresponding target transmission channel and target pipeline type; In the heterogeneous processing pipeline resource pool, pipelines that belong to the target launch channel, are idle, and match the target pipeline type are selected; If a matching pipeline exists, the configuration parameters of the signal generation task are loaded into the matching pipeline, and the matching pipeline generates the corresponding self-contained IQ signal stream in real time. If no matching pipeline exists, then determine from the target launch channel whether there is an idle pipeline that supports reconfiguration to the target pipeline type; If an idle pipeline that supports reconfiguration exists, the idle pipeline is reconfigured, the reconfigured pipeline is configured as the target pipeline type, and the configuration parameters of the signal generation task are loaded. Based on the configuration parameters, the corresponding self-contained IQ signal stream is generated in real time.

[0008] Optionally, determining whether there is an idle pipeline in the target launch channel that supports reconfiguration into the target pipeline type includes: If the target pipeline type is a subtype of digital modulation type, then determine whether the IQ playback type pipeline in the target transmit channel that is in an idle state supports reconstruction into the subtype; If supported, then it is determined that there exists an idle pipeline that can be reconstructed into the target pipeline type; If not supported, then it is determined that there is no idle pipeline that can be reconstructed into the target pipeline type; If the target pipeline type is IQ playback type, then the digital modulation type pipeline that is in an idle state in the target transmit channel is determined as an idle pipeline that supports reconstruction to the target pipeline type.

[0009] Optionally, the step of reconfiguring the idle pipeline and setting the reconfigured pipeline to the target pipeline type includes: Configure a shadow register group for pre-storing configuration parameters for the active register group of the idle pipeline; Load the runtime parameters adapted to the target pipeline type into the shadow register group of the idle pipeline; At the mode switching boundary moment, the running parameters in the shadow register group are synchronously updated to the effective register group; Based on the running parameters in the updated effective register group, the idle pipeline is reconstructed into the target pipeline type.

[0010] Optionally, the step of assigning the signal generation task to an adapted digital echo coprocessor, wherein the digital echo coprocessor performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate a dependent IQ signal stream, includes: Analyze the signal generation task to obtain the corresponding target transmission channel; The signal generation task is assigned to a dedicated digital echo coprocessor for the target transmission channel, and the digital echo coprocessor determines the matching input source based on the input source identifier in the configuration parameters. Based on the convolution kernel parameters in the configuration parameters, a linear convolution operation is performed on the illumination signal output by the input source to generate a preliminary echo signal; Based on the modulation parameters in the configuration parameters, the initial echo signal is modulated to generate a corresponding dependent IQ signal stream.

[0011] Optionally, the step of digitally combining the parallel self-contained IQ signal stream and the dependent IQ signal stream to generate a composite IQ signal stream includes: Obtain the absolute trigger times of the self-contained IQ signal stream and the dependent IQ signal stream; The self-contained IQ signal stream and the dependent IQ signal stream with the same absolute trigger time are digitally combined to generate a composite IQ signal stream.

[0012] Secondly, embodiments of this disclosure also provide a hybrid digital signal generation system, the system including a controller, a heterogeneous processing pipeline resource pool, a digital echo coprocessor, and a digital synthesis unit; The controller is configured to receive a signal event description word stream, parse the signal event description word stream in frames as the smallest unit, extract the signal generation task in real time, and identify the target signal type corresponding to the signal generation task. When the target signal type is a self-contained signal, the signal generation task is assigned to a matching pipeline within the heterogeneous processing pipeline resource pool; When the target signal type is a dependent signal, the signal generation task is assigned to an appropriate digital echo coprocessor. The heterogeneous processing pipeline resource pool is used to generate a self-contained IQ signal stream according to the configuration parameters of the signal generation task through a matched pipeline. The digital echo coprocessor is used to perform digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task, and generate a dependent IQ signal stream. The digital synthesis unit is used to digitally combine parallel self-contained IQ signal streams and dependent IQ signal streams to generate a composite IQ signal stream.

[0013] Optionally, the heterogeneous processing pipeline resource pool includes a digital modulation type pipeline and an IQ playback type pipeline; The digital modulation type pipeline is used to perform signal generation tasks where the target pipeline type is digital modulation; When a signal generation task of the target pipeline type IQ playback needs to be executed, it is reconstructed to the IQ playback type. The IQ playback type pipeline is used to execute signal generation tasks with the target pipeline type being IQ playback; When a signal generation task of the target pipeline type of digital modulation needs to be executed, it is reconstructed to the digital modulation type.

[0014] Optionally, the digital echo coprocessor includes an input selector, an input source, a convolution unit, and an adjustment unit; The input selector is used to determine a matching input source based on the input source identifier in the configuration parameters of the signal generation task, and send the illumination signal output by the input source to the convolution unit. The input source is used to output an illumination signal; The convolutional unit is used to perform a linear convolution operation on the illumination signal based on the convolutional kernel parameters in the configuration parameters to generate a preliminary echo signal; The adjustment unit is used to modulate the initial echo signal based on the modulation parameters in the configuration parameters to generate a corresponding dependent IQ signal stream.

[0015] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the above-described mixed digital signal generation methods.

[0016] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to perform any of the above-described mixed digital signal generation methods.

[0017] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0018] The hybrid digital signal generation method provided in this disclosure, by parsing the signal event description word stream frame by frame, can acquire and distinguish between self-contained and dependent signal tasks in real time. By offloading signal generation tasks with different characteristics to dedicated hardware units for execution, it can avoid the resource mismatch problem of traditional single architectures at the architectural level. For self-contained signals, a heterogeneous processing pipeline resource pool is used for generation. By directly allocating tasks to the matching hardware pipelines in the pool, the signal generation process can be executed through dedicated hardware paths, ensuring stable, real-time, and parallel output of multiple self-contained IQ signal streams, while improving the utilization efficiency of hardware resources and the system's adaptability to various self-contained signals. For dependent signals, a dedicated digital echo coprocessor is used for processing, allowing it to focus on completing digital transformation operations related to the illumination signal, avoiding competition for pipeline resources with self-contained signals, thereby ensuring the real-time performance and stability of dependent IQ signal stream generation. Finally, the self-contained IQ signal stream and the dependent IQ signal stream generated in parallel are digitally merged, enabling the output of a unified composite IQ signal stream within the same physical channel. This allows the two types of signals to work collaboratively within the same generation engine, eliminating the need for two separate hardware sets. Consequently, high-density independent signal generation and high-complexity dependent signal synthesis can be achieved simultaneously within a single chip, effectively improving system integration and resource utilization efficiency. This better meets the application requirements of complex electromagnetic environment simulations such as modern electronic warfare and radar testing.

[0019] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic flowchart illustrating the hybrid digital signal generation method provided in this embodiment of the disclosure; Figure 2 A flowchart illustrating the signal generation task and target signal type acquisition method provided in this embodiment of the disclosure; Figure 3 This is a schematic diagram of the structure of the hybrid digital signal generation system provided in the embodiments of this disclosure; Figure 4 A schematic flowchart of the self-contained IQ signal stream generation method provided in the embodiments of this disclosure; Figure 5 A flowchart illustrating the process of determining whether a pipeline method supporting reconfiguration exists, provided in an embodiment of this disclosure. Figure 6 A schematic flowchart of the pattern reconstruction method provided in the embodiments of this disclosure; Figure 7 A flowchart illustrating the dependent IQ signal stream generation method provided in this embodiment of the disclosure; Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0024] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0027] Reference Figure 1 This disclosure provides a method for generating mixed digital signals, comprising the following steps: S1: Receive signal event description word stream, parse the signal event description word stream in frames as the smallest unit, obtain the signal generation task in real time, and identify the target signal type corresponding to the signal generation task; S2: When the target signal type is a self-contained signal, the signal generation task is assigned to the heterogeneous processing pipeline resource pool. The pipeline matched in the heterogeneous processing pipeline resource pool generates a self-contained IQ signal stream according to the configuration parameters of the signal generation task. S3: When the target signal type is a dependent signal, the signal generation task is assigned to the appropriate digital echo coprocessor. The digital echo coprocessor performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate a dependent IQ signal stream. S4: Digitally combine the parallel self-contained IQ signal stream and the dependent IQ signal stream to generate a composite IQ signal stream.

[0028] The hybrid digital signal generation method disclosed herein can acquire and distinguish between self-contained and dependent signal tasks in real time by parsing signal event description word streams frame by frame. By offloading signal generation tasks with different characteristics to dedicated hardware units for execution, it can avoid the resource mismatch problem of traditional single architectures at the architectural level. For self-contained signals, a heterogeneous processing pipeline resource pool is used for generation. By directly allocating tasks to the matching hardware pipelines in the pool, the signal generation process can be executed based on dedicated hardware paths, ensuring stable, real-time parallel output of multiple self-contained IQ signal streams, while improving the utilization efficiency of hardware resources and the system's adaptability to various self-contained signals.

[0029] A dedicated digital echo coprocessor is used to process dependent signals, allowing it to focus on performing digital transformation calculations related to the illumination signal. This avoids competition for pipeline resources with self-contained signals, thus ensuring the real-time performance and stability of dependent IQ signal stream generation. Finally, the parallel-generated self-contained IQ signal stream and dependent IQ signal stream are digitally merged, enabling the output of a unified composite IQ signal stream within the same physical channel. This allows the two types of signals to work collaboratively within the same generation engine, eliminating the need for two separate hardware sets. Consequently, high-density independent signal generation and high-complexity dependent signal synthesis can be achieved simultaneously within a single chip, effectively improving system integration and resource utilization efficiency. This better meets the application requirements of complex electromagnetic environment simulations such as modern electronic warfare and radar testing.

[0030] In S1, the signal event description word stream is formed by sorted header frames and member frames. The header frames and member frames form a one-to-many control logic. That is, the header frames and member frames with control constraints are combined to form a signal event description word group. This signal event description word group is specifically used to manage a batch of time-related and parameter-sharing signal events (such as a complete radar pulse train or a set of frequency hopping sequences).

[0031] The group header frame includes at least one of the following: a unique group identifier (group_id), the group's start absolute time (timestamp), the number of members in the group (member_count), the number of loops (loop_count), the interval between each loop (loop_interval), the target transmit channel identifier (target_tx_channel_id), and the target pipeline identifier (target_pipeline_id). The unique group identifier clarifies the group's usage nature, distinguishing between one-time dynamic groups (temporary groups for one-time use) and named manageable groups (persistent groups for long-term use), adapting to different signal generation scenario requirements. The group's start absolute time is used for precise timing synchronization, ensuring that each signal event is accurately triggered and output collaboratively at the specified time. The number of members in the group indicates the number of associated service signal parameters. The number of loops supports finite or infinite loops. The interval between each loop defines the loop period. The target transmit channel identifier specifies on which physical transmit channel the group should output on. The target pipeline identifier specifies which specific signal processing pipeline should perform the generation task within the specified target transmit channel. The pipeline is functionally divided into signal generation sub-units such as carrier, DDS (direct digital frequency synthesis), envelope, and modulation. In terms of hardware implementation, these signal generation sub-units are composed of DDS carrier generator, pulse envelope generator, and digital modulation IP cores such as FM (frequency modulation) / AM (amplitude modulation) / PSK (phase shift keying) / QAM (quadrature amplitude modulation).

[0032] Member frames include basic parameters (SED_Base) and signal generation type-specific parameters. The basic parameters belong to the base class and include at least one of the member relative offset (timestamp_offset) and signal generation type (signal_type). The signal generation type-specific parameters belong to the derived class and include service field parameters corresponding to the signal generation type, such as pulse modulation service fields, digital modulation service fields, analog modulation service fields, echo modulation service fields, arbitrary wave modulation service fields, etc. The member relative offset is used in group mode to multiplex a relative time offset relative to the start time of the group. There can be more than one signal generation type, used to instruct the signal generation hardware device how to interpret subsequent service fields. The signal generation type-specific parameters immediately follow the basic parameters. When signal_type is pulse modulation, it is followed by pulse service fields describing parameters such as pulse width and sweep bandwidth. When signal_type is digital modulation, it is followed by digital modulation service fields describing parameters such as modulation type (QPSK, 64QAM, etc.) and code rate. Other signal types follow the same pattern. This design allows developers to define a new signal_type enumeration value and the corresponding business field structure when a new signal type needs to be supported in the future, without having to modify the core parsing framework of the hardware.

[0033] Reference Figure 2 The flowchart illustrating the signal generation task and target signal type acquisition method includes the following steps: "Receiving the signal event description stream, parsing the signal event description stream frame by frame, acquiring the signal generation task in real time, and identifying the target signal type corresponding to the signal generation task": S11: Receive the header frame and member frames that have control constraints with the header frame in the signal event description word stream in sequence; S12: Based on the header frame and member frames that have control and constraint relationships with the header frame, construct the corresponding signal generation task and extract the configuration parameters of the signal generation task; S13: Parse the signal generation type from the member frame and use the signal generation type as the target signal type for the signal generation task.

[0034] In S11, within a signal event description word group, starting with the group header frame, member frames with control constraints related to the group header frame are arranged in ascending order of relative offset. Multiple signal event description word groups generated sequentially are globally sorted according to the absolute start time of the group. All sorted signal event description word groups are then sequentially organized in frames as the smallest unit to form a continuous signal event description word stream. (Refer to...) Figure 3The schematic diagram of the hybrid digital signal generation system shows that the upper-level processor outputs a sorted stream of signal event description words to the controller (also known as the task scheduler, such as the upper-level processor CPU, ARM or FPGA). When the controller receives the stream of signal event description words in units of frames, it first receives the header frame of one group of signal event description words, and then receives the member frames that have control and constraint relationships with the header frame. These frames are buffered in the task queue for subsequent parsing and allocation.

[0035] In S12, the header frame and member frames with control constraints related to it constitute a complete signal generation requirement. Based on this requirement, the controller constructs a signal generation task corresponding to the current waveform generation, channel simulation, or echo simulation scenario. It then parses and extracts all configuration parameters required for the signal generation task from the fields of the header frame and member frames. These configuration parameters include, but are not limited to: the target transmission channel determined by the target transmission channel identifier parsed from the frame structure; the target pipeline type (including digital modulation type and IQ playback type) determined by the target pipeline type identifier; the input source identifier for selecting the illumination signal source; the convolution kernel coefficients and related fixed-point format parameters for linear convolution operations; the modulation parameters for fine echo adjustment; the absolute trigger time parameters for controlling signal synchronization; and operating and timing control parameters such as waveform period, frame length, cycle enable flag, output gain, sampling rate configuration, and operating mode. The absolute trigger time is calculated by combining the reference timestamp, number of cycles, cycle interval, and timestamp offset according to a preset formula. The formula for calculating the absolute trigger time is as follows: t_abs=timestamp+k×loop_interval+timestamp_offset; In the formula, t_abs is the absolute trigger time; k is the current loop count, the initial value of k is 0, and k≤loop_count-1.

[0036] In S13, the signal generation type identifier is parsed from the member frame corresponding to the group header frame, and the signal generation type represented by the signal generation type identifier is determined as the target signal type of the current signal generation task. The signal generation task is then assigned to the heterogeneous processing pipeline resource pool or the digital echo coprocessor for execution based on the target signal type, and the target signal type is used as part of the signal generation task configuration parameters.

[0037] Target signal types include self-contained signals and dependent signals. Self-contained signals are generated without relying on any external input signals or external triggering events. All waveform parameters and control information are fully provided by the signal's own description information, allowing for independent waveform generation. This type of signal is diverse, lightweight in configuration, and exhibits the characteristics of being numerous yet simple. Typical applications include various independent communication signals, pulse signals, noise signals, and IQ playback data, which are directly generated by parametric digital modulation pipelines or IQ playback pipelines based on configuration parameters. Dependent signals, on the other hand, require an external input reference signal and undergo channel or echo simulation processing such as time delay adjustment, Doppler frequency offset modulation, amplitude attenuation, and linear convolution to form the final waveform. They cannot be generated independently of the input signal. This type of signal has a limited variety and complex processing flow, exhibiting the characteristics of being few yet complex. Typical applications include radar echo signals and multipath fading signals, which are typically generated by a dedicated digital echo coprocessor and related computing units performing complex digital transformations on the input illumination signal.

[0038] In S2, refer to Figure 4 The flowchart illustrating the self-contained IQ signal stream generation method includes the following steps: "Assigning the signal generation task to the heterogeneous processing pipeline resource pool, and having the matching pipelines within the heterogeneous processing pipeline resource pool generate the self-contained IQ signal stream according to the configuration parameters of the signal generation task": S21: Analyze the signal generation task to obtain the corresponding target transmission channel and target pipeline type; S22: In the heterogeneous processing pipeline resource pool, filter pipelines that belong to the target launch channel, are idle, and match the target pipeline type; S23: If a matching pipeline exists, the configuration parameters of the signal generation task are loaded into the matching pipeline, and the matching pipeline generates the corresponding self-contained IQ signal stream in real time. S24: If no matching pipeline exists, determine from the target launch channel whether there is an idle pipeline that supports reconstruction to the target pipeline type; S25: If there is an idle pipeline that supports reconfiguration, then perform mode reconfiguration on the idle pipeline, configure the reconfigured pipeline as the target pipeline type, load the configuration parameters of the signal generation task, and generate the corresponding self-contained IQ signal stream in real time based on the configuration parameters.

[0039] In S21-S25, the controller parses the current signal generation task and determines the target transmission channel and the required operating mode, i.e., the target pipeline type, from its configuration parameters. The target pipeline type includes one of digital modulation and IQ playback. When the target pipeline type is digital modulation, it will further determine which type of digital modulation it is. For example, Quadrature Phase Shift Keying (QPSK) is a subclass of digital modulation.

[0040] The heterogeneous processing pipeline resource pool includes digital modulation pipelines and IQ playback pipelines, with the number of pipelines N preferably ≥ 8. The digital modulation pipelines are used to execute signal generation tasks where the target pipeline type is digital modulation; the IQ playback pipelines are used to execute signal generation tasks where the target pipeline type is IQ playback. Therefore, in the heterogeneous processing pipeline resource pool, the system first searches for available pipelines that belong to the target transmission channel, are currently idle, and natively support the target pipeline type, based on the target transmit channel, pipeline status, and supported modes. This achieves precise matching between tasks and hardware resources. When a suitable pipeline is found, the controller writes all configuration parameters of the signal generation task into the effective register group of that pipeline. Under the constraints of a unified sampling clock and absolute trigger timing, the pipeline operates stably according to the target mode and parameters, generating and outputting the corresponding self-contained IQ signal stream in real time.

[0041] When no suitable pipeline is found through screening, the system continues to search for idle pipelines within the target transmit channel that support dynamic reconfiguration between different operating modes. Mode reconfiguration refers to switching an idle pipeline from its current operating mode to the target pipeline type required for the signal generation task, without interrupting the overall output of the channel or affecting the normal operation of other pipelines. Specifically, when a signal generation task with an IQ playback target pipeline type is required, the digital modulation pipeline is reconfigured to an IQ playback type; conversely, when a signal generation task with a digital modulation target pipeline type is required, the IQ playback pipeline is reconfigured to a digital modulation type. If a reconfigurable idle pipeline exists, the controller executes the pipeline dynamic reconfiguration process. After reconfiguration, the configuration parameters for the current signal generation task are loaded, ensuring the reconfigured pipeline operates stably according to the target mode and outputs a self-contained IQ signal stream that meets the task requirements in real time. Here, IQ signal refers to in-phase / quadrature baseband signal.

[0042] By adopting the above-mentioned design approach based on task parsing, pipeline screening, and dynamic mode reconstruction, the heterogeneous processing pipeline resource pool can accurately allocate and flexibly schedule resources according to the target transmission channel and target pipeline type of the signal generation task. When a matching pipeline exists, parameters can be directly loaded and self-contained IQ signal streams can be quickly output. When no directly matching resources exist, seamless switching of working modes can be completed through pipeline dynamic reconstruction. This ensures the real-time performance and timing accuracy of signal generation, while avoiding problems such as channel output interruption, waveform distortion, or phase shift. It significantly improves the utilization rate of hardware resources and the system's adaptability to multiple types of self-contained signals, making the entire signal generation system highly flexible, highly stable, and highly resource-efficient.

[0043] Reference Figure 5 The flowchart illustrating the method for determining whether a pipeline supporting reconfiguration exists, "From the target launch channel, determine whether there is an idle pipeline that supports reconfiguration to the target pipeline type," includes the following steps: S241: Determine whether the target pipeline type is a subtype of digital modulation type or an IQ playback type; if it is a subtype of digital modulation type, execute S242; if it is an IQ playback type, execute S245. S242: Determine whether the IQ playback type pipeline in the target transmission channel that is in an idle state supports reconstruction into a subtype; if it supports it, then execute S243; if it does not support it, then execute S244. S243: Determine that there is an idle pipeline that can be reconfigured into the target pipeline type; S244: Determined that there is no idle pipeline that can be reconstructed into the target pipeline type; S245: Identify the idle digital modulation type pipeline in the target transmit channel as an idle pipeline that can be reconfigured into the target pipeline type.

[0044] In S241-S245, when determining the reconfigurability of idle pipelines within the target transmit channel, a type-compatible hierarchical determination strategy is adopted. When the target pipeline type is a subtype of digital modulation mode, due to the differences in hardware circuits, modulation units, and signal processing paths among different IQ playback type pipelines, not all IQ playback type pipelines are compatible with all digital modulation subtypes. Therefore, it is necessary to check one by one whether the currently idle IQ playback type pipelines within the target transmit channel have the hardware capability and configuration permission to be reconfigured into that subtype. If there is an IQ playback type pipeline that meets the compatibility conditions, it is determined that there is a reconfigurable idle pipeline; otherwise, it is determined that there are no available reconfigurable resources. When the target pipeline type is IQ playback type, since IQ playback type only needs to implement baseband data reading and output, its functional logic is relatively general and simple. On the other hand, digital modulation type pipelines have complete data paths and control logic required for IQ playback in their architecture. Therefore, digital modulation type pipelines usually support dynamic switching to IQ playback type in their architecture. All digital modulation type pipelines in the channel that are in an idle state can be uniformly identified as available pipelines that can be reconstructed into IQ playback type.

[0045] Reference Figure 6 The flowchart illustrating the pattern refactoring method, which involves "refactoring the idle pipeline and configuring the refactored pipeline as the target pipeline type," includes the following steps: S251: Configure a shadow register set for storing configuration parameters for the active register set of the idle pipeline; S252: Load the runtime parameters adapted to the target pipeline type into the shadow register group of the idle pipeline; S253: At the mode switching boundary moment, the running parameters in the shadow register group are synchronously updated to the effective register group; S254: Based on the running parameters in the updated effective register group, reconstruct the idle pipeline to the target pipeline type.

[0046] In S251-S255, idle pipelines that meet the reconfiguration conditions are reconfigured. The core relies on the dual-buffered register architecture to achieve seamless switching. First, the configuration preparation work before reconfiguration is completed: for the idle pipeline to be reconfigured, based on its built-in dual-buffered register architecture, the effective register group and the shadow register group are divided. The shadow register group is designed to temporarily store the new mode configuration parameters. No additional register hardware is required. The configuration can be completed by the controller issuing register partitioning instructions. Then, the controller will accurately load the full set of operating parameters adapted to the target pipeline type, including waveform parameters, timing parameters, path control parameters, etc., into the shadow register group of the pipeline. At this time, the new parameters in the shadow register group are only temporarily stored and will not interfere with the original state of the pipeline, nor will they affect the normal operation of other pipelines in the channel, ensuring the safety and stability of the reconfiguration process.

[0047] After parameter preloading is complete, the system enters the safe triggering phase for mode switching. Accurately identifying the mode switching boundary moments is crucial for smooth reconfiguration. The controller receives real-time operating status signals from the pipeline to be reconfigured. During operation, the pipeline autonomously monitors and reports safe switching boundary nodes. These boundary moments encompass standardized timing nodes such as frame period boundaries, data block boundaries, and waveform period boundaries, representing a safe window with no data output conflicts and no signal distortion. Therefore, these are used as the mode switching boundary moments. Once the controller detects that the current clock has reached the mode switching boundary moment, it immediately issues an atomic switching command. Through a hardware double-buffered switching mechanism, the new operating parameters temporarily stored in the shadow register group are synchronously updated to the effective register group within a single clock cycle, achieving nanosecond-level ultra-fast switching throughout the process, with no parameter misalignment and no timing delay.

[0048] After the parameters are synchronized and updated, the idle pipeline immediately reconfigures its operating mode based on the new configuration in the effective register group, precisely switching to the target pipeline type to match hardware functionality with task requirements. This reconfiguration scheme relies on a double-buffered design of shadow registers and effective registers, combined with a timing-safe boundary triggering mechanism. It can complete single-pipeline mode switching without interrupting the overall output of the channel or affecting the execution of other tasks. Moreover, there is no imperceptible signal interruption during the entire reconfiguration process, and the switching of modes and parameters is perfectly aligned with the sampling boundaries, effectively avoiding waveform distortion, phase shift, and other problems. At the same time, it meets the engineering requirements of low latency and high stability of the system, significantly improving the resource utilization and task adaptability of the heterogeneous processing pipeline resource pool.

[0049] In S3, refer to Figure 7The flowchart illustrating the dependent IQ signal stream generation method includes the following steps: "Assigning the signal generation task to an appropriate digital echo coprocessor, which then performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate the dependent IQ signal stream." S31: Analyze the signal generation task and obtain the corresponding target transmission channel; S32: Assign the signal generation task to the digital echo coprocessor dedicated to the target transmission channel, and the digital echo coprocessor determines the matching input source according to the input source identifier in the configuration parameters; S33: Based on the convolution kernel parameters in the configuration parameters, perform linear convolution operation on the illumination signal output by the input source to generate a preliminary echo signal; S34: Based on the modulation parameters in the configuration parameters, the initial echo signal is modulated to generate the corresponding dependent IQ signal stream.

[0050] In S31-S34, a dedicated digital echo coprocessor is assigned to each transmit channel. When a signal generation task needs to be assigned to the digital echo coprocessor, the controller first parses the target transmit channel information in the task and schedules the task to the dedicated digital echo coprocessor bound to that channel. This ensures that the signal processing path and the transmit channel maintain the same clock source, fixed delay, and sample alignment, thereby achieving low-latency and high-consistency echo simulation. The digital echo coprocessor selects one of two input sources as the illumination signal source based on the input source identifier in the configuration parameters through an internal input selector. The illumination signal refers to the reference input signal used to simulate radar echoes, multipath fading, and other scenarios, serving as the basic input for generating dependent signals. The input sources include buffer playback sources and real-time loopback sources, which can be dynamically selected according to the configuration parameters of the signal generation task. The playback source is typically a DDR playback buffer. DDR stands for Double Data Rate memory. The waveform data from this input source comes from signal samples acquired by the ADC (Analog-to-Digital Converter) or generated locally, and is pre-stored in a DDR circular buffer. It can be read in blocks into the local FIFO (First-In-First-Out) via AXI-DMA (Advanced Extensible Interface-Direct Memory Access). The Out (First-In-First-Out) memory provides a constant throughput illumination signal for the digital echo coprocessor, suitable for echo simulation scenarios with long durations, complex templates, or offline signal acquisition. The real-time loopback source losslessly copies the signal from the digital node before the DAC (Digital-to-Analog Converter). The digital node before the DAC is the signal branch point in the digital baseband domain before the exponential-to-analog conversion. This input source feeds the real-time transmitted baseband signal back to the coprocessor via a low-latency bypass path. Through fixed cascading (register / aligned FIFO) and a co-source clock, it ensures sample consistency and a known constant delay with the main path. It can maintain natural synchronization with the dynamically generated transmitted signal, avoiding double storage and synchronization overhead, and guarantees complete synchronization with the main transmitted signal without phase shift or amplitude distortion. Both input sources can be dynamically selected through configuration parameters to meet the typical engineering requirements of long-sequence signal storage and real-time low-latency loopback.

[0051] The input source sends the illumination signal to the convolution unit. The convolution unit preferably supports a convolution length of no less than 4096 taps, enabling it to support channel impulse response convolution operations of at least order 4096. Internally, it employs a segmented accumulation pipeline structure, allowing it to break down long convolutions into multiple shorter convolutions for parallel operation and merging the results step-by-step. This ensures that the output data maintains a fixed and predictable latency, preventing jitter or uncontrollable delay issues that arise with changes in convolution length, thus guaranteeing the timing accuracy of echo simulation and channel simulation. Therefore, after acquiring the illumination signal, the convolution unit performs linear convolution operations on the signal according to the convolution kernel parameters configured in the parameters list. These kernel parameters include key parameters characterizing the channel impulse response, such as kernel coefficients, bit width, and fixed-point format, used to simulate channel characteristics such as multipath propagation, scattering, and clutter, thereby generating a preliminary echo signal. Subsequently, the adjustment unit of the digital echo coprocessor refines the initial echo signal according to the modulation parameters in the configuration parameters. These modulation parameters include time delay parameters, Doppler frequency offset parameters, and amplitude attenuation parameters, used to simulate physical characteristics such as target motion, range delay, and spatial fading, ultimately generating a dependent IQ signal stream that meets the scenario requirements. The entire processing flow is executed in real-time pipelined under a common clock. Input selection, convolution operations, and modulation adjustments are all uniformly driven by the configuration parameters, ensuring both the realism and flexibility of the echo simulation while achieving strict timing alignment with the transmission channel. This makes it suitable for complex dependent signal generation scenarios such as radar echoes, channel simulation, and interference simulation.

[0052] In S4, the absolute trigger time included in the configuration parameters of the signal generation task is used as the absolute trigger time of the corresponding IQ signal stream. The absolute trigger times of the self-contained IQ signal stream and the dependent IQ signal stream are obtained. The self-contained IQ signal stream and the dependent IQ signal stream with the same absolute trigger time are digitally merged to generate a composite IQ signal stream. This signal merging mechanism based on absolute trigger time enables precise synchronous fusion of multiple types of signals in time, ensuring the consistency of phase, amplitude, and time sequence of the composite signal, and meeting the needs of multi-dimensional signal simulation in complex scenarios. This digital combining operation is performed by a digital synthesis unit, which is essentially a multi-input vector adder tree. It sums all the complex input samples and outputs a single, composite IQ sample stream representing the result of superimposing all signals at the current moment. During the combining phase, the complex vector adder employs a programmable weight configuration and a saturation / limiting joint processing strategy. This strategy involves setting adjustable amplitude weighting coefficients for each input signal via software or configuration parameters during the superposition and combining of multiple complex IQ signals. This ensures that each signal participates in the superposition according to a preset ratio. Simultaneously, a numerical upper limit threshold is set for the superimposed output. When the result exceeds this threshold, automatic saturation or limiting processing is performed, clamping the output within the system's allowed dynamic range. This avoids data bit width overflow, waveform distortion, and amplitude anomalies caused by multi-signal superposition, ensuring the linearity, signal-to-noise ratio, and output stability of the composite IQ signal stream. This composite IQ signal stream is ultimately sent to a digital-to-analog converter (DAC) to be converted into an analog signal and then modulated onto the required carrier frequency.

[0053] To further ensure system performance and reliability, this solution features refined control capabilities in signal synchronization, input switching, signal combining, and parameter configuration. During the multi-path signal timing alignment stage, high-precision synchronization between signal paths is achieved, with a preferred time error of no more than ±2 nanoseconds and a preferred phase consistency of no more than ±1° within a specified frequency range, ensuring the timing accuracy and phase fidelity of the generated composite signal. In the input source selection stage of the digital echo coprocessor, the illumination signal supports dynamic switching between DDR playback sources and real-time loopback sources, with a preferred switching latency of no more than 1 millisecond, and no perceptible signal interruption during the switching process. In the signal combining stage of the digital synthesis unit, the system has a robust output overload protection mechanism. When the amplitude of the superimposed multi-signal exceeds a preset threshold, it automatically adjusts the weighting coefficients of each signal or initiates saturation limiting processing, and simultaneously records the number of saturation events to prevent data overflow and waveform distortion. Furthermore, the units and bit widths of all fixed-point arithmetic parameters in the system correspond one-to-one with the upstream signal description information (SED) field, eliminating the need for runtime unit conversion during parameter parsing and loading, effectively reducing processing latency and improving configuration reliability.

[0054] Reference Figure 3 This disclosure provides a hybrid digital signal generation system, which includes a controller 1, a heterogeneous processing pipeline resource pool 2, a digital echo coprocessor 3, and a digital synthesis unit 4; Controller 1 is used to receive signal event description word stream, parse the signal event description word stream in frames as the smallest unit, extract the signal generation task in real time, and identify the target signal type corresponding to the signal generation task. When the target signal type is a self-contained signal, the signal generation task is assigned to the matching pipeline within the heterogeneous processing pipeline resource pool 2; When the target signal type is a dependent signal, the signal generation task is assigned to the appropriate digital echo coprocessor 3. Heterogeneous processing pipeline resource pool 2 is used to generate a self-contained IQ signal stream according to the configuration parameters of the signal generation task through a matched pipeline; The digital echo coprocessor 3 is used to perform digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task, and generate a dependent IQ signal stream. Digital synthesis unit 4 is used to digitally combine parallel self-contained IQ signal streams and dependent IQ signal streams to generate composite IQ signal streams.

[0055] Furthermore, the heterogeneous processing pipeline resource pool 2 includes a digital modulation type pipeline 21 and an IQ playback type pipeline 22; The digital modulation type pipeline 21 is used to perform signal generation tasks with a target pipeline type of digital modulation. When a signal generation task with a target pipeline type of IQ playback is required, it is reconstructed to the IQ playback type. The IQ playback type pipeline 22 is used to perform signal generation tasks with the target pipeline type being IQ playback; When a signal generation task with a target pipeline type of digital modulation is required, it is reconstructed to the digital modulation type.

[0056] Furthermore, the digital echo coprocessor 3 includes an input selector 31, an input source 32, a convolution unit 33, and an adjustment unit 34; The input selector 31 is used to determine the matching input source 32 based on the input source 32 identifier in the configuration parameters of the signal generation task, and send the illumination signal output by the input source 32 to the convolution unit 33. Input source 32 is used to output the illumination signal; Convolutional unit 33 is used to perform linear convolution operation on the illumination signal based on the convolutional kernel parameters in the configuration parameters to generate a preliminary echo signal; The adjustment unit 34 is used to modulate the initial echo signal based on the modulation parameters in the configuration parameters to generate the corresponding dependent IQ signal stream.

[0057] Furthermore, the system also includes an upper-level processor 5; Upper-level processor 5 is used to generate and send signal event descriptor streams to controller 1.

[0058] This system adopts a heterogeneous processing pipeline resource pool and a digital echo coprocessor architecture. Compared with the traditional single signal generation architecture, this achieves precise adaptation and efficient utilization of hardware resources. By assigning signal generation tasks with different computational characteristics to specially optimized hardware units, it avoids the resource waste caused by using complex processors to perform simple tasks, and also eliminates the performance bottleneck caused by forcing simple processors to handle complex tasks. This ensures that hardware resources are always allocated on demand and operate efficiently. Simultaneously, this architecture can support high-density self-contained signal generation and high-fidelity dependent signal synthesis. The pipeline resource pool is responsible for multi-type, lightweight independent signal output, while the digital echo coprocessor focuses on complex echo simulation dependent on the input signal. This perfectly meets the needs of modern complex electromagnetic environments for multi-dimensional and multi-type signal simulation. Moreover, the digital echo coprocessor uses a full hardware pipeline to implement large-scale convolution and correlation operations, and its performance far exceeds that of equivalent functions implemented in general-purpose logic, meeting the most stringent real-time requirements.

[0059] This system decomposes the signal generation engine into a functionally orthogonal heterogeneous processing pipeline resource pool, a digital echo coprocessor, and a signal merging unit. Each sub-module can be designed, optimized, and verified independently, significantly reducing the overall system's design complexity and verification difficulty. The dedicated digital echo coprocessor uses a fully hardware pipeline to implement large-scale linear convolution and fine modulation operations, with performance far exceeding that of equivalent functions implemented with general logic. It can meet the most stringent real-time requirements and provides a solid guarantee for high-fidelity dependent signal generation.

[0060] Leveraging a dual-buffered register architecture and a pipeline dynamic reconfiguration mechanism triggered by safety boundaries, the heterogeneous processing pipeline resource pool can complete single-pipeline mode switching without interrupting channel output or affecting the execution of other tasks. The atomic switching of modes and parameters is perfectly aligned with the sampling boundaries, eliminating issues such as signal interruption, waveform distortion, or phase shift, further improving resource utilization and task adaptability. Simultaneously, through a signal merging mechanism driven by absolute trigger time, precise timing synchronization and fusion of self-contained IQ signal streams and dependent IQ signal streams can be achieved, ensuring the consistency of phase, amplitude, and timing of composite IQ signal streams, providing highly stable and reliable signal generation capabilities for complex electromagnetic scenario simulation.

[0061] The various variations and specific examples of the hybrid digital signal generation method provided above are also applicable to the hybrid digital signal generation system provided in this disclosure. Through the foregoing detailed description of the hybrid digital signal generation method, those skilled in the art can clearly understand the implementation method of the hybrid digital signal generation system. For the sake of brevity, they will not be described in detail here.

[0062] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0063] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the hybrid digital signal generation methods of the foregoing embodiments of this disclosure.

[0064] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0065] like Figure 8 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 8 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0066] like Figure 8 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0067] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 8 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0068] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the hybrid digital signal generation method of embodiments of this disclosure are performed.

[0069] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0070] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the hybrid digital signal generation methods described in the foregoing embodiments of the present disclosure are performed.

[0071] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0072] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0073] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0074] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0075] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0076] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0077] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0078] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0079] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for generating hybrid digital signals, characterized in that, include: Receive signal event description word stream, parse the signal event description word stream in frames as the smallest unit, obtain the signal generation task in real time, and identify the target signal type corresponding to the signal generation task; When the target signal type is a self-contained signal, the signal generation task is assigned to the heterogeneous processing pipeline resource pool, and the pipeline matched in the heterogeneous processing pipeline resource pool generates a self-contained IQ signal stream according to the configuration parameters of the signal generation task. When the target signal type is a dependent signal, the signal generation task is assigned to an appropriate digital echo coprocessor. The digital echo coprocessor performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate a dependent IQ signal stream. The parallel self-contained IQ signal stream and the dependent IQ signal stream are digitally combined to generate a composite IQ signal stream.

2. The hybrid digital signal generation method according to claim 1, characterized in that, The received signal event description word stream is parsed frame by frame to extract the signal generation task in real time and identify the target signal type corresponding to the signal generation task, including: The header frame and member frames that have control and constraint relationships with the header frame are received sequentially from the signal event description word stream. Based on the group header frame and the member frames that have control and constraint relationships with the group header frame, a corresponding signal generation task is constructed and the configuration parameters of the signal generation task are extracted. The signal generation type is parsed from the member frame and used as the target signal type for the signal generation task.

3. The hybrid digital signal generation method according to claim 1, characterized in that, The step of allocating the signal generation task to a heterogeneous processing pipeline resource pool, and having the matching pipelines within the heterogeneous processing pipeline resource pool generate a self-contained IQ signal stream according to the configuration parameters of the signal generation task, includes: Analyze the signal generation task to obtain the corresponding target transmission channel and target pipeline type; In the heterogeneous processing pipeline resource pool, pipelines that belong to the target launch channel, are idle, and match the target pipeline type are selected; If a matching pipeline exists, the configuration parameters of the signal generation task are loaded into the matching pipeline, and the matching pipeline generates the corresponding self-contained IQ signal stream in real time. If no matching pipeline exists, then determine from the target launch channel whether there is an idle pipeline that supports reconfiguration to the target pipeline type; If an idle pipeline that supports reconfiguration exists, the idle pipeline is reconfigured, the reconfigured pipeline is configured as the target pipeline type, and the configuration parameters of the signal generation task are loaded. Based on the configuration parameters, the corresponding self-contained IQ signal stream is generated in real time.

4. The hybrid digital signal generation method according to claim 3, characterized in that, The step of determining whether there is an idle pipeline in the target transmission channel that supports reconfiguration to the target pipeline type includes: If the target pipeline type is a subtype of digital modulation type, then determine whether the IQ playback type pipeline in the target transmit channel that is in an idle state supports reconstruction into the subtype; If supported, then it is determined that there exists an idle pipeline that can be reconstructed into the target pipeline type; If not supported, then it is determined that there is no idle pipeline that can be reconstructed into the target pipeline type; If the target pipeline type is IQ playback type, then the digital modulation type pipeline that is in an idle state in the target transmit channel is determined as an idle pipeline that supports reconstruction to the target pipeline type.

5. The hybrid digital signal generation method according to claim 3, characterized in that, The step of reconfiguring the idle pipeline and setting the reconfigured pipeline to the target pipeline type includes: Configure a shadow register group for pre-storing configuration parameters for the active register group of the idle pipeline; Load the runtime parameters adapted to the target pipeline type into the shadow register group of the idle pipeline; At the mode switching boundary moment, the running parameters in the shadow register group are synchronously updated to the effective register group; Based on the running parameters in the updated effective register group, the idle pipeline is reconstructed into the target pipeline type.

6. The hybrid digital signal generation method according to claim 1, characterized in that, The step of assigning the signal generation task to an appropriate digital echo coprocessor, wherein the digital echo coprocessor performs digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task to generate a dependent IQ signal stream, includes: Analyze the signal generation task to obtain the corresponding target transmission channel; The signal generation task is assigned to a dedicated digital echo coprocessor for the target transmission channel, and the digital echo coprocessor determines the matching input source based on the input source identifier in the configuration parameters. Based on the convolution kernel parameters in the configuration parameters, a linear convolution operation is performed on the illumination signal output by the input source to generate a preliminary echo signal; Based on the modulation parameters in the configuration parameters, the initial echo signal is modulated to generate a corresponding dependent IQ signal stream.

7. The hybrid digital signal generation method according to claim 1, characterized in that, The step of digitally combining parallel self-contained IQ signal streams and dependent IQ signal streams to generate a composite IQ signal stream includes: Obtain the absolute trigger times of the self-contained IQ signal stream and the dependent IQ signal stream; The self-contained IQ signal stream and the dependent IQ signal stream with the same absolute trigger time are digitally combined to generate a composite IQ signal stream.

8. A hybrid digital signal generation system, characterized in that, The system includes a controller, a heterogeneous processing pipeline resource pool, a digital echo coprocessor, and a digital synthesis unit. The controller is configured to receive a signal event description word stream, parse the signal event description word stream in frames as the smallest unit, extract the signal generation task in real time, and identify the target signal type corresponding to the signal generation task. When the target signal type is a self-contained signal, the signal generation task is assigned to a matching pipeline within the heterogeneous processing pipeline resource pool; When the target signal type is a dependent signal, the signal generation task is assigned to an appropriate digital echo coprocessor. The heterogeneous processing pipeline resource pool is used to generate a self-contained IQ signal stream according to the configuration parameters of the signal generation task through a matched pipeline. The digital echo coprocessor is used to perform digital transformation processing on the selected irradiation signal according to the configuration parameters of the signal generation task, and generate a dependent IQ signal stream. The digital synthesis unit is used to digitally combine parallel self-contained IQ signal streams and dependent IQ signal streams to generate a composite IQ signal stream.

9. The hybrid digital signal generation system according to claim 8, characterized in that, The heterogeneous processing pipeline resource pool includes digital modulation type pipelines and IQ playback type pipelines; The digital modulation type pipeline is used to perform signal generation tasks where the target pipeline type is digital modulation; When a signal generation task of the target pipeline type IQ playback needs to be executed, it is reconstructed to the IQ playback type. The IQ playback type pipeline is used to execute signal generation tasks with the target pipeline type being IQ playback; When a signal generation task of the target pipeline type of digital modulation needs to be executed, it is reconstructed to the digital modulation type.

10. The hybrid digital signal generation system according to claim 8, characterized in that, The digital echo coprocessor includes an input selector, an input source, a convolution unit, and an adjustment unit; The input selector is used to determine a matching input source based on the input source identifier in the configuration parameters of the signal generation task, and send the illumination signal output by the input source to the convolution unit. The input source is used to output an illumination signal; The convolutional unit is used to perform a linear convolution operation on the illumination signal based on the convolutional kernel parameters in the configuration parameters to generate a preliminary echo signal; The adjustment unit is used to modulate the initial echo signal based on the modulation parameters in the configuration parameters to generate a corresponding dependent IQ signal stream.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the mixed digital signal generation method according to any one of claims 1-7.

12. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the hybrid digital signal generation method according to any one of claims 1-7.

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