Verification environment processing method and device, computer device, chip and chip module

Abstract

The application relates to a verification environment processing method and device, computer equipment, a chip and a chip module. The method comprises the following steps: determining a verification level of a verification case corresponding to a to-be-processed verification environment; determining first verification waveform data of the to-be-processed verification environment at the verification level and second verification waveform data of a historical verification environment corresponding to the to-be-processed verification environment at the verification level; determining a verification environment processing instruction corresponding to the to-be-processed verification environment according to the first verification waveform data and the second verification waveform data; and performing corresponding processing on the to-be-processed verification environment according to the verification environment processing instruction to obtain a processed verification environment corresponding to the to-be-processed verification environment. The method can improve the reliability of the verification environment.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a verification environment processing method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product. Background Technology

[0002] In chip post-simulation verification scenarios, it is crucial to effectively adapt the verification environment in order to ensure the effective execution of verification test cases.

[0003] In traditional techniques, the adaptation of the verification environment is usually done manually; however, the results of this manual adaptation lack a standardized verification mechanism, resulting in low reliability of the verification environment. Summary of the Invention

[0004] Therefore, it is necessary to provide a verification environment processing method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product that can improve the reliability of the verification environment in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a method for processing a verification environment, including:

[0006] Determine the verification level of the verification cases corresponding to the verification environment to be processed;

[0007] The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined.

[0008] Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined;

[0009] According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

[0010] In one embodiment, determining the first verification waveform data of the verification environment to be processed at the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed at the verification level, includes:

[0011] Acquire the first initial verification waveform data of the verification environment to be processed, and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed;

[0012] According to the verification level, numerical extraction is performed on the first initial verification waveform data to obtain the first verification waveform data of the verification environment to be processed under the verification level, and numerical extraction is performed on the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0013] In one embodiment, acquiring the first initial verification waveform data of the verification environment to be processed, and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed, includes:

[0014] From the verification cases, target verification cases that satisfy the preset verification level are determined;

[0015] The target verification test case is run in the verification environment to be processed to obtain the first initial verification waveform data of the verification environment to be processed, and the target verification test case is run in the historical verification environment to obtain the second initial verification waveform data of the historical verification environment.

[0016] In one embodiment, determining the verification level of the verification test case corresponding to the verification environment to be processed includes:

[0017] The top-level of the verification test cases corresponding to the verification environment to be processed is independently compiled to obtain an independent compilation result; the independent compilation result is used to represent the verification level index under the top-level;

[0018] The verification test cases are integrated into the verification environment to be processed to obtain the target verification environment, and the target verification environment is incrementally compiled to obtain the incremental compilation result.

[0019] Based on the incremental compilation results, the target verification level index corresponding to the verification test case is determined from the verification level index;

[0020] The verification level of the verification case is determined based on the target verification level index.

[0021] In one embodiment, determining the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data includes:

[0022] A consistency comparison process is performed on the first verification waveform data and the second verification waveform data to obtain a consistency comparison result.

[0023] Based on the consistency comparison results, the verification environment processing instructions corresponding to the verification environment to be processed are determined.

[0024] In one embodiment, before determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result, the method further includes:

[0025] The consistency comparison results are deduplicated to obtain the deduplicated consistency comparison results.

[0026] The step of determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result includes:

[0027] Based on the consistency comparison results after deduplication, the verification environment processing instructions corresponding to the verification environment to be processed are determined.

[0028] Secondly, this application also provides a verification environment processing apparatus, comprising:

[0029] The hierarchy determination module is used to determine the verification hierarchy of the verification cases corresponding to the verification environment to be processed;

[0030] The data determination module is used to determine the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0031] The instruction determination module is used to determine the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data.

[0032] The environment processing module is used to process the verification environment to be processed according to the verification environment processing instructions, so as to obtain the processed verification environment corresponding to the verification environment to be processed.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0034] Determine the verification level of the verification cases corresponding to the verification environment to be processed;

[0035] The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined.

[0036] Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined;

[0037] According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

[0038] Fourthly, this application also provides a chip, including a processor and a communication interface, wherein the processor is configured to cause the chip to perform:

[0039] Determine the verification level of the verification cases corresponding to the verification environment to be processed;

[0040] The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined.

[0041] Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined;

[0042] According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

[0043] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0044] The power module is used to provide power to the chip module;

[0045] The storage module is used to store data and instructions;

[0046] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0047] The chip is used to perform the steps of the method provided in the first aspect above.

[0048] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0049] Determine the verification level of the verification cases corresponding to the verification environment to be processed;

[0050] The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined.

[0051] Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined;

[0052] According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

[0053] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0054] Determine the verification level of the verification cases corresponding to the verification environment to be processed;

[0055] The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined.

[0056] Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined;

[0057] According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

[0058] The aforementioned verification environment processing method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product first determine the verification level of the verification test case corresponding to the verification environment to be processed, then determine the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level. Next, based on the first and second verification waveform data, determine the verification environment processing instruction corresponding to the verification environment to be processed. Finally, according to the verification environment processing instruction, perform corresponding processing on the verification environment to be processed to obtain the processed verification environment corresponding to the verification environment to be processed. In this way, when adapting the verification environment, the verification level of the verification test cases corresponding to the verification environment to be processed is clearly defined, thereby ensuring the dimensional consistency of the verification waveform data comparison. Then, the first verification waveform data of the environment to be processed is accurately compared with the second verification waveform data of the historical verification environment. Based on the differences in the verification waveform data, the deviation of the environment parameters or logical defects of the verification environment to be processed can be accurately located, thereby generating targeted verification environment processing instructions. The environment is then calibrated or optimized according to the instructions, thereby eliminating potential verification vulnerabilities in the verification environment to be processed. This ensures that the processed verification environment can have the same verification capabilities and accuracy as the historical verification environment, which is conducive to improving the reliability of the verification environment. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a flowchart illustrating the verification of an environmental processing method in one embodiment;

[0061] Figure 2 This is a flowchart illustrating the verification of the environmental processing method in another embodiment;

[0062] Figure 3 This is a schematic diagram illustrating a rapid solution for environmental compatibility issues caused by code synthesis optimization in one embodiment.

[0063] Figure 4 This is a structural block diagram of the verification environment processing device in one embodiment;

[0064] Figure 5 This is an internal structural diagram of a computer device in one embodiment;

[0065] Figure 6 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0067] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0068] Currently, all chips inevitably undergo iterations and updates to the verification environment during the R&D process. For example, the process evolves from describing hardware logic using Verilog (a hardware description language) as a behavioral language to converting Verilog code into a gate-level netlist. The synthesis + PR (Physical Implementation / Place and Route) methods used in this process are primarily supported by EDA (Electronic Design Automation) vendor tools. At this point, the design implementations derived from these tools all follow the same underlying logic, which is difficult to define or predict because each chip's manufacturing process, area, and design implementation differ. Consequently, the Verilog code is presented in an unpredictable way on the gate-level netlist, which is very unfriendly to verification. Therefore, whether there is a more robust way to make verification compatible with the inevitable changes made to the code by these tools and to better support the feasibility of verification has become a key issue.

[0069] The iterated verification environment is a gate-level netlist that has undergone synthesis and PR. Its hierarchical structure and signal names differ fundamentally from the pre-iteration verification environment. Directly porting verification test cases from the pre-iteration environment to the unprocessed post-iteration environment will result in issues such as unrecognizable hierarchies and failed signal acquisition, leading to direct test case errors. Therefore, effectively adapting the verification environment is crucial to ensuring the effective execution of verification test cases. Traditional techniques typically involve manual adaptation; however, this manual adaptation lacks a standardized verification mechanism, resulting in low reliability. The verification environment processing in this method involves generating targeted adjustment instructions based on a consistency comparison of waveforms between the verification environment to be processed (e.g., the post-simulation environment) and the historical verification environment (e.g., the pre-simulation environment) at the same verification level. This standardized adaptation operation eliminates the hierarchical and signal differences between the two environments, ensuring that verification test cases can be effectively executed in the corresponding post-processed verification environment, thus improving the reliability of the verification environment.

[0070] In one exemplary embodiment, such as Figure 1As shown, a verification environment processing method is provided. This embodiment illustrates the application of this method to a server. It is understood that this method can also be applied to terminals, systems including terminals and servers, and is implemented through interaction between the terminal and server. It can also be applied to communication equipment, terminal equipment, base stations, network-side equipment, chips, and chip modules. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, and tablets; the server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. In this embodiment, the method includes the following steps:

[0071] Step S101: Determine the verification level of the verification cases corresponding to the verification environment to be processed.

[0072] The verification environment to be processed refers to the target verification environment that needs to be adapted and optimized for the needs of the Design Under Test (DUT). In practical scenarios, the verification environment to be processed can refer to the post-simulation verification environment.

[0073] In this context, a verification test case refers to a test script used to verify the functionality and timing correctness of the object under test. In practical scenarios, verification test cases can refer to post-simulation test cases.

[0074] The verification level refers to the internal RTL (Register Transfer Level) range of the object under test that the verification test case actually accesses, rather than the full level of the DUT.

[0075] For example, the server selects the verification cases corresponding to the current verification environment from the verification cases of the historical verification environments corresponding to the current verification environment; then, it obtains the code text of the verification cases corresponding to the current verification environment, and extracts the syntactic features (such as the hierarchical path fragments, signal call keywords, and code structure of the stimulus / verification logic that appear explicitly in the verification cases) and semantic features (such as the functional tags of the verification cases and the verification coverage targets) corresponding to the code text, all of which are used as the text features corresponding to the code text; next, it obtains the hierarchical tree of the object under test corresponding to the current verification environment, and extracts the hierarchical attribute features (such as the hierarchical depth, module function type, and port signal type) corresponding to the hierarchical tree; then, it encodes the text features using a text encoder and the hierarchical attribute features using a graph structure encoder to obtain the case feature vector and the hierarchical feature vector corresponding to the current verification environment, and fuses the case feature vector and the hierarchical feature vector to obtain the fused feature vector corresponding to the current verification environment; finally, it inputs the fused feature vector into the trained verification level prediction model to obtain the verification level of the verification cases corresponding to the current verification environment.

[0076] Step S102: Determine the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0077] Among them, the first verification waveform data refers to the waveform data collected after the object under test is simulated in the verification environment within the verification level.

[0078] In this context, the historical verification environment refers to a benchmark verification environment that, along with the verification environment to be processed, targets the same design under test (DUT), achieves the same verification objective, and whose verification results are reliable. In practical scenarios, the historical verification environment can refer to the previous simulation verification environment. It should be noted that the verification environment to be processed can also refer to the second, third, or even Nth version of the post-simulation verification environment generated due to DUT netlist iteration, environment parameter optimization, etc. When the verification environment to be processed refers to the second version of the post-simulation verification environment, the historical verification environment corresponding to it is the post-simulation verification environment whose previous verification results are reliable (e.g., the historical verification environment of the second version verification environment is the first version verification environment, and the historical verification environment of the third version verification environment is the second version verification environment).

[0079] The second verification waveform data refers to the waveform data collected after simulating the object under test within the verification level of the historical verification environment. It should be noted that the verification level and the object under test correspond to the first and second verification waveform data.

[0080] For example, the server extracts the input stimulus parameters (such as signal timing, data values, reset trigger conditions, and clock frequency) of the verification test cases in the verification environment to be processed, and calibrates the input stimulus parameters of the historical verification environment to be completely consistent with the verification environment to be processed; based on the calibrated unified input stimulus parameters, simulations are performed on the verification environment to be processed and the historical verification environment corresponding to the verification environment to be processed, respectively, to obtain the simulation results of the verification environment to be processed and the historical verification environment; then, according to unified signal acquisition rules (such as only acquiring module input / output signals and key register signals within the verification level), the first verification waveform data of the verification environment to be processed at the verification level is extracted from the simulation results of the verification environment to be processed, and the second verification waveform data of the historical verification environment at the verification level is extracted from the simulation results of the historical verification environment.

[0081] Step S103: Based on the first verification waveform data and the second verification waveform data, determine the verification environment processing instruction corresponding to the verification environment to be processed.

[0082] Among them, the verification environment processing instructions refer to the instructions that perform standardized adaptation operations on the verification environment to be processed.

[0083] For example, the server inputs the first verification waveform data and the second verification waveform data into the feature extraction model to obtain the feature vectors of the first verification waveform data and the second verification waveform data, respectively. Then, the feature vectors of the first verification waveform data and the second verification waveform data are input into the trained verification environment processing instruction prediction model to obtain the predicted probability of the verification environment to be processed under each preset verification environment processing instruction. Then, the preset verification environment processing instruction with the highest predicted probability is selected from each preset verification environment processing instruction and used as the verification environment processing instruction corresponding to the verification environment to be processed.

[0084] Step S104: According to the verification environment processing instructions, perform corresponding processing on the verification environment to be processed to obtain the processed verification environment corresponding to the verification environment to be processed.

[0085] The post-processing verification environment refers to the verification environment obtained after executing all the adjustment operations in the verification environment processing instructions on the verification environment to be processed.

[0086] For example, the server extracts the following from the verification environment processing instructions according to the instruction type classification rules: hierarchical path mapping adjustment instructions (such as modifying the hierarchical path statement for accessing the DUT in the verification test case, or adding path mapping rules in the environment configuration file so that the test case can recognize the new level of the DUT in the environment to be processed), signal name binding adjustment instructions (such as adding statements in the signal acquisition script, or establishing the correspondence between the old and new signal names in the waveform tool configuration to solve the acquisition failure problem caused by the signal name change), and simulation parameter calibration adjustment instructions (such as updating the timing file path, clock cycle parameter, and netlist loading path in the simulation startup script to ensure that the simulation parameters are consistent with the DUT in the environment to be processed). The process involves several steps: first, matching the DUT version to the processing environment; and second, adjusting redundant signal filtering instructions (e.g., modifying the waveform acquisition configuration file, adding path filtering rules for the verification level, shielding redundant signals outside the level, and reducing waveform data volume). Then, following the hierarchical path mapping adjustment instructions, signal name binding adjustment instructions, simulation parameter calibration adjustment instructions, and redundant signal filtering adjustment instructions, the processing environment is adjusted in these ways to obtain the post-processed verification environment. Finally, the post-processed verification environment is used to simulate the verification test cases, yielding the simulation results.

[0087] In the above verification environment processing method, the verification level of the verification test cases corresponding to the verification environment to be processed is first determined. Then, the first verification waveform data of the verification environment to be processed under the verification level and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level are determined. Next, based on the first and second verification waveform data, the verification environment processing instructions corresponding to the verification environment to be processed are determined. Finally, the verification environment to be processed is processed according to the verification environment processing instructions to obtain the processed verification environment. In this way, when adapting the verification environment, by clarifying the verification level of the verification test cases corresponding to the verification environment to be processed, the dimensional consistency of the verification waveform data comparison is ensured. Then, the first verification waveform data of the verification environment to be processed is accurately compared with the second verification waveform data of the historical verification environment. Based on the differences in the verification waveform data, the deviation of the environment parameters or logical defects of the verification environment to be processed can be accurately located, thereby generating targeted verification environment processing instructions. The environment is calibrated or optimized according to the instructions, thereby eliminating potential verification vulnerabilities in the verification environment to be processed. This ensures that the processed verification environment has the same verification capabilities and accuracy as the historical verification environment, which is conducive to improving the reliability of the verification environment.

[0088] In an exemplary embodiment, step S102, which determines the first verification waveform data of the verification environment to be processed at the verification level and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed at the verification level, specifically includes the following: obtaining the first initial verification waveform data of the verification environment to be processed and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed; extracting values ​​from the first initial verification waveform data according to the verification level to obtain the first verification waveform data of the verification environment to be processed at the verification level, and extracting values ​​from the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed at the verification level.

[0089] The first initial verification waveform data refers to the unfiltered raw waveform data collected after performing a full simulation on the design under test in the verification environment to be processed.

[0090] The second initial verification waveform data refers to the unfiltered raw waveform data collected after performing a full simulation on the design under test in a historical verification environment.

[0091] Numerical extraction refers to a targeted data extraction operation performed on the initial waveform data, using the determined verification level as the filtering boundary.

[0092] For example, the server obtains the first initial verification waveform data of the verification environment to be processed, and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed; then, it determines the hierarchical path corresponding to the verification level from a preset verification level path list (this hierarchical path must match the DUT hierarchical structure of the verification environment to be processed and the historical verification environment); then, according to the hierarchical path corresponding to the verification level, it uses a unified signal filtering rule to extract values ​​from the first initial verification waveform data to obtain the first verification waveform data of the verification environment to be processed under the verification level, and extracts values ​​from the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0093] In this embodiment, by first acquiring the full initial waveform and then extracting directional values ​​based on the verification level in a step-by-step manner, the integrity of the original waveform data is ensured, and waveform information strongly related to the verification target is accurately selected. This effectively eliminates redundant signal data outside the verification level in the full waveform, providing reliable data support for the subsequent generation of accurate verification environment processing instructions.

[0094] In an exemplary embodiment, obtaining the first initial verification waveform data of the verification environment to be processed and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed specifically includes the following: determining the target verification test case that meets the preset verification level from the verification test cases; running the target verification test case in the verification environment to be processed to obtain the first initial verification waveform data of the verification environment to be processed, and running the target verification test case in the historical verification environment to obtain the second initial verification waveform data of the historical verification environment.

[0095] Among them, the preset verification level refers to the verification level of the hierarchical structure of the verification test cases covering the object under test, such as the chip level.

[0096] Among them, the target verification test case, also known as the smoke test case, refers to the chip-level full verification test case that covers all level paths of the preset verification level.

[0097] For example, the server obtains a list of hierarchical paths of the object under test (DUT) based on its complete RTL design architecture; and determines a preset verification level based on the list of hierarchical paths and the verification level of the verification test cases, according to the principle of full hierarchical coverage; then, it determines the target verification test cases that satisfy the preset verification level from the verification test cases; next, it runs the target verification test cases in the verification environment to be processed according to preset simulation parameters (including clock frequency, reset trigger timing, sampling time step, waveform output format, etc.) to obtain the first initial verification waveform data of the verification environment to be processed, and runs the target verification test cases in the historical verification environment according to the same preset simulation parameters to obtain the second initial verification waveform data of the historical verification environment.

[0098] In this embodiment, by filtering out matching target verification test cases through preset verification levels, it is possible to ensure that the test cases of subsequent simulation focus on the core functional modules of the chip, avoid invalid simulation of non-target level test cases, greatly reduce simulation resource consumption and time cost, and provide high-quality and high-matching data support for subsequent numerical extraction and waveform consistency analysis based on verification levels.

[0099] In an exemplary embodiment, step S101, determining the verification level of the verification test case corresponding to the verification environment to be processed, specifically includes the following: independently compiling the top-level of the verification test case corresponding to the verification environment to be processed to obtain an independent compilation result; the independent compilation result is used to represent the verification level index under the top-level; integrating the verification test case into the verification environment to be processed to obtain the target verification environment, and performing incremental compilation on the target verification environment to obtain an incremental compilation result; determining the target verification level index corresponding to the verification test case from the verification level index based on the incremental compilation result; and determining the verification level of the verification test case based on the target verification level index.

[0100] The top-level unit refers to the top-level RTL design unit that matches the verification level (module level / system level / chip level) of the verification test case, specified by the xrun (Xcelium Parallel Simulator, a simulator execution command) tool's exclusive option.

[0101] Independent compilation refers to the operation of compiling only the top-level design code.

[0102] The independent compilation result is used to represent the verification level index under the top level.

[0103] Among them, the verification level index refers to the level index of the full level path generated independently through the top level.

[0104] The target verification environment refers to the complete verification environment that can be executed and simulated after the code, stimulus logic, and collection rules of the verification test cases are fully integrated into the verification environment to be processed.

[0105] Incremental compilation refers to the operation of compiling only the code and related logic of newly added verification test cases, based on the independent compilation of the top-level layer.

[0106] The incremental compilation result refers to the set of binding information between the verification test cases and the verification level output after incremental compilation.

[0107] Among them, the target verification level index refers to the level index that is selected based on the incremental compilation results and completely matches the actual access path of the verification test case.

[0108] For example, the server uses xrun's msie (Module Symbol Interface Extraction) function to independently compile the top-level code of the verification test cases corresponding to the verification environment to be processed, obtaining the verification level index under the top level as the independent compilation result. Then, the verification test cases are deployed to the specified directory of the verification environment to be processed to obtain the target verification environment. In the target verification environment, the test case code and associated interface logic corresponding to the verification test cases are incrementally compiled to obtain the incremental compilation result. Then, the hierarchical path accessed by the verification test cases is extracted from the incremental compilation result, and the target verification level index corresponding to the verification test cases is selected from the verification level index based on the hierarchical path accessed by the verification test cases. Finally, the verification level corresponding to the target verification level index is used as the verification level of the verification test cases.

[0109] In this embodiment, by independently compiling the top-level layer to pre-build a full verification level index, and then combining incremental compilation to process only verification cases and related logic, and accurately matching the target verification level index from the level index based on the incremental compilation results, the actual coverage level of the verification cases can be objectively determined, providing an accurate and reliable basis for level determination for subsequent waveform data acquisition.

[0110] In an exemplary embodiment, step S103, which determines the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data, specifically includes the following: performing a consistency comparison process on the first verification waveform data and the second verification waveform data to obtain a consistency comparison result; and determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result.

[0111] The consistency comparison result is used to represent the quantitative analysis report output after comparing the logic state and timing features of the same signal at the same level in the first verification waveform data and the second verification waveform data point by point. It includes key information such as the signal matching status, deviation type, deviation location and deviation ratio between the first verification waveform data and the second verification waveform data.

[0112] For example, the server performs waveform alignment processing based on timestamps and common signal sets on the first and second verification waveform data to obtain preprocessed first and second verification waveform data. Then, it performs logical consistency comparison processing and timing consistency comparison processing on the preprocessed first and second verification waveform data respectively to obtain logical consistency comparison results and timing consistency comparison results, both of which are used as consistency comparison results. Then, based on the consistency comparison results, it queries the preset correspondence between consistency comparison results and verification environment processing instructions to obtain the verification environment processing instructions corresponding to the verification environment to be processed.

[0113] In this embodiment, by comparing the consistency of the first verification waveform data and the second verification waveform data, the differences between the verification environment to be processed and the historical verification environment in terms of signal logic state and timing characteristics can be accurately identified, and the functional and timing compliance of the environment to be processed can be quantitatively evaluated, which is conducive to improving the efficiency and reliability of verification environment iteration.

[0114] In an exemplary embodiment, before determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result, the following steps are specifically included: performing deduplication processing on the consistency comparison result to obtain a deduplicated consistency comparison result.

[0115] Based on the consistency comparison results, the verification environment processing instructions corresponding to the verification environment to be processed are determined, specifically including the following: Based on the deduplicated consistency comparison results, the verification environment processing instructions corresponding to the verification environment to be processed are determined.

[0116] The consistency comparison result after deduplication refers to the consistency comparison result after deduplication processing.

[0117] For example, the server identifies duplicate (same-origin or related) consistency comparison results. Then, based on the duplication type of the duplicate consistency comparison results, it determines the deduplication method corresponding to each duplicate result. For instance, for duplicates triggered by the same origin, it retains the record with the most obvious deviation characteristics (such as the earliest timestamp or the largest deviation value) and marks the rest as redundant. For nested duplicates, it retains the deviation record of the lowest-level module (for more accurate root cause localization) and merges the association information of the upper-level module into that record. For type-derived duplicates, it retains the main deviation type record (e.g., if logical deviation is the cause and temporal deviation is the effect, it retains the logical deviation record and adds a description of the temporal impact). For redundant duplicates related to tools, it merges the information of the two records and deletes duplicate fields. Then, according to the deduplication method corresponding to the duplicate consistency comparison results, it performs corresponding deduplication processing on the duplicate consistency comparison results to obtain the deduplicated consistency comparison results. Next, based on the deduplicated consistency comparison results, it queries the pre-defined correspondence between the consistency comparison results and the verification environment processing instructions to obtain the verification environment processing instructions corresponding to the verification environment to be processed.

[0118] In this embodiment, by deduplicating the consistency comparison results, duplicate deviation records caused by factors such as signal correlation and hierarchical nesting during waveform comparison can be filtered out, avoiding interference from redundant information on instruction judgment, ensuring the simplicity and accuracy of the consistency comparison results, and improving the efficiency of verification environment problem location and optimization.

[0119] In one exemplary embodiment, such as Figure 2 As shown, another method for processing the verification environment is provided. Taking the application of this method to a server as an example, the specific steps include:

[0120] Step S201: Perform independent compilation processing on the top level of the verification test cases corresponding to the verification environment to be processed, and obtain independent compilation results; the independent compilation results are used to represent the verification level index under the top level.

[0121] Step S202: Integrate the verification test cases into the verification environment to be processed to obtain the target verification environment, and perform incremental compilation processing on the target verification environment to obtain the incremental compilation result.

[0122] Step S203: Based on the incremental compilation results, determine the target verification level index corresponding to the verification test case from the verification level index.

[0123] Step S204: Determine the verification level of the verification test case based on the target verification level index.

[0124] Step S205: From the verification cases, determine the target verification cases whose verification level meets the preset verification level.

[0125] Step S206: Run the target verification test case in the verification environment to be processed to obtain the first initial verification waveform data of the verification environment to be processed, and run the target verification test case in the historical verification environment to obtain the second initial verification waveform data of the historical verification environment.

[0126] Step S207: Based on the verification level, numerical extraction is performed on the first initial verification waveform data to obtain the first verification waveform data of the verification environment to be processed under the verification level, and numerical extraction is performed on the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0127] Step S208: Perform a consistency comparison process on the first verification waveform data and the second verification waveform data to obtain the consistency comparison result.

[0128] Step S209: Deduplication is performed on the consistency comparison results to obtain the deduplicated consistency comparison results.

[0129] Step S210: Based on the consistency comparison results after deduplication, determine the verification environment processing instruction corresponding to the verification environment to be processed.

[0130] Step S211: According to the verification environment processing instructions, perform corresponding processing on the verification environment to be processed to obtain the processed verification environment corresponding to the verification environment to be processed.

[0131] In the above-described verification environment processing method, when adapting the verification environment, the verification level of the verification test cases corresponding to the verification environment to be processed is clearly defined to ensure the dimensional consistency of the verification waveform data comparison. Then, the first verification waveform data of the environment to be processed is accurately compared with the second verification waveform data of the historical verification environment. Based on the differences in the verification waveform data, the deviation of the environment parameters or logical defects of the verification environment to be processed can be accurately located, thereby generating targeted verification environment processing instructions. The environment is calibrated or optimized according to the instructions, thereby eliminating potential verification vulnerabilities in the verification environment to be processed. This ensures that the processed verification environment can have the same verification capabilities and accuracy as the historical verification environment, which is conducive to improving the reliability of the verification environment.

[0132] In an exemplary embodiment, to more clearly illustrate the verification environment processing method provided in this application, the following specific embodiment will be used to describe the verification environment processing method in detail. In one embodiment, as follows... Figure 3 As shown, this application also provides a rapid solution to environmental compatibility issues caused by code synthesis and optimization in post-processing. Specifically, it includes the following:

[0133] 1. Select the target use cases (use cases) that need to be verified in the post-simulation test case pool from the pre-simulation test case pool, and clarify the scope of use cases for this post-simulation regression.

[0134] 2. For each selected test case to be simulated, use xrun's msie function to generate an msie_href.txt file (a type of txt file). (This function will compile an independent DUT library (Design Under Test Library) for a specified RTL top level, and then perform incremental compilation with the verification environment. During the incremental process, it can identify which contents of the DUT library are used in the environment and extract the output) (The content of this txt file is all the RTL levels used by the test case), thereby identifying and extracting all the RTL level paths actually used by the test case.

[0135] 3. Prepare pre_sim.fsdb (pre-simulation waveform file): Generate the corresponding verification waveform in the existing pre-simulation verification environment (this waveform contains the specific values ​​of all RTL level signals at the simulation time).

[0136] 4. Prepare post_sim.fsdb (post-simulation waveform file): After setting up the post-simulation basic environment, debug the smoke test cases and generate the corresponding verification waveforms. (This process can compare not only the pre-simulation and post-simulation stages, but also the post-simulation and the second version of the post-simulation, and even subsequent versions of different netlist code.) Prepare v2_post_sim.fsdb (second version of the post-simulation waveform file): This supports comparison of post-simulation waveforms between subsequent versions of different netlist.

[0137] 5. Extract values ​​from all RTL levels obtained in step 2 sequentially within the waveform files of steps 3 and 4. That is, read each RTL level in msie_href.txt sequentially and use the fsdbreport (a waveform file analysis report tool) tool to extract the corresponding signal values ​​at the simulation time from pre_sim.fsdb, post_sim.fsdb (and v2_post_sim.fsdb). The values ​​of any level signal at any simulation time can be printed out from the waveform.

[0138] 6. The two values ​​obtained in step 5 can be used for consistency comparison (Verilog memory has a four-state structure) to generate a Pre_vs_post (pre-simulation vs. post-simulation comparison) report. Common inconsistency scenarios include:

[0139] (1) Consistency comparison result 1: The signal cannot be found in the post-simulated waveform (because the signal is replaced by the comprehensive equivalence).

[0140] (2) Consistency comparison result 2: The signal value obtained in the post-simulated waveform is z (because the signal is optimized by logic).

[0141] (3) Consistency comparison result 3: The signal value obtained in the post-simulated waveform is inconsistent with that in the pre-simulated waveform (the reason is that the signal at this point is inverted during the comprehensive equivalence substitution).

[0142] 7. Perform automatic screening and deduplication on the results obtained in step 6, filtering out duplicates and deviations caused by similar sources, nesting, or tool redundancy, so that the results are more focused on the core issues and make it easier for users to quickly locate them.

[0143] 8. After comparison, the following four approaches can be taken based on the verified actual usage:

[0144] (1) Separate with POST_SIM (post-simulation): Use macro definitions to isolate this section of code that does not need to be verified by post-simulation.

[0145] (2) Replace the new hierarchy: Find the equivalent signal through netlist to replace the existing signal in the verification environment.

[0146] (3) Change to reg(Register): The use of hierarchy can be changed to standard read and write operations on registers.

[0147] (4) Signal Inversion: Add an inversion operation to the reference of the hierarchy.

[0148] 9. After all RTL-level issues have been resolved and the verification environment has been optimized, start the post-simulation regression. This process preemptively cleans up non-bug (fault) level issues caused by the synthesis tool, avoiding wasting time during debugging and allowing the real issues (to-do items) to be exposed more quickly.

[0149] In the above embodiments, when adapting the verification environment, the verification level of the verification test cases corresponding to the verification environment to be processed is clearly defined, thereby ensuring the dimensional consistency of the verification waveform data comparison. Then, the first verification waveform data of the environment to be processed is accurately compared with the second verification waveform data of the historical verification environment. Based on the differences in the verification waveform data, the deviation of the environment parameters or logical defects of the verification environment to be processed can be accurately located, thereby generating targeted verification environment processing instructions. The environment is calibrated or optimized according to the instructions, thereby eliminating potential verification vulnerabilities in the verification environment to be processed. This ensures that the processed verification environment can have the same verification capabilities and accuracy as the historical verification environment, which is conducive to improving the reliability of the verification environment.

[0150] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0151] Based on the same inventive concept, this application also provides a verification environment processing apparatus for implementing the verification environment processing method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more verification environment processing apparatus embodiments provided below can be found in the limitations of the verification environment processing method described above, and will not be repeated here.

[0152] In one exemplary embodiment, such as Figure 4 As shown, a verification environment processing device is provided, including: a hierarchy determination module 401, a data determination module 402, an instruction determination module 403, and an environment processing module 404, wherein:

[0153] The hierarchy determination module 401 is used to determine the verification hierarchy of the verification cases corresponding to the verification environment to be processed.

[0154] The data determination module 402 is used to determine the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0155] The instruction determination module 403 is used to determine the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data.

[0156] The environment processing module 404 is used to process the verification environment to be processed according to the verification environment processing instructions, so as to obtain the processed verification environment corresponding to the verification environment to be processed.

[0157] In an exemplary embodiment, the data determination module 402 is further configured to acquire first initial verification waveform data of the verification environment to be processed, and second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed; according to the verification level, numerical extraction is performed on the first initial verification waveform data to obtain the first verification waveform data of the verification environment to be processed under the verification level, and numerical extraction is performed on the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

[0158] In an exemplary embodiment, the data determination module 402 is further configured to determine, from the verification cases, a target verification case whose verification level meets the preset verification level; run the target verification case in the verification environment to be processed to obtain the first initial verification waveform data of the verification environment to be processed; and run the target verification case in the historical verification environment to obtain the second initial verification waveform data of the historical verification environment.

[0159] In an exemplary embodiment, the hierarchy determination module 401 is further configured to independently compile the top-level hierarchy of the verification cases corresponding to the verification environment to be processed, and obtain an independent compilation result; the independent compilation result is used to represent the verification hierarchy index under the top-level hierarchy; the verification cases are integrated into the verification environment to be processed to obtain the target verification environment, and incremental compilation is performed on the target verification environment to obtain an incremental compilation result; based on the incremental compilation result, the target verification hierarchy index corresponding to the verification cases is determined from the verification hierarchy index; and the verification hierarchy of the verification cases is determined based on the target verification hierarchy index.

[0160] In an exemplary embodiment, the instruction determination module 403 is further configured to perform a consistency comparison process on the first verification waveform data and the second verification waveform data to obtain a consistency comparison result; and determine the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result.

[0161] In an exemplary embodiment, the verification environment processing device further includes a result deduplication module for deduplicating the consistency comparison results to obtain a deduplicated consistency comparison result; the instruction determination module 403 is further configured to determine the verification environment processing instruction corresponding to the verification environment to be processed based on the deduplicated consistency comparison result.

[0162] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0163] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores first verification waveform data, second verification waveform data, etc. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a verification environment processing method.

[0164] Those skilled in the art will understand that Figure 5The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0165] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0166] Based on the same inventive concept, this application also provides a chip, including a processor coupled to a memory, for executing a computer program or instructions stored in the memory, and implementing the steps in the above method embodiments when the processor executes the computer program or instructions.

[0167] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may include an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD), or other integrated chips, etc.

[0168] Based on the same inventive concept, this application also provides a chip module, such as... Figure 6 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0169] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0170] The implementation of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0171] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0172] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0173] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0174] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0175] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0176] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for processing a verification environment, characterized in that, The method includes: Determine the verification level of the verification cases corresponding to the verification environment to be processed; The first verification waveform data of the verification environment to be processed under the verification level is determined, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level is determined. Based on the first verification waveform data and the second verification waveform data, the verification environment processing instruction corresponding to the verification environment to be processed is determined; According to the verification environment processing instructions, the verification environment to be processed is processed accordingly to obtain the processed verification environment corresponding to the verification environment to be processed.

2. The method according to claim 1, characterized in that, The determination of the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level, includes: Acquire the first initial verification waveform data of the verification environment to be processed, and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed; According to the verification level, numerical extraction is performed on the first initial verification waveform data to obtain the first verification waveform data of the verification environment to be processed under the verification level, and numerical extraction is performed on the second initial verification waveform data to obtain the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level.

3. The method according to claim 2, characterized in that, The step of acquiring the first initial verification waveform data of the verification environment to be processed, and the second initial verification waveform data of the historical verification environment corresponding to the verification environment to be processed, includes: From the verification cases, target verification cases that satisfy the preset verification level are determined; The target verification test case is run in the verification environment to be processed to obtain the first initial verification waveform data of the verification environment to be processed, and the target verification test case is run in the historical verification environment to obtain the second initial verification waveform data of the historical verification environment.

4. The method according to claim 1, characterized in that, The determination of the verification level of the verification test case corresponding to the verification environment to be processed includes: The top-level of the verification test cases corresponding to the verification environment to be processed is independently compiled to obtain an independent compilation result; the independent compilation result is used to represent the verification level index under the top-level; The verification test cases are integrated into the verification environment to be processed to obtain the target verification environment, and the target verification environment is incrementally compiled to obtain the incremental compilation result. Based on the incremental compilation results, the target verification level index corresponding to the verification test case is determined from the verification level index; The verification level of the verification case is determined based on the target verification level index.

5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data includes: A consistency comparison process is performed on the first verification waveform data and the second verification waveform data to obtain a consistency comparison result. Based on the consistency comparison results, the verification environment processing instructions corresponding to the verification environment to be processed are determined.

6. The method according to claim 5, characterized in that, Before determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result, the method further includes: The consistency comparison results are deduplicated to obtain the deduplicated consistency comparison results. The step of determining the verification environment processing instruction corresponding to the verification environment to be processed based on the consistency comparison result includes: Based on the consistency comparison results after deduplication, the verification environment processing instructions corresponding to the verification environment to be processed are determined.

7. A verification environment processing device, characterized in that, The device includes: The hierarchy determination module is used to determine the verification hierarchy of the verification cases corresponding to the verification environment to be processed; The data determination module is used to determine the first verification waveform data of the verification environment to be processed under the verification level, and the second verification waveform data of the historical verification environment corresponding to the verification environment to be processed under the verification level. The instruction determination module is used to determine the verification environment processing instruction corresponding to the verification environment to be processed based on the first verification waveform data and the second verification waveform data. The environment processing module is used to process the verification environment to be processed according to the verification environment processing instructions, so as to obtain the processed verification environment corresponding to the verification environment to be processed.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A chip, characterized in that, The device includes a processor and a communication interface, wherein the processor is configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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