Verification platform generation method and device, computer device, chip and chip module

Abstract

The application relates to a verification platform generation method and device, computer equipment, a chip and a chip module. The method comprises the following steps: acquiring verification platform configuration information, a check rule table and a function coverage table corresponding to an algorithm IP core; generating component code corresponding to the algorithm IP core according to the verification platform configuration information, the check rule table and the function coverage table; and integrating the component code into a basic environment framework corresponding to the algorithm IP core to obtain a verification platform corresponding to the algorithm IP core. The method can improve verification efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a verification platform generation method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product. Background Technology

[0002] In the chip design and verification process, in order to ensure the quality of algorithm IP (Intellectual Property) cores, it is crucial to efficiently generate a verification platform that matches the algorithm IP cores.

[0003] In traditional technologies, the generation of verification platforms is generally achieved by manually writing code; however, this manual coding method is cumbersome and time-consuming, resulting in low verification efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a verification platform generation method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product that can improve verification efficiency in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a method for generating a verification platform, including:

[0006] Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core;

[0007] Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core;

[0008] The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0009] In one embodiment, the verification platform configuration information includes a register configuration table and a vector mapping table corresponding to the algorithm IP core;

[0010] The step of generating the component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table includes:

[0011] Based on the register configuration table, the verification environment initialization component code corresponding to the algorithm IP core is determined; based on the vector mapping table, the input component code corresponding to the algorithm IP core is determined; based on the inspection rule table, the inspection component code corresponding to the algorithm IP core is determined; based on the function coverage table, the coverage collection code corresponding to the algorithm IP core is determined.

[0012] Based on the verification environment initialization component code, the input component code, the inspection component code, and the coverage collection code, the component code corresponding to the algorithm IP core is obtained.

[0013] In one embodiment, determining the verification environment initialization component code corresponding to the algorithm IP core based on the register configuration table includes:

[0014] Obtain the transport-level code corresponding to the algorithm's IP core;

[0015] Based on the register configuration table and the transmission level code, generate clock generation code for generating verification clock signals, input initialization code for initializing input signals, first interface instantiation code for instantiating the algorithm IP core interface, and stimulus control code for controlling the distribution of test stimuli, corresponding to the verification environment of the algorithm IP core.

[0016] Based on the clock generation code, the input initialization code, the first interface instantiation code, and the stimulus control code, the verification environment initialization component code corresponding to the algorithm IP core is obtained.

[0017] In one embodiment, determining the input component code corresponding to the algorithm IP core based on the vector mapping table includes:

[0018] Based on the vector mapping table, generate the driver code corresponding to the input driver of the algorithm IP core, and the first switch code of the first driver switch corresponding to the input driver;

[0019] Based on the driver code and the first switch code, the input component code corresponding to the algorithm IP core is obtained.

[0020] In one embodiment, determining the inspection component code corresponding to the algorithm IP core based on the inspection rule table includes:

[0021] Based on the inspection rule table, generate the inspector code corresponding to the inspector of the algorithm IP core, and the second switch code of the second drive switch corresponding to the inspector;

[0022] Based on the second driver code and the second switch code, the check component code corresponding to the algorithm IP core is obtained.

[0023] In one embodiment, determining the coverage collection code corresponding to the algorithm IP core based on the functional coverage table includes:

[0024] Based on the functional coverage table, generate the functional coverage point code and the second interface instantiation code of the coverage acquisition interface corresponding to the algorithm IP core;

[0025] Based on the functional coverage point code and the second interface instantiation code, the coverage collection code corresponding to the algorithm IP core is obtained.

[0026] Secondly, this application also provides a verification platform generation apparatus, comprising:

[0027] The information acquisition module is used to acquire the verification platform configuration information, inspection rule table and function coverage table corresponding to the algorithm IP core;

[0028] The code generation module is used to generate component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table.

[0029] The platform generation module is used to integrate the component code into the basic environment framework corresponding to the algorithm IP core, so as to obtain the verification platform corresponding to the algorithm IP core.

[0030] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0031] Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core;

[0032] Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core;

[0033] The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0034] Fourthly, this application also provides a chip, including a processor and a communication interface, wherein the processor is configured to cause the chip to perform:

[0035] Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core;

[0036] Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core;

[0037] The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0038] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0039] The power module is used to provide power to the chip module;

[0040] The storage module is used to store data and instructions;

[0041] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0042] The chip is used to perform the steps of the method provided in the first aspect above.

[0043] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0044] Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core;

[0045] Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core;

[0046] The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0047] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0048] Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core;

[0049] Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core;

[0050] The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0051] The aforementioned verification platform generation method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product acquire the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core; based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core; and integrate the component code into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core. In this way, by acquiring the verification platform configuration information, inspection rule table, and function coverage table of the algorithm IP core all at once during the verification platform generation process, redundant work of repeatedly sorting out verification requirements and manually defining configuration rules for different IP cores is avoided. The corresponding component code is automatically generated, replacing the inefficient traditional method of manually writing each functional component. Furthermore, the automatically generated component code is directly integrated into a common basic environment framework, eliminating the need to build a verification platform architecture from scratch for each algorithm IP core. This achieves modular reuse of the verification environment, shortens the cycle from configuration to complete verification platform delivery, and thus improves verification efficiency. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a flowchart illustrating the verification platform generation method in one embodiment;

[0054] Figure 2 This is a schematic diagram of a verification platform in one embodiment;

[0055] Figure 3 This is a flowchart illustrating the verification platform generation method in another embodiment;

[0056] Figure 4 This is a structural block diagram of the verification platform generation device in one embodiment;

[0057] Figure 5 This is an internal structural diagram of a computer device in one embodiment;

[0058] Figure 6 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0060] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0061] In one exemplary embodiment, such as Figure 1 As shown, a verification platform generation method is provided. This embodiment illustrates the application of this method to a server. It is understood that this method can also be applied to terminals, systems including terminals and servers, and is implemented through interaction between the terminal and server. It can also be applied to communication equipment, terminal equipment, base stations, network-side equipment, chips, and chip modules. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, and tablets; the server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. In this embodiment, the method includes the following steps:

[0062] Step S101: Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core.

[0063] Algorithm IP cores, also known as algorithm intellectual property cores, refer to objects with specific algorithmic logic functions (such as reusable integrated circuit design modules, typically existing in the form of register-transfer level code or netlists). They usually include algorithmic operation logic and external signal interfaces (such as data input / output, clock reset, register configuration interfaces, etc.). Examples include data encryption / decryption IP cores, digital signal processing IP cores, and filtering algorithm IP cores. Their functional integrity and timing correctness are the core verification objectives of the verification platform. In practical scenarios, algorithm IP cores can refer to the DUT (Design Under Test) of the verification platform.

[0064] The verification platform configuration information includes the register configuration table and vector mapping table corresponding to the algorithm IP core.

[0065] The register configuration table (Reg excel) is a structured data table used to record the full attributes of the internal registers of the algorithm IP core. It typically includes register address, read / write attributes (read-only / write-only / read-and-write), bit width definition, reset default value, function description (such as the purpose of control register, status register, and data register), field division (such as the mode selection of certain bits of the register corresponding to the algorithm, enable signal, etc.).

[0066] The Test Vector Format, also known as the test vector format table, is a structured data table used to define the correspondence between the input and output signals of the algorithm IP core and the verification stimulus response data. It typically includes information such as signal name, signal type (input / output / bidirectional), data bit width, effective value range, timing trigger conditions, mapping rules between stimulus vectors and signals (such as a specific combination of input signals corresponding to a certain set of test vectors), and sampling timing of response vectors.

[0067] The check excel is a structured data table used to define the criteria for judging the functional correctness of the algorithm IP core. It typically includes the objects to be checked (such as output data, status signals, and interrupt signals), the triggering conditions for checking (such as after register configuration is completed or after the algorithm operation cycle ends), the judgment rules (such as the numerical range verification of output data, the timing relationship verification, and the error code matching rules for abnormal scenarios), the fault tolerance threshold (such as the allowable error range), and the error reporting mechanism (such as log output when the rules are not met and the verification termination conditions).

[0068] The Function Coverage Excel, also known as the Function Coverage Checklist, typically includes information such as the name of the coverage point, the covered object (e.g., input signal, internal state, algorithm mode), the coverage dimension (e.g., the range of signal values, the transition path of the state), the cross-coverage combination rules (e.g., the combination scenario of input data range and enable signal), and the coverage target threshold (e.g., requiring a coverage completion rate of over 95%).

[0069] For example, the server obtains the structured hardware attribute information (such as register address mapping, circuit architecture, resource usage, etc. extracted from the design document), algorithm attribute information (such as algorithm type, algorithm operation precision, data processing bit width, etc.) and physical layer attribute information (target process node, operating voltage, frequency range, etc.) corresponding to the algorithm IP core; then, based on the hardware attribute information, algorithm attribute information and physical layer attribute information corresponding to the algorithm IP core, it determines the verification platform configuration information, inspection rule table and function coverage table corresponding to the algorithm IP core.

[0070] Step S102: Generate the component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table.

[0071] Among them, component code refers to the modular functional code set that constitutes the verification platform of the algorithm IP core. It is used to represent the core components of the verification platform, including verification environment initialization component code, input component code, inspection component code, and coverage collection code.

[0072] Among them, the verification environment initialization component code refers to the code set of initialization signals of the verification platform that constitutes the algorithm IP core.

[0073] The input component code refers to the set of code used to generate and load test stimuli to drive the operation of the algorithm IP core.

[0074] Among them, the inspection component code refers to the set of code used to automatically verify the functional correctness of the algorithm IP core.

[0075] Among them, coverage collection code refers to the set of code used to collect and statistically verify the coverage of algorithm IP cores.

[0076] For example, the server converts the verification platform configuration information, the inspection rule table, and the function coverage table into structured data, and adds the structured data to the corresponding position in the component code template corresponding to the algorithm IP core to obtain the component code corresponding to the algorithm IP core.

[0077] Step S103: Integrate the component code into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0078] The basic environment framework refers to the general underlying software architecture template built for the verification platform of algorithm IP cores. This includes standardized access interfaces for verification components, general scheduling logic for the verification process (such as test case startup / termination and log collection framework), an adaptation layer for simulation tools, and basic clock / reset driver templates. In practical scenarios, the basic environment framework refers to a basic verification environment framework built on SV (SystemVerilog, a system-level verification language) or a basic verification environment framework built on UVM (Universal Verification Methodology), containing standardized drivers, monitors, scoreboards, and coverage collection interfaces.

[0079] Among them, the verification platform refers to a dedicated verification system used to verify the functional integrity and timing correctness of the algorithm IP core.

[0080] For example, the server determines the corresponding basic environment framework template (SV template or UVM template) based on the IP core type of the algorithm IP core. Then, through the script corresponding to the algorithm IP core, it reads the key configuration parameters from the configuration file of the algorithm IP core and fills the key configuration parameters into the corresponding positions in the basic environment framework template to obtain the basic environment framework corresponding to the algorithm IP core. Then, according to the preset interface rules, the component code and the basic environment framework are integrated and processed for interface adaptation, signal interconnection, and logical call relationship configuration to obtain the initial verification platform corresponding to the algorithm IP core. Next, the initial verification platform is subjected to syntax verification and logic verification to obtain the verification result. If the verification result indicates that the initial verification platform has passed the verification, the verified initial verification platform is used as the verification platform corresponding to the algorithm IP core.

[0081] In the above-described method for generating a verification platform, the following steps are taken: First, the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core are obtained. Then, based on these information, the component code corresponding to the algorithm IP core is generated. Finally, the component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform. This method avoids the redundant work of repeatedly sorting out verification requirements and manually defining configuration rules for different IP cores by obtaining the verification platform configuration information, inspection rule table, and function coverage table for the algorithm IP core all at once. It also automatically generates the corresponding component code, replacing the inefficient traditional method of manually writing each functional component. Furthermore, the automatically generated component code is directly integrated into a common basic environment framework, eliminating the need to build a verification platform architecture from scratch for each algorithm IP core. This achieves modular reuse of the verification environment, shortens the cycle from configuration to complete verification platform delivery, and thus improves verification efficiency.

[0082] In one exemplary embodiment, the verification platform configuration information includes a register configuration table and a vector mapping table corresponding to the algorithm IP core.

[0083] Therefore, step S102 above, which generates the component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table, specifically includes the following: determining the verification environment initialization component code corresponding to the algorithm IP core based on the register configuration table; determining the input component code corresponding to the algorithm IP core based on the vector mapping table; determining the inspection component code corresponding to the algorithm IP core based on the inspection rule table; determining the coverage collection code corresponding to the algorithm IP core based on the function coverage table; and obtaining the component code corresponding to the algorithm IP core based on the verification environment initialization component code, the input component code, the inspection component code, and the coverage collection code.

[0084] For example, the server determines the verification environment initialization component code corresponding to the algorithm IP core based on the register configuration table; determines the input component code corresponding to the algorithm IP core based on the vector mapping table; determines the inspection component code corresponding to the algorithm IP core based on the inspection rule table; and determines the coverage collection code corresponding to the algorithm IP core based on the function coverage table. Then, the verification environment initialization component code, input component code, inspection component code, and coverage collection code are all used as the component code corresponding to the algorithm IP core.

[0085] In this embodiment, by using the verification platform configuration information, the inspection rule table, and the function coverage table, the component code of the corresponding algorithm IP core can be generated more accurately, ensuring that the component code fully matches the functional characteristics of the algorithm IP core, which is beneficial to improving the completeness and accuracy of the algorithm IP core function verification.

[0086] In an exemplary embodiment, the verification environment initialization component code corresponding to the algorithm IP core is determined according to the register configuration table. Specifically, this includes: obtaining the transport level code corresponding to the algorithm IP core; generating clock generation code for generating verification clock signals, input initialization code for initializing input signals, first interface instantiation code for instantiating the algorithm IP core interface, and stimulus control code for controlling the issuance of test stimuli, based on the register configuration table and the transport level code; and obtaining the verification environment initialization component code corresponding to the algorithm IP core based on the clock generation code, input initialization code, first interface instantiation code, and stimulus control code.

[0087] Among them, the Register Transfer Level (RTL) code refers to the register transfer level hardware description code of the algorithm IP core, which is usually represented in Verilog or VHDL format.

[0088] The verification clock signal refers to the reference signal that provides synchronization timing for the algorithm IP core.

[0089] The clock generation code, also known as intf_clock.sv (an SV file), refers to the clock generation code that matches the verification environment of the algorithm IP core. It is used to control the clock signal of the algorithm IP core and includes clock generation logic, blocking trigger conditions (such as clock pause instructions under specific test scenarios), blocking duration configuration, clock recovery logic, etc.

[0090] The input signal refers to the data signal input to the algorithm IP core.

[0091] The input initialization code, also known as intf_init.sv (a type of SV file), refers to the input initialization code required in the verification environment of the algorithm IP core. It is used to determine the initial state configuration of the input side of the algorithm IP core, specifically including input signal reset logic, register initial value writing logic, initialization completion judgment condition, and fault tolerance handling for abnormal initialization.

[0092] Among them, the algorithm IP core interface refers to the channel through which the algorithm IP core interacts with the verification environment.

[0093] The first interface instantiation code, also known as intf_line.sv (a type of SV file), refers to the interface instantiation code required in the verification environment of the algorithm IP core. It is used to implement the instantiation and adaptation of the core interactive interface of the algorithm IP core, including interface parameter instantiation (such as bit width and protocol type), interconnection mapping between interface signals and top-level signals of the verification platform, binding of interface clock / reset signals, and interface status monitoring logic.

[0094] Among them, test stimuli refer to control instructions issued to the IP core according to preset rules.

[0095] The incentive control code, also known as reg_cfg.sv (an SV file), refers to the incentive control code of the registers controlled by tv (Test Vector). It is used to schedule and manage the test incentive distribution logic of the algorithm IP core. Specifically, it includes incentive trigger condition judgment (such as starting incentive after register configuration is completed), incentive pause / continue logic, polling scheduling of multiple incentives, and injection control of abnormal incentives (such as out-of-range data, timing violation incentives).

[0096] For example, the server obtains the transport-level code corresponding to the algorithm IP core by parsing the interface specification document of the algorithm IP core; then, using the script corresponding to the algorithm IP core, it performs structured parsing of the register configuration table to extract key numerical parameters such as the clock frequency, initialization default value, interface bit width, and excitation trigger conditions corresponding to the algorithm IP core; next, using the script corresponding to the algorithm IP core, it performs syntax parsing and logic extraction on the transport-level code corresponding to the algorithm IP core to identify core logic rules such as the clock blocking trigger rules, input initialization execution logic, interface timing protocol, and excitation control timing constraints corresponding to the algorithm IP core; finally, based on the clock frequency and clock blocking... The code generates clock generation code for the verification environment of the algorithm IP core based on the trigger rules; it generates input initialization code for the verification environment of the algorithm IP core based on the initialization default values ​​and input initialization execution logic of the algorithm IP core; it generates first interface instantiation code for the verification environment of the algorithm IP core based on the interface bit width and interface timing protocol of the algorithm IP core; it generates excitation control code for the verification environment of the algorithm IP core based on the excitation trigger conditions and excitation control timing constraints of the algorithm IP core; and then, the clock generation code, input initialization code, first interface instantiation code, and excitation control code are all used as the verification environment initialization component code for the algorithm IP core.

[0097] In this embodiment, four types of core code are generated in a targeted manner: clock generation, input initialization, first interface instantiation, and excitation control. This ensures that the generated code fully matches the interface transmission characteristics and register configuration logic of the algorithm IP core, avoiding logical errors and timing incompatibility caused by misunderstandings of interface protocols or register rules when writing code manually.

[0098] In an exemplary embodiment, the input component code corresponding to the algorithm IP core is determined according to the vector mapping table, specifically including the following: generating the driver code corresponding to the input driver of the algorithm IP core and the first switch code of the first driver switch corresponding to the input driver according to the vector mapping table; and obtaining the input component code corresponding to the algorithm IP core based on the driver code and the first switch code.

[0099] The input driver, also known as wire*_drv (a type of driver), represents a separate driver for the input data of the algorithm IP core, enabling independent driving of each input signal / interface of the algorithm IP core. For an example, refer to [link / reference]. Figure 2 The input driver can refer to wire*_drv, wire0_drv, wire1_drv, or wire2_drv, in addition to wire*_drv.

[0100] Among them, the driver code refers to the driver code corresponding to the input driver of the algorithm IP core.

[0101] The first driver switch, also known as wire*_drv_en (a type of switch), is a logic switch representing the independent driver of the algorithm IP core's input data. It controls the start / stop and mode switching of the independent input driver of the algorithm IP core. For example, refer to [link / reference]. Figure 2 The first driving switch can refer to wire*_drv_en, as well as wire0_drv_en, wire1_drv_en, and wire2_drv_en.

[0102] The first switch code refers to the switch code corresponding to the first drive switch.

[0103] For example, the server performs structured parsing of the vector mapping table using the script corresponding to the algorithm IP core to obtain the driving logic parameters such as vector data, timing protocol, and interface binding relationship corresponding to the algorithm IP core, as well as the control logic parameters such as switch trigger conditions, state definitions, and linkage rules corresponding to the algorithm IP core. Then, the driving logic parameters are filled into the corresponding positions of the preset driving code template to obtain the driving code corresponding to the input driver of the algorithm IP core, and the control logic parameters are filled into the corresponding positions of the preset switch code template to obtain the first switch code corresponding to the first driving switch of the input driver. Then, both the driving code and the first switch code are used as the input component code corresponding to the algorithm IP core.

[0104] In this embodiment, by using a vector mapping table as the core to generate driver code and first switch code in a targeted manner, it is ensured that the test stimulus can accurately drive the main input interface of the algorithm IP core according to the preset timing and format. This avoids problems such as incorrect stimulus delivery timing and format mismatch that are easy to occur when writing code manually, and helps to improve the reusability of the input component code and the coverage of test scenarios.

[0105] In an exemplary embodiment, the inspection component code corresponding to the algorithm IP core is determined according to the inspection rule table, specifically including the following: generating the inspector code corresponding to the inspector of the algorithm IP core and the second switch code of the second driving switch corresponding to the inspector according to the inspection rule table; and obtaining the inspection component code corresponding to the algorithm IP core based on the second driving code and the second switch code.

[0106] The checker, also known as wire*_chk (a driver), represents a separate driver that automatically verifies the output data of the algorithm IP core. For example, see [reference needed]. Figure 2 The input driver can refer to wire*_chk, as well as wire0_chk, wire1_chk, and wire2_chk.

[0107] Among them, the checker code refers to the driver code corresponding to the checker of the algorithm IP core.

[0108] The second driver switch, also known as wire*_chk_en (a type of switch), is a separate logic switch used to automatically verify the output data of the algorithm IP core. It controls the start and stop of the verification process of the algorithm IP core's checker, the switching of verification modes (such as full verification / sampling verification), and the triggering of abnormal verification scenarios. For example, refer to [link / reference]. Figure 2 The input driver can refer to wire*_chk_en, as well as wire0_chk_en, wire1_chk_en, and wire2_chk_en.

[0109] The second switch code refers to the switch code corresponding to the second drive switch.

[0110] For example, the server uses the script corresponding to the algorithm IP core to perform structured parsing based on the inspection rule table to obtain the verification logic parameters such as the expected value range, timing deviation threshold, and anomaly judgment conditions corresponding to the algorithm IP core, as well as the control logic parameters such as the switch trigger conditions (e.g., test phase, register configuration value, timestamp), switch state definition (enabled / disabled / sampling verification), and linkage rules between the switch and the verification logic (e.g., verification frequency in sampling mode) corresponding to the algorithm IP core. Then, the verification logic parameters are filled into the corresponding positions of the preset driver code template to obtain the checker code corresponding to the algorithm IP core's checker, and the control logic parameters are filled into the corresponding positions of the preset switch code template to obtain the second switch code corresponding to the second driver switch of the checker. Finally, both the second driver code and the second switch code are used as the inspection component code corresponding to the algorithm IP core.

[0111] In this embodiment, by generating second driver code and second switch code based on the inspection rule table, the verification of IP core output data or interface status is ensured to be accurate and in line with design expectations. This avoids problems such as rule omissions and logical deviations that are prone to occur when manually writing verification code, and helps to ensure a high degree of compatibility between the verification function and the characteristics of the algorithm IP core output side.

[0112] In an exemplary embodiment, the coverage collection code corresponding to the algorithm IP core is determined according to the functional coverage table, specifically including the following: generating functional coverage point code and second interface instantiation code of the coverage collection interface corresponding to the algorithm IP core according to the functional coverage table; and obtaining the coverage collection code corresponding to the algorithm IP core based on the functional coverage point code and the second interface instantiation code.

[0113] The coverage acquisition interface refers to the dedicated interface in the algorithm IP core verification platform used to collect coverage data of the algorithm IP core.

[0114] Among them, the functional coverage point code refers to the code that implements the coverage statistics logic of the algorithm IP core, including coverpoint (coverage point definition) statement, cross (cross coverage group) statement, coverage target threshold setting, real-time acquisition and statistics logic of coverage data, etc.

[0115] The second interface instantiation code refers to the code used to instantiate the coverage acquisition interface and bind signals.

[0116] For example, the server performs structured parsing of the functional coverage table using the script corresponding to the algorithm IP core, obtaining functional coverage point parameters such as the coverage point name, signal value combination, cross-coverage rules, and coverage target percentage corresponding to the algorithm IP core, as well as interface parameters such as the interface identifier, the list of IP core signals to be bound, the interface bit width, clock / reset synchronization rules, and data acquisition timing constraints corresponding to the algorithm IP core. Then, the functional coverage point parameters are filled into the corresponding positions of the preset functional coverage point code template to obtain the functional coverage point code of the coverage acquisition interface corresponding to the algorithm IP core, and the interface parameters are filled into the corresponding positions of the preset interface instantiation code template to obtain the second interface instantiation code of the coverage acquisition interface corresponding to the algorithm IP core. Finally, both the functional coverage point code and the second interface instantiation code are used as the coverage collection code corresponding to the algorithm IP core.

[0117] In this embodiment, by generating functional coverage point code and second interface instantiation code based on the functional coverage table, the coverage statistics dimensions and collection rules defined in the functional coverage table are fully matched, ensuring that the triggering states of various functional scenarios during the operation of the IP core can be captured comprehensively and accurately, avoiding problems such as omission of coverage points and incorrect binding of collection interfaces that are easy to occur when manually writing code.

[0118] In one exemplary embodiment, such as Figure 3 As shown, another method for generating a verification platform is provided. Taking the application of this method to a server as an example, the specific steps include:

[0119] Step S301: Obtain the register configuration table, vector mapping table, inspection rule table, and function coverage table corresponding to the algorithm IP core.

[0120] Step S302: Obtain the transport-level code corresponding to the algorithm IP core.

[0121] Step S303: Based on the register configuration table and the transmission level code, generate the clock generation code, input initialization code, first interface instantiation code, and excitation control code corresponding to the verification environment of the algorithm IP core.

[0122] Step S304: Based on the clock generation code, input initialization code, first interface instantiation code, and stimulus control code, the verification environment initialization component code corresponding to the algorithm IP core is obtained.

[0123] Step S305: Based on the vector mapping table, generate the driver code corresponding to the input driver of the algorithm IP core, and the first switch code of the first driver switch corresponding to the input driver.

[0124] Step S306: Based on the driver code and the first switch code, obtain the input component code corresponding to the algorithm IP core.

[0125] Step S307: Based on the inspection rule table, generate the inspector code corresponding to the inspector of the algorithm IP core, and the second switch code of the second drive switch corresponding to the inspector.

[0126] Step S308: Based on the second driver code and the second switch code, obtain the check component code corresponding to the algorithm IP core.

[0127] Step S309: Based on the functional coverage table, generate the functional coverage point code and the second interface instantiation code of the coverage acquisition interface corresponding to the algorithm IP core.

[0128] Step S310: Based on the functional coverage point code and the second interface instantiation code, obtain the coverage collection code corresponding to the algorithm IP core.

[0129] Step S311: Initialize component code based on verification environment, input component code, check component code and coverage collection code to obtain component code corresponding to algorithm IP core.

[0130] Step S312: Integrate the component code into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

[0131] In the above-mentioned method for generating a verification platform, the platform generation process obtains the verification platform configuration information, check rule table, and function coverage table for each algorithm IP core in one go. This avoids the redundant work of repeatedly sorting out verification requirements and manually defining configuration rules for different IP cores. It also automatically generates the corresponding component code, replacing the inefficient traditional method of manually writing each functional component. Furthermore, the automatically generated component code is directly integrated into a common basic environment framework, eliminating the need to build a verification platform architecture from scratch for each algorithm IP core. This achieves modular reuse of the verification environment, which helps to shorten the cycle from configuration to complete verification platform delivery, thereby improving verification efficiency.

[0132] In an exemplary embodiment, to more clearly illustrate the verification platform generation method provided in this application, the following specific embodiment will be used to describe the verification platform generation method in detail. In one embodiment, this application also provides a verification platform suitable for the automated generation of algorithm-based IP. Specifically, it includes the following:

[0133] 1. Read the specifications, understand the IP functions and algorithms, and have the DE define the TV vector format.

[0134] 2. Reg excel (Register Configuration Table): Records information about the internal registers of the IP.

[0135] 3. TV format (test vector format table): contains input / output signals. The TV file name needs to be mapped to the input / output lines.

[0136] 4. Check Excel (Check Rules Table): This includes the effective time of the check signal, the critical path nodes to be checked, and the corresponding output TV.

[0137] 5. func cov excel (Function Coverage Checklist): Lists the function coverage points that need attention, as well as various scenarios that require cross-collection.

[0138] 6. Use a script to generate the basic SV / UVM environment.

[0139] 7. Use a script to read the IP top rtl (the top-level transport level code of the algorithm IP core) and reg excel to generate the following (basic component code for the verification environment): intf_clock.sv (clock_blocking code required in the environment), intf_init.sv (input initialization code required in the environment), intf_line.sv (interface instantiation code required in the environment), and reg_cfg.sv (excitation control code of the registers controlled by tv for input).

[0140] 8. Merge the intf_clock.sv, intf_init.sv, intf_line.sv, and reg_cfg.sv generated in operation 7 into the base environment of operation 6.

[0141] 9. Use a script to read the TV format table and generate individual drivers for the input of each algorithm class IP core, wire*_drv, as well as the switch wire*_drv_en for each individual driver.

[0142] 10. Merge the wire*_drv and wire*_drv_en generated in operation 9 into the base environment of operation 6.

[0143] 11. Use a script to read the check Excel spreadsheet to generate a separate checker for the output of each algorithm class IP core, as well as the switch for each separate checker, the interface for the line to be checked, the code for instantiating the interface, and the logic processing for some lines. Details need to be modified manually.

[0144] 12. Merge the wire*_chk and wire*_chk_en generated in operation 11 into the base environment of operation 6.

[0145] 13. Use a script to extract the func cov excel, generate the cover point, the interface collected by the coverage, and the code for instantiating the interface, but the cross needs to be modified in detail.

[0146] 14. Merge the coverage collection code generated in operation 14 into the base environment of operation 6.

[0147] 15. Build test cases. At this point, most of the code will be automatically generated. Modify it according to each IP specification. Trig events of key nodes in the environment need to be manually modified. SVA and specifications that do not appear in TV format need to be built separately for the environment and test cases.

[0148] In the above embodiments, during the generation of the verification platform, the verification platform configuration information, inspection rule table, and function coverage table of the algorithm IP core are obtained at once. This avoids the redundant work of repeatedly sorting out verification requirements and manually defining configuration rules for different IP cores. The corresponding component code is automatically generated, replacing the inefficient traditional method of manually writing each functional component. Furthermore, the automatically generated component code is directly integrated into the general basic environment framework. There is no need to build a verification platform architecture from scratch for each algorithm IP core. This achieves modular reuse of the verification environment, which helps to shorten the cycle from configuration to delivery of a complete verification platform, thereby improving verification efficiency.

[0149] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0150] Based on the same inventive concept, this application also provides a verification platform generation apparatus for implementing the verification platform generation method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more verification platform generation apparatus embodiments provided below can be found in the limitations of the verification platform generation method described above, and will not be repeated here.

[0151] In one exemplary embodiment, such as Figure 4 As shown, a verification platform generation device is provided, including: an information acquisition module 401, a code generation module 402, and a platform generation module 403, wherein:

[0152] The information acquisition module 401 is used to acquire the verification platform configuration information, inspection rule table and function coverage table corresponding to the algorithm IP core.

[0153] The code generation module 402 is used to generate component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table; the component code corresponds to the verification platform configuration information.

[0154] The platform generation module 403 is used to integrate the component code into the basic environment framework corresponding to the algorithm IP core, so as to obtain the verification platform corresponding to the algorithm IP core.

[0155] In an exemplary embodiment, the code generation module 402 is further configured to: determine the verification environment initialization component code corresponding to the algorithm IP core according to the register configuration table; determine the input component code corresponding to the algorithm IP core according to the vector mapping table; determine the inspection component code corresponding to the algorithm IP core according to the inspection rule table; determine the coverage collection code corresponding to the algorithm IP core according to the functional coverage table; and obtain the component code corresponding to the algorithm IP core based on the verification environment initialization component code, input component code, inspection component code, and coverage collection code.

[0156] In an exemplary embodiment, the code generation module 402 is further configured to obtain the transport-level code corresponding to the algorithm IP core; generate clock generation code, input initialization code, first interface instantiation code, and stimulus control code corresponding to the verification environment of the algorithm IP core according to the register configuration table and the transport-level code; and obtain the verification environment initialization component code corresponding to the algorithm IP core based on the clock generation code, input initialization code, first interface instantiation code, and stimulus control code.

[0157] In an exemplary embodiment, the code generation module 402 is further configured to generate, according to the vector mapping table, the driver code corresponding to the input driver of the algorithm IP core, and the first switch code of the first driver switch corresponding to the input driver; and obtain the input component code corresponding to the algorithm IP core based on the driver code and the first switch code.

[0158] In an exemplary embodiment, the code generation module 402 is further configured to generate, according to the inspection rule table, the inspector code corresponding to the inspector of the algorithm IP core, and the second switch code of the second driving switch corresponding to the inspector; and obtain the inspection component code corresponding to the algorithm IP core based on the second driving code and the second switch code.

[0159] In an exemplary embodiment, the code generation module 402 is further configured to generate functional coverage point code and second interface instantiation code of the coverage acquisition interface corresponding to the algorithm IP core according to the functional coverage table; and obtain the coverage collection code corresponding to the algorithm IP core based on the functional coverage point code and the second interface instantiation code.

[0160] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0161] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores verification platform configuration information, component code, and other data. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a verification platform generation method.

[0162] Those skilled in the art will understand that Figure 5The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0163] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0164] Based on the same inventive concept, this application also provides a chip, including a processor coupled to a memory, for executing a computer program or instructions stored in the memory, and implementing the steps in the above method embodiments when the processor executes the computer program or instructions.

[0165] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may include an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD), or other integrated chips, etc.

[0166] Based on the same inventive concept, this application also provides a chip module, such as... Figure 6 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0167] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0168] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0169] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0170] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0171] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0172] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0173] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0174] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating a verification platform, characterized in that, The method includes: Obtain the verification platform configuration information, inspection rule table, and function coverage table corresponding to the algorithm IP core; Based on the verification platform configuration information, the inspection rule table, and the function coverage table, generate the component code corresponding to the algorithm IP core; The component code is integrated into the basic environment framework corresponding to the algorithm IP core to obtain the verification platform corresponding to the algorithm IP core.

2. The method according to claim 1, characterized in that, The verification platform configuration information includes the register configuration table and vector mapping table corresponding to the algorithm IP core; The step of generating the component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table includes: Based on the register configuration table, the verification environment initialization component code corresponding to the algorithm IP core is determined; based on the vector mapping table, the input component code corresponding to the algorithm IP core is determined; based on the inspection rule table, the inspection component code corresponding to the algorithm IP core is determined; based on the function coverage table, the coverage collection code corresponding to the algorithm IP core is determined. Based on the verification environment initialization component code, the input component code, the inspection component code, and the coverage collection code, the component code corresponding to the algorithm IP core is obtained.

3. The method according to claim 2, characterized in that, The step of determining the verification environment initialization component code corresponding to the algorithm IP core based on the register configuration table includes: Obtain the transport-level code corresponding to the algorithm's IP core; Based on the register configuration table and the transmission level code, generate clock generation code for generating verification clock signals, input initialization code for initializing input signals, first interface instantiation code for instantiating the algorithm IP core interface, and stimulus control code for controlling the distribution of test stimuli, corresponding to the verification environment of the algorithm IP core. Based on the clock generation code, the input initialization code, the first interface instantiation code, and the stimulus control code, the verification environment initialization component code corresponding to the algorithm IP core is obtained.

4. The method according to claim 2, characterized in that, The step of determining the input component code corresponding to the algorithm IP core based on the vector mapping table includes: Based on the vector mapping table, generate the driver code corresponding to the input driver of the algorithm IP core, and the first switch code of the first driver switch corresponding to the input driver; Based on the driver code and the first switch code, the input component code corresponding to the algorithm IP core is obtained.

5. The method according to claim 2, characterized in that, The step of determining the inspection component code corresponding to the algorithm IP core based on the inspection rule table includes: Based on the inspection rule table, generate the inspector code corresponding to the inspector of the algorithm IP core, and the second switch code of the second drive switch corresponding to the inspector; Based on the second driver code and the second switch code, the check component code corresponding to the algorithm IP core is obtained.

6. The method according to claim 2, characterized in that, The step of determining the coverage collection code corresponding to the algorithm IP core based on the functional coverage table includes: Based on the functional coverage table, generate the functional coverage point code and the second interface instantiation code of the coverage acquisition interface corresponding to the algorithm IP core; Based on the functional coverage point code and the second interface instantiation code, the coverage collection code corresponding to the algorithm IP core is obtained.

7. A verification platform generation device, characterized in that, The device includes: The information acquisition module is used to acquire the verification platform configuration information, inspection rule table and function coverage table corresponding to the algorithm IP core; The code generation module is used to generate component code corresponding to the algorithm IP core based on the verification platform configuration information, the inspection rule table, and the function coverage table. The platform generation module is used to integrate the component code into the basic environment framework corresponding to the algorithm IP core, so as to obtain the verification platform corresponding to the algorithm IP core.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A chip, characterized in that, The device includes a processor and a communication interface, wherein the processor is configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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