Hardware specification testing tools, methods, and related devices

Abstract

Embodiments of the present application provide a hardware specification test tool, a method and related equipment, wherein the hardware specification test tool comprises: a plurality of special test modules; one special test module tests one hardware specification of an acceleration computing chip; different special test modules are aimed at different hardware specifications to cover all hardware specifications of the acceleration computing chip; when testing the hardware specification, one or more special test modules are dispatched, and the dispatched special test module tests the hardware specification in at least one dimension; wherein one dimension corresponds to a quantifiable performance item of the hardware specification in a specific test direction, and multiple dimensions cooperatively cover the overall performance characteristics of the hardware specification. The technical scheme provided by the embodiments of the present application can perform integrated and complete hardware specification testing on the acceleration computing chip, and improve the test comprehensiveness of the hardware specification test tool.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a hardware specification testing tool, method, and related equipment. Background Technology

[0002] In computationally intensive applications such as High Performance Computing (HPC) and Artificial Intelligence (AI), accelerator chips, including General-Purpose Computing on Graphics Processing Units (GPGPUs), have become crucial for accelerating computing. The computational performance of accelerator chips depends not only on traditional metrics like core count and clock frequency, but also on various hardware specifications such as memory bandwidth, instruction execution efficiency, and power management. Therefore, testing the hardware specifications of accelerator chips is essential to avoid issues like inaccurate specification claims, task incompatibility, and sudden failures during operation, directly ensuring the efficiency, stability, and success rate of accelerated computing tasks.

[0003] However, hardware specification testing tools for general-purpose accelerated computing chips still fall short. Therefore, providing a technical solution to perform integrated and comprehensive hardware specification testing of accelerated computing chips, and improving the testing comprehensiveness of hardware specification testing tools, has become a pressing technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a hardware specification testing tool, method and related equipment to perform integrated and complete hardware specification testing on accelerated computing chips, thereby improving the testing comprehensiveness of the hardware specification testing tool.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, embodiments of the present invention provide a hardware specification testing tool, comprising: Multiple specialized test modules; each specialized test module tests one hardware specification of the accelerated computing chip; different specialized test modules target different hardware specifications to cover all hardware specifications of the accelerated computing chip; When testing a target hardware specification by scheduling one or more of the aforementioned specialized testing modules, the scheduled specialized testing modules test the target hardware specification in at least one dimension; wherein, one dimension corresponds to a quantifiable performance item of the target hardware specification in a specific testing direction, and multiple dimensions work together to cover the overall performance characteristics of the target hardware specification.

[0007] In a second aspect, embodiments of the present invention provide a hardware specification testing method, applied to the hardware specification testing tool described in the first aspect, the method comprising: Identify the accelerated computing chip to be tested; Call at least one specialized test module of the hardware specification testing tool; a specialized test module is for one hardware specification of the accelerated computing chip under test, and different specialized test modules are for different hardware specifications to cover all hardware specifications of the accelerated computing chip. Based on the activated specialized testing module, at least one dimension of the targeted hardware specification is tested to obtain the test results; one dimension corresponds to the quantifiable performance item of the targeted hardware specification in a specific testing direction, and multiple dimensions work together to cover the overall performance characteristics of the targeted hardware specification.

[0008] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the hardware specification testing method as described in the second aspect.

[0009] Fourthly, embodiments of the present invention provide a storage medium storing a program that, when executed, implements the hardware specification testing method as described in the second aspect.

[0010] Fifthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the hardware specification testing method as described in the second aspect.

[0011] This invention provides a hardware specification testing tool, comprising: multiple specialized testing modules; each specialized testing module tests a hardware specification of an accelerated computing chip; different specialized testing modules target different hardware specifications to cover all hardware specifications of the accelerated computing chip; when testing a targeted hardware specification by scheduling one or more of the specialized testing modules, the scheduled specialized testing module tests the targeted hardware specification in at least one dimension; wherein, one dimension corresponds to a quantifiable performance item of the targeted hardware specification in a specific testing direction, and multiple dimensions collaboratively cover the overall performance characteristics of the targeted hardware specification.

[0012] As can be seen, the technical solution provided by the embodiments of the present invention, firstly, includes multiple specialized testing modules in the hardware specification testing tool. Each specialized testing module tests a specific hardware specification of the accelerated computing chip, and different specialized testing modules target different hardware specifications to cover all hardware specifications of the accelerated computing chip. Therefore, the sum of the hardware specifications targeted by each specialized testing module is for the complete hardware specifications of the accelerated computing chip. Thus, the hardware specification testing tool constructed by the embodiments of the present invention can integrate the testing of all hardware specifications of the accelerated computing chip. Secondly, each specialized testing module tests from different dimensions involved in the hardware specification it targets, thereby enabling the formation of multi-dimensional test results for a hardware specification. Since one dimension corresponds to a quantifiable performance item of the targeted hardware specification in a specific testing direction, multiple dimensions synergistically cover the overall performance characteristics of the targeted hardware specification, thus improving the comprehensiveness of the test results for each hardware specification. At the same time, since each dimension can cover the overall performance characteristics of the hardware specification, the test results obtained from different dimensions can be correlated, thereby fully reflecting the comprehensive testing situation of a hardware specification. As can be seen, the hardware specification testing tool provided in this embodiment of the invention can achieve simultaneous multi-indicator, correlation analysis, and unified benchmarking, enabling a comprehensive evaluation of hardware specifications. This avoids the limitations of testing only a single or partial hardware specification, while quickly identifying problems and improving testing efficiency. It better meets the comprehensive analytical needs of real-world scenarios, providing more valuable test results in situations requiring a complete understanding of the hardware. Ultimately, it achieves integrated and complete hardware specification testing of accelerated computing chips, enhancing the comprehensiveness of hardware specification testing tools. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the hardware specification testing tool provided in an embodiment of the present invention; Figure 2 This is another structural schematic diagram of the hardware specification testing tool provided in this embodiment of the invention; Figure 3 This is a schematic diagram of memory operation provided in an embodiment of the present invention; Figure 4a This is a schematic diagram of the data reading method of the convolution operator provided in the embodiment of the present invention; Figure 4b yes Figure 4a An enlarged view of point A is shown below; Figure 5 This is a schematic diagram of a test result from the memory bandwidth-specific test module provided in an embodiment of the present invention; Figure 6a This is a schematic diagram of a test result from the power consumption-specific test module provided in an embodiment of the present invention; Figure 6b This is another schematic diagram of the test results of the power consumption-specific test module provided in this embodiment of the invention; Figure 6c This is a schematic diagram of another test result of the power consumption-specific test module provided in this embodiment of the invention; Figure 6d This is another test result diagram of the power consumption-specific test module provided in this embodiment of the invention; Figure 7 This is a flowchart illustrating a hardware specification testing method provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0016] As mentioned in the background, GPGPU is an important acceleration tool for computationally intensive applications such as HPC and AI. Its performance is affected by many factors such as the number of cores and memory bandwidth. Therefore, establishing a comprehensive hardware specification testing framework is crucial for evaluating and optimizing its performance.

[0017] In related technologies, performance analysis tools are typically used to provide a certain level of hardware performance testing and analysis. However, since performance analysis tools focus on scenario-based performance diagnosis and software optimization, while hardware specification testing tools focus on verifying standardized hardware nominal specifications, even though performance analysis tools can partially test hardware specifications, it is still necessary to build dedicated hardware specification testing tools to meet the core needs of standardized comparison, accurate verification, compliance certification, and extreme performance testing.

[0018] Due to the inherent complexity of GPGPU and other accelerated computing chips, the lack of standardized testing standards, and the significant differences in requirements across various application scenarios, it is difficult to use a single tool to cover the testing of all hardware specifications.

[0019] It is evident that performance analysis tools in related technologies focus on software-level analysis, lacking in-depth testing of underlying hardware data paths, computing power, and memory access behavior. Hardware specification testing tools often rely on external instruments for power consumption and memory bandwidth testing, lacking unified testing standards. Memory and cache latency testing is difficult to measure accurately, and the comparability between different architectures is weak; there are no tools that support integrated testing of complete hardware specifications.

[0020] To address the aforementioned issues, this invention provides a hardware specification testing tool to perform integrated and comprehensive hardware specification testing on accelerated computing chips, thereby improving the testing comprehensiveness of the hardware specification testing tool.

[0021] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the hardware specification testing tool provided in an embodiment of the present invention.

[0022] like Figure 1 As shown, the hardware specification testing tool includes: Multiple specialized test modules 1; each specialized test module 1 tests a specific hardware specification of the accelerated computing chip; different specialized test modules 1 target different hardware specifications to cover all hardware specifications of the accelerated computing chip; When testing the target hardware specification by scheduling one or more of the aforementioned specialized test modules 1, the scheduled specialized test module 1 tests the target hardware specification in at least one dimension; wherein, one dimension corresponds to a quantifiable performance item of the target hardware specification in a specific test direction, and multiple dimensions work together to cover the overall performance characteristics of the target hardware specification.

[0023] Accelerated computing chips include multiple different hardware specifications. In order to perform targeted testing on each hardware specification, different specialized test modules can be established according to different hardware specifications.

[0024] For example, when establishing different specialized test modules 1, the specialized test module 1 can execute a predefined set of test items corresponding to the targeted hardware specifications to achieve testing on different dimensions of the hardware specifications. That is, the specialized test module 1 is the execution entity, and the set of test items is the specific means of testing the hardware specifications. A set of test items can include test items that implement testing on different dimensions.

[0025] For example, GPGPU hardware specifications such as memory bandwidth, memory latency, computing power, and power consumption each represent different characteristics and performance indicators of the hardware. Establishing corresponding specialized test modules for these specific hardware specifications allows for more targeted and in-depth testing of the hardware's specific performance characteristics.

[0026] Due to the complexity of the hardware architecture of accelerated computing chips, the diversity of application scenarios, and the correlation of performance, a hardware specification has multiple dimensions, thus fully and realistically reflecting the overall performance characteristics of that hardware specification.

[0027] Dimensions serve hardware specifications. The specific test directions of all dimensions are to verify the true performance of the hardware specification they target. For example, when the hardware specification is computing power, dimensions such as "FP32 computing power" and "INT8 computing power" are ultimately used to evaluate the overall level of computing power.

[0028] It should be noted that under the same hardware specifications, specific test directions in different dimensions (such as test scenarios / architectural levels) do not overlap. For example, sequential reads of video memory and random writes of L1 cache correspond to different architectural levels and access scenarios, and there is no overlap between them, thus avoiding duplicate testing.

[0029] The number of specialized test modules 1 can be determined based on the number of hardware specifications included in the specific accelerated computing chip. The specific test dimensions involved in each specialized test module 1 can be set according to the specific hardware specifications targeted, so as to meet the requirements of full and comprehensive testing of all hardware specifications in different dimensions, making the test results more reliable and accurate.

[0030] After constructing each specialized test module 1 based on specific hardware specifications, one or more specialized test modules 1 can be selected and called according to the current specific testing requirements to test the hardware specifications targeted by the specialized test module and that meet the testing requirements. This facilitates integrated testing of different hardware specifications and allows for comprehensive analysis of the performance of the accelerated computing chip based on test results obtained from different dimensions, avoiding inaccurate performance analysis caused by single and one-sided test results.

[0031] As can be seen, the technical solution provided by the embodiments of the present invention, firstly, includes multiple specialized testing modules 1 in the hardware specification testing tool. Each specialized testing module 1 tests a specific hardware specification of the accelerated computing chip, and different specialized testing modules 1 target different hardware specifications to cover all hardware specifications of the accelerated computing chip. Therefore, the sum of the hardware specifications targeted by each specialized testing module 1 is for the complete hardware specifications of the accelerated computing chip. Thus, the hardware specification testing tool constructed by the embodiments of the present invention can integrate the testing of all hardware specifications of the accelerated computing chip. Secondly, each specialized testing module 1 tests from different dimensions involved in the hardware specification it targets, thereby enabling the formation of test results from multiple dimensions for a single hardware specification. Since one dimension corresponds to a quantifiable performance item of the targeted hardware specification in a specific testing direction, multiple dimensions collaboratively cover the overall performance characteristics of the targeted hardware specification, thus improving the comprehensiveness of the test results for each hardware specification. At the same time, since each dimension can cover the overall performance characteristics of the hardware specification, the test results obtained from different dimensions can be correlated with each other, thereby fully reflecting the comprehensive testing situation of a hardware specification. As can be seen, the hardware specification testing tool provided in this embodiment of the invention can achieve simultaneous multi-indicator, correlation analysis, and unified benchmarking, enabling a comprehensive evaluation of hardware specifications. This avoids the limitations of testing only a single or partial hardware specification, while quickly identifying problems and improving testing efficiency. It better meets the comprehensive analytical needs of real-world scenarios, providing more valuable test results in situations requiring a complete understanding of the hardware. Ultimately, it achieves integrated and complete hardware specification testing of accelerated computing chips, enhancing the comprehensiveness of hardware specification testing tools.

[0032] Please continue to refer to this. Figure 1 In one embodiment, the special testing module 1 may include: a memory bandwidth special testing module 11; the hardware specification targeted by the memory bandwidth special testing module 11 is the memory bandwidth hardware specification. When scheduling the memory bandwidth dedicated test module 11 to test the memory bandwidth hardware specifications, the test is carried out according to the bandwidth test strategies corresponding to different dimensions; wherein, the dimensions corresponding to the memory bandwidth dedicated test module 11 are divided based on the hardware modules in the accelerated computing chip associated with the memory bandwidth hardware specifications, or based on the application scenarios of the memory bandwidth hardware specifications.

[0033] The memory bandwidth hardware specification is an independent and comprehensive description of the specification. When testing the memory bandwidth hardware specification, comprehensive testing can be carried out from multiple dimensions to obtain test results of the memory bandwidth hardware specification from different dimensions. The memory bandwidth hardware specification can be comprehensively evaluated by combining the test results from various dimensions.

[0034] When dividing the hardware modules in the accelerated computing chip based on the aforementioned memory bandwidth hardware specifications, the hardware modules associated with the memory bandwidth hardware specifications can be different types or levels of storage structures related to memory bandwidth, such as device memory and on-chip cache, each corresponding to different dimensions during bandwidth testing. Application scenarios include memory bandwidth testing in various applications, such as deep learning operators.

[0035] In other words, hardware modules are based on the design of the hardware itself (for example, storage structures are divided into L1 cache / L2 cache / device memory, which naturally correspond to different bandwidth dimensions), while application scenarios are based on actual usage needs (for example, different access modes in deep learning correspond to different combinations of bandwidth dimensions). This is a parallel classification from both hardware and demand perspectives.

[0036] The dimension division method corresponding to the memory bandwidth hardware specification can be flexibly selected so that the divided dimensions are more targeted and avoid the one-sidedness of the test.

[0037] Please continue to refer to this. Figure 1 In one embodiment, when the dimension is a partition of hardware modules in the accelerated computing chip associated with the memory bandwidth hardware specifications, the hardware module includes: device memory and on-chip cache; the memory bandwidth dedicated testing module 11 includes: device memory bandwidth dedicated testing module 111 and on-chip cache bandwidth dedicated testing module 112; the device memory bandwidth dedicated testing module 111 executes the device memory bandwidth testing strategy corresponding to the device memory dimension; the on-chip cache bandwidth dedicated testing module 112 executes the on-chip cache bandwidth testing strategy corresponding to the on-chip cache dimension; The device memory bandwidth testing strategy is as follows: based on different combinations of hardware resource configuration methods and data read / write methods, and with a fixed amount of first data, the device memory bandwidth is tested by combining the read / write time of reading the first data in different combinations of scenarios. The on-chip cache bandwidth testing strategy is as follows: based on different combinations of hardware resource configuration methods and data read / write methods, and combined with the target storage structure in the on-chip cache currently being tested, the target data read / write path for reading and writing the target storage structure is determined. On the target data read / write path, the bandwidth of the target storage structure is tested in different combinations of scenarios by using a second amount of data to read and write and the read / write time for reading and writing the second amount of data.

[0038] The bandwidth testing strategies differ depending on the hardware module. This is because device memory (also known as video memory in GPGPU and other accelerated computing chips) is a massive data storage device (i.e., the primary data volume is massive). Therefore, the bandwidth testing strategy for device memory is designed around "peak value, large granularity, and multiple channels". On-chip cache is characterized by high-frequency data reuse, so the bandwidth testing strategy for on-chip cache is usually designed around "efficiency, small granularity, and multiple cores".

[0039] When testing the bandwidth of device memory and on-chip cache, it is usually necessary to pre-configure hardware resources and data read / write methods. However, the pre-configuration of on-chip cache is a fine-grained configuration, otherwise the true value cannot be measured. The pre-configuration of device memory is a basic standardized configuration. The core is to eliminate interference and approximate the peak value. There is no need for overly complex customization. Therefore, it can be configured specifically based on the test requirements of the specific hardware module to adapt to the test requirements under different dimensions of memory bandwidth.

[0040] The aforementioned device memory bandwidth dedicated test module 111 and on-chip cache bandwidth dedicated test module 112 can be referenced. Figure 1 and Figure 2 , Figure 2 This is another structural schematic diagram of the hardware specification testing tool provided in the embodiments of the present invention.

[0041] like Figure 1 and Figure 2 As shown, the memory bandwidth testing module 11 includes a device memory bandwidth testing module 111 and an on-chip cache bandwidth testing module 112, which are used to test different dimensions of memory bandwidth.

[0042] Of course, the device memory bandwidth test module 111 can be configured with corresponding device memory bandwidth test items, and the on-chip cache bandwidth test module 112 can be configured with corresponding on-chip cache bandwidth test items, together forming the set of bandwidth test items executed by the memory bandwidth test module 11.

[0043] Please continue to refer to this. Figure 1 and Figure 2 To support the configuration of different hardware resources and data read / write methods, and to enable the construction of different combined scenarios, the memory bandwidth dedicated test module 11 may further include: The hardware resource and data read / write mode configuration module 113 is used to provide a resource configuration interaction interface and a data read / write mode determination interaction interface. The resource configuration interaction interface is used for users to configure hardware resources according to current test requirements; the data read / write mode determination interaction interface is used for users to determine the target data read / write mode. The device memory bandwidth dedicated testing module 111 includes: The test parameter configuration module is used to configure the first data volume, which is greater than the total capacity of the on-chip cache. The device memory data read / write and timing module is used to read and write the first amount of data configured by the test parameter configuration module, and record the first read / write time of the first amount of data. The device memory bandwidth calculation module is used to obtain the bandwidth test results of the device memory under the scenario of the configured hardware resources and target data read and write method combination, based on the first read and write time and the first data volume; The device memory bandwidth output module is used to output the bandwidth test results of the device memory under different combinations of hardware resources and data read / write methods.

[0044] The test parameter configuration module pre-configures a first data volume as the test data for the device's memory bandwidth. Setting the first data volume to be greater than the total capacity of the on-chip cache ensures that data penetrates the on-chip cache and is transmitted entirely through the device's memory, avoiding bandwidth mixing. Without pre-configuration, the default test data volume may be less than the total capacity of the on-chip cache, resulting in the measured bandwidth being the on-chip cache bandwidth instead of the device's memory bandwidth. Setting a fixed first data volume also allows for comparison of differences in device memory bandwidth under different combinations of scenarios.

[0045] Of course, the initial data volume also has an upper limit. For example, the upper limit of the initial data volume can be determined based on the total capacity of the device memory to avoid occupying too much device memory and causing interference from other processes.

[0046] For example, in GPGPUs, global memory is typically GDDR (Graphics Double Data Rate) or HBM (High Bandwidth Memory). Global memory is a critical resource affecting the overall performance of a GPGPU, and its access latency is much higher than that of on-chip cache. Computational units often idle while waiting for global memory. Therefore, the bandwidth capability of global memory is an important indicator for evaluating the quality of GPGPUs and other accelerated computing chips.

[0047] Different accelerated computing chips have different architectures, resulting in different types and frequencies of device memory, as well as different throughput and data read / write methods (such as access modes). Therefore, when testing device memory, different test requirements and test objects (accelerated computing chips) lead to different hardware resources and data read / write methods, resulting in different combined scenarios. To adapt to memory bandwidth testing under various combined scenarios, this embodiment of the invention provides a module that can configure hardware resources and data read / write methods: a hardware resource and data read / write method configuration module 113. This module allows for the combination of different hardware resource configurations and different data read / write methods, such as linear or matrix data read / write methods, to facilitate comparative testing of memory bandwidth under multiple combined scenarios (data read / write methods + hardware resource configurations).

[0048] Specifically, the testing method may include the following steps: First, the hardware resources and target data read / write mode are pre-configured through the hardware resource and data read / write mode configuration module 113 to form a current set of combined scenarios. For example, the number of wavefronts of each computing unit is set, which is the basic unit of actual operation of each computing unit, and the target data read / write mode is determined, for example, it is determined to be a linear data read / write mode.

[0049] Then, the test parameter configuration module allocates a sufficient amount of initial data (which can be set by the user) so that the size of the initial data can be the size of the full on-chip cache (e.g., L2 cache), thereby reducing the on-chip cache hit rate and avoiding errors in the memory bandwidth of the test device caused by consecutive on-chip cache hits.

[0050] In addition, the first read / write time is recorded when the first amount of data is read or written. For example, a timestamp can be used to record the time before and after loading the first amount of data, and the first read / write time (i.e., the loading time of the first amount of data) can be obtained based on the difference between the two.

[0051] Finally, by combining the bandwidth calculation formula: total data volume / read / write time, and using the first data volume and the first read / write time, the bandwidth test results of the device memory under a determined combined scenario can be calculated.

[0052] Since the hardware resources and data read / write configuration module 113 can realize different test scenario combinations, and then calculate the device memory bandwidth test results under each set of scenario combinations, the device memory bandwidth test results under each set of scenario combinations can be output through the device memory bandwidth output module, so as to fully understand the device memory bandwidth performance, accurately match the scenario, avoid the one-sidedness of a single test result, and directly transform the test value into a basis for actual use / optimization.

[0053] Since on-chip caches typically consist of multiple levels of storage structure, and the hardware characteristics of different levels are completely independent, targeted testing based on the specific hierarchical structure of the on-chip cache is necessary to accurately test its bandwidth. Please refer to [link / reference needed]. Figure 2 The on-chip cache bandwidth dedicated testing module 112 includes: The Level 1 cache bandwidth testing module 1121 is used to test the bandwidth of the Level 1 cache when the target storage structure is a Level 1 cache; The L2 cache bandwidth testing module 1122 is used to test the bandwidth of the L2 cache when the target storage structure is a L2 cache; The shared cache bandwidth testing module 1123 is used to test the bandwidth of the shared local cache when the target storage structure is a shared local cache.

[0054] Continuing with the GPGPU example, in GPGPU, the local shared cache is a subset of the on-chip cache functionality. And because the access scope of the local shared cache is limited, it can also be called local memory compared to the device memory (also known as global memory) mentioned above.

[0055] To better understand the complete workings of memory, please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of memory operation provided in an embodiment of the present invention.

[0056] like Figure 3 As shown, on-chip cache 3 may include: Private cache (e.g.) Figure 3 The first-level cache shown is L1 cache 31): it is exclusively used by a single computing unit 4, and is frequently reused locally by the service computing unit 4; Shared cache (e.g.) Figure 3 The L2 cache shown is 32 bytes: shared by all GPGPU cores (compute unit 4), serving as a data transfer intermediary for multiple cores; Local shared cache 33: Shared by specific thread blocks / core groups, serving small-scale inter-thread data exchange. All three are physically located within the GPGPU chip, and their core function is high-speed data caching / sharing, only differing in the scope of sharing.

[0057] like Figure 3 As shown, when testing the bandwidth of device memory (global memory) 2, during the data read and write process, when reading the first amount of data, the data read and write path is device memory 2 - vector general-purpose register (located in computing unit 4), that is, directly accessing the vector general-purpose register, without hitting L2 cache 32, L1 cache 31 and local shared cache 33, so that the bandwidth obtained by the test is the bandwidth of device memory 2.

[0058] When testing on-chip cache bandwidth, because the hardware characteristics of each level of the memory structure are independent of each other, they need to be tested independently, such as... Figure 3 As shown, when testing the bandwidth of L2 cache 32, it is necessary to ensure that data does not hit L1 cache 31 and directly accesses the vector general-purpose register so that the bandwidth test is entirely for L2 cache 32.

[0059] Therefore, the on-chip cache bandwidth dedicated test module 112 may include a dedicated test module for bandwidth testing of each level of the memory structure (such as...). Figure 2 (As shown).

[0060] like Figure 3 As shown, the target data read / write paths are different for bandwidth tests of different storage structures. The target data read / write paths can ensure that the bandwidth test is completely specific to the target storage structure. Therefore, in order to accurately test the bandwidth of different storage structures, the bandwidth-specific test module for each storage structure must be designed accordingly.

[0061] In one implementation, the Level 1 cache bandwidth dedicated testing module includes: The Level 1 Data Read / Write Path Configuration Module is used to configure the Level 1 target data read / write path that hits the Level 1 cache before testing the Level 1 cache bandwidth begins. The first-level cache data preheating module is used to execute the first read instruction to load a fixed amount of first-level second data into the first-level cache through the first-level target data read / write path; The first-level cache data read / write and timing module is used to repeatedly execute the second read instruction after a preset number of executions, iteratively read and write a fixed amount of first-level second data to the first-level cache through the first-level target data read / write path, and record the first-level read / write time. The first-level cache bandwidth test module is used to obtain the bandwidth test results of the first-level cache based on the second data volume of the first level and the first-level read / write time.

[0062] The hardware module corresponding to the first-level cache is the first-level high-speed cache (e.g., ...). Figure 3 The L1 cache shown is 31). The specific testing process for L1 cache bandwidth is as follows: First, the data from device memory to the L2 cache is preheated, and then the data from the L1 cache to the register (vgpr) is further preheated to ensure that the data can hit the L1 cache. That is, the L1 target data read and write path is configured to ensure that the data will not hit the L2 cache, device memory, or local shared cache.

[0063] like Figure 3As shown, when reading and writing data in the GPGPU, the physical location relationship between the local shared cache 33 and the L1 cache 31 makes the local shared cache 33 an upper / lower link of the non-L1 cache 31. Therefore, when performing bandwidth testing on the L1 cache 31, data preheating processing of the local shared cache 33 is not required, and it can also be ensured that the data hits the L1 cache in subsequent tests.

[0064] During testing, a read instruction is executed first to preheat a fixed amount of data (Level 1, Level 2) into the target storage structure: Level 1 cache. This ensures that the data hits the Level 1 cache and avoids cache cold start misses in the early stages of testing.

[0065] Then, a second read instruction is executed, which reads and writes data of the second data size of the first level to the first level cache through the first level target data read and write path. The execution process of the second read instruction is tested, and the clock difference before and after the second read instruction is executed can be recorded to obtain the first level read and write time. Then, the first level cache bandwidth is calculated by combining the first level second data size and the first level read and write time.

[0066] To mask and reduce the transmission delay of the timing command and the second read command, a loop program is set up outside the second read command to repeatedly execute the second read command. This reduces the error percentage by increasing the total amount of first-level second data. The loop program defines a preset number of executions, for example, between 100 and 1000.

[0067] Setting the preset execution count ensures that the loop program can be fully expanded, enabling the cyclic execution of the second read instruction. It also reduces the problem of excessive branch instruction generation due to an excessive number of loop iterations, thus minimizing errors caused by additional branch instructions. For example, if the preset execution count is too large, loop programs like for loops will increase the need to check the loop iteration count (i.e., generate branch instructions), leading to additional execution errors from the branch instructions.

[0068] In other embodiments, the secondary cache bandwidth dedicated testing module 1122 may include: The secondary data read / write path configuration module is used to configure the secondary target data read / write path that hits the secondary cache before the secondary cache bandwidth test begins. The secondary cache data preheating module is used to execute the first read instruction multiple times. Each time the first read instruction is executed, a certain amount of secondary second data is loaded into the secondary cache. The second-level cache data read / write and timing module is used to repeatedly execute the second read instruction after a preset number of executions, iteratively read and write a fixed amount of second-level second data to the second-level cache according to the second-level target data read / write path, and record the second-level read / write time; The secondary cache bandwidth testing module is used to obtain the bandwidth test results of the secondary cache based on the amount of secondary data and the secondary read / write time. Before testing the bandwidth of the second-level cache, addresses are allocated to the sub-cache modules of the second-level cache through an address interleaving mapping strategy.

[0069] For example, the configuration of the secondary target data read / write path can be implemented through instruction configuration. For instance, a read data instruction can be used to set a cache consistency policy, bypassing the L1 cache. This instruction-level control locks the specific path from device memory to the L2 cache to the computing unit. The cache consistency policy ensures that the data in the L2 cache is up-to-date after bypassing the L1 cache, making the secondary target data read / write path securely available.

[0070] The hardware module corresponding to the L2 cache is the second-level cache (such as...). Figure 3 The L2 cache shown is 32. The core hardware characteristic of the L2 cache is its multi-bank (sub-cache module, bank) parallel design. Each bank is an independent storage unit. The upper limit of the L2 cache bandwidth is determined by the parallelism of the banks. Whether the parallelism can be fully utilized depends on the precise matching of the number of banks N and the address interleaving strategy. Therefore, before testing the L2 cache bandwidth, in order to maximize the parallel memory access capability of the L2 cache and ensure bandwidth testing for the L2 cache, the hardware specification testing tool first optimizes the address allocation logic of the L2 cache.

[0071] When testing L2 cache bandwidth, it is also necessary to warm up the data from the device's memory to the L2 cache to reduce test bias caused by cold starts. During the test, the method of using two read commands is continued, and the clock difference before and after the second read command is recorded.

[0072] To hide the delay in instruction sending and instruction scheduling processing in the data read / write path when executing the first read instruction for data warm-up, a loop program (such as a for loop) with a preset number of executions can also be set outside the second read instruction to increase the amount of second-level second data and reduce the error ratio.

[0073] In some implementations, the absolute error in instruction sending and instruction scheduling in the secondary target data read / write path can be masked by increasing the number of first read instructions sent.

[0074] In one embodiment, the shared cache bandwidth dedicated testing module 1123 includes: The shared cache data path configuration module is used to configure the shared cache target data read / write path that hits the local shared cache before the local shared cache bandwidth test begins. The thread configuration module provides a thread configuration interface for users to configure the thread reading mode. The shared cache data read / write and timing module is used to execute data loading instructions multiple times, read and write a fixed amount of shared second data to the local shared cache according to the shared cache target data read / write path, and record the shared cache read / write time. The shared cache bandwidth test module is used to obtain the bandwidth test results of the local shared cache based on the shared second data volume and the shared cache read / write time.

[0075] Before testing the local shared cache bandwidth, controlling the thread read mode to reduce memory conflicts can eliminate artificial bottlenecks at the software level in advance, ensuring that all memory can work at maximum parallelism during testing.

[0076] The local shared cache bandwidth test targets the maximum data transfer rate of a thread initiating a request through a register to read / write to the local shared cache. It eliminates interference from other storage structures such as L1 / L2 caches and device memory, while also avoiding the influence of non-memory access factors such as instruction scheduling and thread synchronization. Therefore, the test method of continuously loading instructions and iteratively reading and writing local shared data creates a pure memory access scenario with full load, no conflicts, and no cross-level interference. This fully unleashes the parallel capabilities of the multiple storage banks of the local shared cache, ultimately measuring the true peak bandwidth of the register-local shared cache. This avoids the test results being distorted by irrelevant factors such as instruction scheduling, other storage levels, and synchronization overhead, ensuring that the results accurately reflect the hardware transmission capacity of the cache.

[0077] In other embodiments, when the dimension is divided into application scenarios based on the memory bandwidth hardware specifications, the application scenario is a data access scenario formed by the data read and write methods of different application operators; the memory bandwidth dedicated test module 11 may include: a scenario-based memory bandwidth dedicated test module. The scenario-based memory bandwidth testing module includes: The operator feature parsing module is used to parse the type of the target operator and determine the target data read / write method of the target operator. The configuration management module is used to determine the target memory access structure under the target data read / write mode, wherein the target memory access structure is device memory or on-chip cache; A memory access structure adaptation module is used to configure the hardware resources of the target memory access structure; The test data generation module is used to generate test data based on the target operator and the configured hardware resources; The test data read / write and timing module is used to read and write the test data to the target memory access structure and record the read / write time. The memory access bandwidth testing module is used to obtain the bandwidth test results of the target operator accessing the target memory structure under the target data read / write mode and the configured hardware resources, based on the test data and the recorded read / write time.

[0078] Optionally, the operators may include: element-wise operators (Element-wise OperationOperator), Flash Attention operators (Flash Attention: Fast and Memory-Efficient Exact Attention with IO-Awareness), convolution operators, and gemm (general eatrix multiplication) operators.

[0079] Different types of operators have different data read / write methods (either the data reading method or the data writing method of the operator). For example, element-wise operators control the number of elements accessed and the stride by simulating element-wise operations such as addition / multiplication. Their corresponding data read / write methods include both continuous and discontinuous data read / write methods. Therefore, when the target operator is determined to be an element-wise operator, different data read / write method options can be provided for the user to select the target data read / write method.

[0080] For the Flash Attention operator, which performs attention calculations on fixed dimensions (such as 8192 or 4096), the data is divided into multiple blocks and read and write in parallel within the workgroup. The position of the calculation within the workgroup is located by thread, constructing a working scenario adapted to real Flash Attention.

[0081] The convolution operator (Tiling Read) uses a data read / write method (primarily for data retrieval) that is "block-aligned contiguous + high-concurrency read-only + vector-level granularity." Its core principle is to transform large feature maps into continuous memory access streams through block division, maximizing the spatial locality of on-chip cache and the parallel capabilities of multiple memory banks. Please refer to [reference needed]. Figure 4a and Figure 4b , Figure 4a This is a schematic diagram of the data reading method of the convolution operator provided in an embodiment of the present invention. Figure 4b yes Figure 4a A magnified view of point A shown.

[0082] like Figure 4a and Figure 4bAs shown, a convolution operator read strategy is used to simulate memory access behavior (data reading method) in matrix multiplication: the memory is divided along the H (height) and W (width) dimensions by blocks in the x-direction and along the C (channels) dimensions in the y-direction. Finally, a sliding window strategy is used to pre-calculate the starting address of each thread to achieve precise control over the target memory access structure. The sliding strategy is tested in two ways: sliding over overlapping parts and sliding over non-overlapping windows.

[0083] When performing feature analysis on the gemm operator, the operator feature parsing module loads data in chunks based on the block access methods of the two matrices to be tested in the row and column directions in real-world scenarios, and sets different dimensional sizes to simulate various real-world scenarios.

[0084] For example, such as Figure 2 As shown, in the hardware specification testing tool, the memory bandwidth-specific testing module 11 can provide data read and write methods for different operators: Element-wise operator data reading method, gemm data reading method, convolution read (data reading method for convolution operator), and block interleaving write (e.g., data writing method for Flash Attention operator).

[0085] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a test result from the memory bandwidth-specific test module provided in an embodiment of the present invention.

[0086] like Figure 5 As shown, the hardware specification testing tool provided in this embodiment of the invention can support memory bandwidth testing for different storage structures under different data read / write methods. For example, it can provide test results for memory bandwidth corresponding to device memory read, device memory write, device memory copy, matrix read, matrix write, matrix copy, mapping matrix write, and tiling read.

[0087] Based on different data read / write methods and the specific storage structure accessed, memory bandwidth under different conditions can be comprehensively tested, thereby facilitating the acquisition of comprehensive test results for memory bandwidth hardware specifications.

[0088] Please continue to refer to this. Figure 1 The specialized testing module includes: a memory latency specialized testing module 12; the hardware specifications targeted by the memory latency specialized testing module 12 are memory latency hardware specifications; The memory latency testing module 12 divides the memory access data path indicated by different memory access instruction types into dimensions to test the latency of the memory access structure accessed by different memory access instructions. Before calling the memory latency testing module 12 for testing, a certain amount of data is preheated into the memory access structure corresponding to each memory access data path, and during the process of calling the memory latency testing module 12 for testing, the memory access instructions corresponding to each memory access data path are executed iteratively.

[0089] Memory access instructions uniquely and precisely associate with a specific memory access data path by specifying the address space and access attributes. Testing the latency of a memory access instruction is equivalent to testing the pure transmission latency of the path indicated by the memory access instruction, which means that the memory access latency of accessing different memory access structures can be tested.

[0090] In one embodiment, the memory latency testing module 12 may include: The target memory access data path determination module is used to provide a pre-set memory access data path test set for users to determine the target memory access data path of the target memory access instruction. The memory access instruction latency testing module is used to record the total time from the formal initiation of the read or load memory access instruction to the complete transmission of data through the first memory access path to the memory structure accessed by the read or load memory access instruction, and the data becoming available, when the target memory access data path is determined to be the first memory access data path indicated by the read or load memory access instruction; the memory access structure accessed by the read or load memory access instruction is device memory and / or shared memory and / or registers and / or constant memory; The atomic instruction latency testing module is used to record the total time from the formal initiation of the atomic memory access instruction to the complete transmission of data through the second memory access path to the memory structure accessed by the atomic memory access instruction, and the data becoming available, when the target memory access data path is determined to be the second memory access data path indicated by the atomic memory access instruction; the memory access structure accessed by the atomic memory access instruction is device memory and / or shared memory. The shared cache instruction latency test module is used to record the total time from the official initiation of the local shared cache access instruction to the complete transmission of data through the third access data path to the local shared cache structure and the availability of the data, when the target memory access data path is determined to be the third memory access data path indicated by the local shared cache access instruction. The matrix multiplication instruction latency testing module is used to record the total time from the formal initiation of the matrix multiplication instruction to the complete transmission of data through the fourth memory access path to the memory structure accessed by the matrix multiplication instruction, provided that the target memory access data path is determined to be the fourth memory access data path indicated by the matrix multiplication instruction, and the data is available. This module obtains the latency of the memory access structure accessed by the matrix multiplication instruction. The memory access structure accessed by the matrix multiplication instruction is device memory and / or shared memory and / or registers.

[0091] Specifically, when calling the atomic instruction latency test module and the shared cache instruction latency test module to perform latency tests, a thread-level synchronization barrier strategy is executed, and the number and distribution of threads are controlled; when calling the memory access instruction latency test module and the atomic instruction latency test module to perform latency tests, a fixed-point stubbing timing strategy is executed to record data read and write times.

[0092] To facilitate testing of latency for different memory access data paths, embodiments of the present invention provide a memory access data path test set, which includes memory access data paths corresponding to different types of memory access instructions, to cover various memory access structures that different types of memory access instructions may access.

[0093] Please continue to refer to this. Figure 2 The memory latency testing module 12 may include an on-chip cache latency testing module 121 and a device memory latency testing module 122. The on-chip cache latency testing module 121 is further divided into: Level 1 cache read / write latency and Level 2 cache read / write latency according to the different levels of storage structure it contains.

[0094] Since memory access instructions can include both read and write instructions, the device memory latency testing module 122 is configured with corresponding memory latency testing modules for memory access instructions of different operation directions: different read instruction latency and different write instruction latency.

[0095] For example, the memory access data path test suite may include, but is not limited to, memory access data paths of various memory access instruction types: (1) The first memory access data path for reading or loading memory access instructions, including read and write operations from memory access structures of different storage levels such as device memory, local shared cache, registers, and constant memory, and testing the latency of different basic memory access structures.

[0096] (2) The second memory access data path of atomic memory access instructions, such as the delay of loading or reading data from the target memory access structure in atomic addition or subtraction instructions, to test the delay of inter-thread contention access.

[0097] (3) The third memory access path of the local shared cache access instruction is used to test the latency of the local shared cache inside the thread block in a computing unit.

[0098] (4) The fourth memory access data path for executing matrix multiplication instructions (such as MMA (Matrix Multiply-Accumulate) / TensorCore in GPGPU) is used to evaluate the operator call latency in the underlying Tensor Core path.

[0099] Of course, in other implementations, other memory access instructions involving data migration between different storage levels may also be included, all of which can determine the corresponding memory access data path as part of the memory access data path test set, and thus test the corresponding memory latency.

[0100] To improve the stability and accuracy of memory latency test results, the following strategies can be selectively adopted when calling the above modules, depending on the specific memory access data path being tested: (1) The combination of each memory access data path and the corresponding type of memory access instruction runs with a high number of iterations to reduce the error caused by jitter; (2) Introduce a warm-up phase before testing memory latency to ensure that the data has been loaded into the target memory access structure, such as the L1 cache or register level, to avoid the impact of cold start; (3) Use thread-level synchronization barriers to ensure the timing consistency of test sample execution; (4) Control the number and distribution of test threads to eliminate the impact of wavefront context switching on latency; (5) For access to memory data paths with different memory access structures (such as reading data from L1 cache, L2 cache, and device memory), the latency is accurately measured by a fixed-point piling timing method (such as recording the start and end times by a counter).

[0101] The aforementioned memory access instruction latency testing modules, atomic instruction latency testing modules, shared cache instruction latency testing modules, and matrix multiplication instruction latency testing modules can all adapt to the first and second optimization strategies to ensure reliable implementation of the test initialization process.

[0102] The latter three optimization strategies can be selected based on the specific memory latency testing module and the memory access data path targeted by it. The appropriate memory access data path for testing can be selected.

[0103] The memory access data path test set can provide accurate underlying memory latency data support for chip architecture designers, driver developers, and upper-level algorithm optimizers.

[0104] Please continue to refer to this. Figure 1 The specialized testing module 1 may include: a computing power specialized testing module 13; the hardware specifications targeted by the computing power specialized testing module 13 are computing power hardware specifications; the computing power specialized testing module 13 performs tests around different instruction precision dimensions; The computing power testing module 13 may include: The instruction precision determination module provides multiple different instruction precisions so that users can determine the target instruction precision based on current testing requirements. The computational data structure construction module is used to construct the target data structure used by the target computation based on the target computation to be performed. The computing resource configuration module provides a computing resource configuration interface, allowing users to configure the corresponding target computing resources according to the computing requirements of the target operation. The computing power testing module is used to compute the target data structure using the configured target computing resources under the target instruction precision, and obtain the corresponding actual computing power peak.

[0105] When designing the computing power test module 13, it can be designed based on the core logic of computing power, namely, computing power is the coupling result of "instruction precision + operation type + data structure + resource configuration", to ensure that the test results of computing power hardware specifications have practical significance.

[0106] Please continue to refer to this. Figure 2 In this embodiment of the invention, multiple instruction precisions are provided for the computing power-specific testing module 13, such as... Figure 2 The precision of each instruction, such as FP32, FP16, BF16, and INT8, is shown.

[0107] Taking matrix multiplication, which is performed using a matrix multiplication-addition data path, as an example, the computing power testing module 13 can simulate real-world load scenarios in typical deep learning and high-performance computing to test the computing power hardware specifications. The specific testing process is as follows: Determine the precision of the target instruction: This can be done... Figure 2 The various instruction precisions covered are specified, such as FP32, FP16, BF16, and INT8. For the matrix-type instructions corresponding to the target operation, different instruction precisions are selected, and the hardware execution efficiency under different instruction precisions is tested.

[0108] Construct the target data structure for target computation based on the actual scenario: For matrix operations, two matrices A and B, and a matrix C' (formed in device memory) are constructed. After performing the multiplication calculation of matrix A and matrix B through MMA or SIMD instructions, the matrix is ​​added to matrix C', realizing the standard matrix multiplication and addition process C' = A × B + C'.

[0109] At the same time, the target computing resources are configured in parallel scheduling. During this process, the user can schedule and configure computing resources, such as reasonably configuring thread groups, the number of warps, and the number of matrix blocks executed in each block, to maximize the mobilization of computing resources.

[0110] To facilitate a clear and intuitive demonstration of the differences in instruction execution latency and throughput under different instruction precisions, the actual peak computing power obtained from tests under different instruction precisions can be recorded separately. At the same time, the theoretical peak computing power under different instruction precisions can be determined, which facilitates a clear comparison between the theoretical peak computing power and the actual peak computing power for subsequent hardware characteristic analysis and software optimization.

[0111] Please continue to refer to this. Figure 1 The special testing module may include: a power consumption special testing module 14; the hardware specifications targeted by the power consumption special testing module 14 are power consumption hardware specifications; the power consumption special testing module 14 performs tests around the dimension of extreme power consumption scenarios; The power consumption-specific testing module 14 may include: The load construction module is used to construct the maximum power consumption scenario; The power consumption test module is used to run the accelerated computing chip under the maximum power consumption scenario and test the upper limit of the peak power consumption of the accelerated computing chip.

[0112] The power consumption test module 14 can test the power consumption stability and thermal management capability of the accelerated computing chip under high load conditions.

[0113] Specifically, a maximum power consumption scenario can be constructed using a load testing module. For example, this can be achieved through continuous high-density TensorCore instruction execution and concurrent read / write operations on device memory and local shared cache. Alternatively, a maximum power consumption scenario can be constructed using thread resource saturation testing, such as keeping all computing units, memory channels, and TensorCores active.

[0114] After constructing the maximum power consumption scenario, the peak upper limit of the power consumption of the accelerated computing chip can be observed.

[0115] In one implementation, external tools, such as a monitor, can be used to monitor and view the power consumption in real time.

[0116] In addition, to facilitate a more intuitive display of the power consumption hardware specifications during testing, a graphing tool can be used to plot the power consumption test data monitored over a period of time, and the plotting results can be stored or displayed. This allows for further analysis of power consumption and frequency fluctuations based on the stored or displayed content.

[0117] To facilitate the demonstration of test results for power consumption hardware specifications, please refer to [link / reference]. Figure 6a , Figure 6b , Figure 6c and Figure 6d , Figure 6a This is a schematic diagram of a test result from the power consumption-specific test module provided in an embodiment of the present invention. Figure 6b This is another schematic diagram of the test results of the power consumption-specific test module provided in this embodiment of the invention. Figure 6c This is a schematic diagram of another test result from the power consumption-specific test module provided in this embodiment of the invention. Figure 6d This is another test result diagram of the power consumption-specific test module provided in this embodiment of the invention.

[0118] Figures 6a-6d The horizontal axis represents time, and the vertical axis represents power consumption.

[0119] Figure 6a This displays the GPU core voltage test results from the power consumption testing module. Figure 6b This display shows the voltage test results of the video memory (first device memory 20) tested by the power consumption test module. Figure 6c The results shown are the overall card voltage (GPU core + VRAM memory) test results from the power consumption testing module. Figure 6d The results shown are the voltage test results of the video memory (second device memory 21) tested by the power consumption test module.

[0120] It allows for a direct view of the power consumption test results of different modules, and also enables comparison of the power consumption test results of different modules over the same period of time, providing an analytical basis for accelerating the design and improvement of computing chips.

[0121] In one embodiment, the hardware specification testing tool is implemented using C++ language combined with assembly language; the hardware specification testing tool supports testing of the same type of accelerated computing chips produced by different manufacturing sources; the accelerated computing chip is a general-purpose computing graphics processor, or a field-programmable gate array, or a tensor processing unit.

[0122] Building hardware specification testing tools using a combination of C++ and assembly language allows for lower-level instruction-level control, enabling direct invocation of low-level hardware instructions. This allows for precise scheduling and performance measurement of specific instruction sequences, improving the granularity and accuracy of testing, and is suitable for instruction-level microarchitecture analysis.

[0123] As can be seen, the hardware specification testing tool provided in this embodiment of the invention has been finely designed for specialized testing modules for different hardware specifications, and provides configuration modules that can be flexibly configured by the user. For example, the hardware resource and data read / write mode configuration module in the memory bandwidth specialized testing module; the shared cache data path configuration module and thread configuration module in the shared cache bandwidth specialized testing module, etc., can support the optimization of resource binding and scheduling mechanisms, and can realize the setting of target data results under different instruction precision, and the precise control of instruction arrangement, thereby accurately controlling the arrangement order of instructions in the execution unit, avoiding scheduling uncertainty from interfering with the measurement results, and thus more accurately evaluating the behavior of hardware under specific resource allocation.

[0124] Meanwhile, the hardware specification testing tool provided in this embodiment of the invention also covers a variety of memory access and caching strategies, achieving more comprehensive test coverage. It supports the configuration of various test scenarios (such as global memory access, local shared cache access, L1 / L2 cache access, matrix instruction operations, etc.) and caching strategies (such as configuring the target data access path that hits the target memory access result). Through the construction of refined test scenarios, it comprehensively tests memory latency test specifications.

[0125] Furthermore, the hardware specification testing tool provided in this embodiment of the invention supports cross-architecture testing capabilities (i.e., supports testing of the same type of accelerated computing chips produced by different manufacturing sources), which facilitates horizontal comparison and trend analysis.

[0126] The hardware specification testing framework provided in this invention embeds multiple different assembly language methods, exhibiting high portability and the ability to generate instruction set test code (hardware specification testing tool code) for different GPGPU architectures. Therefore, by maintaining consistent test logic, cross-architecture consistent performance evaluation and data comparison can be achieved, facilitating architecture optimization and chip iteration evaluation.

[0127] This invention also provides a hardware specification testing method, which is applied to the hardware specification testing tool described in any of the foregoing embodiments.

[0128] Please refer to Figure 7 , Figure 7 This is a schematic flowchart of a hardware specification testing method provided in an embodiment of the present invention, wherein the method is applied to the hardware specification testing tool described in any of the foregoing embodiments.

[0129] like Figure 7 The method includes the following steps: Step S110: Determine the accelerated computing chip to be tested.

[0130] Step S120: Invoke the special test module of the hardware specification test tool.

[0131] Step S130: Based on the set of test items executed by the activated special test module, the hardware specifications of the accelerated computing chip to be tested are tested in at least one dimension to obtain the test results.

[0132] Different test sets target different hardware specifications to cover all hardware specifications of the accelerated computing chip.

[0133] As can be seen, the technical solution provided by the embodiments of the present invention includes multiple specialized testing modules in the hardware specification testing tool. Each specialized testing module tests a specific hardware specification of the accelerated computing chip, and different specialized testing modules target different hardware specifications to cover all hardware specifications of the accelerated computing chip. Therefore, the sum of the hardware specifications targeted by each specialized testing module is for the complete hardware specifications of the accelerated computing chip. Thus, the hardware specification testing tool constructed by the embodiments of the present invention can integrate the testing of all hardware specifications of the accelerated computing chip. Secondly, each specialized testing module tests from different dimensions involved in its targeted hardware specification, thereby generating test results from multiple dimensions for a single hardware specification. Since each dimension corresponds to a quantifiable performance item of the targeted hardware specification in a specific testing direction, multiple dimensions collaboratively cover the overall performance characteristics of the targeted hardware specification, thus improving the comprehensiveness of the test results for each hardware specification. Simultaneously, since each dimension can cover the overall performance characteristics of the hardware specification, the test results obtained from different dimensions are interrelated, thereby fully reflecting the comprehensive testing situation of a hardware specification. As can be seen, the hardware specification testing tool provided in this embodiment of the invention can achieve simultaneous multi-indicator, correlation analysis, and unified benchmarking, enabling a comprehensive evaluation of hardware specifications. This avoids the limitations of testing only a single or partial hardware specification, while quickly identifying problems and improving testing efficiency. It better meets the comprehensive analytical needs of real-world scenarios, providing more valuable test results in situations requiring a complete understanding of the hardware. Ultimately, it achieves integrated and complete hardware specification testing of accelerated computing chips, enhancing the comprehensiveness of hardware specification testing tools.

[0134] This invention also provides an electronic device, including a memory and a processor. The memory stores a program, and the processor calls the program stored in the memory to execute the hardware specification testing method as described in the foregoing embodiments.

[0135] This invention also provides a storage medium storing a program that, when executed, implements the hardware specification testing method as described in the foregoing embodiments.

[0136] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the hardware specification testing method as described in the foregoing embodiments.

[0137] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A hardware specification testing tool, characterized in that, include: Multiple specialized testing modules; A dedicated test module tests a hardware specification of the accelerated computing chip; Different specialized test modules target different hardware specifications to cover all hardware specifications of the accelerated computing chip; When testing a target hardware specification by scheduling one or more of the aforementioned specialized testing modules, the scheduled specialized testing modules test the target hardware specification in at least one dimension; wherein, one dimension corresponds to a quantifiable performance item of the target hardware specification in a specific testing direction, and multiple dimensions work together to cover the overall performance characteristics of the target hardware specification.

2. The hardware specification testing tool as described in claim 1, characterized in that, The specialized testing module includes: a memory bandwidth specialized testing module; the hardware specifications targeted by the memory bandwidth specialized testing module are memory bandwidth hardware specifications; When scheduling the memory bandwidth dedicated test module to test the memory bandwidth hardware specifications, the test is carried out according to the bandwidth test strategies adapted to different dimensions; wherein, the dimensions corresponding to the memory bandwidth dedicated test module are divided based on the hardware modules in the accelerated computing chip associated with the memory bandwidth hardware specifications, or based on the application scenarios of the memory bandwidth hardware specifications.

3. The hardware specification testing tool as described in claim 2, characterized in that, When the dimension is used to divide the hardware modules in the accelerated computing chip based on the memory bandwidth hardware specifications, the hardware modules include: device memory and on-chip cache; the memory bandwidth dedicated testing module includes: a device memory bandwidth dedicated testing module and an on-chip cache bandwidth dedicated testing module; the device memory bandwidth dedicated testing module executes the device memory bandwidth testing strategy corresponding to the device memory dimension; the on-chip cache bandwidth dedicated testing module executes the on-chip cache bandwidth testing strategy corresponding to the on-chip cache dimension; The device memory bandwidth testing strategy is as follows: based on different combinations of hardware resource configuration methods and data read / write methods, and with a fixed amount of first data, the device memory bandwidth is tested by combining the read / write time of reading the first data in different combinations of scenarios. The on-chip cache bandwidth testing strategy is as follows: based on different combinations of hardware resource configuration methods and data read / write methods, and combined with the target storage structure in the on-chip cache currently being tested, the target data read / write path for reading and writing the target storage structure is determined. On the target data read / write path, the bandwidth of the target storage structure is tested in different combinations of scenarios by using a second amount of data to read and write and the read / write time for reading and writing the second amount of data.

4. The hardware specification testing tool as described in claim 3, characterized in that, The memory bandwidth testing module also includes: The hardware resource and data read / write mode configuration module is used to provide a resource configuration interactive interface and a data read / write mode determination interactive interface. The resource configuration interactive interface is used for users to configure hardware resources according to current test requirements; the data read / write mode determination interactive interface is used for users to determine the target data read / write mode. The device memory bandwidth testing module includes: The test parameter configuration module is used to configure the first data volume, which is greater than the total capacity of the on-chip cache. The device memory data read / write and timing module is used to read and write the first amount of data configured by the test parameter configuration module, and record the first read / write time of the first amount of data. The device memory bandwidth calculation module is used to obtain the bandwidth test results of the device memory under the scenario of the configured hardware resources and target data read and write method combination, based on the first read and write time and the first data volume; The device memory bandwidth output module is used to output the bandwidth test results of the device memory under different combinations of hardware resources and data read / write methods.

5. The hardware specification testing tool as described in claim 4, characterized in that, The on-chip cache bandwidth testing module includes: The Level 1 cache bandwidth testing module is used to test the bandwidth of the Level 1 cache when the target storage structure is a Level 1 cache. The secondary cache bandwidth testing module is used to test the bandwidth of the secondary cache when the target storage structure is a secondary cache. The shared cache bandwidth testing module is used to test the bandwidth of the shared local cache when the target storage structure is a shared local cache.

6. The hardware specification testing tool as described in claim 5, characterized in that, The dedicated test module for first-level cache bandwidth includes: The Level 1 Data Read / Write Path Configuration Module is used to configure the Level 1 target data read / write path that hits the Level 1 cache before testing the Level 1 cache bandwidth begins. The first-level cache data preheating module is used to execute the first read instruction to load a fixed amount of first-level second data into the first-level cache through the first-level target data read / write path; The first-level cache data read / write and timing module is used to repeatedly execute the second read instruction after a preset number of executions, iteratively read and write a fixed amount of first-level second data to the first-level cache through the first-level target data read / write path, and record the first-level read / write time. The first-level cache bandwidth testing module is used to obtain the bandwidth test results of the first-level cache based on the second data volume of the first level and the first-level read / write time.

7. The hardware specification testing tool as described in claim 5, characterized in that, The dedicated test module for secondary cache bandwidth includes: The secondary data read / write path configuration module is used to configure the secondary target data read / write path that hits the secondary cache before the secondary cache bandwidth test begins. The secondary cache data preheating module is used to execute the first read instruction multiple times. Each time the first read instruction is executed, a certain amount of secondary second data is loaded into the secondary cache. The second-level cache data read / write and timing module is used to repeatedly execute the second read instruction after a preset number of executions, iteratively read and write a fixed amount of second-level second data to the second-level cache according to the second-level target data read / write path, and record the second-level read / write time; The secondary cache bandwidth testing module is used to obtain the bandwidth test results of the secondary cache based on the amount of secondary data and the secondary read / write time. Before testing the bandwidth of the second-level cache, addresses are allocated to the sub-cache modules of the second-level cache through an address interleaving mapping strategy.

8. The hardware specification testing tool as described in claim 5, characterized in that, The shared cache bandwidth testing module includes: The shared cache data path configuration module is used to configure the shared cache target data read / write path that hits the local shared cache before the local shared cache bandwidth test begins. The thread configuration module provides a thread configuration interface for users to configure the thread reading mode. The shared cache data read / write and timing module is used to execute data loading instructions multiple times, read and write a fixed amount of shared second data to the local shared cache according to the shared cache target data read / write path, and record the shared cache read / write time. The shared cache bandwidth test module is used to obtain the bandwidth test results of the local shared cache based on the shared second data volume and the shared cache read / write time.

9. The hardware specification testing tool as described in claim 2, characterized in that, When the dimension is used to divide application scenarios based on the memory bandwidth hardware specifications, the application scenario is a data access scenario formed by the data read and write methods of different application operators; The memory bandwidth testing module includes: a scenario-based memory bandwidth testing module; The scenario-based memory bandwidth testing module includes: The operator feature parsing module is used to parse the type of the target operator and determine the target data read / write method of the target operator. The configuration management module is used to determine the target memory access structure under the target data read / write mode, wherein the target memory access structure is device memory or on-chip cache; A memory access structure adaptation module is used to configure the hardware resources of the target memory access structure; The test data generation module is used to generate test data based on the target operator and the configured hardware resources; The test data read / write and timing module is used to read and write the test data to the target memory access structure and record the read / write time. The memory access bandwidth testing module is used to obtain the bandwidth test results of the target operator accessing the target memory structure under the target data read / write mode and the configured hardware resources, based on the test data and the recorded read / write time.

10. The hardware specification testing tool as described in claim 1, characterized in that, The specialized testing module includes: a memory latency specialized testing module; the hardware specifications targeted by the memory latency specialized testing module are memory latency hardware specifications; The memory latency testing module divides the memory access data path indicated by different memory access instruction types into dimensions to test the latency of the memory access structure accessed by different memory access instructions. Before calling the memory latency testing module, a certain amount of data is preheated into the memory access structure corresponding to each memory access data path. During the process of calling the memory latency testing module, the memory access instructions corresponding to each memory access data path are executed iteratively.

11. The hardware specification testing tool as described in claim 10, characterized in that, The memory latency testing module includes: The target memory access data path determination module is used to provide a pre-set memory access data path test set for users to determine the target memory access data path of the target memory access instruction. The memory access instruction latency testing module is used to record the total time from the formal initiation of the read or load memory access instruction to the complete transmission of data through the first memory access path to the memory structure accessed by the read or load memory access instruction, and the data becoming available, when the target memory access data path is determined to be the first memory access data path indicated by the read or load memory access instruction; the memory access structure accessed by the read or load memory access instruction is device memory and / or shared memory and / or registers and / or constant memory; The atomic instruction latency testing module is used to record the total time from the formal initiation of the atomic memory access instruction to the complete transmission of data through the second memory access path to the memory structure accessed by the atomic memory access instruction, and the data becoming available, when the target memory access data path is determined to be the second memory access data path indicated by the atomic memory access instruction; the memory access structure accessed by the atomic memory access instruction is device memory and / or shared memory. The shared cache instruction latency test module is used to record the total time from the official initiation of the local shared cache access instruction to the complete transmission of data through the third access data path to the local shared cache structure and the availability of the data, when the target memory access data path is determined to be the third memory access data path indicated by the local shared cache access instruction. The matrix multiplication instruction latency testing module is used to record the total time from the formal initiation of the matrix multiplication instruction to the complete transmission of data through the fourth memory access path to the memory structure accessed by the matrix multiplication instruction, provided that the target memory access data path is determined to be the fourth memory access data path indicated by the matrix multiplication instruction, and the data is available. This module obtains the latency of the memory access structure accessed by the matrix multiplication instruction. The memory access structure accessed by the matrix multiplication instruction is device memory and / or shared memory and / or registers.

12. The hardware specification testing tool as described in claim 1, characterized in that, The specialized testing module includes: a computing power specialized testing module; the hardware specifications targeted by the computing power specialized testing module are computing power hardware specifications; the computing power specialized testing module performs tests around different instruction precision dimensions; The computing power-specific testing module includes: The instruction precision determination module provides multiple different instruction precisions so that users can determine the target instruction precision based on current testing requirements. The computational data structure construction module is used to construct the target data structure used by the target computation based on the target computation to be performed. The computing resource configuration module provides a computing resource configuration interface, allowing users to configure the corresponding target computing resources according to the computing requirements of the target operation. The computing power testing module is used to compute the target data structure using the configured target computing resources under the target instruction precision, and obtain the corresponding actual computing power peak.

13. The hardware specification testing tool as described in claim 1, characterized in that, The specialized testing module includes: a power consumption specialized testing module; the hardware specifications targeted by the power consumption specialized testing module are power consumption hardware specifications; the power consumption specialized testing module conducts tests around the dimension of extreme power consumption scenarios; The power consumption-specific testing module includes: The load construction module is used to construct the maximum power consumption scenario; The power consumption test module is used to run the accelerated computing chip under the maximum power consumption scenario and test the upper limit of the peak power consumption of the accelerated computing chip.

14. The hardware specification testing tool as described in claim 1, characterized in that, The hardware specification testing tool is implemented using C++ and assembly language; the hardware specification testing tool supports testing of the same type of accelerated computing chips produced by different manufacturing sources; the accelerated computing chip is a general-purpose computing graphics processor, or a field-programmable gate array, or a tensor processing unit.

15. A hardware specification testing method, characterized in that, The method, applied to the hardware specification testing tool as described in any one of claims 1-14, comprises: Identify the accelerated computing chip to be tested; Call at least one specialized test module of the hardware specification testing tool; a specialized test module is for one hardware specification of the accelerated computing chip under test, and different specialized test modules are for different hardware specifications to cover all hardware specifications of the accelerated computing chip. Based on the activated specialized testing module, at least one dimension of the targeted hardware specification is tested to obtain the test results; one dimension corresponds to the quantifiable performance item of the targeted hardware specification in a specific testing direction, and multiple dimensions work together to cover the overall performance characteristics of the targeted hardware specification.

16. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a program, and the processor calling the program stored in the memory to execute the hardware specification testing method as described in claim 15.

17. A storage medium, characterized in that, The storage medium stores a program that, when executed, implements the hardware specification testing method as described in claim 15.

18. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the hardware specification testing method as described in claim 15.

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