An FPGA-based DFM Pattern Match hardware accelerator and method
By using an FPGA-based DFM Pattern Match hardware accelerator and employing parallel computing and streaming processing methods, the problem of high computational complexity in large-scale integrated circuit layout data processing is solved, achieving efficient pattern matching and accelerating the DFM Pattern Match process.
Patent Information
- Application Number
- CN202610515529.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-18
- Publication Date
- 2026-07-14
AI Technical Summary
Existing DFM Pattern Matching methods have high computational complexity in processing large-scale integrated circuit layout data, resulting in high consumption of computing resources and slow matching speed, becoming a performance bottleneck in the field of electronic design automation.
The DFM Pattern Match hardware accelerator based on FPGA is adopted. Through the collaborative work of the data distribution module, hash calculation module, hash comparison module, candidate FIFO, target region generation module, edge filtering module and precise matching module, parallel computing and streaming processing are achieved, reducing the number of invalid precise geometric verifications and improving matching efficiency.
It significantly improves pattern matching speed, maintains high throughput and low latency, accelerates the matching process of large-scale layout data, adapts to complex patterns of different process nodes, and improves the overall design verification efficiency.
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Figure CN122389774A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of hardware-accelerated electronic design automation, and in particular to an FPGA-based DFMPattern Match hardware accelerator and method thereof. Background Technology
[0002] As integrated circuit manufacturing processes continue to advance towards advanced process nodes, the interaction between layout geometry and manufacturing processes such as lithography and etching becomes increasingly complex. Some local geometries are prone to forming lithographic hotspots or other manufacturing defects during the manufacturing process, thus affecting chip manufacturability and final yield. To identify potential manufacturing risks in advance during the design phase, modern electronic design automation (EDA) tools have introduced Design for Manufacturability (DFM) analysis techniques on top of traditional physical verification (PV). Among these, pattern matching technology, by searching for geometric structures in the layout similar to known hotspot patterns and comparing them with a pre-established pattern library, identifies critical areas that may affect chip yield and has become an important component of the physical verification process.
[0003] Existing DFM Pattern Matching methods are typically implemented on general-purpose processors (CPUs) or graphics processing units (GPUs). They detect hotspots by traversing the geometric data in the layout and matching detected local geometric structures one by one with templates in a pattern library. However, with the development of advanced process nodes, the scale of integrated circuit layouts continues to expand. A single chip may contain a huge number of polygonal structures and billions of geometric edges. At the same time, the number of hotspot patterns in the pattern library is also constantly increasing, reaching tens of thousands or even more in some industrial applications. This makes the pattern matching process require processing massive amounts of geometric data and performing large-scale template comparisons, resulting in a significant increase in computational complexity.
[0004] In traditional software implementation frameworks, pattern matching often consumes significant computational resources and runtime. When processing large-scale layout data, the matching process can easily become a performance bottleneck in the physical verification process due to limitations in data access efficiency and parallel computing capabilities imposed by general-purpose processor architectures, thus impacting overall design verification efficiency. Therefore, how to leverage hardware parallel computing capabilities to accelerate the DFM Pattern Match process and improve the matching efficiency of large-scale layout data has become a crucial technical problem urgently needing to be solved in the field of electronic design automation. Summary of the Invention
[0005] This invention proposes an FPGA-based DFM Pattern Match hardware accelerator and method, which can be used for efficient pattern matching of circuit layouts in integrated circuit physical verification, solving the problems of large computational load and slow matching speed of traditional pattern matching methods.
[0006] The present invention adopts the following technical solution.
[0007] An FPGA-based DFM Pattern Match hardware accelerator is provided to achieve high throughput and low latency acceleration of the DFM Pattern Match process. The accelerator includes:
[0008] The data distribution module is used to receive and group the buffered streaming input layout edge data, and send different groups of edge data to the hash calculation module in parallel; that is, it is used to group the input layout edge data and send different edge data to the hash calculation module in parallel.
[0009] The hash calculation module is used to perform parallel directional bucket partitioning and calculate the corresponding hash value for each edge based on the relative geometric position of the edge data and the selected anchor polygon; that is, it is used to calculate the directional bucket and hash value in parallel based on the relative geometric position of the edge and the selected anchor polygon.
[0010] The hash comparison module is used to compare the hash values of each bucket in parallel with the hash value of the target pattern, and extract matching items to generate candidate items through the priority encoder; that is, it is used to compare the calculated hash values of different buckets in parallel with the hash features of the target pattern, and extract matching items through the priority encoder.
[0011] Candidate FIFO is used to cache candidate matches to decouple the pre-screening stage from the precise geometric verification stage; that is, it is used to store pre-screened matches and decouple the pre-screening stage from the precise geometric verification stage.
[0012] The target region generation module is used to transform the boundary of the target pattern to the layout coordinate system according to the geometric parameters of the candidate, so as to obtain the target search region; that is, it is used to transform the boundary of the target pattern to the layout coordinate system according to the geometric transformation parameters in the matching item to obtain the target search region.
[0013] The edge filtering module is used to quickly filter out all edges located in the target search area from the map.
[0014] The precise matching module is used to map the edges output by the edge filtering module to the target pattern coordinate system and perform parallel comparison with each edge of the target pattern to determine whether the target search area is consistent with the target pattern.
[0015] The data distribution module includes a data loading unit, an edge storage array, and an address calculation unit. The data loading unit is used to receive streaming edge data and perform grouping processing. The edge storage array is used to store the data transmitted by the data loading unit. The address calculation unit is used to read edge data from the edge storage array in parallel and send the reading result to the hash calculation module.
[0016] like Figure 1 As shown, the accelerator also includes an HBM interface, a RAM array, and a pre-stored target pattern storage unit; the HBM interface is simultaneously connected to the data distribution module and the RAM array, and simultaneously receives the streaming input layout edge data; the hash calculation module is connected to the hash comparison module; the hash comparison module is connected to the pre-stored target pattern storage unit, and is connected to the target region generation module through a candidate FIFO; the edge filtering module is bidirectionally connected to the RAM array to read edge data; the precise matching module is connected to the edge filtering module, the pre-stored target pattern storage unit, and the HBM interface to complete the final matching verification and result feedback.
[0017] like Figure 2 The diagram illustrates a flowchart of a hardware accelerator operation method for DFM Pattern Match based on FPGA. Edge data from the layout is first received and cached by the data distribution module, then sent to the hash calculation module to complete directional bucket partitioning and hash value generation. The hash comparison module performs parallel comparisons of the generated hash signature with the hash of the target pattern to obtain candidate matches and writes them into the candidate FIFO. The target region generation module then sequentially retrieves candidate matches from the candidate FIFO and calculates the corresponding target search region. The edge filtering module then reads and filters relevant edges from the RAM array based on the search region and sends the filtering results to the precise matching module. The precise matching module then performs coordinate mapping and parallel comparisons on the edges to determine whether the candidate matches. The entire process is driven by the transfer of data between modules, with each module working collaboratively to achieve a fully streaming hardware-accelerated matching process from pre-screening to precise verification.
[0018] The hash calculation module includes multiple parallel hash processing units and aggregation units;
[0019] The hash processing unit is used to compare the anchor point polygon hash signature with the pre-stored template hash signature in parallel according to the direction bucket, and extract the matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items, that is: calculate the direction bucket and local hash value of the edge based on the relative geometric relationship between the edge and the anchor point polygon.
[0020] The aggregation unit is used to receive the local hash values output by each hash processing unit, and accumulate the local hash values in the same direction bucket to generate the hash signature of the anchor point polygon.
[0021] like Figure 3 The diagram shows the block structure of the data distribution module. The data loading unit is responsible for receiving input edge data. The input edges are pre-divided into several batches based on their spatial position in the layout. Edges within the same batch are arranged in ascending order according to their polygon IDs and written to the current storage array in sequence: the first edge is written to address 0 of BRAM1, the second edge is written to address 0 of BRAM2, ..., the nth edge is written to address 0 of BRAMn; the (n+1)th edge is written to address 1 of BRAM1, and so on. During the loading process, it is simultaneously checked whether the number of edges of the polygon to which each edge belongs is consistent with the number of edges of the target mode anchor point polygon. If they are consistent and the polygon has not yet been recorded, it is written to the global BRAM. The address generation unit is responsible for generating the read address.
[0022] When the edge data of the same batch is fully loaded, the polygon of each record is retrieved sequentially from the global BRAM, and for that polygon, n edges are read in parallel from the local BRAM array in batches, so that the polygon and all the edges of the records in this batch are hashed sequentially; after completion, the process switches to the next polygon until all polygons in the batch have been processed; the storage array adopts a ping-pong buffer structure to achieve continuous streaming processing.
[0023] The hash comparison module is used to perform parallel comparison of the anchor point polygon hash signature with the pre-stored template hash signature by direction bucket, and extract matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items.
[0024] like Figure 4 The diagram illustrates the principle of the hash calculation module in calculating directional buckets and local hash values based on anchor point polygons. When calculating directional buckets and local hash values based on anchor point polygons, the hash calculation module, for each target pattern's hash signature calculation, selects a polygon in the target pattern as the anchor point polygon. Based on the positions of other edges relative to the anchor point polygon, these edges are divided into three different directional buckets (right, bottom, and bottom right). The geometric offset of their endpoints relative to the reference point is calculated, and the offsets are accumulated to obtain the local hash value.
[0025] In the specific implementation, for each edge, first obtain its endpoint coordinates (x1, y1) and (x2, y2), and then use the reference point (x1, y1) of the anchor polygon as the reference point. a ,y a Using x1 as a reference, calculate the offset (dx1, dy1) of the edge endpoints relative to the reference point = (x1 - x) / dy1. a ,y1-y a ) and (dx2,dy2)=(x2-x a ,y2-y aBased on the endpoint offsets (dx1, dy1) and (dx2, dy2), the spatial orientation of the edge relative to the anchor polygon is determined, and the edge is assigned to a preset direction bucket. Then, the endpoint offsets are accumulated to calculate the local hash code of the edge. The local hash values of each edge are accumulated within the same direction bucket to generate the direction hash value of the anchor polygon. The local hash values of the same direction bucket calculated by all hash processing units are accumulated to obtain the direction hash. Finally, the overall hash signature {H} of the anchor polygon is obtained. R H D H RD};
[0026] During the matching phase, the polygons in the layout calculate signatures in the same way and compare them with the target pattern library. Since hashing is based on the relative geometry of anchor points, it remains invariant to rotation, mirroring, and translation. To support rotation and mirroring, the direction buckets are expanded to eight: left, top-left, top, top-right, right, bottom-right, bottom, and bottom-left; changes between directions are implemented through simple index remapping, for example, a 90° rotation maps (right, bottom, bottom-right) to (bottom, left, bottom-left).
[0027] This accelerator employs a two-stage pipeline architecture, such as Figure 1 As shown, the two stages are the pre-screening stage and the precise matching stage. The former deals with large-scale edge data and requires high-throughput parallel screening; the latter processes a smaller amount of data but requires strict geometric verification of each data item, resulting in a long calculation cycle. To avoid the high-concurrency processing of the front end being hindered by the time consumption of the back end, this accelerator design introduces a FIFO buffer queue between the two stages to achieve task decoupling and load balancing. In the pre-screening stage, candidate regions are written into the FIFO, and in the precise matching stage, they are read on demand for verification, so that the front end keeps running in a streaming manner and avoids pipeline blockage.
[0028] like Figure 5 The diagram shows a K-way edge data cache RAM array. During accelerator operation, the RAM array stores edge data. Each batch of edge data is loaded into this RAM array simultaneously when it is loaded into the data distribution module. The edge filtering module reads edge data line by line from one of the RAMs based on the target search area and filters out edges located within that area. If only a traditional two-way ping-pong RAM is used, pipeline congestion will occur when the next batch of data is loaded during the pre-filtering stage while the exact matching process is still processing the previous batch. This invention extends the ping-pong structure to a K-way RAM array, allowing flexible switching between write and read paths across multiple RAMs. This mitigates congestion caused by differences in processing speed across stages. As the value of K increases and the candidate FIFO depth increases, pipeline congestion can be effectively alleviated or even completely eliminated.
[0029] The FPGA-based DFM Pattern Match hardware acceleration method uses the FPGA-based DFMP Pattern Match hardware accelerator described above and includes the following steps;
[0030] Step 1) The data distribution module receives the input map edge data and groups and caches it, while storing the polygon information to which the edge belongs, and sends each group of data to the hash calculation module in parallel;
[0031] Step 2) The hash calculation module calculates the direction bucket and hash value of each edge relative to the anchor polygon in parallel, generating the hash signature of the anchor polygon;
[0032] Step 3) The hash comparison module performs a parallel comparison between the anchor polygon hash signature and the target pattern hash signature to generate candidate matches and their geometric transformation parameters;
[0033] Step 4) Cache candidate matches in a candidate FIFO to decouple the pre-screening stage from the precise geometric verification.
[0034] Step 5) The target region generation module transforms the target pattern boundary to the layout coordinate system according to the geometric transformation parameters of the candidate matching items to obtain the target search region;
[0035] Step 6) The edge filtering module filters out edges located within the target search area from the edge data and passes the filtering results to the precise matching module;
[0036] Step 7) The precise matching module performs coordinate mapping on the filtered edges and compares them with the target pattern edge set to determine the matching result.
[0037] In step 7, the specific processing method of the precise matching module is as follows: the edge filtering module outputs one edge to the precise matching module every cycle; the precise matching module maps the received edge to the target pattern coordinate system and performs parallel comparison with each edge of the target pattern; at the same time, it counts the number of edges that have been successfully matched for the current candidate matching item, and when the number of successfully matched edges is equal to the total number of edges of the target pattern, the candidate matching item is determined to be successful; when any required edge comparison fails, the current candidate matching is immediately terminated and the next candidate is switched to, and the matching count is reset to process the next candidate.
[0038] When the precise matching module maps the received edges to the target pattern coordinate system, it first performs coordinate transformation on the received edges according to the geometric transformation parameters in the candidate matching items. The transformation includes translation and rotation, for example, by (x',y') = R(x,y) + T, where R is the rotation matrix and T is the translation vector. Then, the transformed edges are geometrically compared with each edge of the target pattern in parallel to determine whether the matching requirements are met. The system also counts the number of edges matched by the current candidate matching item. When the number of matched edges is equal to the total number of edges in the target pattern, the candidate matching item is considered successful. If a necessary edge cannot be matched, the current candidate matching is immediately terminated and the system switches to the next candidate item, while resetting the matching count to process the next candidate item.
[0039] This invention discloses an FPGA-based DFM Pattern Match hardware accelerator and method. The accelerator includes: a data distribution module for grouping input layout edge data and sending different edge data in parallel to a hash calculation module; a hash calculation module for parallel calculation of directional buckets and hash values based on the relative geometric positions of edges and selected anchor polygons; a hash comparison module for parallel comparison of the calculated hash values of different directional buckets with the hash features of the target pattern, and extracting matches using a priority encoder; a candidate FIFO for storing pre-selected matches and decoupling the pre-selection stage from the precise geometric verification stage; a target region generation module for transforming the boundaries of the target pattern to the layout coordinate system according to the geometric transformation parameters in the matches, obtaining the target search region; an edge filtering module for quickly filtering all edges located in the target search region from the layout; and a precise matching module for transforming the filtered edges to the target pattern coordinate system and performing parallel geometric comparison with each edge of the target pattern to determine whether the pattern within the target search region is completely consistent with the target. This invention can achieve high throughput and low latency acceleration of the DFM Pattern Match process.
[0040] Compared with the prior art, the present invention has the following advantages:
[0041] (1) By constructing a full-stream parallel hardware architecture for DFM Pattern Match, this invention can significantly improve the overall matching speed and maintain high throughput and high-speed processing capability under large-scale pattern data input.
[0042] (2) The present invention adopts a hash signature based on directional bucket and a fast candidate filtering mechanism, which can effectively reduce the number of invalid precise geometric verifications, thereby improving the overall processing efficiency and ensuring the accuracy of the pattern matching results.
[0043] (3) The acceleration architecture of the present invention has good adaptability to the pattern scale and different process nodes, and can support the rapid matching of a large number of complex patterns in advanced processes. Attached Figure Description
[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0045] Appendix Figure 1 This is a schematic diagram of the structure of a DFM Pattern Match hardware accelerator based on FPGA according to the present invention;
[0046] Appendix Figure 2 This is a schematic diagram of the computation method of the DFM Pattern Match hardware accelerator based on FPGA according to the present invention;
[0047] Appendix Figure 3 This is a schematic diagram of the data distribution module structure;
[0048] Appendix Figure 4 This is a schematic diagram illustrating the principle of hash calculation module calculating directional buckets and local hash values based on anchor point polygons;
[0049] Appendix Figure 5 This is a schematic diagram of a K-side data cache RAM array. Detailed Implementation
[0050] As shown in the figure, an FPGA-based DFM Pattern Match hardware accelerator can be used to achieve high throughput and low latency acceleration of the DFM Pattern Match process. The accelerator includes:
[0051] The data distribution module is used to receive and group the buffered streaming input layout edge data, and send different groups of edge data to the hash calculation module in parallel; that is, it is used to group the input layout edge data and send different edge data to the hash calculation module in parallel.
[0052] The hash calculation module is used to perform parallel directional bucket partitioning and calculate the corresponding hash value for each edge based on the relative geometric position of the edge data and the selected anchor polygon; that is, it is used to calculate the directional bucket and hash value in parallel based on the relative geometric position of the edge and the selected anchor polygon.
[0053] The hash comparison module is used to compare the hash values of each bucket in parallel with the hash value of the target pattern, and extract matching items to generate candidate items through the priority encoder; that is, it is used to compare the calculated hash values of different buckets in parallel with the hash features of the target pattern, and extract matching items through the priority encoder.
[0054] Candidate FIFO is used to cache candidate matches to decouple the pre-screening stage from the precise geometric verification stage; that is, it is used to store pre-screened matches and decouple the pre-screening stage from the precise geometric verification stage.
[0055] The target region generation module is used to transform the boundary of the target pattern to the layout coordinate system according to the geometric parameters of the candidate, so as to obtain the target search region; that is, it is used to transform the boundary of the target pattern to the layout coordinate system according to the geometric transformation parameters in the matching item to obtain the target search region.
[0056] The edge filtering module is used to quickly filter out all edges located in the target search area from the map.
[0057] The precise matching module is used to map the edges output by the edge filtering module to the target pattern coordinate system and perform parallel comparison with each edge of the target pattern to determine whether the target search area is consistent with the target pattern.
[0058] The data distribution module includes a data loading unit, an edge storage array, and an address calculation unit. The data loading unit is used to receive streaming edge data and perform grouping processing. The edge storage array is used to store the data transmitted by the data loading unit. The address calculation unit is used to read edge data from the edge storage array in parallel and send the reading result to the hash calculation module.
[0059] like Figure 1 As shown, the accelerator also includes an HBM interface, a RAM array, and a pre-stored target pattern storage unit; the HBM interface is simultaneously connected to the data distribution module and the RAM array, and simultaneously receives the streaming input layout edge data; the hash calculation module is connected to the hash comparison module; the hash comparison module is connected to the pre-stored target pattern storage unit, and is connected to the target region generation module through a candidate FIFO; the edge filtering module is bidirectionally connected to the RAM array to read edge data; the precise matching module is connected to the edge filtering module, the pre-stored target pattern storage unit, and the HBM interface to complete the final matching verification and result feedback.
[0060] like Figure 2The diagram illustrates a flowchart of a hardware accelerator operation method for DFM Pattern Match based on FPGA. Edge data from the layout is first received and cached by the data distribution module, then sent to the hash calculation module to complete directional bucket partitioning and hash value generation. The hash comparison module performs parallel comparisons of the generated hash signature with the hash of the target pattern to obtain candidate matches and writes them into the candidate FIFO. The target region generation module then sequentially retrieves candidate matches from the candidate FIFO and calculates the corresponding target search region. The edge filtering module then reads and filters relevant edges from the RAM array based on the search region and sends the filtering results to the precise matching module. The precise matching module then performs coordinate mapping and parallel comparisons on the edges to determine whether the candidate matches. The entire process is driven by the transfer of data between modules, with each module working collaboratively to achieve a fully streaming hardware-accelerated matching process from pre-screening to precise verification.
[0061] The hash calculation module includes multiple parallel hash processing units and aggregation units;
[0062] The hash processing unit is used to compare the anchor point polygon hash signature with the pre-stored template hash signature in parallel according to the direction bucket, and extract the matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items, that is: calculate the direction bucket and local hash value of the edge based on the relative geometric relationship between the edge and the anchor point polygon.
[0063] The aggregation unit is used to receive the local hash values output by each hash processing unit, and accumulate the local hash values in the same direction bucket to generate the hash signature of the anchor point polygon.
[0064] like Figure 3 The diagram shows the block structure of the data distribution module. The data loading unit is responsible for receiving input edge data. The input edges are pre-divided into several batches based on their spatial position in the layout. Edges within the same batch are arranged in ascending order according to their polygon IDs and written to the current storage array in sequence: the first edge is written to address 0 of BRAM1, the second edge is written to address 0 of BRAM2, ..., the nth edge is written to address 0 of BRAMn; the (n+1)th edge is written to address 1 of BRAM1, and so on. During the loading process, it is simultaneously checked whether the number of edges of the polygon to which each edge belongs is consistent with the number of edges of the target mode anchor point polygon. If they are consistent and the polygon has not yet been recorded, it is written to the global BRAM. The address generation unit is responsible for generating the read address.
[0065] When the edge data of the same batch is fully loaded, the polygon of each record is retrieved sequentially from the global BRAM, and for that polygon, n edges are read in parallel from the local BRAM array in batches, so that the polygon and all the edges of the records in this batch are hashed sequentially; after completion, the process switches to the next polygon until all polygons in the batch have been processed; the storage array adopts a ping-pong buffer structure to achieve continuous streaming processing.
[0066] The hash comparison module is used to perform parallel comparison of the anchor point polygon hash signature with the pre-stored template hash signature by direction bucket, and extract matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items.
[0067] like Figure 4 The diagram illustrates the principle of the hash calculation module in calculating directional buckets and local hash values based on anchor point polygons. When calculating directional buckets and local hash values based on anchor point polygons, the hash calculation module, for each target pattern's hash signature calculation, selects a polygon in the target pattern as the anchor point polygon. Based on the positions of other edges relative to the anchor point polygon, these edges are divided into three different directional buckets (right, bottom, and bottom right). The geometric offset of their endpoints relative to the reference point is calculated, and the offsets are accumulated to obtain the local hash value.
[0068] In the specific implementation, for each edge, first obtain its endpoint coordinates (x1, y1) and (x2, y2), and then use the reference point (x1, y1) of the anchor polygon as the reference point. a ,y a Using x1 as a reference, calculate the offset (dx1, dy1) of the edge endpoints relative to the reference point = (x1 - x) / dy1. a ,y1-y a ) and (dx2,dy2)=(x2-x a ,y2-y a Based on the endpoint offsets (dx1, dy1) and (dx2, dy2), the spatial orientation of the edge relative to the anchor polygon is determined, and the edge is assigned to a preset direction bucket. Then, the endpoint offsets are accumulated to calculate the local hash code of the edge. The local hash values of each edge are accumulated within the same direction bucket to generate the direction hash value of the anchor polygon. The local hash values of the same direction bucket calculated by all hash processing units are accumulated to obtain the direction hash. Finally, the overall hash signature {H} of the anchor polygon is obtained. R H D H RD};
[0069] During the matching phase, the polygons in the layout calculate signatures in the same way and compare them with the target pattern library. Since hashing is based on the relative geometry of anchor points, it remains invariant to rotation, mirroring, and translation. To support rotation and mirroring, the direction buckets are expanded to eight: left, top-left, top, top-right, right, bottom-right, bottom, and bottom-left; changes between directions are implemented through simple index remapping, for example, a 90° rotation maps (right, bottom, bottom-right) to (bottom, left, bottom-left).
[0070] This accelerator employs a two-stage pipeline architecture, such as Figure 1 As shown, the two stages are the pre-screening stage and the precise matching stage. The former deals with large-scale edge data and requires high-throughput parallel screening; the latter processes a smaller amount of data but requires strict geometric verification of each data item, resulting in a long calculation cycle. To avoid the high-concurrency processing of the front end being hindered by the time consumption of the back end, this accelerator design introduces a FIFO buffer queue between the two stages to achieve task decoupling and load balancing. In the pre-screening stage, candidate regions are written into the FIFO, and in the precise matching stage, they are read on demand for verification, so that the front end keeps running in a streaming manner and avoids pipeline blockage.
[0071] like Figure 5 The diagram shows a K-way edge data cache RAM array. During accelerator operation, the RAM array stores edge data. Each batch of edge data is loaded into this RAM array simultaneously when it is loaded into the data distribution module. The edge filtering module reads edge data line by line from one of the RAMs based on the target search area and filters out edges located within that area. If only a traditional two-way ping-pong RAM is used, pipeline congestion will occur when the next batch of data is loaded during the pre-filtering stage while the exact matching process is still processing the previous batch. This invention extends the ping-pong structure to a K-way RAM array, allowing flexible switching between write and read paths across multiple RAMs. This mitigates congestion caused by differences in processing speed across stages. As the value of K increases and the candidate FIFO depth increases, pipeline congestion can be effectively alleviated or even completely eliminated.
[0072] The FPGA-based DFM Pattern Match hardware acceleration method uses the FPGA-based DFMP Pattern Match hardware accelerator described above and includes the following steps;
[0073] Step 1) The data distribution module receives the input map edge data and groups and caches it, while storing the polygon information to which the edge belongs, and sends each group of data to the hash calculation module in parallel;
[0074] Step 2) The hash calculation module calculates the direction bucket and hash value of each edge relative to the anchor polygon in parallel, generating the hash signature of the anchor polygon;
[0075] Step 3) The hash comparison module performs a parallel comparison between the anchor polygon hash signature and the target pattern hash signature to generate candidate matches and their geometric transformation parameters;
[0076] Step 4) Cache candidate matches in a candidate FIFO to decouple the pre-screening stage from the precise geometric verification.
[0077] Step 5) The target region generation module transforms the target pattern boundary to the layout coordinate system according to the geometric transformation parameters of the candidate matching items to obtain the target search region;
[0078] Step 6) The edge filtering module filters out edges located within the target search area from the edge data and passes the filtering results to the precise matching module;
[0079] Step 7) The precise matching module performs coordinate mapping on the filtered edges and compares them with the target pattern edge set to determine the matching result.
[0080] In step 7, the specific processing method of the precise matching module is as follows: the edge filtering module outputs one edge to the precise matching module every cycle; the precise matching module maps the received edge to the target pattern coordinate system and performs parallel comparison with each edge of the target pattern; at the same time, it counts the number of edges that have been successfully matched for the current candidate matching item, and when the number of successfully matched edges is equal to the total number of edges of the target pattern, the candidate matching item is determined to be successful; when any required edge comparison fails, the current candidate matching is immediately terminated and the next candidate is switched to, and the matching count is reset to process the next candidate.
[0081] When the precise matching module maps the received edges to the target pattern coordinate system, it first performs coordinate transformation on the received edges according to the geometric transformation parameters in the candidate matching items. The transformation includes translation and rotation, for example, by (x',y') = R(x,y) + T, where R is the rotation matrix and T is the translation vector. Then, the transformed edges are geometrically compared with each edge of the target pattern in parallel to determine whether the matching requirements are met. The system also counts the number of edges matched by the current candidate matching item. When the number of matched edges is equal to the total number of edges in the target pattern, the candidate matching item is considered successful. If a necessary edge cannot be matched, the current candidate matching is immediately terminated and the system switches to the next candidate item, while resetting the matching count to process the next candidate item.
[0082] Example:
[0083] In this example, the edge data refers to the geometric edges in the integrated circuit layout during circuit layout design. By searching for geometric structures similar to known hotspot patterns in the layout and comparing them with a pre-established pattern library, key areas that may affect chip yield can be identified.
[0084] like Figure 1The diagram shows a block diagram of an FPGA-based DFM Pattern Match hardware accelerator, including a data distribution module, a hash calculation module, a hash comparison module, a candidate FIFO, a target region generation module, a RAM array, an edge filtering module, a precise matching module, and a pre-stored target pattern storage unit. The HBM interface is connected to both the data distribution module and the RAM array, simultaneously receiving streaming layout edge data. The hash calculation module is connected to the hash comparison module; the hash comparison module is connected to the pre-stored target pattern storage unit and, through the candidate FIFO, to the target region generation module; the edge filtering module is bidirectionally connected to the RAM array to read edge data; and the precise matching module is connected to the edge filtering module, the pre-stored target pattern storage unit, and the HBM interface to complete the final matching verification and result feedback.
[0085] like Figure 2 The diagram illustrates a flowchart of a hardware accelerator operation method for DFM Pattern Match based on FPGA. Layout edge data is first received and cached by the data distribution module, then sent to the hash calculation module to complete directional bucket partitioning and hash value generation. The hash comparison module performs parallel comparisons of the generated hash signature with the hash of the target pattern, obtaining candidate matches and writing them into the candidate FIFO. The target region generation module sequentially retrieves candidate items from the candidate FIFO and calculates the corresponding target search region. The edge filtering module reads and filters relevant edges from the RAM array based on the search region and sends the filtering results to the precise matching module. The precise matching module performs coordinate mapping and parallel comparisons on the edges to determine whether the candidate items truly match. The entire process is driven by the transfer of data between modules, with each module working collaboratively to achieve a fully streaming hardware-accelerated matching process from pre-screening to precise verification.
[0086] like Figure 3 The diagram shows the block structure of the data distribution module. The data loading unit is responsible for receiving input edge data. The input edges are pre-divided into several batches based on their spatial position in the layout. Edges within the same batch are arranged in ascending order according to their polygon IDs and written to the current memory array in sequence: the first edge is written to address 0 of BRAM1, the second edge is written to address 0 of BRAM2, ..., the nth edge is written to BRAM... nThe first edge is written to address 0; the (n+1)th edge is written to address 1 of BRAM1, and so on. During the loading process, it is simultaneously checked whether the number of edges of the polygon to which each edge belongs is consistent with the number of edges of the target mode anchor point polygon. If they are consistent and the polygon has not yet been recorded, it is written to the global BRAM. The address generation unit is responsible for generating the read address. When the edge data of this batch is completely loaded, the polygon of each record is retrieved from the global BRAM in sequence, and for this polygon, n edges are read in parallel from the local BRAM array in batches, so that the polygon and all the edges of the record in this batch are hashed in sequence; after completion, it switches to the next polygon, until all polygons in this batch have been processed. The storage array adopts a ping-pong buffer structure to realize continuous streaming processing.
[0087] like Figure 4 The diagram illustrates the principle of the hash calculation module in calculating directional buckets and local hash values based on anchor polygons. For each target pattern's hash signature calculation, a polygon is selected as the anchor polygon within the target pattern. Based on the positions of other edges relative to the anchor polygon, these edges are divided into three different directional buckets (right, bottom, and bottom right). The geometric offsets of their endpoints relative to the reference point are calculated, and these offsets are accumulated to obtain the local hash value. In the specific implementation, for each edge, its endpoint coordinates (x1, y1) and (x2, y2) are first obtained. Using the reference point (x1, y1) of the anchor polygon as an example... a ,y a Using x1 as a reference, calculate the offset (dx1, dy1) of the edge endpoints relative to the reference point = (x1 - x) / dy1. a ,y1-y a ) and (dx2,dy2)=(x2-x a ,y2-y a Based on the endpoint offsets (dx1, dy1) and (dx2, dy2), the spatial orientation of the edge relative to the anchor point polygon can be determined, and the edge is assigned to a preset direction bucket. Then, the endpoint offsets are accumulated to calculate the local hash code of the edge. The local hash values of each edge are accumulated within the same direction bucket to generate the direction hash value of the anchor point polygon. By accumulating the local hash values of the same direction bucket calculated by all hash processing units, the direction hash is obtained, and finally, the overall hash signature {H} of the anchor point polygon is obtained. R H D H RDDuring the matching phase, the polygons in the layout are signed in the same way and compared with the target pattern library. Since hashing is based on the relative geometry of anchor points, it remains invariant to rotation, mirroring, and translation. To support rotation and mirroring, the direction buckets are expanded to eight: left, top-left, top, top-right, right, bottom-right, bottom, and bottom-left; changes between directions can be achieved through simple index remapping, for example, a 90° rotation maps (right, bottom, bottom-right) to (bottom, left, bottom-left).
[0088] This design employs a two-stage pipeline architecture, such as Figure 1 As shown, the two stages are the pre-screening stage and the precise matching stage. The former deals with large-scale edge data and requires high-throughput parallel screening; the latter processes a smaller amount of data but requires rigorous geometric verification for each item, resulting in a longer computation cycle. To avoid the high-concurrency processing of the front end being hindered by the time-consuming backend, this design introduces a FIFO buffer queue between the two stages to achieve task decoupling and load balancing. In the pre-screening stage, candidate regions are written into the FIFO, and in the precise matching stage, they are read and verified as needed, keeping the front end running in a streaming manner and avoiding pipeline blockage.
[0089] like Figure 5 The diagram illustrates a K-way edge data cache RAM array. This RAM array stores edge data, and each batch of edge data is simultaneously loaded into this RAM array when it is loaded into the data distribution module. The edge filtering module reads edge data line by line from one of the RAMs according to the target search area and filters out edges located within the target search area. If only a traditional two-way ping-pong RAM is used, pipeline blockage will occur when the next batch of data is loaded in the pre-filtering stage while the exact matching is still processing the previous batch. This invention extends the ping-pong structure to a K-way RAM array, which can flexibly switch between write and read paths among multiple RAMs, mitigating the blockage caused by differences in processing speed across stages. As the value of K increases and the candidate FIFO depth increases, pipeline blockage can be effectively alleviated or even completely eliminated.
Claims
1. An FPGA-based DFM Pattern Match hardware accelerator, capable of achieving high throughput and low latency acceleration of the DFM Pattern Match process in integrated circuit design, characterized in that: The accelerator includes: The data distribution module is used to receive and group the buffered streaming input layout edge data, and send different groups of edge data to the hash calculation module in parallel; The hash calculation module is used to perform directional bucket partitioning and calculate the corresponding hash value for each edge in parallel based on the relative geometric position of the edge data and the selected anchor point polygon. The hash comparison module is used to compare the hash values of each bucket with the hash value of the target pattern in parallel, and extract the matching items through the priority encoder to generate candidate items; Candidate FIFO is used to cache candidate matches in order to decouple the pre-screening stage from the precise geometric verification stage; The target region generation module is used to transform the boundary of the target pattern to the layout coordinate system based on the geometric parameters of the candidate, so as to obtain the target search region; The edge filtering module is used to quickly filter out all edges located in the target search area from the map. The precise matching module is used to map the edges output by the edge filtering module to the target pattern coordinate system and perform parallel comparison with each edge of the target pattern to determine whether the target search area is consistent with the target pattern.
2. The FPGA-based DFM Pattern Match hardware accelerator according to claim 1, characterized in that: The data distribution module includes a data loading unit, a side storage array, and an address calculation unit; the data loading unit is used to receive streaming side data and perform grouping processing; the side storage array is used to store the data transmitted by the data loading unit. The address calculation unit is used to read edge data in parallel from the edge storage array and send the reading result to the hash calculation module.
3. The FPGA-based DFM Pattern Match hardware accelerator according to claim 2, characterized in that: The accelerator also includes an HBM interface, a RAM array, and a pre-stored target pattern storage unit; the HBM interface is connected to both the data distribution module and the RAM array, and simultaneously receives streaming layout edge data. The hash calculation module is connected to the hash comparison module; the hash comparison module is connected to the pre-stored target pattern storage unit and to the target region generation module through the candidate FIFO; the edge filtering module is bidirectionally connected to the RAM array to read edge data; the precise matching module is connected to the edge filtering module, the pre-stored target pattern storage unit, and the HBM interface to complete the final matching verification and result feedback.
4. The FPGA-based DFM Pattern Match hardware accelerator according to claim 3, characterized in that: The edge data of the map is first received and cached by the data distribution module, and then sent to the hash calculation module to complete the directional bucket partitioning and hash value generation; the hash comparison module compares the generated hash signature with the hash of the target pattern in parallel to obtain candidate matching items and writes them into the candidate FIFO; then the target region generation module takes out the candidate items in sequence from the candidate FIFO and calculates the corresponding target search region. The edge filtering module then reads and filters relevant edges from the RAM array based on the search area, and sends the filtering results to the precise matching module. The precise matching module then performs coordinate mapping and parallel comparison on the edges to determine whether the candidate edge is a true match.
5. The FPGA-based DFM Pattern Match hardware accelerator according to claim 4, characterized in that: The hash calculation module includes multiple parallel hash processing units and aggregation units; The hash processing unit is used to compare the anchor point polygon hash signature with the pre-stored template hash signature in parallel according to the direction bucket, and extract the matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items, that is: calculate the direction bucket and local hash value of the edge based on the relative geometric relationship between the edge and the anchor point polygon. The aggregation unit is used to receive the local hash values output by each hash processing unit, and accumulate the local hash values in the same direction bucket to generate the hash signature of the anchor point polygon.
6. The FPGA-based DFM Pattern Match hardware accelerator according to claim 5, characterized in that: The data loading unit is responsible for receiving input edge data. The input edges are pre-divided into several batches according to their spatial position in the layout. Edges within the same batch are sorted in ascending order according to their respective polygon IDs and written to the current storage array in sequence. During the loading process, it is simultaneously checked whether the number of edges of each edge's polygon is consistent with the number of edges of the target mode anchor point polygon. If they are consistent and the polygon has not yet been recorded, it is written to the global BRAM. The address generation unit is responsible for generating the read address. When the edge data of the same batch is fully loaded, the polygon of each record is retrieved sequentially from the global BRAM, and for that polygon, n edges are read in parallel from the local BRAM array in batches, so that the polygon and all the edges of the records in this batch are hashed sequentially; after completion, the process switches to the next polygon until all polygons in the batch have been processed; the storage array adopts a ping-pong buffer structure to achieve continuous streaming processing.
7. The FPGA-based DFM Pattern Match hardware accelerator according to claim 6, characterized in that: The hash comparison module is used to perform parallel comparison of the anchor point polygon hash signature with the pre-stored template hash signature by direction bucket, and extract matching items based on the matching results and determine the corresponding geometric transformation parameters to generate candidate items.
8. The FPGA-based DFM Pattern Match hardware accelerator according to claim 7, characterized in that: When the hash calculation module calculates the directional buckets and local hash values based on the anchor point polygon, for the hash signature calculation of each target pattern, a polygon is selected in the target pattern as the anchor point polygon. Based on the position of other edges relative to the anchor point polygon, these edges are divided into three different directional buckets, and the geometric offset of their endpoints relative to the reference point is calculated. The offsets are accumulated to obtain the local hash value. For each edge, first obtain its endpoint coordinates (x1, y1) and (x2, y2), and then use the reference point (x1, y1) of the anchor polygon as the reference point. a ,y a Using x1 as a reference, calculate the offset (dx1, dy1) of the edge endpoints relative to the reference point. a ,y1-y a ) and (dx2,dy2)=(x2-x a ,y2-y a Based on the endpoint offsets (dx1, dy1) and (dx2, dy2), the spatial orientation of the edge relative to the anchor point polygon is determined, and the edge is divided into a preset direction bucket. Then, the endpoint offsets are accumulated to calculate the local hash code of the edge. The local hash values of each edge are accumulated within the same direction bucket to generate the direction hash value of the anchor point polygon. The local hash values of the same direction bucket calculated by all hash processing units are accumulated to obtain the direction hash. Finally, the overall hash signature of the anchor point polygon is obtained. During the matching phase, the polygons in the layout calculate signatures in the same way and compare them with the target pattern library. Since hashing is based on the relative geometry of anchor points, it remains invariant to rotation, mirroring, and translation. To support rotation and mirroring, the direction buckets are expanded to eight; changes between directions are implemented through index remapping. This accelerator adopts a two-stage pipeline architecture, consisting of a pre-screening stage and a precise matching stage. The former deals with large-scale edge data and requires high-throughput parallel screening; the latter processes smaller amounts of data but requires rigorous geometric verification of each data item, resulting in a longer computation cycle. To prevent high-concurrency front-end processing from being hindered by back-end time consumption, a FIFO buffer queue is introduced between the two stages to achieve task decoupling and load balancing. In the pre-screening stage, candidate regions are written into the FIFO, and in the precise matching stage, they are read on demand for verification, keeping the front-end running in a streaming manner and avoiding pipeline blockage. When the accelerator is working, the RAM array is used to store the side data. Each batch of side data is loaded into the RAM array synchronously when it is loaded into the data distribution module. The edge filtering module reads edge data one by one from one of the RAMs according to the target search area and filters out the edges located within the target search area; the ping-pong structure is expanded into a K-way RAM array to flexibly switch the write and read paths between multiple RAMs, thereby mitigating the blocking caused by the difference in processing speed across stages.
9. An FPGA-based DFM Pattern Match hardware acceleration method, using the FPGA-based DFM Pattern Match hardware accelerator as described in claim 8, characterized in that: The method includes the following steps; Step 1) The data distribution module receives the input map edge data and groups and caches it, while storing the polygon information to which the edge belongs, and sends each group of data to the hash calculation module in parallel; Step 2) The hash calculation module calculates the direction bucket and hash value of each edge relative to the anchor polygon in parallel, generating the hash signature of the anchor polygon; Step 3) The hash comparison module performs a parallel comparison between the anchor polygon hash signature and the target pattern hash signature to generate candidate matches and their geometric transformation parameters; Step 4) Cache candidate matches in a candidate FIFO to decouple the pre-screening stage from the precise geometric verification. Step 5) The target region generation module transforms the target pattern boundary to the layout coordinate system according to the geometric transformation parameters of the candidate matching items to obtain the target search region; Step 6) The edge filtering module filters out edges located within the target search area from the edge data and passes the filtering results to the precise matching module; Step 7) The precise matching module performs coordinate mapping on the filtered edges and compares them with the target pattern edge set to determine the matching result.
10. The FPGA-based DFM Pattern Match hardware acceleration method according to claim 9, characterized in that: In step 7, the specific processing method of the precise matching module is as follows: the edge filtering module outputs one edge to the precise matching module every cycle; the precise matching module maps the received edge to the target pattern coordinate system and performs parallel comparison with each edge of the target pattern; at the same time, it counts the number of edges that have been successfully matched for the current candidate matching item, and when the number of successfully matched edges is equal to the total number of edges of the target pattern, the candidate matching item is determined to be successful; when any required edge comparison fails, the current candidate matching is immediately terminated and the next candidate is switched to, and the matching count is reset to process the next candidate.