Scan chain analysis using a predetermined capture signature

Abstract

The device includes multiple circuit blocks, multiple scan-enabled flip-flop circuits, and multiple scan signature circuits. The multiple scan-enabled flip-flop circuits may be sequentially coupled across multiple circuit blocks and configured to shift scan chain test signals from a test input interface to a test output interface. The multiple scan signature circuits may be coupled to one of each subset of the multiple scan-enabled flip-flop circuits and configured to simultaneously load known scan chain patterns into the subset of scan-enabled flip-flop circuits in response to a specific test signal. The multiple scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of known scan chain patterns to the test output interface.

Description

Technical Field

[0001] The embodiments described herein relate to computing systems that include a system-on-chip (SoC). More specifically, embodiments related to techniques for using scan chain analysis in an SoC are disclosed.

Background Art

[0002] Scan-based diagnostics is a test technique that can be used on integrated circuits (ICs) that include clock logic circuits, such as systems-on-a-chip (SoCs). This technique uses scan-enabled memory circuits, such as flip-flops, coupled to one or more scan chains. One or more scan chain patterns are then applied to a test input interface and can be shifted through the scan chain until the output becomes available at the test output interface. If the scan test output matches the expected output, the logic circuits included in the scan chain can function correctly. If one or more scan outputs deviate from the expected value, one or more logic circuits in the corresponding scan chain may be faulty. Scan-based diagnostics are widely used to identify yield limiters in logic circuits. If the scan chain patterns are shifted correctly, the fault-indicating outputs can be analyzed to identify the specific faulty logic circuit. To load known scan chain patterns simultaneously, one of several scan signature circuits is configured to shift corresponding portions of known scan chain patterns to one scan input node in each of a subset of scan-enabled flip-flop circuits. However, diagnosing a scan output failure can be difficult if a flip-flop circuit located after a faulty point in a given scan chain is not properly configured during scan chain pattern loading. In addition, flip-flop circuits located before a broken point in the scan chain may not be observable during scan chain unloading. Identifying the faulty circuit in such cases may require a complex and expensive debugging process. Furthermore, as 3D stacking and back-side metallization of IC chips become more prevalent in SoC design, some of these debugging processes may not be feasible because physical access to the signal lines carrying a given scan chain pattern may be blocked by interconnects.

[0003] For a detailed explanation, please refer to the attached diagrams briefly described below. [Brief explanation of the drawing]

[0004] [Figure 1] This is a block diagram of one embodiment of a system-on-chip including a scan chain having a scan signature circuit.

[0005] [Figure 2] This is a block diagram of a non-faulty system-on-chip, showing the scan chain status at four different points in time.

[0006] [Figure 3] This is a block diagram of a faulty system-on-chip, showing the scan chain state at four different points in time.

[0007] [Figure 4] This is a block diagram of one embodiment of a faulty system-on-chip, including a scan signature circuit, showing the state of the scan chain at three points in time.

[0008] [Figure 5] This is a block diagram of one embodiment of a faulty system-on-chip, including a scan signature circuit, showing the state of the scan chain at two points in time.

[0009] [Figure 6] This is a block diagram of one embodiment of a system for scan testing a system-on-chip that includes a scan signature circuit and a scan chain having a backup scan-enabled flip-flop circuit.

[0010] [Figure 7] This is a block diagram of one embodiment of a computer system for designing a system-on-a-chip that includes a scan chain having a scan signature circuit.

[0011] [Figure 8]This is a flowchart of one embodiment of a method for scan testing a system-on-chip that includes a scan chain having a scan signature circuit.

[0012] [Figure 9] This is a flowchart of one embodiment of another method for scan testing a system-on-a-chip that includes a scan chain having a scan signature circuit.

[0013] [Figure 10] This figure shows various embodiments of a system including an integrated circuit that utilizes the disclosed technique.

[0014] [Figure 11] This is a block diagram of an exemplary computer-readable medium according to several embodiments.

[0015] While the embodiments described in this disclosure may be subject to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and the detailed description relating to them are not intended to limit the embodiments to any particular form disclosed, but rather to cover all modifications, equivalents, and alternative forms that fall within the spirit and scope of the appended claims. [Modes for carrying out the invention]

[0016] As disclosed above, scan-based diagnostics is a technique that can be used to identify faulty logic circuits within an IC. In some cases, a logic failure may be a manufacturing defect, such as a random occurrence caused by a single grain of dust falling onto the IC during manufacturing, which causes a particular transistor to malfunction. In other cases, a particular logic circuit may have a high failure rate across a significant number of dies, potentially indicating a logic circuit yield problem. In such cases, identifying the specific faulty logic circuit can enable the design team to revise the design to make it more robust and therefore less prone to failure. Higher yields can lead to lower IC costs, thereby making the product more price-competitive and / or more profitable. Higher yield ICs can also result in a more reliable end product.

[0017] As used herein, “scan chain” refers to a logic circuit including scan-enabled memory circuits that are coupled together to propagate one or more scan chain patterns from an input interface to an output interface. “Scan chain pattern” refers herein to a pattern of logic data (e.g., 0s and 1s) that is loaded into scan-enabled memory circuits included in a scan chain and can be shifted out to test the functionality of the logic circuits included in the scan chain. “Scan-enabled memory circuit” refers herein to a clock memory element (e.g., a flip-flop circuit) that is enabled in scan mode and can shift bits of the scan chain pattern in response to specific transitions of the scan clock signal.

[0018] Typical scan test techniques involve serially shifting the pattern bits of a scan chain pattern composed of logic high and low strings into the scan test input of an IC from an external test device. Successive scan clock transitions can shift the pattern bits from the first scan - compliant memory circuit (e.g., scan - compliant flip - flop) in the scan chain to the next scan - compliant memory circuit in the chain. When reaching the last scan - compliant memory circuit of the chain, the output of the scan chain pattern is presented at the scan test output of the IC, and the external test device can receive the scan chain output pattern and compare it with the expected pattern. However, if one or more scan - compliant memory circuits have a stack - at - 1 or a stack - at - 0 (collectively called a "stack - at - fault"), the scan chain output pattern can simply be a string of all 1s or all 0s. In such a case, it is determined which scan - compliant memory circuit in the chain is faulty.

[0019] A novel technique is disclosed in which a predetermined scan signature logic is added to the scan - compliant memory circuits within an IC. In a first mode, for example, all scan - compliant memory circuits including the scan signature logic can be initialized simultaneously with a first predetermined scan chain pattern. In a second mode, these scan - compliant memory circuits can be initialized simultaneously with a second predetermined scan chain pattern, which can in some cases be the inverse of the first pattern. The initialized scan chain pattern can be shifted out in each mode. Since the scan - compliant memory circuits are initialized by additional scan signature logic rather than by shifting in the scan chain pattern, the scan - compliant memory circuits before and after a faulty circuit in the scan chain can be loaded with either of two known patterns. Any deviation from the known patterns can indicate a malfunctioning logic circuit. By using two known patterns, it can be possible to identify a logic circuit having either a stack - at - 1 or a stack - at - 0 (collectively called a "stack - at - fault").

[0020] The present disclosure contemplates a novel circuit for use in an integrated circuit (IC) to implement a technique for identifying a failed logic circuit within a scan chain. An exemplary apparatus (e.g., an IC) may include a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be sequentially coupled across the plurality of circuit blocks and configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits. In response to a particular test signal, the plurality of scan signature circuits may simultaneously load a known scan chain pattern into the subset of scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may sequentially output at least a portion of the known scan chain pattern to the test output interface.

[0021] The use of a predetermined scan chain pattern that can be simultaneously loaded into the scan-enabled memory circuits rather than shifted in may increase the likelihood of identifying circuits having a stack at failure, thereby enabling the ability to identify failed circuits at a finer granularity. This ability to identify failed circuits enables revisions to the IC design that improve manufacturing yield, thereby improving the reliability and profitability of the end product using the IC.

[0022] Figure 1 shows a block diagram of one embodiment of a system that uses scan signature circuits to load a predetermined scan chain pattern into scan-enabled memory circuits in a scan chain. The system-on-chip (SoC) 100 includes circuit blocks 105a and 105b (collectively 105). Each of the circuit blocks 105 includes a plurality of scan-enabled flip-flop circuits (scan FFs) 120a to 120i (collectively 120) and a plurality of scan signature circuits 115a to 115d (collectively 115). The SoC 100 includes a test input interface 150 for receiving scan chain pattern inputs and a test output interface 152 on which scan chain pattern outputs are asserted. Two test signals 130a and 130b are also included. The SoC 100 may further be part of a computing system such as a desktop or laptop computer, smartphone, tablet computer, or wearable smart device.

[0023] As shown, circuit block 105 includes scan chains 110a and 110b (collectively 110), each of which is distributed across both circuit blocks 105. Each scan chain 110 includes a plurality of scan-enabled flip-flop circuits (scan FFs) 120. Scan chain 110a includes scan-enabled flip-flop circuits 120a to 120d sequentially coupled across circuit block 105. Similarly, scan chain 110b also includes scan-enabled flip-flop circuits 120e to 120i sequentially coupled across circuit block 105. Each of scan chains 110a and 110b is configured to shift the scan chain test signal from the test input interface 150 to the test output interface 152.

[0024] The SoC100 also includes a plurality of scan signature circuits 115 coupled to one of each of the subsets of scan-enabled flip-flop circuits 120. The scan signature circuits 115 are configured to simultaneously load known scan chain patterns into the subsets of scan-enabled flip-flop circuits 120 in response to a test signal 130b, as shown in the figure. A given scan signature circuit 115 may include a logic circuit configuration that causes a specific logic state to be asserted at one of the inputs of each of the scan-enabled flip-flop circuits 120.

[0025] For example, a specific value of test signal 130b may instruct scan signature circuits 115d and 115e to load specific logic values ​​into scan-enabled flip-flop circuits 120e and 120g, respectively. Scan-enabled flip-flop circuit 120 is further configured to sequentially output at least a portion of a known scan chain pattern to the test output interface. When test signal 130a is active, it may be a scan test clock signal that causes scan-enabled flip-flop circuits 120e to 120i in scan chain 110b to shift their respective contents for each active transition of test signal 130a, including predetermined pattern values ​​loaded into scan-enabled flip-flop circuits 120e and 120g.

[0026] The output of scan-enabled flip-flop circuit 120i is coupled to the test output interface 152, as shown, allowing, for example, a test monitoring device to observe the output pattern from scan chain 110b. Similarly, similar actions may be performed to load a predetermined scan chain pattern into scan-enabled flip-flop circuits 120b, 120c, and 120d, and to shift the output to the test output interface 152 for observation. The monitored output from scan-enabled flip-flop circuit 120i or 120d may be compared to an expected value by the test monitoring device, and any discrepancy between the observed pattern and the expected pattern may be used, for example, to identify a specific scan-enabled flip-flop circuit 120 that is faulty. In some cases, different values ​​of the test signal 130b may be used to load different predetermined scan chain patterns, such as the reverse of a previous scan chain pattern, into each subset of scan-enabled flip-flop circuits 120. By using the reverse pattern, a subset of scan-enabled flip-flop circuits 120 can store both high and low logic states when attempting to detect whether any of the scan-enabled flip-flop circuits 120 have a stack in failure. Further details regarding a given scan chain pattern are presented below.

[0027] It should be noted that the SoC100 shown in Figure 1 is merely an example. The SoC100 has been simplified to highlight the features relevant to this disclosure. Elements not used have been omitted to illustrate the details of the disclosed concepts. For example, the SoC100 may include various additional circuits not shown, such as one or more processor circuits, memory management circuits, and memory circuits. Only two scan chains are shown, including nine scan-enabled flip-flop circuits 120 and five scan signature circuits 115. In other embodiments, any suitable number of scan chains may be included, and each scan chain may consist of any suitable number of elements, including, for example, logic elements not shown. In various embodiments, circuit block 105, and other circuits of the SoC100 not shown, may be implemented using any suitable combination of sequential logic circuits and combinational logic circuits. In addition, registers and / or memory circuits, such as static random access memory (SRAM), may be used in these circuits to temporarily hold information such as instructions, data, and address values.

[0028] Figure 1 discloses a scan chain utilizing a scan signature circuit. The benefits of using a scan signature circuit can be understood in terms of scan operation. Figures 2 and 3 show the scan operation of a non-faulty and a faulty SOC.

[0029] Moving to Figure 2, a block diagram of the scan chain at four points in time during the scan operation is shown. A non-faulting SoC200 includes a scan chain 210 having multiple scan-enabled flip-flop circuits, one end of which is coupled to the test input interface 250 and the other end to the test output interface 252. The scan chain 220 is configured to shift the scan chain pattern from the first scan-enabled flip-flop circuit coupled to the test input interface 250, through a sequence of scan-enabled flip-flop circuits, until the last scan-enabled flip-flop circuit provides the scan chain pattern to the test output interface 252.

[0030] As shown at time t0, the scan-enabled flip-flop circuit in scan chain 220 is in an uninitialized state. The test input interface 250 represents the first bit of the scan chain pattern at the input of scan chain 220. For simplicity, the scan chain pattern is shown with only 6 bits of pattern data. In other embodiments, the scan chain pattern may include any appropriate number of pattern data bits. The test clock signal is toggled, and as a result, at time t1, the first bit of the scan chain pattern may be latched into the first scan-enabled flip-flop circuit of scan chain 220.

[0031] By time t2, the scan chain pattern is loaded into scan chain 220, and subsequent transitions of the test clock may shift the loaded pattern toward the test output interface 252. By time t3, all but one pattern data bit have been shifted out to the test output interface 252. Note that this example shows an output scan chain pattern that matches the input scan chain pattern. In other embodiments, the expected output scan chain pattern may differ from the input scan chain pattern due to the logic circuitry between subsequent scan-enabled flip-flop circuits.

[0032] Moving on to Figure 3, a block diagram of the scan chain at four points in time during the scan operation is again shown, this time for the failed SoC. The failed SoC 200 includes a scan chain 310 having a sequence of scan-enabled flip-flop circuits, one end of which is coupled to the test input interface 350 and the other end to the test output interface 352. In this example, one scan-enabled flip-flop circuit has a stack of 1 failure, as shown.

[0033] As illustrated at time t0, the same scan chain pattern is ready to be loaded into scan chain 310. At time t1, the first bit of the scan chain pattern is shifted to scan chain 310. However, it should be noted that, due to a stack failure of 1, the incorrect logic value of 1 is shifted to a scan-enabled flip-flop circuit adjacent to and downstream of the failed scan-enabled flip-flop circuit. As used herein, “downstream” refers to a scan-enabled flip-flop circuit between a given scan-enabled flip-flop circuit and the test output interface. Conversely, “upstream” refers to a scan-enabled flip-flop circuit between the test input interface and a given scan-enabled flip-flop circuit.

[0034] As the scan chain pattern continues to shift through scan chain 310 at time t2, the scan chain pattern is corrupted in the failed scan-enabled flip-flop circuit, and all scan-enabled flip-flop circuits downstream from the failed scan-enabled flip-flop circuit have the shifted-in logic 1 value. At time t3, the test output interface 352 simply receives a string of logic 1 values ​​instead of the expected output pattern. Since the input scan chain pattern must be loaded from the first scan-enabled flip-flop circuit coupled to the test input interface, analysis of the received output scan chain pattern does not provide any indication of which of the scan-enabled flip-flop circuits is failed.

[0035] The explanations related to Figures 2 and 3 disclose scan chain operation that does not benefit from scan signature circuits. The use of scan signature circuits can provide the ability to identify faulty scan-responsive flip-flop circuits without relying on other expensive, time-consuming, and irrelevant techniques. Figures 4 and 5 provide examples of the use of scan signature circuits.

[0036] Moving on to Figure 4, another block diagram of a failed embodiment of the SoC300 is shown. As shown, the SoC300 includes a scan chain 310 and a scan signature circuit 415. Figure 4 shows three additional time points after time t3 in Figure 3, during which time the scan signature circuit 415 is used to help identify the failed scan-enabled flip-flop circuit.

[0037] As illustrated at time t4, the scan signature circuit 415 is configured to simultaneously load a known scan chain pattern into the scan-enabled flip-flop circuits in the scan chain 310. This may be performed in response to a specific test signal, such as the test signal 130b in Figure 1. To simultaneously load a known scan chain pattern, the scan signature circuit 415 is further configured to set one of each of the scan-enabled flip-flop circuits to a specific logic state, as shown at time t5. For example, the scan signature circuit 415 may shift a corresponding portion (e.g., one pattern bit) of a known scan chain pattern to one of the scan input nodes of each of the scan-enabled flip-flop circuits in the scan chain 310. In other embodiments, the first scan signature circuit of the scan signature circuit 415 may assert one of the set nodes of each of the scan-enabled flip-flop circuits, while the second scan signature circuit asserts the reset node of a different subset of the scan-enabled flip-flop circuits.

[0038] In some embodiments, the scan signature circuit 415 is configured to select one of several known scan chain patterns to load simultaneously into a subset of scan-enabled flip-flop circuits, based on the value of the test signal 130b. As illustrated, the first pattern of the several known scan chain patterns may be an iterative pattern of a particular sequence of high and low logic states. In this case, the iterative pattern proceeds from right to left as the test output interface 352 receives the pattern data bits, with two high states followed by two low states. The scan signature circuit 415 may be configured as a group with any suitable number of other patterns suitable for analyzing the scan chain 310.

[0039] At time t6, the functional portion of the scan-enabled flip-flop circuit of scan chain 310 may be further configured to sequentially output at least a portion of known scan chain patterns to the test output interface 352. This functional portion of scan chain 310 includes one of the scan-enabled flip-flop circuits positioned between the faulty scan-enabled flip-flop circuit and the test output interface 352. A second portion of the scan-enabled flip-flop circuit positioned between the test input interface 350 and the faulty scan-enabled flip-flop circuit may function, preventing the propagation of the loaded known scan chain patterns to the test output interface 352. Therefore, this second portion may not be considered part of the functional portion of scan chain 310.

[0040] The test output interface 352 receives an output from the scan chain 310. As shown, the received scan chain pattern output matches the expected output (in this case, what is loaded into the scan chain 310 at time t5), except for the last two (leftmost) pattern data bits, which are logic 1 instead of the expected logic 0. Based on this information, it can be determined that at least one of the scan-enabled flip-flop circuits enclosed by the three circles is a failed flip-flop. However, at least one additional scan chain pattern may be used to narrow down which scan-enabled flip-flop circuit is failed.

[0041] Referring to Figure 5, two time points after time t6 in Figure 4 are shown for scan chain 310 and scan signature circuit 415. During these two additional time points, a second known scan chain pattern is used in conjunction with scan signature circuit 415 to help identify the failed scan-enabled flip-flop circuit.

[0042] As shown at time t7, a second pattern of multiple known scan chain patterns is loaded into scan chain 310. This second pattern is different from the first pattern shown in Figure 4. As illustrated, this second known scan chain pattern is the inverse of the first pattern.

[0043] At time t8, the functional portion of the scan-enabled flip-flop circuit of scan chain 310 may be further configured to sequentially output at least a portion of the second scan chain pattern to the test output interface 352. The test output interface 352 receives the second output from scan chain 310. In this example, the received scan chain pattern output matches the expected output (which is loaded into scan chain 310 at time t7), except for two bold and italicized pattern data bits that are logic 1 instead of the expected logic 0.

[0044] Based on the output when using the first pattern, and this additional output when using the second pattern, a faulty flip-flop circuit can be identified. The combination of the two received output patterns is only possible when the scan-enabled flip-flop circuit enclosed in the circle has a stack of 1 failure. However, it is not possible to determine whether any of the scan-enabled flip-flop circuits upstream of the faulty scan-enabled flip-flop circuit are also faulty. Details on how upstream flip-flop circuits can also be tested are provided below.

[0045] It should be noted that Figures 2–5 are merely examples to demonstrate the disclosed concepts. While a single scan chain is shown, any appropriate number of scan chains may be included in a given SoC, and similarly, any appropriate number of included scan chains may be enabled and activated for a given scan operation.

[0046] The explanation relating to Figures 4 and 5 discloses the use of a scan signature circuit to identify at least a first failed scan-enabled flip-flop circuit. Additional techniques may be used to identify whether any scan-enabled flip-flop circuits upstream of the failed flip-flop circuit are also failed. Figure 6 illustrates one such technique.

[0047] Moving on to Figure 6, we see a block diagram of one embodiment of the system that uses scan signature circuits to identify a failed scan-enabled memory circuit and to enable an alternative path around the failed scan-enabled memory circuit. As shown, the system 600 includes an SoC 601, which further includes a scan chain 610 containing scan-enabled flip-flop circuits 620a-620h (collectively 620). A subset of scan-enabled flip-flop circuits 620 contains one of each of the scan signature circuits 615a-615h (collectively 615). Scan-enabled flip-flop circuits 620c and 620 do not contain scan signature circuits, while the rest of the scan-enabled flip-flop circuits 620 do contain scan signature circuits. The SoC 601 also includes spare scan-enabled flip-flop circuits 622a-622h (collectively 622). Several bypass switches 660a–660c are shown coupled to specific scan-enabled flip-flop circuits 620. The SoC601 further includes a test circuit 640 coupled to a test input interface 650 and a test output interface 652. The SoC601 is coupled to a test device 670 via the test input interface 650 and the test output interface 652.

[0048] As shown in the figure, the test apparatus 670 is configured to assert input signals to the device under test (DUT) and to monitor output signals from the DUT. In various embodiments, the test apparatus 670 may be an automated test apparatus used in a production manufacturing process, an evaluation apparatus in a research or failure analysis laboratory, or an SoC included with the DUT in a product (e.g., a desktop or laptop computer, smartphone, tablet, wearable computer device, etc.). The SoC 601 may be coupled to the test apparatus 670 as part of a production test process, laboratory evaluation, field debugging session, etc.

[0049] The SoC601 includes multiple scan chains, such as scan chain 610. The SoC601 may be configured to receive a first scan chain pattern from the test device 670 at a test input interface 650 for scan chain 610, and to send a response to the first scan chain pattern back to the test device 670 at a test output interface 652. The test circuit 640 may be configured to generate appropriate signals to the scan-enabled flip-flop circuit 620 to shift the first scan chain pattern through scan chain 610. The test device 670 may be further configured to send a specific test signal to the SoC601 in response to a determination that the response does not match the expected response. In response to the specific test signal, the SoC601 may simultaneously load known scan chain patterns into a subset of the scan-enabled flip-flop circuits 620 included in scan chain 610. As shown in the figure, scan-enabled flip-flop circuits 620a, 620b, 620d, 620e, 620g, and 620h each include one of the scan signature circuits 615a, 615b, 615d, 615e, 615g, and 615h, respectively. As described above, the scan signature circuit 615 may be configured to load the corresponding scan-enabled flip-flop circuit 620 with one or more known scan chain patterns in response to one or more specific test signals from the test circuit 640. The SoC 601 then transmits the response to the known scan chain pattern at the test output interface 652 to the test device 670.

[0050] As shown, the test circuit 640 may be configured to identify a faulty scan-enabled flip-flop circuit 620 from among several scan-enabled flip-flop circuits 620. In some embodiments, identification may be performed by the test device 670 alone or in combination with the test circuit 640. For example, a scan-enabled flip-flop circuit 620b may have a stack of failures. Due to the faulty scan-enabled flip-flop circuit 620b, the output from scan-enabled flip-flop circuit 620a cannot pass through scan-enabled flip-flop circuit 620b, and therefore scan-enabled flip-flop circuit 620a may not be able to be tested. The SoC 601 is configured to enable an alternative scan chain route that bypasses the faulty scan-enabled flip-flop circuit in the scan chain, as shown. The SoC 601 includes a bypass switch 660a that can allow the scan chain pattern to be routed around the faulty scan-enabled flip-flop circuit 620b, for example, forming an alternative scan chain route. As shown in the figure, the test circuit 640 can activate the bypass switch 660a in response to a determination that the scan-enabled flip-flop circuit 620b is faulty, thereby enabling a scan chain path that bypasses the scan-enabled flip-flop circuit 620b. When the bypass switch 660a is closed, an alternative path is created that connects the input node of the faulty scan-enabled flip-flop circuit 620b to the output node of the scan-enabled flip-flop circuit 620b, thereby bypassing the faulty scan-enabled flip-flop circuit 620b and allowing the scan-enabled flip-flop circuit 620a to be tested by directly transmitting a signal to the scan-enabled flip-flop circuit 620c. The bypass switch can be implemented using any suitable type of switching circuit, for example, an n-channel or p-channel metal oxide semiconductor field-effect transistor (MOSFET).

[0051] In some embodiments, a bypass switch may be used to "repair" a faulty scan-enabled flip-flop circuit by routing a signal between the faulty scan-enabled flip-flop circuit and a spare flip-flop circuit, rather than bypassing the faulty scan-enabled flip-flop circuit itself. For example, scan-enabled flip-flop circuit 620g may be determined to be faulty. To repair the faulty scan-enabled flip-flop circuit 620g, the test circuit 640 may be configured to activate bypass switch 660b to route the input node of the faulty scan-enabled flip-flop circuit 620g to the input node of a spare scan-enabled flip-flop circuit 622g, and to activate bypass switch 660c to route the output node of the spare scan-enabled flip-flop circuit 622g to the output node of the faulty scan-enabled flip-flop circuit 620g. In some embodiments, a separate switch may be activated to disconnect the output of a failed scan-enabled flip-flop circuit 620g from the input node of scan-enabled flip-flop circuit 620h, thereby allowing the output of a spare scan-enabled flip-flop circuit 622g to drive the input of scan-enabled flip-flop circuit 620h.

[0052] In various embodiments, the activation of one or more of the bypass switches 660 may be temporary, and for example, they may only be activated by a signal asserted by the test circuit 640, as long as the test circuit 640 asserts a signal. Such embodiments may enable improved scan test coverage in an SoC having one or more failed scan-enabled flip-flop circuits. In other embodiments, non-volatile memory elements (e.g., flash memory, fuses, etc.) may be used with spare scan-enabled flip-flop circuits to enable more permanent repair of the failed scan-enabled flip-flop circuits. The bypass switches 660 may be implemented using any suitable type of switch circuit, such as metal oxide semiconductor field-effect transistors (MOSFETs), programmable logic arrays, or fuses.

[0053] Please note that the embodiment in Figure 6 is an example for demonstration purposes only. For clarity, only a few bypass switches and a single scan chain are shown. Other embodiments may include any appropriate number of bypass switches, spare scan-enabled flip-flop circuits, scan chains, etc.

[0054] In the embodiments described in Figures 1 to 6, the scan chains are shown as independent of each other. The output signals from the flip-flop circuits of one scan chain are not shown to fan out to one or more input nodes in other scan chains. However, in some SoC designs, scan chains can fan out such that the output nodes of the intermediate flip-flop circuits of a first scan chain can be coupled to the input nodes of one or more flip-flop circuits of other scan chains. An example of this is shown in Figure 7.

[0055] Moving to Figure 7, a block diagram of one embodiment of a computer system for designing an SoC is shown. The computer system 700 is shown with two versions of SoC design information, 790a and 790b. SoC design information 790a represents the design information of the SoC before the addition of scan signature circuits. SoC design information 790b represents the design information of the same SoC after the scan signature circuits have been added to the scan chain. The computer system 700 may be implemented using a desktop or laptop computer system, one or more server computer systems, a virtual computer running across multiple computer systems, etc. In some embodiments, the SoC design information 790a and 790b may be stored in a computer-readable non-temporary storage medium. The SoC design information 790 specifies the design of at least a portion of a hardware integrated circuit in a format recognizable by a semiconductor manufacturing system configured to use the design information to manufacture a hardware integrated circuit according to the SoC design information 790.

[0056] A design engineer or team of design engineers may design a new SoC by creating SoC design information 790a using any suitable set of integrated circuit design tools running on the computer system 700. The SoC design information 790a specifies that the hardware integrated circuit comprises multiple circuit blocks, such as one or more processor circuits, graphics and audio processor circuits, network circuits, timer circuits, memory array and memory controller circuits, and other types of circuits that may be included on various types of SoCs.

[0057] At a specific point in the design of a new SoC (or possibly at various points in time), scan-enabled flip-flop circuits 720a–720x (collectively 720) for scan chains 710a–710c may be inserted into the integrated circuit design information to create SoC design information 790a. As used herein, “inserting” a circuit element such as a scan-enabled flip-flop circuit means adding the circuit element to a specific location (e.g., being coupled to a specific circuit already included in the design). In some cases, inserting a circuit element into existing design information may involve adding one or more lines of Register Transfer Language (RTL) to the design information. As shown, the scan-enabled flip-flop circuits may form scan chains 710a–710c across multiple circuit blocks and be configured to shift the scan chain test signal from the test input interface to the test output interface in a manner similar to that described above for Figure 1. Scan chain 710a includes scan-enabled flip-flop circuits 720a to 720h, scan chain 710b includes scan-enabled flip-flop circuits 720i to 720p, and scan chain 710c includes scan-enabled flip-flop circuits 720q to 720x.

[0058] After the addition of scan-enabled flip-flop circuit 720, a portion of scan-enabled flip-flop circuits 720q~720x within scan chain 710c may be identified. This portion includes scan-enabled flip-flop circuits 720s and 720v that receive their respective scan data signals based on signals from other scan chains 710a and 710b. In some embodiments, scan-enabled flip-flop circuits 720s and 720v may be identified because they receive their respective data input signals derived from a threshold number of scan chains. For example, a scan-enabled flip-flop circuit 720 that receives data input signals from two or more other scan chains may be included in the identified portion. Receiving data input signals from a threshold number of other scan chains is referred to herein as “high fan-in”. A scan-enabled flip-flop circuit with high fan-in has input signals composed of multiple scan chains. Therefore, if a scan-enabled flip-flop circuit with high fan-in fails, there may be one or more other scan chain paths for the data signals to travel to enter the failed scan-enabled flip-flop circuit. Scan-enabled flip-flop circuits with high fan-in can, in some cases, be identified without the need to utilize scan signature circuits.

[0059] The design of the new SoC may involve inserting a set of scan signature circuits 715q~715x (collectively 715) into one of each of the subsets of scan-enabled flip-flop circuits 720q~720x in the scan chain 710c, thereby creating SoC design information 790b. The subset includes all of the multiple scan-enabled flip-flop circuits 720q~720x, excluding scan-enabled flip-flop circuits 720s and 720v in the identified portion. Because scan-enabled flip-flop circuits 720s and 720v have high fan-in, the corresponding scan signature circuits may not be very useful in identifying when these two scan-enabled flip-flop circuits have failed. By omitting the scan signature circuits from scan-enabled flip-flop circuits 720s and 720v, die area and power consumption can be reduced. This omission can also reduce the complexity of the SoC design information 790b, which in turn can simplify other design tasks such as timing analysis.

[0060] In the illustrated embodiment, the scan signature circuit 715 is included in one of each of the subsets of scan-enabled flip-flop circuits 720q to 720x. For example, the design information for scan-enabled flip-flop circuits 720q, 720r, 720t, 720u, 720w, and 720x may be replaced with a scan-enabled flip-flop circuit design that includes the respective scan signature circuit. In other embodiments, the scan signature circuit 715 is included in separate design information and then coupled to one of each of a plurality of scan-enabled flip-flop circuits that are excluded from the identified portion of scan-enabled flip-flop circuit 720.

[0061] The generated SoC design information 790b specifies the hardware integrated circuit of the SoC design information 790a by adding a scan signature circuit 715, which is contained in one of each of the subsets of scan-enabled flip-flop circuits 720q to 720x. As described above, the scan signature circuit 715 is configured to simultaneously load a known scan chain pattern into one of each of the subsets of scan-enabled flip-flop circuits 720q to 720x in response to a specific signal.

[0062] It should be noted that the embodiment in Figure 7 is an example for demonstrating the disclosed technique. For clarity, many elements that may be included in the SoC design have been omitted. For example, various circuit blocks such as processor circuits, network circuits, memory circuits, and test interfaces are omitted from Figure 7 but may be included in other embodiments.

[0063] In summary, various embodiments of a system utilizing a prefetch denial list circuit are disclosed. In an exemplary device, an integrated circuit includes multiple circuit blocks, multiple scan-enabled flip-flop circuits, and multiple scan signature circuits. The multiple scan-enabled flip-flop circuits may be sequentially coupled across multiple circuit blocks and configured to shift scan chain test signals from a test input interface to a test output interface. The multiple scan signature circuits may be coupled to one of each subset of the multiple scan-enabled flip-flop circuits and configured to simultaneously load known scan chain patterns into the subset of scan-enabled flip-flop circuits in response to a particular test signal. The multiple scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of known scan chain patterns to the test output interface.

[0064] In a further example, to load known scan chain patterns simultaneously, multiple scan signature circuits may be configured to set one of each of a subset of scan-enabled flip-flop circuits to a specific logic state. In one example, multiple scan signature circuits may be further configured to simultaneously load a selection of several known scan chain patterns into a subset of scan-enabled flip-flop circuits based on the value of a specific test signal.

[0065] In another example, the first pattern of a set of known scan chain patterns could be an iterative pattern of a specific sequence of high and low logical states. In one example, the first pattern of a set of known scan chain patterns could be the inverse of the second pattern of a set of known scan chain patterns.

[0066] In a further example, a given scan-enabled flip-flop circuit may be configured to receive data input signals derived based on multiple logic paths, each containing a scan-enabled flip-flop circuit. A given scan-enabled flip-flop circuit may be excluded from coupling to each scan signature circuit.

[0067] In another example, the device may further include a test circuit configured to identify a faulty scan-enabled flip-flop circuit among several scan-enabled flip-flop circuits and to enable an alternative scan chain path that avoids the faulty scan-enabled flip-flop circuit in the scan chain. In one example, several scan signature circuits may be contained within one of each of several subsets of scan-enabled flip-flop circuits.

[0068] The circuits and techniques described above with respect to Figures 1 to 7 can be implemented using a wide variety of methods. Two methods related to the use of scan signature circuits are described below with respect to Figures 8 and 9.

[0069] Referring here to Figure 8, a flowchart of one embodiment of a method for performing a scan test using multiple scan signature circuits is shown. Method 800 may be performed by any of the systems disclosed herein, such as SoCs 100-300 and 601 in Figures 1-6. In some embodiments, some or all of the operation of Method 800 may be performed using instructions contained in non-temporary computer-readable memory having a program, and the instructions are executable by one of SoCs 100-300 and 601 to cause the operation described with reference to Figure 8. Method 800 is described below using SoC 100 in Figure 1 as an example. References to elements in Figure 1 are included as non-limiting examples.

[0070] In 810, method 800 begins by shifting a scan chain pattern from an input port to an output port of the test interface of an integrated circuit by a scan chain comprising multiple scan-enabled flip-flop circuits. For example, the scan chain pattern is received by the SoC 100 at the test input interface 150 and shifted to the test output interface 152 via scan-enabled flip-flop circuits 120e-120i included in scan chain 130b. In this example, at least one of the scan-enabled flip-flop circuits 120e-120i fails to shift the scan chain pattern. For example, scan-enabled flip-flop circuit 120f may have a stack in failure.

[0071] Method 800 continues in 820 after the scan chain pattern fails to shift to the output port, by loading a known scan chain pattern into a subset of scan-enabled flip-flop circuits simultaneously using multiple scan signature circuits coupled to one of each of the subsets of scan-enabled flip-flop circuits. The scan chain pattern output presented in the test output interface 152 may include one or more pattern bits that match the expected output pattern and at least some of the output patterns that do not match the expected output pattern. In this example, it may not be possible to identify which of the scan-enabled flip-flop circuits 120e-120i is faulty. Therefore, scan signature circuits 115d and 115e may be used to insert a known pattern into a subset of the faulty scan-enabled flip-flop circuits 120e-120i in the scan chain 110b. As shown, scan signature circuits 115d and 115e may load a known pattern into scan-enabled flip-flop circuits 120e and 120g simultaneously, respectively. For example, simultaneously loading known scan chain patterns may involve a scan signature circuit 115d setting a scan-enabled flip-flop circuit 120e to a first logic state, while a second scan signature circuit 115e sets a scan-enabled flip-flop circuit 120g to a second logic state. In some embodiments, scan signature circuits 115d and 115e may be configured to load one of a plurality of known scan chain patterns based on a specific test signal.

[0072] In 830, method 800 proceeds to shift at least a portion of a known scan chain pattern to the output port by the functional portion of the scan chain. For example, if scan-enabled flip-flop circuit 120f fails, the functional portion of scan chain 110b includes scan-enabled flip-flop circuits 120g to 120i located between the failed scan-enabled flip-flop circuit 120f and the test output interface 152. The portion of the known scan chain pattern loaded into one or more of the scan-enabled flip-flop circuits 120g to 120i may be correctly presented at the test output interface 152. At least some of the remaining pattern bits of the known scan chain pattern may not be correctly presented.

[0073] Therefore, the use of the scan signature circuit 115 can help identify a faulty scan-enabled flip-flop circuit among the 120e-120i. In this example, the scan-enabled flip-flop circuits 120g-120i are determined to be functioning, and the faulty portion of the scan chain 110b can be narrowed down to one or more of the scan-enabled flip-flop circuits 120e and 120f. The ability to narrow down the identification of a faulty scan-enabled flip-flop circuit in the scan chain can improve the ability to identify design weaknesses so that design changes can be made to improve the functionality and / or reliability of the integrated circuit. In some embodiments, identifying a faulty scan-enabled flip-flop circuit makes it possible to replace the faulty scan-enabled flip-flop circuit with a spare flip-flop circuit, and as a result the integrated circuit can continue to be used.

[0074] Note that the method in Figure 8 includes blocks 810-830. Method 800 may terminate at block 830, or some or all blocks of the method may be repeated. For example, method 800 may repeat blocks 820 and 830 to rescan scan chain 110b with a different known scan chain pattern. In some cases, method 800 or a part thereof may be executed concurrently with other instantiations of the method. For example, scan chains 110a and 110b in Figure 1 may be coupled to different pins in the test input interface 150 and the test output interface 152, thereby allowing their respective scan chain patterns to be shifted simultaneously.

[0075] Moving on to Figure 9, a flowchart of another embodiment of a method for performing a scan test using multiple scan signature circuits is shown. Similar to Method 800, Method 900 may be used in conjunction with any of the systems disclosed herein, such as SoCs 100-300 and 601. Some or all of the operation of Method 900 may be performed using instructions stored in non-temporary computer-readable memory, which are executable by one of the SoCs 100-300 and 601 to produce the operation described with reference to Figure 9. Method 900 is described below using system 600 in Figure 6 as an example. References to elements in Figure 6 are included as non-limiting examples. In some embodiments, Method 900 may be performed after Method 800 has been performed.

[0076] Method 900 begins in 910 with shifting at least a portion of a known scan chain pattern to an output port, and then simultaneously loading the reverse of the known scan chain pattern into a subset of scan-enabled flip-flop circuits using multiple scan signature circuits. As shown, Method 900 is performed, for example, using an embodiment of Method 800, after the known scan chain pattern has been shifted to the test output interface 652. Given one of the scan-enabled flip-flop circuits 620a-620h, for example, scan-enabled flip-flop circuit 620b, is faulty. However, the known scan chain pattern may not be usable to specifically identify scan-enabled flip-flop circuit 620b, even if it can narrow down which of the scan-enabled flip-flop circuits 620a-620h is faulty. Therefore, a second known scan chain pattern is loaded into a subset of scan-enabled flip-flop circuits 620a-620h coupled to each of the scan signature circuits 615. In some embodiments, the test circuit 640 may send an appropriate signal to the scan signature circuit 615 to load a second scan chain pattern. To identify which scan-responsive flip-flop circuit is faulty, the second scan chain pattern is the reverse of a known pattern used when method 800 was performed.

[0077] In 920, method 900 proceeds to shift at least a portion of the inverse of a known scan chain pattern to the output port by a functional part of the scan chain. After the second scan chain pattern is loaded, it is shifted out via the functional part of the scan chain 610, for example, via scan-enabled flip-flop circuits 620e to 620h. The second scan chain pattern is presented at the test output interface 652. In some embodiments, the test device 670 may receive the output of the second scan chain pattern.

[0078] Method 900 continues in 930 by having the test circuit identify the faulty of the multiple scan-enabled flip-flop circuits. In various embodiments, the test circuit 640, the test device 670, or a combination thereof may receive and analyze a second scan chain pattern output from the test output interface 652. By analyzing both the first and second scan chain pattern outputs, the test circuit 640 (or the test device 670) may be able to identify scan-enabled flip-flop circuit 620b as a faulty scan-enabled flip-flop circuit, for example, using the techniques described above with respect to Figures 4 and 5.

[0079] In 940, method 900 proceeds by enabling an alternative scan chain path that bypasses a faulty scan-enabled flip-flop circuit in the scan chain using a test circuit. For example, enabling an alternative scan chain path may include allowing a bypass switch 660a to route the input node of scan-enabled flip-flop circuit 620b to the output node of scan-enabled flip-flop circuit 620b. Enabling the bypass switch 660a may allow the output of scan-enabled flip-flop circuit 620a to be routed around the faulty scan-enabled flip-flop circuit 620b in order to determine whether scan-enabled flip-flop circuit 620a is also faulty.

[0080] In some embodiments, one of the spare scan-enabled flip-flop circuits 622 may be routed in place of the failed scan-enabled flip-flop circuit. For example, bypass switches 660b and 660c illustrate how a spare scan-enabled flip-flop circuit 622g may be routed in place of scan-enabled flip-flop circuit 620g. Such substitution may allow the SoC 601 to continue to be used despite having a failed scan-enabled flip-flop circuit.

[0081] Note that method 900 includes blocks 910-940. Method 900 may terminate at block 940, or it may repeat some or all blocks of the method. For example, method 900 may repeat 910 and 921 one or more times for additional scan chains not shown. In the same manner as described above for method 800, method 900 may be executed concurrently with other instantiations of itself and / or method 800. For example, an instance of method 800 may be executed for a second scan chain, while an instance of method 900 is executed for scan chain 610.

[0082] Figures 1 to 9 illustrate circuits and methods for a system, such as an integrated circuit including a scan chain having a scan signature circuit. Any embodiment of the disclosed system may be included in one or more of a wide variety of computer systems, such as desktop computers, laptop computers, smartphones, tablets, and wearable devices. In some embodiments, the above-described circuits may be implemented on a system-on-a-chip (SoC) or other types of integrated circuits. A block diagram showing one embodiment of system 1000 is shown in Figure 10. In some embodiments, system 1000 may include any disclosed embodiment of the system disclosed herein, such as SoCs 100 to 300 and 601 shown in Figures 1 to 6.

[0083] In the illustrated embodiment, system 1000 includes at least one instance of system-on-chip (SoC) 1006, which may include multiple types of processor circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or others, a communication fabric, and interfaces to memory and input / output devices. SoC 1006 may correspond to instances of SoC disclosed herein. In various embodiments, SoC 1006 is coupled to an external memory circuit 1002, peripheral devices 1004, and a power supply 1008.

[0084] A power supply 1008 is also provided that supplies a supply voltage to the SoC 1006 and one or more supply voltages to the external memory circuit 1002 and / or peripheral device 1004. In various embodiments, the power supply 1008 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 1006 are included (and two or more external memory circuits 1002 are also included).

[0085] The external memory circuit 1002 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.), SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), or static RAM (SRAM). In some embodiments, the external memory circuit 1002 may include non-volatile memory such as flash memory, ferroelectric random access memory (FRAM®), or magnetoresistive RAM (MRAM). One or more memory devices may be coupled on a circuit board to form a memory module such as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Alternatively, the devices may be implemented in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration together with an SoC or integrated circuit.

[0086] The peripheral device 1004 includes any desired circuit configuration depending on the type of system 1000. For example, in one embodiment, the peripheral device 1004 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 1004 also includes additional storage, such as RAM storage, solid-state storage, or disk storage. The peripheral device 1004 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0087] As illustrated, system 1000 is shown to be applicable to a wide range of areas. For example, system 1000 may be used as part of a chip, circuit, or component in a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 1060 are also illustrated. In some embodiments, the smartwatch may include a wide variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. In various embodiments, the smartwatch described above may include some or any health monitoring-related functions, or it may not. Other wearable devices 1060 are also envisioned, such as a device worn around the neck, a device attached to a hat or other headgear, a device implantable in the human body, or glasses designed to provide augmented and / or virtual reality experiences.

[0088] System 1000 may be further used as part of one or more cloud-based services 1070. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 1000 may be used in one or more devices of a home 1080 other than those described above. For example, appliances in a home may monitor and detect conditions of note. Various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and provide alerts to the homeowner (or repair facility) if certain events are detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 10 also shows the application of System 1000 to various modes of transport 1090. For example, System 1000 may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, scooters (rented or owned), etc. In various cases, system 1000 may be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods.

[0089] It should be noted that the diverse potential applications of System 1000 may include a wide variety of performance, cost, and power consumption requirements. Therefore, a scalable solution that allows the use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be beneficial. Many other embodiments of these are possible and contemplated. It should be noted that the devices and applications shown in Figure 10 are illustrative and not intended to be limiting. Other devices are possible and contemplated.

[0090] As disclosed in relation to Figure 10, System 1000 may include one or more integrated circuits contained within a personal computer, smartphone, tablet computer, or other type of computing device. The process of designing and manufacturing an integrated circuit using design information is shown in Figure 11 below.

[0091] Figure 11 is a block diagram showing an example of a non-temporary computer-readable storage medium storing circuit design information according to several embodiments. The embodiment in Figure 11 may be used, for example, in a process for designing and manufacturing an integrated circuit, which includes one or more instances of SoCs (or parts thereof) 100-300 and 601 as shown in Figures 1-6. In the illustrated embodiment, a semiconductor manufacturing system 1120 is configured to process design information 1115 stored in a non-temporary computer-readable storage medium 1110 and to manufacture an integrated circuit 1130 based on the design information 1115.

[0092] The non-temporary computer-readable storage medium 1110 may include any of various suitable types of memory devices or storage devices. The non-temporary computer-readable storage medium 1110 may include installation media, e.g., CD-ROMs, floppy disks, or tape devices; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, or Rambus RAM; non-volatile memory, registers, or other similar types of memory elements, such as flash memory, magnetic media, e.g., hard drives, or optical storage devices. The non-temporary computer-readable storage medium 1110 may also include other types of non-temporary memory, or combinations thereof. The non-temporary computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, e.g., in different computer systems connected via a network.

[0093] The design information 1115 may be specified using any of a variety of suitable computer languages, including but not limited to hardware description languages ​​such as VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, and MyHDL. In some embodiments, the design information 1115 may correspond to the SoC design information 790a and 790b in Figure 7 and may be generated using a computer system 700. The design information 1115 may be made available to a semiconductor manufacturing system 1120 for manufacturing at least a portion of the integrated circuit 1130. The format of the design information 1115 may be recognized by at least one semiconductor manufacturing system, such as the semiconductor manufacturing system 1120. In some embodiments, the design information 1115 may include a netlist specifying the elements of a cell library, as well as their connections. One or more cell libraries used during the logic synthesis of the circuits contained in the integrated circuit 1130 may also be included in the design information 1115. Such a cell library may include information indicating the device or transistor-level netlist, mask design data, characterization data, etc., of the cells contained in the cell library.

[0094] In various embodiments, the integrated circuit 1130 may include one or more custom macrocells, such as memory, analog circuits, or mixed-signal circuits. In such cases, the design information 1115 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a graphics data system (GDSII) or any other preferred format.

[0095] The semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured for manufacturing integrated circuits. These may include, for example, elements for depositing semiconductor material (e.g., on a wafer, which may include masking), removing material, changing the shape of deposited material, and modifying material (e.g., by doping the material or by changing the dielectric constant using ultraviolet treatment). The semiconductor manufacturing system 1120 may also be configured to perform various tests of the manufactured circuit for correct operation.

[0096] In various embodiments, the integrated circuit 1130 is configured to operate according to the circuit design specified by the design information 1115, which may include performing any of the functions described herein. For example, the integrated circuit 1130 may include any of the various elements shown or described herein. Furthermore, the integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components.

[0097] As used herein, the phrase “design information specifying a circuit configured to…” does not mean that the circuit in question must be manufactured for its elements to be fulfilled. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, is configured to perform a specified action or contains specified components. ***

[0098] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concepts. References to “embodiments,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0099] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0100] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0101] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0102] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0103] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0104] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0105] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0106] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0107] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0108] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0109] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0110] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0111] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0112] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase indicates that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.”

[0113] Within this disclosure, various entities (which may be referred to as "units," "circuits," or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when it is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, systems having a processor unit and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0114] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0115] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0116] For the purposes of a U.S. patent application based on this disclosure, any claim that states a structure is “configured” to perform one or more tasks is not expressly intended to invoke Section 112(f) of the U.S. Patent Act with respect to that claim element. If an applicant wishes to invoke Section 112(f) during the examination process of a U.S. patent application based on this disclosure, it would use “means for” performing the function to describe the claim element. ***

[0117] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0118] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0119] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements may be defined by the function or operation they are configured to perform. The arrangement of such circuits / units / components relative to each other and the way they interact generates a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA, forming a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art, presented with the microarchitecture definitions provided pursuant to this disclosure, can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0120] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0121] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. It is a device, Multiple circuit blocks, Multiple scan-enabled flip-flop circuits are sequentially coupled across the aforementioned multiple circuit blocks and configured to shift the scan chain test signal from the test input interface to the test output interface, A plurality of scan signature circuits coupled to one of each of the subsets of the plurality of scan-enabled flip-flop circuits, In response to a specific test signal, a known scan chain pattern is simultaneously loaded into the subset of the scan-enabled flip-flop circuits. Multiple scan signature circuits configured as follows, Equipped with, The apparatus further comprises the plurality of scan-enabled flip-flop circuits, which are configured to sequentially output at least a portion of the known scan chain pattern to the test output interface.

2. The apparatus according to claim 1, wherein, in order to load the known scan chain patterns simultaneously, a given one of the plurality of scan signature circuits is configured to shift the corresponding portion of the known scan chain pattern to one scan input node of each of the subset of scan-enabled flip-flop circuits.

3. The apparatus according to claim 1, wherein the plurality of scan signature circuits are further configured to select one of a plurality of known scan chain patterns to load simultaneously into the subset of scan-responsive flip-flop circuits based on the value of the particular test signal.

4. The apparatus according to claim 3, wherein the first pattern of the plurality of known scan chain patterns is an iterative pattern of a specific sequence of high and low logic states.

5. The apparatus according to claim 3, wherein the first pattern of the plurality of known scan chain patterns is the inverse of the second pattern of the plurality of known scan chain patterns.

6. The apparatus according to claim 1, wherein a given scan-enabled flip-flop circuit is configured to receive data input signals derived based on a plurality of logic paths, each of which includes a scan-enabled flip-flop circuit, and the given scan-enabled flip-flop circuit is excluded from coupling to each scan signature circuit.

7. Identify the faulty one of the aforementioned multiple scan-enabled flip-flop circuits, To enable an alternative scan chain path that bypasses the faulty scan-enabled flip-flop circuit in the scan chain. The apparatus according to claim 1, further comprising a test circuit configured as such.

8. The apparatus according to claim 1, wherein the plurality of scan signature circuits are included in each of the subsets of the plurality of scan-enabled flip-flop circuits.

9. It is a method, A scan chain including multiple scan-enabled flip-flop circuits provides a scan chain pattern from the input port of the test interface of an integrated circuit to the output port of the test interface, wherein at least one of the multiple scan-enabled flip-flop circuits fails to shift the scan chain pattern. After the scan chain pattern fails to shift to the output port, a plurality of scan signature circuits coupled to one of each of the subsets of scan-enabled flip-flop circuits simultaneously load the known scan chain pattern into the subset of scan-enabled flip-flop circuits. The functional portion of the scan chain shifts at least a portion of the known scan chain pattern to the output port, Includes, method.

10. The method according to claim 9, wherein the functional portion of the scan chain includes a sequence of scan-enabled flip-flop circuits positioned between a faulty scan-enabled flip-flop circuit and the output port.

11. After shifting at least the portion of the known scan chain pattern to the output port, the plurality of scan signature circuits simultaneously load the inverse of the known scan chain pattern into the subset of scan-enabled flip-flop circuits. The functional portion of the scan chain shifts at least a portion of the inverse of the known scan chain pattern to the output port, The method according to claim 9, further comprising:

12. Loading the aforementioned known scan chain patterns simultaneously is The first scan signature circuit asserts one set node in each of the subset of scan-enabled flip-flop circuits, While the first scan signature circuit asserts the set node, the second scan signature circuit asserts the reset node of a different subset of the scan-enabled flip-flop circuits, The method according to claim 9, including the method described in claim 9.

13. The test circuit identifies the faulty of the multiple scan-enabled flip-flop circuits, The test circuit enables an alternative scan chain path that bypasses the faulty scan-enabled flip-flop circuit in the scan chain, The method according to claim 9, further comprising:

14. The method according to claim 13, wherein enabling the alternative scan chain path allows the bypass switch circuit to route the input node of the faulty scan-enabled flip-flop circuit to the output node of the faulty scan-enabled flip-flop circuit.

15. A computer-readable non-temporary storage medium storing design information, wherein the design information specifies the design of at least a portion of the hardware integrated circuit in a format recognizable by a semiconductor manufacturing system configured to use the design information to produce a hardware integrated circuit according to the design information, and the design information specifies that the hardware integrated circuit is Multiple circuit blocks, Multiple scan-enabled flip-flop circuits are configured to form one or more scan chains across the aforementioned multiple circuit blocks and to shift scan chain test signals from a test input interface to a test output interface. Multiple scan signature circuits, each included in one of the subsets of the plurality of scan-enabled flip-flop circuits, and configured to simultaneously load known scan chain patterns into the subset of scan-enabled flip-flop circuits in response to a specific signal, Specifying that it be equipped, The plurality of scan-enabled flip-flop circuits are further configured to sequentially output at least a portion of the known scan chain pattern to the test output interface. Computer-readable non-temporary storage medium.

16. The computer-readable non-temporary storage medium according to claim 15, wherein the plurality of scan signature circuits are further configured to simultaneously load a selection of a plurality of known scan chain patterns into the subset of scan-responsive flip-flop circuits based on the value of the particular signal.

17. The computer-readable non-temporary storage medium according to claim 15, wherein the known scan chain pattern is a repeating pattern of a specific sequence of high and low logical states.

18. The computer-readable non-temporary storage medium according to claim 15, wherein the plurality of scan-enabled flip-flop circuits include a given scan-enabled flip-flop circuit configured to form a plurality of scan chains and to receive a threshold number of data input signals derived from the plurality of scan chains, the given scan-enabled flip-flop circuit is excluded from the subset of the plurality of scan-enabled flip-flop circuits.

19. The aforementioned hardware integrated circuit It is a test circuit, Identify the faulty one of the aforementioned multiple scan-enabled flip-flop circuits, To enable an alternative scan chain path that bypasses the faulty scan-enabled flip-flop circuit in the scan chain. A computer-readable non-temporary storage medium according to claim 15, further comprising a test circuit configured as such.

20. In order to enable the alternative scan chain path, the test circuit, In order to route the input node of the faulty scan-enabled flip-flop circuit to the input node of a spare scan-enabled flip-flop circuit, a first set of bypass switch circuits is activated. To route the output node of the spare scan-enabled flip-flop circuit to the output node of the faulty scan-enabled flip-flop circuit, activate a second set of bypass switch circuits. A computer-readable non-temporary storage medium according to claim 19, further configured as follows.

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