A MEMS radio frequency chip test method based on a probe stick de-embedding

Abstract

This application relates to the fields of microelectronics and radio frequency integrated circuit technology, and particularly to a MEMS radio frequency chip testing method based on probe de-embedding. The method includes: constructing a probe-chip optimized model based on the layout of the SAW filter chip under test; fabricating the optimized MEMS probe and performing parasitic effect de-embedding tests on the SAW filter chip under test to obtain the true S-parameters of the chip ports; the de-embedding effect test includes: simultaneously fabricating open-circuit, short-circuit, and through-circuit test structures with the SAW filter chip under test, measuring the S-parameters of three calibration components, and calculating the parasitic network model; and subtracting the parasitic effects from the test results of the chip under test. This application establishes a MEMS probe model through electromagnetic simulation and uses a matching calibration standard substrate for calibration and de-embedding, thereby eliminating the influence introduced by the probe and restoring the true response of the device, thus solving the problem of probes affecting the accuracy of chip testing.

Description

Technical Field

[0001] This application relates to the field of microelectronics and radio frequency integrated circuit technology, specifically to a MEMS radio frequency chip testing method based on probe card de-embedding. Background Technology

[0002] In the context of 5G IoT and other technologies, especially in CP (pre-dicing wafer chip) testing of WLP-packaged SAW devices, wafer testing is crucial for ensuring yield and cost control. As a key interface connecting the test system and the packaged device, the probe card plays a critical role in the reliability of test results when testing electrical performance. Traditional CP test probe cards mainly use cantilever probe cards or spring vertical (pogo pin) probe cards. When testing WLP-packaged SAW devices, especially wafer testing, they have problems such as test passband distortion, mechanical stability, and test consistency, which are difficult to meet the requirements of high-precision testing.

[0003] In existing technologies, MEMS probe cards have become an ideal choice for high-frequency chip testing due to their advantages such as precise dimensions and good high-frequency performance. The physical structure of a MEMS probe card closely approximates a distributed parameter transmission model, maintaining stable characteristic impedance and avoiding or reducing reflections and resonances caused by impedance mismatch. Essentially, the card is a microwave transmission line with specific geometric shapes and material properties, allowing for high-precision modeling and performance prediction using electromagnetic simulation software such as HFSS. However, two major challenges remain when applying MEMS probe cards to test RF chips:

[0004] First, the probe itself is a complex microwave transmission structure. Its intervention will change the electromagnetic environment of the device under test, especially interfering with the acoustic-electric coupling characteristics of acoustic devices (such as SAW / BAW filters). Existing design methods often consider the probe and the chip separately, which makes it impossible to accurately predict the performance under the combined working state.

[0005] Second, parasitic parameters such as probe contact resistance, pad capacitance, and internal chip connection trace resistance in the test path will be superimposed on the chip's actual signal, making the measured S-parameters unable to reflect the true performance of the chip's ports.

[0006] Therefore, there is an urgent need for a method to improve the accuracy and reliability of MEMS probe card testing. Summary of the Invention

[0007] In view of this, this application discloses a MEMS RF chip testing method based on probe card de-embedding to solve the above-mentioned technical problems, including:

[0008] S1. Based on the layout of the SAW filter chip under test, construct a probe model optimized for probe-chip;

[0009] S2. Fabricate MEMS detectors based on the optimized detector model;

[0010] S3. The MEMS probe card made in S2 is used to perform parasitic effect de-embedding test on the SAW filter chip under test to obtain the true S-parameters of the chip port.

[0011] The de-embedding effect test includes: fabricating open-circuit, short-circuit, and through-circuit test structures simultaneously with the SAW filter chip under test; measuring the S-parameters of three calibration components and calculating a parasitic network model based on the S-parameters; testing the SAW filter chip under test and subtracting the parasitic effect from the probe tip to the chip port from the test results based on the parasitic network model.

[0012] The beneficial effects of this application include at least the following:

[0013] This application addresses the problem that cantilever probe cards and pogo pins have large parasitic inductance and inter-segment parasitic capacitance, making it difficult to achieve high-precision error elimination. This results in the actual test results being the frequency response of the "probe card-filter" composite network, causing test passband distortion. By establishing a high-precision model of the MEMS probe card through electromagnetic simulation and using a matching calibration standard substrate for calibration and de-embedding, the influence introduced by the probe card can be effectively eliminated, restoring the true response of the device and solving the problem of probe cards affecting the accuracy of chip testing in existing technologies.

[0014] A high-precision chip de-embedding solution is provided. This solution is based on the OPEN, SHORT, THRU structure of the DUT in the same process and a mature de-embedding algorithm. It can effectively remove parasitic parameters of the test interface and obtain real performance data that is close to the chip design port, which greatly improves the test accuracy and provides a guarantee for the accurate selection of high-performance chips.

[0015] By performing joint electromagnetic simulation of the probe model and chip layout, and then verifying the system in ADS, the impact of probe intervention on the performance of surface acoustic wave (SAW) devices can be predicted in advance, thereby optimizing the probe during the design phase and reducing trial and error costs.

[0016] The method designed in this application includes a closed loop of "design-simulation-processing-testing". The simulation results directly guide the processing of the probe, and the de-embedding method in the testing stage can ensure the comparability of the measured data with the simulation target. This complete quality feedback loop has engineering applicability.

[0017] By restoring the true response of the chip port, this design approach is applicable not only to SAW / BAW filters but also to the development of probe card testing solutions for other high-frequency RF chips that are sensitive to the test interface, providing a design approach for those skilled in the art. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the MEMS RF chip testing method based on probe card de-embedding in the embodiments of this application;

[0019] Figure 2 This is a schematic diagram illustrating the construction of a probe model optimized for probe-chip in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram illustrating the fabrication of the MEMS detector in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of contact pad parasitic de-embedding in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of open-circuit de-embedding of pads in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of pad short-circuit de-embedding in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of pad pass-through de-embedding in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the parasitic parameter model in the embodiments of this application;

[0026] Figure 9 This is a schematic diagram of the on-chip calibration structure layout in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, features, and advantages of this application clearer and to facilitate a better understanding of the technical solutions of this application by those skilled in the art, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments.

[0028] This embodiment includes a MEMS RF chip testing method based on probe de-embedding, applicable to the wafer testing stage, such as... Figure 1 As shown, it includes:

[0029] S1. Based on the layout of the SAW filter chip under test, construct a probe model optimized for probe-chip; specifically, such as... Figure 2 As shown, it includes:

[0030] S11. Obtain the chip layout and pad coordinates of the SAW filter chip under test.

[0031] In this embodiment, the chip layout is specifically an AutoCAD file. In some embodiments, the chip layout may also be a simplified geometric model.

[0032] S12. Based on the pad layout, construct the MEMS probe card model.

[0033] In this embodiment, ANSYS HFSS software is used to model the MEMS probe card. The model structure is: ground-signal-ground, with the signal tip set at the center of the model and ground tips on both sides. The coplanar waveguide transmission line from the tip to the external connection pad is further drawn.

[0034] S13. Perform joint electromagnetic simulation on the MEMS probe model and chip layout, and extract the N-port S-parameter electromagnetic simulation file containing the probe effect.

[0035] Specifically, in the same HFSS project, import the chip layout of the SAW filter and accurately set the material properties and thickness of each layer, such as the piezoelectric substrate (e.g., lithium tantalate) and metal electrodes.

[0036] Move the probe model directly above the chip pads, define all excitation ports, and run a full-wave electromagnetic simulation to solve for the electromagnetic field distribution in the presence of the probe. All excitation ports include filter input / output ports and possible internal nodes.

[0037] After the simulation is completed, export the N-port S-parameter matrix of the entire "probe-chip" system and save it as an S-parameter SnP file, such as Probe_SAW_Model.snp.

[0038] S14. Based on the electromagnetic simulation file, perform circuit-level S-parameter simulation on the SAW filter chip model under test.

[0039] Specifically, open the Keysight ADS software and create a circuit schematic; insert SnP components and import the Probe_SAW_Model.snp file. Simultaneously, insert an S-PARAMETERS model representing the SAW resonator, which is derived from simulation results during the chip's independent design. Connect the SnP components and the SAW resonator model according to the circuit connection relationships. Set the simulation frequency range to 1.5-2.8 GHz and perform S-parameter simulation.

[0040] S15. Based on the S-parameter simulation results, perform detector-chip optimization on the detector model and adjust the detector model.

[0041] The S-parameter simulation results include information such as isolation and passband effect changes. Based on the simulation results, the effects introduced by the probe are evaluated, and the probe structure is optimized in reverse, such as changing the spacing between the signal and the ground signal, and the direction of the transmission line.

[0042] In this embodiment, we take the discovery that the filter's passband insertion loss increased by 0.3 dB due to the proximity effect of the probe's metal structure as an example. Optimizing the MEMS probe model includes: returning to HFSS and modifying the probe model:

[0043] Step 1: Increase the spacing between GSG tips to reduce disturbance to the electric field distribution on the chip surface;

[0044] Step 2: Adjust the transmission line routing to make the path shorter and the bends smoother, in order to reduce unnecessary crosstalk and loss.

[0045] Repeat the iterative simulation until the simulation shows that the insertion loss is less than the preset insertion loss threshold (0.1dB in this embodiment), indicating that the current design has met the requirements and no external matching network is needed.

[0046] S2. Fabricate MEMS detectors based on the optimized detector model.

[0047] Based on the geometric parameters (such as tip size, spacing, transmission line width / spacing, etc.) determined by the final optimized HFSS model, the probe card is processed, as follows: Figure 3 As shown, it includes:

[0048] S21. A sacrificial layer is formed by sputtering silicon oxide on a silicon substrate; a first polyimide film is prepared by spin coating and processed based on photolithography.

[0049] The process is based on photolithography. Photoresist is spin-coated onto a polyimide film, and the probe circuit pattern designed in S1 is transferred onto the photoresist. Development dissolves the photoresist in the exposed area, exposing the polyimide. Reactive ion etching is used to etch away the polyimide that is not protected by the photoresist.

[0050] S22. The first conductive seed layer is prepared based on PVD physical vapor deposition; the conductive seed layer is obtained by sputtering a titanium / copper composite layer on the device surface.

[0051] S23. Prepare a second polyimide film on the first conductive seed layer.

[0052] S24. Prepare the second conductive seed layer.

[0053] S25. The probe tip is formed by electroplating nickel-cobalt.

[0054] S26. Peeling: Deep silicon etching is performed on the device from the bottom, and HF acid is used to etch silicon oxide, selectively dissolving the sacrificial layer, so that the first polyimide film is peeled off from the sacrificial layer, and a thin film probe that can move vertically is obtained.

[0055] S27. Use a support frame to fix the flexible thin film probe so that it can be connected to the external PCB board for circuitry, which facilitates electrical performance testing and completes the fabrication of the MEMS probe card.

[0056] S3. Using the MEMS probe card prepared in S2, a parasitic effect de-embedding test is performed on the SAW filter chip under test to obtain the true S-parameters of the chip port. The de-embedding effect test includes: fabricating open-circuit, short-circuit, and through-circuit test structures simultaneously with the SAW filter chip under test; measuring the S-parameters of the three calibration components; and calculating the parasitic network model based on the S-parameters. The SAW filter chip under test is then tested, and the parasitic effect from the probe tip to the chip port is subtracted from the test results based on the parasitic network model. Specifically, this includes:

[0057] S31. At the edge of the wafer near the surface acoustic wave (SAW) device, OPEN, SHORT, and THRU test structures are fabricated synchronously with the SAW filter chip under test. In this embodiment, the calibration components fabricated synchronously are as follows: Figure 9 As shown in the figure, a, b, and c correspond to open circuit, short circuit, and straight-through structures, respectively.

[0058] S32. Calibrate the probe tip of the MEMS probe card.

[0059] Specifically, mount the probe card on the probe station and connect it to the network analyzer. Use a standard SOLT (Short-Open-Load-Thru) calibration kit to perform calibration at the probe tip port (via an extension cable).

[0060] S33. Measure the S-parameters of the three calibration pieces in sequence.

[0061] Specifically, the probe station is moved to measure the OPEN, SHORT, and THRU structure pads on the wafer and save the corresponding S-parameter files; in this embodiment, they are saved as OPEN.s2p, SHORT.s2p, and THRU.s2p.

[0062] S34. Calculate the parasitic network model based on the S-parameters of the calibration piece.

[0063] Specifically, in the Keysight PNA network analyzer's "De-embed / Embed" settings menu, select the "2-port Adapter" type; in "Method," select "Open-Short-Thru." Import the three files saved in step 3 in sequence. The instrument will then calculate the parasitic network model based on these files.

[0064] S35. Move the probe to the pad of the SAW filter chip under test and test the chip; subtract the parasitic effect between the probe tip and the chip port from the raw data obtained from the test to obtain the true S-parameters of the chip port.

[0065] At this point, the network analyzer is displaying data that has undergone de-embedding, specifically after deducting the probe contact impedance (C) shown in Figure 8. TIP ), solder pad capacitors (C) PAD ), connecting trace resistor (R) PAD S-parameters, reflecting the actual port performance of the chip after parasitic effects.

[0066] The above three stages fully realize the entire process from virtual design to physical testing, and obtain high-precision test results. Comparing the test results after embedding removal with the optimized simulation results of ADS in S14, the two are highly consistent in key indicators, verifying the effectiveness of this method.

[0067] Finally, it should be noted that the above description only depicts some embodiments of this application. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of this application. The scope of protection of this application is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of this application.

[0068] Furthermore, in the above description of the embodiments, unless otherwise explicitly specified and limited, if the terms "upper," "lower," "horizontal," "inner," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not limit or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application; if the terms "first," "second," etc., appear, they are only used to distinguish the description and should not be construed as indicating or implying relative importance. The components shown and described in the accompanying drawings and embodiments can be arranged and designed in various different configurations. The term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. "Horizontal" simply means that its direction is more horizontal than "vertical," not that the structure must be completely horizontal, but rather that it can be slightly tilted. The terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

Claims

1. A MEMS RF chip testing method based on probe de-embedding, characterized in that, include: S1. Based on the layout of the SAW filter chip under test, construct a probe model optimized for probe-chip; S2. Fabricate MEMS detectors based on the optimized detector model; S3. The MEMS probe card made in S2 is used to perform parasitic effect de-embedding test on the SAW filter chip under test to obtain the true S-parameters of the chip port. The de-embedding effect test includes: fabricating open-circuit, short-circuit, and through-circuit test structures simultaneously with the SAW filter chip under test; measuring the S-parameters of three calibration components and calculating a parasitic network model based on the S-parameters; testing the SAW filter chip under test and subtracting the parasitic effect from the probe tip to the chip port from the test results based on the parasitic network model.

2. The MEMS RF chip testing method based on probe de-embedding according to claim 1, characterized in that, The optimization for the probe-chip includes: reducing the disturbance of the probe to the electric field distribution on the chip surface; and adjusting the transmission line routing to reduce unnecessary crosstalk and loss.

3. The MEMS RF chip testing method based on probe de-embedding according to claim 1, characterized in that, The construction of the probe model optimized for probe-chip includes: S11. Obtain the chip layout and pad coordinates of the SAW filter chip under test; S12. Based on the pad layout, construct the MEMS probe model; S13. Perform joint electromagnetic simulation on the MEMS probe model and chip layout, and extract the N-port S-parameter electromagnetic simulation file containing the probe effect. S14. Based on the electromagnetic simulation file, perform circuit-level S-parameter simulation on the SAW filter chip model under test. S15. Based on the S-parameter simulation results, perform detector-chip optimization on the detector model and adjust the detector model.

4. The MEMS RF chip testing method based on probe de-embedding according to claim 3, characterized in that, The constructed MEMS detector model has the following structure: grounding-signal-grounding.

5. The MEMS RF chip testing method based on probe de-embedding according to claim 3, characterized in that, S13~S15 are executed in a loop.

6. The MEMS RF chip testing method based on probe de-embedding according to claim 1, characterized in that, The process of fabricating a MEMS detector based on the optimized detector model includes: S21. A sacrificial layer is formed by sputtering silicon oxide on a silicon substrate; a first polyimide film is prepared by spin coating and processed based on photolithography; S22. The first conductive seed layer is prepared based on PVD physical vapor deposition; S23. Prepare a second polyimide film on the first conductive seed layer; S24. Prepare the second conductive seed layer; S25. The probe tip is formed by electroplating nickel-cobalt. S26. Tear off the film to obtain a thin film probe that can move vertically; S27. Use a support frame to fix the thin film probe and complete the MEMS probe card fabrication.

7. The MEMS RF chip testing method based on probe de-embedding according to claim 6, characterized in that, The film peeling process includes: deep silicon etching of the device from the bottom, immersion in HF acid to etch silicon oxide, and peeling the first polyimide film off from the sacrificial layer.

8. The MEMS RF chip testing method based on probe de-embedding according to claim 1, characterized in that, The de-embedding effect test includes: S31. At the edge of the wafer near the surface acoustic wave (SAW) device, simultaneously fabricate open-circuit, short-circuit, and through-circuit test structures with the SAW filter chip under test. S32. Calibrate the probe tip of the MEMS detector card; S33. Measure the S-parameters of open-circuit, short-circuit, and through-circuit calibration components; S34. Calculate the parasitic network model based on the S-parameters of the calibration piece; S35. Move the probe of the MEMS probe card to the pad of the SAW filter chip under test and test the chip; based on the parasitic network model, subtract the parasitic effect between the probe tip and the chip port from the raw data obtained from the test to obtain the true S-parameters of the chip port.

9. The MEMS RF chip testing method based on probe de-embedding according to claim 8, characterized in that, The parasitic network model calculated based on the S-parameters of the calibration component is implemented using a network analyzer.

10. The MEMS RF chip testing method based on probe de-embedding according to claim 8, characterized in that, The parasitic effects between the probe tip and the chip port include probe contact impedance, pad capacitance, and connection trace resistance.

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