Chip verification method and device, computer device, medium and program product
By automating SoC chip verification using large language models, the problems of low efficiency and poor accuracy of manual verification are solved, and an efficient and accurate chip verification process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNISOC TECH CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-12
AI Technical Summary
In existing technologies, the SoC chip verification process suffers from high labor costs, low efficiency, and low accuracy due to manual operation.
An automated chip verification method based on a large language model is adopted. By obtaining the chip description document, a verification page is generated, and automated verification is performed according to the verification scheme. The verification results are labeled, and historical data is used to optimize the analysis of failure reasons.
Reduce manpower and time costs, improve verification efficiency, avoid human error, ensure verification accuracy, and provide convenient verification results and failure cause analysis.
Smart Images
Figure CN122195744A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a chip verification method, apparatus, computer equipment, medium, and program product. Background Technology
[0002] As the size of SoC (System on Chip) chips continues to increase, the chip documentation becomes more and more complex, and the number of functional points that need to be verified in the documentation is increasing.
[0003] Currently, the functional points that need to be verified are usually extracted from the documentation manually, and verification plans are developed. It is evident that these tasks consume a lot of manpower, have low verification efficiency, and have low verification accuracy due to the bias of manual operation. Summary of the Invention
[0004] Therefore, it is necessary to provide a chip verification method, apparatus, computer equipment, medium, and program product that can save labor costs, improve verification efficiency, and enhance verification accuracy in response to the aforementioned technical problems.
[0005] In a first aspect, this application provides a chip verification method, comprising: obtaining a description document of a chip to be verified; processing the description document based on a first language model to obtain the functions to be verified of the chip and the corresponding verification schemes for the functions to be verified; generating a verification page based on the functions to be verified and the corresponding verification schemes; verifying the corresponding functions to be verified according to the verification schemes to obtain the corresponding verification results, and marking the verification results on the corresponding functions to be verified on the verification page.
[0006] In one embodiment, the method further includes: for the function to be verified that failed verification, obtaining the verification log of the function to be verified; obtaining historical correction record data corresponding to the historical verification failure reasons; and analyzing the verification log based on the historical correction record data according to the second language model to obtain the verification failure reasons of the function to be verified.
[0007] In one embodiment, the method further includes: marking the reason for the verification failure on the corresponding function to be verified on the verification page.
[0008] In one embodiment, the verification failure reason output by the second language model is the first verification failure reason; the method further includes: for the function to be verified that the verification result is failed, analyzing the verification failure reason of the function to be verified according to the verification log of the function to be verified to obtain the second verification failure reason; in response to the fact that the first verification failure reason and the second verification failure reason are different, correcting the verification failure reason of the function to be verified to the second verification failure reason; and saving the correction record data of the verification failure reason.
[0009] In one embodiment, based on a first major language model, the description document is processed to obtain the function to be verified of the chip to be verified and the corresponding verification scheme for the function to be verified. This includes: processing the description document into document data in a preset data format; generating prompt information according to preset verification requirements; and inputting the document data and prompt information into the first major language model to obtain the function to be verified of the chip to be verified and the corresponding verification scheme for the function to be verified.
[0010] In one embodiment, the corresponding function to be verified is verified according to the verification scheme to obtain the corresponding verification result, including: obtaining at least one test case; and verifying the corresponding function to be verified according to the verification scheme based on the at least one test case to obtain the corresponding verification result.
[0011] Secondly, this application provides a chip verification apparatus, comprising: a document acquisition module for acquiring a description document of the chip to be verified; a document processing module for processing the description document based on a first language model to obtain the functions to be verified of the chip and the corresponding verification schemes for the functions to be verified; a page generation module for generating a verification page based on the functions to be verified and the corresponding verification schemes; and a verification processing module for verifying the corresponding functions to be verified according to the verification schemes, obtaining the corresponding verification results, and marking the verification results on the corresponding functions to be verified on the verification page.
[0012] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method provided in the first aspect.
[0013] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in the first aspect.
[0014] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method provided in the first aspect.
[0015] The aforementioned chip verification method, apparatus, computer equipment, medium, and program product, based on the first major language model, process the description document to obtain the functions to be verified and the corresponding verification schemes for the chip under test. Compared to manually extracting the functions to be verified and manually formulating the verification schemes, this application does not require human intervention, reducing labor and time costs and thus improving verification efficiency. It also avoids human error-induced omissions. Based on the functions to be verified and the corresponding verification schemes, a verification page is generated. Chip engineers or other personnel can view each function to be verified and its corresponding verification scheme on the verification page, facilitating manual verification. According to the verification scheme, the corresponding functions to be verified are verified, and the corresponding verification results are obtained. The verification results are marked on the corresponding functions to be verified on the verification page, allowing chip engineers or other personnel to see the verification results for each function and understand the overall verification results of the chip under test. Since no human intervention is required during the verification process, human error can be avoided, improving verification accuracy. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart illustrating a chip verification method in one embodiment;
[0018] Figure 2 This is a flowchart illustrating the cause analysis steps in one embodiment;
[0019] Figure 3 This is a flowchart illustrating the cause labeling steps in one embodiment;
[0020] Figure 4 This is a flowchart illustrating the cause correction steps in one embodiment;
[0021] Figure 5 This is a flowchart illustrating the first major language model processing step in one embodiment;
[0022] Figure 6 This is a flowchart illustrating the verification steps in one embodiment;
[0023] Figure 7 This is a structural block diagram of a chip verification device in one embodiment;
[0024] Figure 8This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0026] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.
[0027] In one exemplary embodiment, a chip verification method is provided, such as... Figure 1 As shown, the chip verification method includes:
[0028] S110, Obtain the description document of the chip to be verified.
[0029] The description document of the chip to be verified includes a detailed description of the chip, such as its various functions and the methods for implementing those functions.
[0030] S120, based on the first major language model, processes the description document to obtain the functions to be verified of the chip and the corresponding verification schemes for the functions to be verified.
[0031] Through pre-training, the first language model has learned to extract the functions to be verified from the description document and to generate verification schemes for each function. Therefore, when the description document is input into the first language model, it can output each function to be verified and the corresponding verification scheme for each function.
[0032] The verification scheme can be understood as a method to verify whether the function to be verified conforms to the corresponding function description information. Different verification schemes are used to detect different functions to be verified.
[0033] For example, for chip A to be verified, the first language model outputs five functions to be verified and their respective verification schemes, and saves the output of the first language model to a preset location in a preset format.
[0034] S130 generates a verification page based on the function to be verified and the corresponding verification scheme.
[0035] The verification page can be in the form of a webpage or other forms, and there are no restrictions here.
[0036] Understandably, the verification page contains various functions to be verified and their corresponding verification schemes.
[0037] In practical scenarios, page generation tools can be used to generate verification pages. Specifically, the page generation tool fills each function to be verified and its corresponding verification scheme into a pre-set page template, thus obtaining the verification page. Chip engineers can then view each function to be verified and its respective verification scheme on the verification page.
[0038] S140, According to the verification scheme, verify the corresponding function to be verified, obtain the corresponding verification result, and mark the verification result on the corresponding function to be verified on the verification page.
[0039] The verification result for a function to be verified can be either successful or unsuccessful. Successful verification indicates that the function to be verified conforms to the corresponding function description information, while unsuccessful verification indicates that the function to be verified does not conform to the corresponding function description information.
[0040] The validation results can also be referred to as regression results.
[0041] The verification results can be saved in JSON format or other formats to the path of the verification page, thereby marking the verification results on the corresponding functions to be verified on the verification page.
[0042] Understandably, once the verification of a function is completed, the verification result is marked on the verification page, allowing chip engineers to see the result. This also helps chip engineers understand which functions have been verified and track the overall verification progress.
[0043] The aforementioned chip verification method, based on the first major language model, processes the description document to obtain the functions to be verified and their corresponding verification schemes for the chip under test. Compared to manually extracting the functions to be verified and manually formulating the verification schemes, this embodiment eliminates the need for human intervention, reducing labor and time costs and thus improving verification efficiency. It also avoids human error in omissions. A verification page is generated based on the functions to be verified and their corresponding verification schemes. Chip engineers or other personnel can view each function to be verified and its corresponding verification scheme on the verification page, facilitating manual verification. The corresponding functions to be verified are then verified according to the verification scheme, yielding the corresponding verification results. These results are marked on the corresponding functions on the verification page, allowing chip engineers or other personnel to see the verification results for each function and understand the overall verification results of the chip under test. Since no human intervention is required during the verification process, human error is avoided, improving verification accuracy.
[0044] Based on the technical solutions provided in the above embodiments, an optional embodiment is provided, in which the chip verification method is further refined to include a cause analysis step.
[0045] See Figure 2 The cause analysis steps include:
[0046] S210: For functions to be verified that failed verification, obtain the verification log of the function to be verified.
[0047] The verification log is the log information generated during the verification process of the function to be verified.
[0048] S220, retrieve the historical correction record data corresponding to the historical verification failure reasons.
[0049] Among them, the reasons for historical verification failures can be understood as the reasons analyzed by the second language model for the historical verification failure results.
[0050] In real-world scenarios, the accuracy of the second language model is initially low, so the reasons for validation failures it outputs may be inaccurate. When the reasons for validation failures are inaccurate, data is recorded to correct the reasons output by the second language model. As the second language model is used more frequently, the reasons for validation failures it outputs become increasingly accurate.
[0051] S230, based on the second largest language model, analyzes the verification logs according to historical correction record data to obtain the reasons for the verification failure of the function to be verified.
[0052] That is, the historical correction record data and the verification log of the function to be verified that failed in this verification are input into the second language model. The second language model analyzes the verification log with the prompts of the historical correction record data, so as to obtain the reason for the failure of this verification, that is, the reason for the verification failure.
[0053] In this embodiment, the second language model analyzes the verification log based on historical correction record data, which can improve the accuracy of the reasons for verification failures. Moreover, compared to manual analysis of reasons, analysis based on the second language model can improve analysis efficiency.
[0054] Based on the technical solutions provided in the above embodiments, an optional embodiment is provided, in which the chip verification method is further refined to include a cause labeling step.
[0055] See Figure 3 The steps for indicating the cause include:
[0056] S310 will indicate the reason for the verification failure on the corresponding function to be verified on the verification page.
[0057] For example, if the verification result of function a to be verified is a failure, the reason for the failure of function a to be verified is analyzed based on the second language model, and the reason for the failure of function a to be verified is marked in the corresponding position of function a to be verified on the verification page.
[0058] In this embodiment, the reason for the verification failure is marked on the corresponding function to be verified on the verification page. This allows chip engineers or other personnel to see the reason for the verification failure on the verification page, which facilitates subsequent analysis or improvement of the chip to be verified.
[0059] Based on the technical solutions provided in the above embodiments, an optional embodiment is provided. In this optional embodiment, the verification failure reason output by the second language model is used as the first verification failure reason, and the chip verification method is refined to include a reason correction step.
[0060] See Figure 4 The steps to correct the cause include:
[0061] S410: For a function to be verified that fails verification, analyze the reasons for the verification failure based on the verification log of the function to be verified to obtain a second reason for verification failure.
[0062] It is evident that S410 does not perform validation failure analysis based on the second major language model. Specifically, the validation logs could be analyzed using highly accurate analysis tools to determine the second validation failure cause. Alternatively, manual analysis of validation failure causes can also be employed, which is not limited here.
[0063] S420, in response to the fact that the first verification failure reason and the second verification failure reason are different, corrects the verification failure reason of the function to be verified to the second verification failure reason.
[0064] For example, for the function to be verified, 'a', the first verification failure reason output by the second language model is 'b', and the second verification failure reason obtained after analysis by S410 is 'c'. Since 'b' and 'c' are different, the second verification failure reason 'c' obtained by analysis by S410 is taken as the correct reason. Therefore, the verification failure reason of the function to be verified, 'a', is corrected from the first verification failure reason 'b' to the second verification failure reason 'c'. Simultaneously, correction record data is obtained: for the function to be verified and its verification log, the verification failure reason of the function to be verified, 'a', is corrected from the first verification failure reason 'b' to the second verification failure reason 'c'.
[0065] S430, save the correction record data for the reason for the verification failure.
[0066] Understandably, the correction record data obtained this time is added to the historical correction record data to update the historical correction record data. In this way, when using the second language model next time, the updated historical correction record data can be used to analyze the reasons for the verification failure.
[0067] In this embodiment, when the second language model is first used and the accuracy of the verification failure reasons analyzed by the second language model is low, the first verification failure reason output by the second language model is corrected based on the second verification failure reason obtained by other methods. This ensures that chip engineers can obtain more accurate verification failure reasons. The correction record data of the verification failure reasons is saved to improve the accuracy of subsequent analyses by the second language model.
[0068] Based on the technical solutions provided in the above embodiments, an optional embodiment is provided, in which the first major language model processing step in S120 is refined.
[0069] See Figure 5 The first major step in refining the language model processing includes:
[0070] S510 processes the description document into document data in a preset data format.
[0071] For example, the description document is parsed into a vector form that the first major language model can recognize.
[0072] S520 generates prompt information based on preset verification requirements.
[0073] In real-world scenarios, chip engineers can generate corresponding prompts based on personalized verification needs (e.g., functions that require key verification, functions that do not require verification, etc.).
[0074] S530: The document data and prompt information are input into the first language model to obtain the function to be verified of the chip and the corresponding verification scheme for the function to be verified.
[0075] As can be seen, the first language model processes the document data under the prompts to extract the functions to be verified and the corresponding verification schemes, thereby meeting personalized verification needs.
[0076] Based on the technical solutions provided in the above embodiments, an optional embodiment is provided, in which the verification steps in S140 are refined.
[0077] See Figure 6 The detailed verification steps include:
[0078] S610, Obtain at least one test case.
[0079] S620 verifies the corresponding function to be verified based on at least one test case and according to the verification scheme, and obtains the corresponding verification results.
[0080] For example, for the function to be verified, a, various test cases applicable to the function are obtained, such as test case d and test case e. Test case d performs functional verification on the function to be verified based on the verification plan, obtaining verification result f. Test case e performs functional verification on the function to be verified based on the verification plan, obtaining verification result g. The verification result of the function to be verified includes: both verification result f and verification result g are successful, or at least one of verification result f and verification result g is a verification failure. For example, if verification result f is a verification failure and verification result g is a verification success, then the verification page will mark the function to be verified as follows: verification result f of test case d is a verification failure, and verification result f of test case g is a verification success. The reasons for the verification failure of test case d will be analyzed and marked in the corresponding position on the verification page.
[0081] In this embodiment, at least one test case is pre-set. Using at least one test case, the corresponding function to be verified is verified according to the verification plan, which can improve verification efficiency. Moreover, test cases can simulate user operations and extreme conditions, thereby identifying logical errors, compatibility issues, or performance bottlenecks in the function to be verified, improving verification accuracy.
[0082] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0083] Based on the same inventive concept, this application also provides a chip verification apparatus for implementing the chip verification method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more chip verification apparatus embodiments provided below can be found in the limitations of the chip verification method described above, and will not be repeated here.
[0084] In one exemplary embodiment, a chip verification apparatus is provided, such as... Figure 7 As shown, the chip verification device includes a document acquisition module 710, a document processing module 720, a page generation module 730, and a verification processing module 740, wherein:
[0085] Document acquisition module 710 is used to acquire the description document of the chip to be verified;
[0086] The document processing module 720 is used to process the description document based on the first major language model to obtain the function to be verified of the chip and the corresponding verification scheme for the function to be verified.
[0087] Page generation module 730 is used to generate a verification page based on the function to be verified and the corresponding verification scheme;
[0088] The verification processing module 740 is used to verify the corresponding functions to be verified according to the verification scheme, obtain the corresponding verification results, and mark the verification results on the corresponding functions to be verified on the verification page.
[0089] In one embodiment, the apparatus further includes: a cause analysis module, configured to: obtain the verification log of the function to be verified for which the verification result is a failure; obtain historical correction record data corresponding to historical verification failure reasons; and analyze the verification log based on the historical correction record data according to the second language model to obtain the verification failure reason of the function to be verified.
[0090] In one embodiment, the apparatus further includes a reason labeling module, used to label the reason for verification failure on the corresponding function to be verified on the verification page.
[0091] In one embodiment, the verification failure reason output by the second language model is the first verification failure reason; the apparatus further includes: a reason correction module, used to analyze the verification failure reason of the function to be verified based on the verification log of the function to be verified for a verification failure result, and obtain a second verification failure reason; in response to the first verification failure reason and the second verification failure reason being different, correcting the verification failure reason of the function to be verified to the second verification failure reason; and saving the correction record data of the verification failure reason.
[0092] In one embodiment, the document processing module is specifically used to: process the description document into document data in a preset data format; generate prompt information according to preset verification requirements; and input the document data and prompt information into the first large language model to obtain the function to be verified of the chip to be verified and the corresponding verification scheme for the function to be verified.
[0093] In one embodiment, the verification processing module is specifically used to: obtain at least one test case; and based on the at least one test case, verify the corresponding function to be verified according to the verification scheme to obtain the corresponding verification result.
[0094] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0095] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 8As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a chip verification method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.
[0096] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0097] In one exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: obtaining a description document of a chip to be verified; processing the description document based on a first language model to obtain the function to be verified of the chip and the corresponding verification scheme for the function to be verified; generating a verification page according to the function to be verified and the corresponding verification scheme; verifying the corresponding function to be verified according to the verification scheme, obtaining the corresponding verification result, and marking the verification result on the corresponding function to be verified on the verification page.
[0098] In one embodiment, when the processor executes the computer program, it further performs the following steps: for the function to be verified that has failed verification, obtain the verification log of the function to be verified; obtain historical correction record data corresponding to the historical verification failure reasons; and analyze the verification log based on the historical correction record data according to the second language model to obtain the verification failure reasons of the function to be verified.
[0099] In one embodiment, when the processor executes the computer program, it also performs the following steps: marking the reason for the verification failure on the corresponding function to be verified on the verification page.
[0100] In one embodiment, the verification failure reason output by the second language model is the first verification failure reason; when the processor executes the computer program, it also performs the following steps: for the function to be verified that has failed verification, analyze the verification failure reason of the function to be verified according to the verification log of the function to be verified to obtain the second verification failure reason; in response to the fact that the first verification failure reason and the second verification failure reason are different, correct the verification failure reason of the function to be verified to the second verification failure reason; and save the correction record data of the verification failure reason.
[0101] In one embodiment, the step of "processing the description document based on the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function" implemented by the processor when executing the computer program includes: processing the description document into document data in a preset data format; generating prompt information according to preset verification requirements; and inputting the document data and prompt information into the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function.
[0102] In one embodiment, the step of "verifying the corresponding function to be verified according to the verification scheme and obtaining the corresponding verification result" implemented by the processor when executing the computer program includes: obtaining at least one test case; verifying the corresponding function to be verified according to the verification scheme based on at least one test case and obtaining the corresponding verification result.
[0103] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: obtaining a description document of a chip to be verified; processing the description document based on a first language model to obtain the function to be verified of the chip and the corresponding verification scheme for the function to be verified; generating a verification page according to the function to be verified and the corresponding verification scheme; verifying the corresponding function to be verified according to the verification scheme, obtaining the corresponding verification result, and marking the verification result on the corresponding function to be verified on the verification page.
[0104] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: for the function to be verified that has failed verification, obtain the verification log of the function to be verified; obtain historical correction record data corresponding to the historical verification failure reasons; and analyze the verification log based on the historical correction record data according to the second language model to obtain the verification failure reasons of the function to be verified.
[0105] In one embodiment, when the computer program is executed by the processor, it also performs the following steps: marking the reason for the verification failure on the corresponding function to be verified on the verification page.
[0106] In one embodiment, the verification failure reason output by the second language model is the first verification failure reason; when the computer program is executed by the processor, it also performs the following steps: for the function to be verified that the verification result is failed, analyze the verification failure reason of the function to be verified according to the verification log of the function to be verified to obtain the second verification failure reason; in response to the fact that the first verification failure reason and the second verification failure reason are different, correct the verification failure reason of the function to be verified to the second verification failure reason; save the correction record data of the verification failure reason.
[0107] In one embodiment, the step of "processing the description document based on the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function" implemented when the computer program is executed by the processor includes: processing the description document into document data in a preset data format; generating prompt information according to preset verification requirements; and inputting the document data and prompt information into the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function.
[0108] In one embodiment, the step of "verifying the corresponding function to be verified according to the verification scheme and obtaining the corresponding verification result" implemented when the computer program is executed by the processor includes: obtaining at least one test case; verifying the corresponding function to be verified according to the verification scheme based on at least one test case and obtaining the corresponding verification result.
[0109] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps: obtaining a description document of a chip to be verified; processing the description document based on a first language model to obtain the functions to be verified of the chip and corresponding verification schemes for the functions to be verified; generating a verification page based on the functions to be verified and the corresponding verification schemes; verifying the corresponding functions to be verified according to the verification schemes, obtaining corresponding verification results, and marking the verification results on the corresponding functions to be verified on the verification page.
[0110] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: for the function to be verified that has failed verification, obtain the verification log of the function to be verified; obtain historical correction record data corresponding to the historical verification failure reasons; and analyze the verification log based on the historical correction record data according to the second language model to obtain the verification failure reasons of the function to be verified.
[0111] In one embodiment, when the computer program is executed by the processor, it also performs the following steps: marking the reason for the verification failure on the corresponding function to be verified on the verification page.
[0112] In one embodiment, the verification failure reason output by the second language model is the first verification failure reason; when the computer program is executed by the processor, it also performs the following steps: for the function to be verified that the verification result is failed, analyze the verification failure reason of the function to be verified according to the verification log of the function to be verified to obtain the second verification failure reason; in response to the fact that the first verification failure reason and the second verification failure reason are different, correct the verification failure reason of the function to be verified to the second verification failure reason; save the correction record data of the verification failure reason.
[0113] In one embodiment, the step of "processing the description document based on the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function" implemented when the computer program is executed by the processor includes: processing the description document into document data in a preset data format; generating prompt information according to preset verification requirements; and inputting the document data and prompt information into the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function.
[0114] In one embodiment, the step of "verifying the corresponding function to be verified according to the verification scheme and obtaining the corresponding verification result" implemented when the computer program is executed by the processor includes: obtaining at least one test case; verifying the corresponding function to be verified according to the verification scheme based on at least one test case and obtaining the corresponding verification result.
[0115] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A chip verification method, characterized in that, include: Obtain the description document of the chip to be verified; Based on the first major language model, the description document is processed to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function. Generate a verification page based on the function to be verified and the corresponding verification scheme; According to the verification scheme, the corresponding functions to be verified are verified to obtain the corresponding verification results, and the verification results are marked on the corresponding functions to be verified on the verification page.
2. The method according to claim 1, characterized in that, The method further includes: For the function to be verified that fails the verification, obtain the verification log of the function to be verified; Retrieve historical correction records corresponding to the reasons for historical verification failures; Based on the second language model, the verification log is analyzed according to the historical correction record data to obtain the reasons for the verification failure of the function to be verified.
3. The method according to claim 2, characterized in that, The method further includes: The reason for the verification failure will be marked on the corresponding function to be verified on the verification page.
4. The method according to claim 2, characterized in that, The validation failure reason output by the second large language model is the first validation failure reason; the method further includes: For the function to be verified that fails the verification, the reasons for the verification failure are analyzed based on the verification log of the function to be verified to obtain a second reason for the verification failure. In response to the fact that the first verification failure reason is different from the second verification failure reason, the verification failure reason of the function to be verified is corrected to the second verification failure reason; Save the correction record data for the verification failure reason.
5. The method according to any one of claims 1 to 4, characterized in that, The description document is processed based on the first major language model to obtain the function to be verified of the chip and the corresponding verification scheme for the function to be verified, including: The description document is processed into document data in a preset data format; Generate prompt information based on preset verification requirements; The document data and the prompt information are input into the first language model to obtain the function to be verified of the chip to be verified and the corresponding verification scheme for the function to be verified.
6. The method according to any one of claims 1 to 4, characterized in that, The step of verifying the corresponding function to be verified according to the verification scheme and obtaining the corresponding verification results includes: Obtain at least one test case; Based on the at least one test case, the corresponding function to be verified is verified according to the verification scheme, and the corresponding verification results are obtained.
7. A chip verification device, characterized in that, The device includes: The document acquisition module is used to acquire the description document of the chip to be verified; The document processing module is used to process the description document based on the first major language model to obtain the verification function of the chip to be verified and the corresponding verification scheme of the verification function. The page generation module is used to generate a verification page based on the function to be verified and the corresponding verification scheme. The verification processing module is used to verify the corresponding functions to be verified according to the verification scheme, obtain the corresponding verification results, and mark the verification results on the corresponding functions to be verified on the verification page.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.