A method and system capable of testing i3c protocol and i2c protocol

Abstract

The application provides a method and system for testing I3C protocol and I2C protocol, which can give consideration to both. The application sends I3C data format to I3C PHY physical layer, and the I3C PHY physical layer forwards the test instruction of the I3C data format to the I3C module to be tested. Then, the I3C module to be tested responds according to the test instruction, and the response to the test instruction is sent to the MCU through the I3C PHY physical layer. The MCU sends the response to the computer control end, and the computer control end judges whether the I3C module to be tested responds correctly according to the returned response. Since the I3C protocol can support the I2C protocol, the application can also send the I2C data format to the I3C module to be tested through the I3C PHY physical layer for testing through the I2C instruction format. Therefore, the application can test the I3C protocol and the I2C protocol.

Description

Technical Field

[0001] This application relates to the field of instruction testing technology, and in particular to a method and system that can test both I3C and I2C protocols. Background Technology

[0002] I3C is a two-wire serial bus protocol launched in 2016 by the MIPI (Mobile Industry Processor Interface) alliance. Its full name is Improved Inter Integrated Circuit, and it aims to optimize the performance bottleneck of the I2C interface while incorporating the advantages of SPI. Given that I3C is a relatively recent bus protocol, there are few similar products on the market, and related testing equipment and methods are even scarcer.

[0003] To address or mitigate the problems in the prior art, embodiments of this application provide a method that can simultaneously test I3C and I2C protocols, including: Test commands are sent via a computer controller and received and parsed by an MCU. The MCU identifies whether the test command is in I3C or I2C data format. If the received test command is in I2C data format, the MCU initializes the I3C PHY physical layer according to the I2C protocol. The MCU sends a test command to the I3C module under test through the I3C PHY physical layer according to the I2C protocol. The MCU receives the corresponding response from the I3C module under test according to the test command and feeds it back to the computer control terminal, waiting for the computer controller to send a new test command. If the received test instruction is in I3C data format, the I3C PHY physical layer is initialized according to the I3C protocol based on the test instruction. The MCU then parses the test instruction, determines the type of the test instruction, and performs the corresponding test based on the type of the test instruction.

[0004] As a preferred embodiment of this application, the step of determining the type of the test instruction based on the test instruction, and performing a corresponding test based on the type of the test instruction, includes: If the test command is a register read / write command, a broadcast command, or a direct command, the MCU sends the test command to the I3C module under test through the I3C PHY physical layer according to the I3C protocol. The MCU receives the corresponding response from the I3C module under test based on the test command and feeds it back to the computer control terminal, waiting for the computer controller to send a new test command.

[0005] As a preferred embodiment of this application, the method further includes: Acquire the communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer and the I3C module under test; The communication signal is analyzed according to the I3C protocol, and the I3C module under test is judged to be responding correctly based on the analysis results.

[0006] Secondly, embodiments of this application also provide a system that can test both I3C and I2C protocols. The system is used to execute the method described in any of the first aspects, including: a computer control terminal, an MCU, an I3C PHY physical layer, and an I3C module under test. The computer control terminal is connected to the MCU via a communication interface. The MCU is connected to the I3C PHY physical layer. The I3C PHY physical layer is connected to the I3C module under test via a clock line and / or a bidirectional data line interface. The computer control terminal sends test commands to the MCU through the communication interface, and at the same time, the communication interface receives feedback signals from the MCU regarding the execution status of the test commands. The test commands are set and configured with different parameters according to the I2C / I3C protocol. The MCU receives test commands sent by the computer control terminal, parses the test commands, and controls the I3C PHY physical layer to perform initialization, I2C register and I3C register read and write operations, and I3C type test command transmission and reception according to the I2C / I3C protocol based on the parsing result. At the same time, it feeds back the results to the computer control terminal based on the execution status. The I3C PHY physical layer receives test commands sent by the MCU and interacts with the I3C module under test via clock lines and / or bidirectional data lines using I2C / I3C information.

[0007] As a preferred embodiment of this application, an I3C signal capture device is also included; The I3C signal capture unit communicates with the clock line and / or bidirectional data line interface; The I3C signal capture device is used to acquire communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer and the I3C module under test.

[0008] Compared with existing technologies, this application provides a method and system that can simultaneously test both I3C and I2C protocols. Since the I3C PHY physical layer is inherently present, but I3C protocol testing equipment is extremely limited, this application sends I3C data in a specific format to the I3C PHY physical layer. The I3C PHY physical layer forwards test commands in the I3C data format to the I3C module under test (DUT). The DUT then responds to the test commands, and the I3C PHY physical layer sends the response to the test commands to the MCU. The MCU then sends the response to the computer control terminal, which determines whether the DUT's response is correct based on the returned response. Because the I3C protocol supports the I2C protocol, this application can also send I2C data in the I3C PHY physical layer to the DUT for testing using I3C command formats. Therefore, this application is compatible with both I3C and I2C protocol testing. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This application provides a flowchart that can simultaneously test both I3C and I2C protocols; Figure 2 This application provides a system block diagram that can simultaneously test I3C and I2C protocols. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0011] Firstly, such as Figure 1 As shown, this application provides a method that can simultaneously test I3C and I2C protocols, including: Step S101: Send test commands through the computer controller, and receive and parse the test commands through the MCU202; It should be noted that the computer control terminal 201 can be test command generation software installed on the computer. Since the computer control terminal 201 is connected to the MCU 202 through a communication interface, when the computer control terminal 201 sends a test command, the MCU 202 will receive the test command. After receiving the test command, the MCU 202 will parse the test command.

[0012] Step S102: The MCU202 identifies whether the test command is in I3C data format or I2C data format; It should be noted that the test instruction includes multiple fields, specifically the test frame length, the test instruction data format, and the test content corresponding to the test instruction; the test content includes the type of test instruction.

[0013] Step S103: If the received test command is in I2C data format, the MCU 202 initializes the I3C PHY physical layer 203 according to the I2C protocol based on the test command; the MCU 202 sends a test command to the I3C module under test 204 through the I3C PHY physical layer 203 according to the I2C protocol; the MCU 202 receives the corresponding response from the I3C module under test 204 based on the test command and feeds it back to the computer control terminal 201, waiting for the computer controller to send a new test command; It should be noted that since one of the fields in the test instruction contains information about the test instruction data format, when the MCU202 receives the test instruction, it can easily obtain the field about the data format after parsing the test instruction, and thus obtain the data format of the test instruction.

[0014] Since the I3C PHY physical layer 203 exists in the MCU 202, and the I3C PHY physical layer 203 can forward both I2C data format and I3C test commands, when the test command is in I2C data format, the I3C PHY physical layer 203 can also forward the I2C test command to the I3C module under test 204. The MCU 202 receives the corresponding response from the I3C module under test 204 according to the test command and feeds it back to the computer control terminal 201, waiting for the computer controller to send a new test command.

[0015] Step S104: If the received test instruction is in I3C data format, the I3C PHY physical layer 203 is initialized according to the I3C protocol based on the test instruction. The MCU 202 further parses the test instruction, determines the type of the test instruction, and performs the corresponding test based on the type of the test instruction.

[0016] It should be noted that, since the I3C PHY physical layer 203 exists in the MCU 202, but there is no dedicated testing device for the I3C protocol, this application forwards I3C data format test instructions through the I3C PHY physical layer 203, further parses the test instructions through the MCU 202, determines the type of the test instructions based on the test instructions, and performs corresponding tests based on the type of the test instructions.

[0017] The step of determining the type of the test instruction based on the test instruction, and performing the corresponding test based on the type of the test instruction, includes: If the test instruction is a register read / write command, broadcast command, or direct command, the MCU 202 sends the test instruction to the I3C module under test 204 through the I3C PHY physical layer 203 according to the I3C protocol. The MCU 202 receives the corresponding response from the I3C module under test 204 according to the test instruction and feeds it back to the computer control terminal 201, waiting for the computer controller to send a new test instruction.

[0018] Specifically, if the test instruction is a register read / write operation, specifically, the test instruction performs read / write operations on the I3C module under test according to the I3C protocol. The I3C module under test automatically recognizes the I3C read / write and provides the corresponding I3C response. After receiving the read / write response, the MCU feeds back the result to the computer control terminal and waits for the computer control terminal to send a new test instruction. If the test is a broadcast command, which is a one-to-many command, the broadcast command is sent through the I3C PHY physical layer 203 according to the I3C protocol. The I3C module under test 204 automatically recognizes the I3C broadcast command and provides the corresponding response. After receiving the response, the MCU 202 feeds back the result to the computer control terminal 201 and waits for the computer control terminal 201 to send a new test instruction. If the test is a direct command, which is a one-to-one command, the direct command is sent through the I3C PHY physical layer 203 according to the I3C protocol. The I3C module under test 204 automatically recognizes the I3C direct CCC command and provides the corresponding response. After receiving the response, MCU202 sends the result back to computer control terminal 201, returns to the main state machine, and waits for computer control terminal 201 to send a new test command.

[0019] The method further includes: Acquire the communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer 203 and the I3C module under test 204; The communication signal is analyzed according to the I3C protocol, and the I3C module under test is judged to be responding correctly based on the analysis results.

[0020] It should be noted that during the test, the I3C signal capture unit 205 can capture waveform data on the clock line and / or bidirectional data line, and perform waveform data judgment according to the I3C protocol.

[0021] Secondly, such as Figure 2 As shown, this application embodiment also provides a system that can test both I3C and I2C protocols. The system is used to execute the method described in any of the first aspects, including: a computer control terminal 201, an MCU 202, an I3CPHY physical layer 203, and an I3C module under test 204. The computer control terminal 201 is connected to the MCU 202 via a communication interface. The MCU is connected to the I3C PHY physical layer 203. The I3C PHY physical layer 203 is connected to the I3C module under test 204 via a clock line and / or a bidirectional data line interface. The computer control terminal 201 sends test commands to the MCU 202 through the communication interface. At the same time, the communication interface receives feedback signals from the MCU 202 regarding the execution status of the test commands. The test commands are set and configured with different parameters according to the I2C / I3C protocol. The MCU 202 receives test commands sent by the computer control terminal 201, parses the test commands, and controls the I3C PHY physical layer 203 to perform initialization, I2C register and I3C register read and write operations, and I3C type test command transmission and reception according to the I2C / I3C protocol based on the parsing result. At the same time, it feeds back the results to the computer control terminal 201 based on the execution status. The I3C PHY physical layer 203 receives test commands sent by the MCU 202 and interacts with the I3C module under test 204 via clock lines and / or bidirectional data lines using I2C / I3C information.

[0022] The system also includes an I3C signal capture device 205; The I3C signal capture device 205 communicates with the clock line and / or bidirectional data line interface. The I3C signal capture device 205 is used to acquire communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer 203 and the I3C module under test 204.

[0023] This application provides a method and system that can test both I3C and I2C protocols. Since the I3C PHY physical layer is inherently present, but I3C protocol testing equipment is extremely rare, this application sends I3C data in a specific format to the I3C PHY physical layer. The I3C PHY physical layer forwards test commands in the I3C data format to the I3C module under test (DUT). The I3C DUT then responds to the test commands, and the I3C PHY physical layer sends the response to the test commands to the MCU. The MCU then sends the response to the computer control terminal, which determines whether the I3C DUT responded correctly based on the returned response. Because the I3C protocol supports the I2C protocol, this application can also send I2C data in the I3C PHY physical layer to the I3C DUT for testing using I3C command formats. Therefore, this application is compatible with both I3C and I2C protocol testing. The embodiments of this application are compatible with both I2C and I3C type testing, and can systematically test I3C modules under test in the absence of I3C testing equipment.

[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method that can simultaneously test I3C and I2C protocols, characterized in that, include: Test commands are sent via a computer controller and received and parsed by an MCU. The MCU identifies whether the test command is in I3C or I2C data format. If the received test command is in I2C data format, the MCU initializes the I3C PHY physical layer according to the I2C protocol based on the test command. The MCU sends test commands to the I3C module under test through the I3C PHY physical layer according to the I2C protocol. The MCU receives the corresponding response from the I3C module under test based on the test command and feeds it back to the computer control terminal, waiting for the computer controller to send new test instructions. If the received test instruction is in I3C data format, the I3CPHY physical layer is initialized according to the I3C protocol based on the test instruction. The MCU then parses the test instruction, determines the type of the test instruction, and performs the corresponding test based on the type of the test instruction.

2. The method for testing both I3C and I2C protocols as described in claim 1, characterized in that, The step of determining the type of the test instruction based on the test instruction, and performing the corresponding test based on the type of the test instruction, includes: If the test command is a register read / write command, a broadcast command, or a direct command, the MCU sends the test command to the I3C module under test through the I3C PHY physical layer according to the I3C protocol. The MCU receives the corresponding response from the I3C module under test based on the test command and feeds it back to the computer control terminal, waiting for the computer controller to send a new test command.

3. The method for testing both I3C and I2C protocols as described in claim 1, characterized in that, The method further includes: Acquire the communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer and the I3C module under test; The communication signal is analyzed according to the I3C protocol, and the I3C module under test is judged to be responding correctly based on the analysis results.

4. A system capable of testing both I3C and I2C protocols, characterized in that, The system is used to perform the method as described in any one of claims 1 to 3, comprising: a computer control terminal, an MCU, an I3C PHY physical layer, and an I3C module under test; The computer control terminal is connected to the MCU via a communication interface. The MCU is connected to the I3C PHY physical layer. The I3C PHY physical layer is connected to the I3C module under test via a clock line and / or a bidirectional data line interface. The computer control terminal sends test commands to the MCU through the communication interface, and at the same time, the communication interface receives feedback signals from the MCU regarding the execution status of the test commands. The test commands are set and configured with different parameters according to the I2C / I3C protocol. The MCU receives test commands sent by the computer control terminal, parses the test commands, and controls the I3C PHY physical layer to perform initialization, I2C register and I3C register read and write operations, and I3C type test command transmission and reception according to the I2C / I3C protocol based on the parsing result. At the same time, it feeds back the results to the computer control terminal based on the execution status. The I3C PHY physical layer receives test commands sent by the MCU and interacts with the I3C module under test via clock lines and / or bidirectional data lines using I2C / I3C information.

5. A system for testing both I3C and I2C protocols as described in claim 4, characterized in that, It also includes an I3C signal catcher; The I3C signal capture unit communicates with the clock line and / or bidirectional data line interface; The I3C signal capture device is used to acquire communication signals on the clock line and / or bidirectional data line between the I3C PHY physical layer and the I3C module under test.

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