FPGA prototype verification system, chip verification method and upper computer

Abstract

Provided in the present application are an FPGA prototype verification system, a chip verification method and an upper computer. The FPGA prototype verification system comprises: N chipsets, each chipset comprising M Chiplet units, each Chiplet unit being used for configuring a functional module to be verified, and N and M both being positive integers; a first communication bus unit, said functional modules configured in all of the Chiplet units being connected to the first communication bus unit, and the first communication bus unit being configured with a first communication protocol for enabling the communication between said functional modules; and a memory connected to the first communication bus unit, said functional modules configured in the Chiplet units accessing the memory by means of the first communication bus unit. The FPGA prototype verification system can improve the efficiency of verifying Chiplets.

Description

FPGA prototype verification system and chip verification method, host computer Technical Field

[0001] This application relates to the field of chip testing, and specifically, provides an FPGA prototype verification system and chip verification method, as well as a host computer. Background Technology

[0002] The more transistors integrated into a single chip, the more prone the chip becomes to defects. Currently, chiplet technology is used to break down complex chips into multiple small, independent, and reusable modules. These modules can be processor cores, memory chips, sensors, or other types of integrated circuits. Finally, multiple chiplets are integrated into a single chip using specific design architectures and packaging technologies to achieve complete functionality. This approach helps simplify the chip design and verification process and improve chip yield.

[0003] Before chip fabrication, FPGA (Field Programmable Gate Array) prototyping is performed to verify the chip's functionality. When verifying chiplets using FPGA prototyping, each chiplet requires an independent DDR MEM (Double Data Rate Memory), which necessitates a large number of pins, resulting in numerous pin constraints, complex architecture, and high design difficulty.

[0004] On the other hand, in some systems that include multiple chiplets, these chiplets communicate with each other via a UCIe (Universal Chiplet Interconnect Express) bus. Therefore, when verifying chiplets using FPGA prototyping, multiple chiplets are typically connected via a UCIe bus in the FPGA prototyping system to test data transmission between different chiplets. However, using the UCIe bus requires designing circuit boards with corresponding conversion circuits for the connections between each chiplet, resulting in long design, production, and debugging cycles for UCIe bus circuit boards. Summary of the Invention

[0005] In view of this, this application aims to provide an FPGA prototype verification system, chip verification method, and host computer to reduce the time required for FPGA prototype verification of Chiplet and improve verification efficiency.

[0006] In a first aspect, embodiments of this application provide an FPGA prototype verification system, comprising: N chipsets, each chipset including M chipplet units, each chipplet unit being configured with a functional module to be verified; wherein N and M are both positive integers; a first communication bus unit, wherein the functional modules to be verified configured in all the chipplet units are respectively connected to the first communication bus unit; the first communication bus unit is configured with a first communication protocol enabling communication between the functional modules to be verified; and a memory connected to the first communication bus unit; wherein the functional modules to be verified configured in each chipplet unit access the memory through the first communication bus unit.

[0007] Verifying a chiplet is essentially verifying the corresponding functional module. In this embodiment, chiplet units are pre-configured in the FPGA prototype verification system. During FPGA prototype verification, the functional module to be verified can be configured into the chiplet unit, enabling the configured chiplet unit to perform the chiplet's function and thus verifying the functional module within the chiplet. Chiplet requires a UCIe protocol board connection; however, in this embodiment, since the verification focuses on the functional module rather than the chiplet itself, there is no need for UCIe protocol-compliant boards to connect and communicate between chiplet units. Because the functional modules within a chiplet communicate using a first protocol, a first communication bus unit can be set up to allow communication between chiplet units containing the functional module to be verified. Furthermore, since each chiplet unit is connected to the first communication bus unit and accesses memory through it, rather than each chiplet unit accessing memory separately, the number of pins and pin constraints are reduced, simplifying the architecture and lowering the design difficulty of the FPGA prototype verification system for testing chiplets.

[0008] In one embodiment, the FPGA prototype verification system includes an FPGA prototype verification board, on which the first communication bus unit and all the chipsets are disposed.

[0009] In this embodiment, the first communication bus unit and all chipsets are mounted on the FPGA prototype verification board, which improves the integration of the FPGA prototype verification system. This allows communication between chipsets through the internal circuitry of the FPGA prototype verification board, reducing the impact of external interference on test accuracy. Simultaneously, it simplifies testing, reducing the need for connections between chipsets and between chipsets and the first communication bus unit during actual testing. Only the functional module to be verified needs to be configured to its corresponding position on the FPGA prototype verification board.

[0010] In one embodiment, the number of memories is 1; the memory is divided into M subspaces according to the address space, and each subspace corresponds to one chiplet unit.

[0011] Each chiplet requires a corresponding memory. In this embodiment, the memory address space is divided into multiple subspaces, so that each chiplet unit has a corresponding subspace. Through the first communication bus unit, the functional modules to be verified in each chiplet unit can access the memory. This makes each subspace equivalent to the memory corresponding to each chiplet unit. Therefore, only one memory needs to be set up, reducing the use of memory and thus reducing the complexity and cost of the verification system during verification.

[0012] In one embodiment, the memory includes a double-rate synchronous dynamic random access memory.

[0013] In this embodiment, Double Data Rate Synchronous Dynamic Random Access Memory (DDR) has high data transfer efficiency, which can improve the efficiency of FPGA prototype verification. Furthermore, DDR is widely used; using DDR as the memory in the FPGA prototype verification system of this application allows verification based on the FPGA prototype verification system provided in this application to match most real-world scenarios, resulting in verification results that are closer to actual scenarios.

[0014] In one embodiment, the first communication bus unit includes M bandwidth modules, each bandwidth module corresponding to a subspace; each bandwidth module is connected to a different chipplet unit, and the subspace corresponding to the bandwidth module is the same as the subspace corresponding to the chipplet unit to which the bandwidth module is connected; the bandwidth module is used to configure the bandwidth blocking and clock delay of signal transmission between the chipplet unit connected to the bandwidth module and the memory.

[0015] During use, chiplets utilize the UCIe bus to transmit signals between different chiplets. The UCIe bus circuit board experiences clock delays and bandwidth congestion during signal transmission. In this embodiment, a corresponding bandwidth module is configured for each chiplet unit to access its corresponding subspace. This bandwidth module can be configured with bandwidth congestion and clock delay, thereby providing a more realistic verification environment and improving verification effectiveness.

[0016] In one embodiment, each bandwidth module includes a bandwidth register and a delay register; the bandwidth register and the delay register are connected in series and connected between the chiplet cell corresponding to the bandwidth module and the memory; the bandwidth register is configured with a preset periodic gating signal, and the bandwidth register is used to control the blocking of signal transmission between the chiplet cell and the memory based on the periodic gating signal; the delay register is configured with a preset clock delay, and the delay register is used to control the clock delay of signal transmission between the chiplet cell and the memory based on the preset clock delay.

[0017] In this embodiment, registers are used to simulate bandwidth blocking and clock delay, which effectively reduces the complexity of simulating bandwidth blocking and clock delay and simplifies the structure of the FPGA prototype verification system.

[0018] In one embodiment, each chipset further includes a second communication module, which is configured with a second communication protocol that enables the functional module to be verified to communicate with external devices, and each chipset is connected to the host computer through the second communication module; the second communication module is connected to each chipplet unit in the chipset in which the second communication module is located, and the second communication module is used to convert the control instructions of the second communication protocol output by the host computer into control instructions of the first communication protocol.

[0019] FPGA prototyping involves porting the timing control code of the designed chip into the FPGA and evaluating its functionality and timing. This requires control from a host computer. For the functional module to be verified, the host computer is an external device. When the chip communicates, the communication protocols used between internal functional modules are usually different from the communication protocols between the chip and external devices. In the embodiments of this application, a second communication module is configured in each chipset of the FPGA prototyping board. The second communication module enables the chipplet unit to access external devices and converts control commands into control commands that the functional module to be verified can execute. This simulates the communication between the chipplet unit and external devices in a real-world scenario and performs verification, improving the accuracy of the verification results.

[0020] In one embodiment, each of the Chiplet units further includes: a first DMA (Direct Memory Access) module, the first DMA module being connected to the first communication bus unit and the second communication module respectively; the first DMA module is used to access the subspace of the memory corresponding to other Chiplet units within the same chipset, excluding the Chiplet unit where the first DMA module is located, through the first communication bus unit.

[0021] A device contains multiple functional modules, and different functional modules may interact with each other. In this embodiment, the first DMA module can enable each chipplet unit to access the memory subspace corresponding to other chipplet units outside itself, thereby simulating the interaction within the same device and verifying the interaction between different chipplet units of the same chipset.

[0022] In one embodiment, the first DMA module includes a selection submodule, which is used to select a corresponding bandwidth module according to the subspace to be accessed by the control instruction, so as to access the subspace based on the corresponding bandwidth module.

[0023] In this embodiment, the number of memories can be one. When there is only one memory, it is divided into multiple subspaces according to addresses, so that each chiplet unit can have a corresponding subspace. Unlike the method where each chiplet unit corresponds to one memory, different subspaces within a memory need to be distinguished by different addresses. That is, each subspace corresponds to a different address in the memory. Therefore, different addresses can be selected by selecting a submodule, thereby realizing the selection of different subspaces within a memory.

[0024] In one embodiment, each of the chipsets further includes a second DMA module, which is connected to the first communication bus unit and the second communication module respectively; the second DMA module is used to access all subspaces of the memory corresponding to all the chiplets.

[0025] Data interaction also exists between different devices. In the embodiments of this application, by setting a second DMA module, the Chiplet unit can access the memory subspace of other chipsets outside its own chipset, thereby verifying the interaction between Chiplet units of different chipsets.

[0026] In one embodiment, each chipset further includes: a proxy module; the proxy module is connected to each of the first DMA modules and the second DMA modules in the chipset where the proxy module is located, and the proxy module is also connected to the second communication module; the proxy module is further configured to convert the control commands output by the second communication module into control signals of the protocols supported by the second DMA module and each of the first DMA modules.

[0027] The second communication protocol module is used to convert the control commands of the second communication protocol of the external device into control commands of the first communication protocol. However, the first DMA module and the second DMA module may not support the control commands of the first communication protocol. Therefore, in this embodiment, a proxy module can also be set to convert the control commands output by the second communication module into control signals of the protocols supported by the first DMA module and the second DMA module.

[0028] In one embodiment, the proxy module is further configured to connect to the functional module to be verified; each chipset further includes a functional protocol conversion module, which is connected to the proxy module and each of the functional modules to be verified respectively; the proxy module is further configured to convert the control commands output by the second communication module into control signals of the protocol supported by the second DMA module or the first DMA module, and the functional protocol conversion module is configured to convert the control signals of the protocol supported by the second DMA module or the first DMA module into control signals of the protocol supported by each of the functional modules to be verified.

[0029] The control commands output by the host computer may not be usable by the functional modules to be verified. Therefore, in the embodiments of this application, on the basis that the proxy module has already performed a conversion, a functional protocol conversion module can be set up to further convert the control signals of the protocol supported by the second DMA module or the first DMA module into the control signals of the protocol supported by each functional module to be verified.

[0030] In one embodiment, the FPGA prototype verification system further includes a physical layer interface module, which is connected to the first communication bus unit and the memory respectively. The physical layer interface module is used to convert the digital signal output by the first communication bus unit into an analog signal and store it in the memory. The physical layer interface module is also used to convert the analog signal output by the memory into a digital signal and transmit it through the first communication bus unit.

[0031] In this embodiment of the application, by setting a physical layer interface module, the first communication bus unit can access the memory, thereby realizing reading and storing.

[0032] In one embodiment, the physical layer interface module is disposed on the FPGA prototype verification board, and the physical layer interface module includes a physical layer chip with the same control logic as the FPGA prototype verification board.

[0033] In this embodiment, the physical layer interface module includes the same control logic as the FPGA prototype verification board. This simplifies the structure, eliminates the need for additional circuit boards to implement the corresponding conversion logic, and improves verification efficiency.

[0034] Secondly, embodiments of this application provide a verification method applied to a functional module to be verified, the functional module to be verified being configured in a Chiplet unit of an FPGA prototype verification system as described in any of the first aspects, the FPGA prototype verification system being connected to a host computer; the chip verification method includes: receiving a control command generated by the host computer; and in response to the control command, accessing a memory based on a first communication bus unit.

[0035] Thirdly, embodiments of this application provide a verification method applied to a host computer, wherein the host computer is communicatively connected to an FPGA prototype verification system as described in any of the first aspects, and the chip verification method includes: sending a control command to the FPGA prototype verification system to control the functional module to be verified to access the memory based on a first communication bus unit, wherein the functional module to be verified is pre-configured in the Chiplet unit of the FPGA prototype verification system.

[0036] Fourthly, embodiments of this application provide a host computer, which includes a storage unit, a processor, and a communication unit; the communication unit is used to communicate with an FPGA prototyping system as described in any of the first aspects; the storage unit stores computer-readable instructions, which, when executed by the processor, configure the host computer to: send control instructions to the FPGA prototyping system to control the functional module to be verified to access the memory based on a first communication bus unit, wherein the functional module to be verified is pre-configured in the chiplet unit of the FPGA prototyping system. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 is a schematic diagram of an FPGA prototype verification system provided in an embodiment of this application;

[0039] Figure 2 is a schematic diagram of the extended structure of an FPGA prototype verification system provided in an embodiment of this application;

[0040] Figure 3 is a schematic diagram of memory partitioning in one embodiment of this application;

[0041] Figure 4 is a schematic diagram showing the relationship between the functional module to be verified and the bandwidth module provided in an embodiment of this application;

[0042] Figure 5 is a schematic diagram of the structure of a bandwidth module provided in an embodiment of this application;

[0043] Figure 6 is a schematic diagram of the working signals of a bandwidth register provided in an embodiment of this application;

[0044] Figure 7 is a schematic diagram of the working signals of a delay register provided in an embodiment of this application;

[0045] Figure 8 is a schematic diagram showing the relationship between the first DMA module and the first communication bus unit provided in an embodiment of this application;

[0046] Figure 9 is a schematic diagram showing the relationship between the second DMA module and the first communication bus unit provided in an embodiment of this application;

[0047] Figure 10 is a schematic diagram of signal transmission of an FPGA prototype verification system provided in an embodiment of this application;

[0048] Figure 11 is a flowchart of a chip verification method applied to a functional module to be verified according to an embodiment of this application;

[0049] Figure 12 is a schematic diagram of a host computer provided in an embodiment of this application.

[0050] Icons: Chipset 100; Chiplet unit 110; Functional module to be verified 111; First DMA module 112; Second communication module 120; Second DMA module 130; Proxy module 140; First communication bus unit 200; Bandwidth module 210; Bandwidth register 211; Delay register 212; Memory 300; FPGA prototype verification board 400; Physical layer interface module 410; Host computer 500; Processor 510; Storage unit 520; Communication unit 530. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0052] First, this application provides an FPGA prototype verification system. Please refer to Figure 1. Figure 1 is a schematic diagram of an FPGA prototype verification system provided in an embodiment of this application. The FPGA prototype verification system includes: N chipsets 100, a first communication bus unit 200, and a memory 300.

[0053] In the embodiments of this application, each chipset 100 includes M Chiplet units 110, and each Chiplet unit 110 is used to configure the functional module 111 to be verified.

[0054] In this embodiment, apart from the functional module 111 to be verified, the other structures of each Chiplet unit 110 can be identical. Each Chiplet unit 110 can be pre-built, and during FPGA prototype verification, the functional module 111 to be verified, built based on the functionality of the Chiplet to be verified, can be configured within each Chiplet unit 110. That is, in this embodiment, the functional module corresponding to the Chiplet is verified, rather than the Chiplet itself. By placing the functional module 111 to be verified into the Chiplet unit 110, the functional module 111 to be verified and the Chiplet unit 110 can jointly simulate a Chiplet.

[0055] Functional modules can be pre-designed circuit functional modules in ASICs (Application Specific Integrated Circuits) or FPGAs. For example, functional modules can include IP cores (intellectual property cores), which can include Soft IP Cores, Hard IP Cores, and Firm IP Cores. Soft cores are functional blocks described in HDL (Hardware Description Language), hard cores are design modules described in layout form based on specific design processes, and firm cores are synthesized functional blocks provided in the form of netlists. Functional modules can refer to existing technologies and will not be described in detail here. In the embodiments of this application, the functional module 111 to be verified has the same function as the chiplet to be verified.

[0056] In the embodiments of this application, the number of chipsets 100 is N, where N and M are both positive integers, and N and M can be the same or different, without limitation. A chiplet is a design method that breaks down a complex chip into multiple small, independent, and reusable modules. That is, it breaks down different functions of a complex chip into different functional modules, executed by different chiplets. Therefore, in the embodiments of this application, chipset 100 can be used to simulate a complex chip, which includes multiple chiplets. Chiplet units 110 are used to simulate chiplets. The number of chipsets 100 and the number of chiplet units 110 can be configured according to the number of complex chips and chiplets to be verified, without limitation. For example, when only one chiplet needs to be verified, both N and M can be 1; when chiplets corresponding to different functional modules of the same complex chip need to be verified, N can be 1, and M can be greater than or equal to 2; when the interaction between chiplets corresponding to functional modules of different complex chips needs to be verified, both N and M can be greater than or equal to 2. Taking Figure 1 as an example, in the embodiment shown in Figure 1, the product to be verified includes two chips, which correspond to two chipsets 100 respectively. Each chip includes four chiplets. The function of each chiplet is constructed as a functional module and configured in a chiplet unit 110. Each chiplet unit 110 is used to simulate a chiplet.

[0057] The first communication bus unit 200, and the functional modules 111 to be verified configured in all Chiplet units 110 are respectively connected to the first communication bus unit 200.

[0058] In the embodiments of this application, the first communication bus unit 200 is configured with a first communication protocol that enables communication between the various functional modules 111 to be verified. That is, the first communication bus unit 200 is for communication between the functional modules, and the first communication protocol is the protocol that enables communication between the functional modules inside the chip. Therefore, the first communication bus unit 200 can be an AMBA (Advanced Microcontroller Bus Architecture) bus, including but not limited to the AXI (Advanced Extensible Interface) bus and the AHB (Advanced High-performance Bus) bus in the AMBA bus.

[0059] The memory 300 is connected to the first communication bus unit 200 and is used to provide storage space so that each functional module 111 to be verified can store or read data.

[0060] In the embodiments of this application, the memory 300 may be DDR MEM (Double Data Rate Memory), including but not limited to DDR SDRAM (Double Data Rate SDRAM, DDR), DDR2 SDRAM (DDR2), DDR3 SDRAM (DDR3), DDR4 SDRAM (DDR4), etc. Compared with other memories, DDR MEM has a higher data transfer bandwidth, which helps to improve data transfer efficiency and verification efficiency.

[0061] In other embodiments, the memory 300 may also use SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), etc., without limitation.

[0062] In the embodiments of this application, verifying a Chiplet is actually verifying the functional module corresponding to the Chiplet. Therefore, the Chiplet unit 110 can be pre-configured in the FPGA prototype verification system. When performing FPGA prototype verification, the functional module 111 to be verified can be configured into the Chiplet unit 110 so that the Chiplet unit 110 after configuring the functional module 111 to be verified can realize the function of the Chiplet, thereby realizing the verification of the functional module in the Chiplet.

[0063] Unlike chiplet verification (which requires circuit boards to connect chiplets via various communication protocols such as UCIe), this embodiment verifies the functional module 111 to be verified, rather than the chiplets themselves. Therefore, chiplet units 110 do not need to use circuit boards corresponding to the UCIe protocol for connection and communication. Instead, they can communicate using a first protocol (such as the AXI bus) between the functional modules within the chiplet. Thus, a first communication bus unit 200 can be set up to enable communication connections between chiplet units 110, including the functional module 111 to be verified. This eliminates the need to design and manufacture UCIe circuit boards, effectively reducing the time required for circuit board design and manufacturing, and shortening the verification cycle.

[0064] Furthermore, since each Chiplet unit 110 is connected to the first communication bus unit 200 and accesses the memory 300 uniformly through the first communication bus unit 200, instead of each Chiplet unit 110 being connected to the memory 300 separately, the number of pins and the constraints on the pins can be reduced, the architecture can be simplified, and the design difficulty of the FPGA prototype verification system for testing Chiplet can be reduced.

[0065] In the embodiments of this application, the FPGA prototype verification system may further include an FPGA prototype verification board 400, on which the structure including the first communication bus unit 200 and all chipsets 100 are disposed.

[0066] Please refer to Figure 2, which is a schematic diagram of the extended structure of an FPGA prototype verification system provided in an embodiment of this application. In this embodiment, except for the memory 300, all other structures in the FPGA prototype verification system are mounted on the FPGA prototype verification board 400. When using the FPGA prototype verification system provided in this embodiment for verification, the hardware structures that actually need to be changed each time are the functional module 111 to be verified and the memory 300. The other structures can remain unchanged. Therefore, for structures that do not need to be changed, they can be integrated using the FPGA prototype verification board 400 to improve the verification efficiency each time the FPGA prototype is verified. Only the functional module 111 to be verified needs to be replaced, and the memory 300 connected to the FPGA prototype verification board 400 needs to be replaced. There is no need to assemble other structures in the FPGA prototype verification system except for the functional module 111 to be verified, and there is no need to reconsider the connection method between the modules. This reduces the occurrence of situations where the FPGA prototype verification system cannot obtain accurate verification results due to improper operation.

[0067] Each chiplet requires a corresponding memory 300. Therefore, in some embodiments of this application, the number of memory 300 can be M, which is the same as the number of chiplet units 110, with each chiplet unit 110 corresponding to one memory 300.

[0068] Referring again to Figure 1, in some embodiments of this application, the number of memory 300 may also be one. The memory 300 is divided into M subspaces according to the address space, and each subspace corresponds to a chiplet unit 110.

[0069] The memory 300 can be divided according to its address space by dividing it equally according to the address space order based on its capacity. Please refer to Figure 3, which is a schematic diagram of memory 300 division in one embodiment of this application. In this embodiment, the memory 300 is a DDR MEM with a capacity of 16GB. As shown in the embodiment of Figure 1, the number of Chiplet units 110 is 8. Corresponding to the embodiment of Figure 1, the memory 300 is divided into 8 subspaces, each with a capacity of 2GB. The resulting subspaces include: subspaces with addresses 0G to 2G, 2G to 4G, 4G to 6G, 6G to 8G, 8G to 10G, 10G to 12G, 12G to 14G, and 14G to 16G.

[0070] In some embodiments of this application, the memory 300 can be divided into multiple subspaces with different capacities according to the address space, based on the memory space required by each functional module.

[0071] In some embodiments of this application, the number of memories 300 can also be N, each memory 300 corresponds to a chipset 100, and the address space of each memory 300 is divided according to the number of chiplets 110 in the chipset 100.

[0072] In the embodiments of this application, the first communication bus unit 200 includes M bandwidth modules 210, each bandwidth module 210 corresponds to a subspace, each bandwidth module 210 is connected to a different Chiplet unit 110, and the subspace corresponding to the bandwidth module 210 is the same as the subspace corresponding to the Chiplet unit 110 to which the bandwidth module 210 is connected.

[0073] During data transmission, the UCIe protocol experiences transmission delays and bandwidth congestion due to excessive bus load, leading to delays and bandwidth blocking. In actual chiplet testing, the impact of transmission delays and bandwidth congestion on interactions between different chiplets must be considered. In the embodiments of this application, the first communication bus unit 200 is used for data transmission. Therefore, a bandwidth module 210 can be configured in the first communication bus unit 200, and bandwidth congestion and clock delay for signal transmission between the chiplet unit 110 connected to the bandwidth module 210 and the memory 300 can be configured within the bandwidth module 210 to simulate clock delays and bandwidth congestion during UCIe bus data transmission.

[0074] Please refer to Figure 4, which is a schematic diagram of the relationship between the functional module 111 to be verified and the bandwidth module 210 provided in an embodiment of this application. In this embodiment, the subspace corresponding to the functional module 111 to be verified is 0G to 2G. In the embodiments of this application, each functional module 111 to be verified can directly access the subspace corresponding to that functional module 111. Therefore, a corresponding bandwidth module 210 can be configured for each functional module 111 to simulate the clock delay and bandwidth blocking of different functional modules 111 to the memory 300.

[0075] Please refer to Figure 5, which is a schematic diagram of the structure of a bandwidth module 210 provided in one embodiment of this application. In one embodiment of this application, each bandwidth module 210 includes a bandwidth register 211 and a delay register 212; the bandwidth register 211 and the delay register 212 are connected in series, and the order of the bandwidth register 211 and the delay register 212 is not limited. The bandwidth register 211 and the delay register 212 are connected between the chiplet unit 110 and the memory 300 corresponding to the bandwidth module 210.

[0076] In this embodiment, the bandwidth register 211 is configured with a preset periodic gating signal. The bandwidth register 211 is used to control the blocking of signal transmission between the Chiplet unit 110 and the memory 300 based on the periodic gating signal.

[0077] Please refer to Figure 6, which is a schematic diagram of the working signals of the bandwidth register 211 provided in an embodiment of this application. In this embodiment, the signal can only be transmitted when the bandwidth is high, that is, m_rvalid = s_rvalid & bandwidth.

[0078] & represents a bitwise AND operation, s_rvalid represents the input control signal, m_rvalid represents the output control signal, and bandwidth is a preset periodic gating signal.

[0079] In this embodiment, based on a preset periodic gating signal, the frequency of the output control signal can be reduced. When the control signal is transmitted, the frequency of transmission based on the m_rvalid control signal is even lower, thereby simulating bandwidth blocking.

[0080] The delay register 212 is used to control the clock delay of signal transmission between the Chiplet unit 110 and the memory 300 based on a preset clock delay. For example, please refer to FIG7, which is a schematic diagram of the working signals of the delay register 212 provided in an embodiment of this application. In this embodiment, the clock delay is latency, that is, 4 clock cycles. Compared with s_rvalid, the clock of m_rvalid will be delayed by 4 cycles, thereby simulating the clock delay at the data transmission end.

[0081] Furthermore, the handshake signals in the AXI protocol include: bvalid, bready, wvalid, wready, arvalid, already, awvalid, and awready. In the embodiments of this application, bvalid / bready is only controlled by the latency signal, and wvalid / wready is only controlled by the bandwidth signal. arvalid / arready and awvalid / awready are transmitted directly without control. The types and functions of the aforementioned handshake signals can be found in existing technologies and will not be elaborated upon here.

[0082] In the embodiments of this application, each Chiplet unit 110 further includes a first DMA module 112, and each chipset 100 further includes a second communication module 120, a second DMA module 130, and a function protocol conversion module.

[0083] The second communication module 120 is configured with a second communication protocol that enables the functional module 111 to communicate with external devices, and each chipset 100 is connected to the host computer through the second communication module 120.

[0084] There are various communication protocols, each with different functions. For example, the aforementioned AXI and AHB protocols enable communication within the chip itself. However, when the chip communicates with external devices, such as a host computer, the host computer typically uses the PCIe protocol to issue control signals to the FPGA. The FPGA, however, usually uses an AMBA bus (such as AXI) for data exchange, and the two are not interoperable. A protocol typically used for communication with external devices is used. For example, the PCIe interface can be configured with various protocols. Therefore, in the embodiments of this application, the second communication protocol can be any protocol configured on the PCIe interface, and the second communication module 120 can be a PCIe module. Alternatively, it could be a protocol configured on an interface such as USB (Universal Serial Bus), TCP (Transmission Control Protocol), or M.2 (a new host interface scheme). The second communication module 120 can be a module for the corresponding interface.

[0085] In this embodiment, the second communication module 120 is connected to each chiplet unit 110 in the chipset 100 where the second communication module 120 is located. The second communication module 120 can convert the control commands of the second communication protocol output by the host computer into control commands of the first communication protocol.

[0086] For example, the second communication module 120 is configured with a conversion relationship between the PCIe protocol and the AXI protocol, which can convert PCIe protocol control signals into AXI protocol control signals to be sent to each functional module 111 to be verified or the memory 300. The conversion relationship between the PCIe protocol and the AXI protocol can be implemented by the AXI-Bridge-PCIe IP. The AXI-Bridge-PCIe IP (AXI bus bridge) is a functional module for protocol conversion, which dynamically maps the AXI4 (a type of AXI protocol) memory-mapped address range provided by the AXI BAR (AXI base address register) parameter to the PCIe address range, so as to realize the conversion between the PCIe protocol and the AXI protocol.

[0087] The functional module 111 to be verified can directly access the memory 300 through the first communication bus unit 200. However, within the same chipset 100, there may be interaction requirements between different Chiplet units. Therefore, it is necessary to enable different Chiplet units 110 to access the subspace of other Chiplet units 110. In one embodiment of this application, each Chiplet unit 110 further includes: a first DMA module 112, which is connected to the first communication bus unit 200 and the second communication module 120 respectively. The first DMA module 112 is used to access the subspace of the memory 300 of other Chiplet units 110 within the same chipset 100, excluding the Chiplet unit 110 where the first DMA module 112 is located, through the first communication bus unit 200.

[0088] In this embodiment, the first DMA module 112 can implement the DMA function to access the memory 300 according to the address. The principle of DMA can be referred to the existing DMA, and will not be elaborated here. Taking Figure 1 as an example, the space of the memory 300 corresponding to the first chipset 100 is 0G to 8G, and the subspace corresponding to the first chipplet unit 110 is 0G to 2G. Through the first DMA module 112 in the chipplet unit 110, the chipplet unit 110 can access the space of the memory 300 with addresses from 2G to 8G.

[0089] Please refer to Figure 8, which is a schematic diagram of the relationship between the first DMA module 112 and the first communication bus unit 200 provided in an embodiment of this application.

[0090] The first DMA module 112 includes a CDMA (Central Direct Memory Access) submodule and a selection submodule, AXI Bridge Crossbar. The selection submodule selects the corresponding bandwidth module 210 based on the subspace required for access according to the control command, allowing access to the subspace based on the corresponding bandwidth module 210. For example, it selects one subspace from four subspaces with addresses 0G~2G, 2G~4G, 4G~6G, and 6G~8G. In some embodiments of this application, the first communication bus unit is an AXI bus unit; therefore, the protocol corresponding to AXI Bridge Interconnect and the protocol implemented by the selection submodule can be an AXI Bridge implementing the AXI protocol. The CDMA submodule moves data from a starting address to a target address from the selected subspace via the AXI Bridge Interconnect. The AXI Bridge Interconnect is a bus bridge module used to convert multiple buses into a single bus.

[0091] The first DMA module 112 described above is used to realize the interaction between different chipsets within the communication chipset 100. Since there is also interaction between different chipsets 100, in the embodiments of this application, each chipset 100 may further include a second DMA module 130. As shown in FIG2, the second DMA module 130 is connected to the first communication bus unit 200 and the second communication module 120 respectively.

[0092] In the embodiments of this application, the second DMA module 130 is used to access all subspaces of the memory 300 corresponding to all chiplet units 110. The difference between the second DMA module 130 and the first DMA module 112 is that the subspaces accessed are different; the second DMA module 130 can access all subspaces.

[0093] In this embodiment, the structure of the second DMA module 130 can be the same as that of the first DMA module 112, both of which can include a CDMA submodule and a selection submodule Crossbar (a type of bus bridge module). The Crossbar is used to convert one bus into multiple buses according to the address space. The difference is that the second DMA module 130 can access all subspaces through the bandwidth module 210 of all subspaces. For example, taking Figure 2 as an example, the first DMA module 112 of each chipplet in the first chipset 100 can only access the address space from 0G to 8G, while the second DMA module 130 of the first chipset 100 can access the address space from 0G to 16G.

[0094] Please refer to Figure 9, which is a schematic diagram of the operation of the proxy module 140 provided in one embodiment of this application.

[0095] The first DMA module 112 and the second DMA module 130 may not support control instructions that may be converted to the first communication protocol by the second communication module 120. For example, in some embodiments, the protocol supported by the first DMA module 112 and the second DMA module 130 is the AXI-LITE protocol (a lightweight address-mapped single-transfer interface protocol). The control instructions of the first communication protocol (such as the AXI protocol) converted by the second communication module 120 may not be directly usable by the first DMA module 112 and the second DMA module 130. Therefore, in the embodiments of this application, each chipset 100 may further include: a proxy module 140, which is used to convert the control instructions output by the second communication module 120 into control signals of the protocols supported by the second DMA module 130 and each of the first DMA modules 112. For example, the proxy module 140 is configured with a conversion relationship between the AXI protocol and the AXI-LITE protocol, and can convert the control instructions of the AXI protocol into instructions of the AXI-LITE protocol so that the second DMA module 130 and each of the first DMA modules 112 can execute them. In this embodiment, the proxy module 140 is connected to each of the first DMA modules 112 and the second DMA modules 130 in the chipset 100 where the proxy module 140 is located, and to the function module 111 to be verified. The proxy module 140 is also connected to the second communication module 120.

[0096] Furthermore, the protocol supported by the functional module 111 to be verified may also be different from that of the first DMA module 112 and the second DMA module 130. For example, the protocol supported by the functional module 111 to be verified may be AHB, while the protocol converted by the proxy module 140 is AXI-LITE. The control instructions converted by the proxy module 140 may not be usable by the functional module 111 to be verified.

[0097] Therefore, in the embodiments of this application, the proxy module 140 is also used to connect to the functional module 111 to be verified. Each chipset 100 further includes a function protocol conversion module, which is connected to the proxy module 140 and each of the functional modules 111 to be verified. The proxy module 140 is also used to convert the control commands output by the second communication module 120 into control signals of the protocol supported by the second DMA module 130 or the first DMA module 112. The function protocol conversion module is used to convert the control signals of the protocol supported by the second DMA module 130 or the first DMA module 112 into control signals of the protocol supported by each functional module 111 to be verified. Continuing with the above example, the function protocol conversion module can convert the control commands of AXI-LITE into control commands of the AHB protocol that the functional module 111 to be verified can use.

[0098] In some embodiments of this application, the proxy module 140 includes a bandwidth control register and a delay control register. The bandwidth control register is connected to the bandwidth register 211 of each bandwidth module 210 in the first communication bus unit 200, and the delay control register is connected to the delay register 212 of each bandwidth module 210 in the first communication bus unit 200. The bandwidth control register and the delay control register are used to configure the clock delay and the periodic gating signal for controlling bandwidth blocking according to the received control signal. The proxy module 140 can send the required clock delay signal and periodic gating signal to the designated bandwidth module 210 according to the value of the internal register.

[0099] As shown in Figure 2, in some embodiments of this application, the FPGA prototype verification system further includes a physical layer interface module 410, which is connected to the first communication bus unit 200 and the memory 300 respectively. The physical layer interface module 410 is used to convert the digital signal output by the first communication bus unit 200 into an analog signal and store it in the memory 300. The physical layer interface module 410 is also used to convert the analog signal output by the memory 300 into a digital signal and transmit it through the first communication bus unit 200.

[0100] In some embodiments, the first communication bus unit 200 may not be able to directly access the memory 300. Therefore, in the embodiments of this application, a physical layer interface module 410 may also be provided so that the first communication bus unit 200 can access the memory 300 through the physical layer interface module 410 to realize data reading and storage.

[0101] In one embodiment of this application, the physical layer interface module 410 is disposed on the FPGA prototype verification board 400. Therefore, during each verification, it is unnecessary to connect the first communication bus unit 200 to the physical layer interface module 410, improving testing efficiency. On the other hand, the physical layer interface module 410 includes a physical layer chip with the same control logic as the FPGA prototype verification board 400. For example, each manufacturer typically configures a corresponding physical layer chip based on its own FPGA configuration. This physical layer chip integrates a memory control module to implement the control flow for memory read / write operations. When developing the FPGA prototype verification board 400 provided by the FPGA circuit boards provided by various manufacturers, the corresponding physical layer chip can be used without the need for an additional conversion circuit board, reducing the development process of the control flow for memory 300 read / write operations and improving verification efficiency.

[0102] For ease of understanding, an example is provided here to illustrate the signal transmission process of the FPGA prototyping system provided in this application. Please refer to Figure 10, which is a schematic diagram of the signal transmission of an FPGA prototyping system provided in an embodiment of this application.

[0103] In this embodiment, the FPGA prototype verification system is connected to the host computer through second communication modules 120 of different chipsets 100. The host computer sends control commands to different second communication modules 120. The second communication modules 120 perform a first protocol conversion, such as converting PCIe control commands to AXI protocol control commands. Then, a second conversion is performed by the proxy module 140, for example, converting the AXI protocol control commands to AXI-LITE protocol control commands supported by the first DMA module 112 and the second DMA module 130 and sending them to the first DMA module 112 and the second DMA module 130. Alternatively, a third conversion can be performed on the AXI-LITE protocol control commands by the functional protocol module, converting the AXI-LITE protocol control commands to AHB protocol control commands supported by the functional module 111 to be verified. Then, the control commands of the first DMA module 112, the second DMA module 130, and the functional module 111 to be verified can all be transmitted to the physical layer interface module through the bandwidth module 210 in the first communication bus unit 200, so that they can be converted into control commands for accessing the memory 300 by the physical layer interface module.

[0104] Based on the same inventive concept, this application also provides a chip verification method. This chip verification method can be applied to a functional module to be verified. The functional module to be verified is configured in the Chiplet unit of the FPGA prototype verification system provided in the foregoing embodiments of this application. The FPGA prototype verification system is connected to a host computer.

[0105] Please refer to Figure 11, which is a flowchart of a chip verification method applied to a functional module to be verified according to an embodiment of this application. The chip verification method applied to the functional module to be verified includes:

[0106] The S510 receives control commands generated by the host computer.

[0107] S520, in response to control commands, accesses the memory based on the first communication bus unit.

[0108] Based on the same inventive concept, embodiments of this application also provide a chip verification method, which can be applied to a host computer that is communicatively connected to the FPGA prototype verification system described in any of the foregoing claims. The chip verification method applied to the host computer includes:

[0109] Control commands are sent to the FPGA prototyping system to control the functional module to be verified to access the memory via the first communication bus unit. The functional module to be verified is pre-configured within the chiplet unit of the FPGA prototyping system.

[0110] Based on the same inventive concept, this application also provides a host computer. Please refer to Figure 12. Figure 12 is a schematic diagram of a host computer 500 provided in this application embodiment, which can be used as the execution subject of the chip verification method applied to the host computer. The host computer includes: a processor 510, a storage unit 520 and a communication unit 530. The processor 510 is connected to the storage unit 520 and the communication unit 530. The communication unit 530 is used to communicate with the FPGA prototype verification system provided in any of the foregoing embodiments.

[0111] The storage unit 520 stores computer-readable instructions that can be executed by the processor 510. These computer-readable instructions can be executed by the processor 510 to enable the host computer 500 to execute the chip verification method applied to the host computer in the aforementioned embodiment. That is, the host computer is configured to send control commands to the FPGA prototype verification system to control the functional module to be verified to access the memory based on the first communication bus unit. The functional module to be verified is pre-configured in the chiplet unit of the FPGA prototype verification system.

[0112] The processor 510 and the storage unit 520 are connected, but are not limited to, via a communication bus.

[0113] The processor 510 can be a data processing core of a GPU (Graphics Processing Unit), CPU (Central Processing Unit), AI (Artificial Intelligence), NPU (Neural Network Processing Unit), ISP (Image Signal Processor), DPU (Display Processing Unit), VPU (Video Processing Unit), or DSP (Digital Signal Processor), or a processor chip used in scenarios involving large-scale data computation. The above are merely examples and should not be construed as limiting this application.

[0114] The storage unit 520 may include, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0115] It is understood that the host computer 500 may also include more general modules required by itself, which will not be described one by one in this embodiment of the application.

[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0117] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. An FPGA prototype verification system, characterized in that, include: There are N chipsets, each chipset including M chiplets, each chiplet being used to configure a functional module to be verified; where N and M are both positive integers. The first communication bus unit is connected to all the functional modules to be verified configured in the Chiplet units; the first communication bus unit is configured with a first communication protocol that enables communication between the functional modules to be verified. The memory is connected to the first communication bus unit; The functional modules to be verified configured in each of the Chiplet units access the memory through the first communication bus unit.

2. The FPGA prototype verification system according to claim 1, characterized in that, The FPGA prototype verification system includes an FPGA prototype verification board, on which the first communication bus unit and all the chipsets are mounted.

3. The FPGA prototype verification system according to claim 2, characterized in that, The number of the memory is 1; The memory is divided into M subspaces according to the address space, and each subspace corresponds to one chiplet unit.

4. The FPGA prototype verification system according to claim 3, characterized in that, The memory includes a double-rate synchronous dynamic random access memory.

5. The FPGA prototype verification system according to claim 3, characterized in that, The first communication bus unit includes M bandwidth modules, each of which corresponds to one of the subspaces; Each of the bandwidth modules is connected to a different chiplet unit, and the subspace corresponding to the bandwidth module is the same as the subspace corresponding to the chiplet unit to which the bandwidth module is connected; The bandwidth module is used to configure the bandwidth blocking and clock delay of signal transmission between the Chiplet unit connected to the bandwidth module and the memory.

6. The FPGA prototype verification system according to claim 5, characterized in that, Each bandwidth module includes a bandwidth register and a delay register; the bandwidth register and the delay register are connected in series, and the bandwidth register and the delay register are connected between the chiplet cell corresponding to the bandwidth module and the memory; The bandwidth register is configured with a preset periodic gating signal, and the bandwidth register is used to control the blocking of signal transmission between the Chiplet unit and the memory based on the periodic gating signal; The delay register is used to control the clock delay of signal transmission between the Chiplet unit and the memory based on the preset clock delay.

7. The FPGA prototype verification system according to claim 5, characterized in that, Each of the chipsets further includes a second communication module, which is configured with a second communication protocol that enables the functional module to be verified to communicate with external devices, and each of the chipsets is connected to the host computer through the second communication module; The second communication module is connected to each of the chiplets in the chipset where the second communication module is located. The second communication module is used to convert the control commands of the second communication protocol output by the host computer into control commands of the first communication protocol.

8. The FPGA prototype verification system according to claim 7, characterized in that, Each of the Chiplet units further includes: a first DMA module, which is connected to the first communication bus unit and the second communication module respectively; The first DMA module is used to access the subspace of the memory corresponding to other Chiplet units within the same chipset, excluding the Chiplet unit where the first DMA module is located, through the first communication bus unit.

9. The FPGA prototype verification system according to claim 8, characterized in that, The first DMA module includes a selection submodule, which is used to select the corresponding bandwidth module according to the subspace to be accessed according to the control command, so as to access the subspace based on the corresponding bandwidth module.

10. The FPGA prototype verification system according to claim 8, characterized in that, Each of the chipsets further includes: a second DMA module, the second DMA module being connected to the first communication bus unit and the second communication module respectively; The second DMA module is used to access all subspaces of the memory corresponding to all the Chiplet units.

11. The FPGA prototype verification system according to claim 10, characterized in that, Each of the chipsets further includes: a proxy module; the proxy module is connected to each of the first DMA modules and the second DMA modules in the chipset where the proxy module is located, and the proxy module is also connected to the second communication module; The proxy module is also used to convert the control commands output by the second communication module into control signals of the protocols supported by the second DMA module and each of the first DMA modules.

12. The FPGA prototype verification system according to claim 11, characterized in that, The proxy module is also used to connect to the functional module to be verified; Each of the chipsets further includes a function protocol conversion module, which is connected to the proxy module and each of the function modules to be verified. The proxy module is further configured to convert the control commands output by the second communication module into control signals of the protocol supported by the second DMA module or the first DMA module, and the function protocol conversion module is configured to convert the control signals of the protocol supported by the second DMA module or the first DMA module into control signals of the protocol supported by each of the functional modules to be verified.

13. The FPGA prototype verification system according to claim 2, characterized in that, The FPGA prototype verification system also includes a physical layer interface module, which is connected to the first communication bus unit and the memory respectively. The physical layer interface module is used to convert the digital signal output by the first communication bus unit into an analog signal and store it in the memory. The physical layer interface module is also used to convert the analog signal output by the memory into a digital signal and transmit it through the first communication bus unit.

14. The FPGA prototype verification system according to claim 13, characterized in that, The physical layer interface module is mounted on the FPGA prototype verification board, and the physical layer interface module includes a physical layer chip with the same control logic as the FPGA prototype verification board.

15. A chip verification method, characterized in that, The method is applied to a functional module to be verified, wherein the functional module to be verified is configured in a Chiplet unit of the FPGA prototype verification system as described in any one of claims 1-14, and the FPGA prototype verification system is connected to a host computer. The chip verification method includes: Receive control commands generated by the host computer; In response to the control command, the memory is accessed via the first communication bus unit.

16. A chip verification method, characterized in that, The method is applied to a host computer, which is communicatively connected to the FPGA prototype verification system as described in any one of claims 1-14, and the chip verification method includes: Control commands are sent to the FPGA prototype verification system to control the functional module to be verified to access the memory based on the first communication bus unit. The functional module to be verified is pre-configured in the chiplet unit of the FPGA prototype verification system.

17. A host computer, characterized in that, The host computer includes a storage unit, a processor, and a communication unit; the communication unit is used to communicate with the FPGA prototype verification system as described in any one of claims 1-14. The storage unit stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the host computer is configured to send control instructions to the FPGA prototype verification system to control the functional module to be verified to access the memory based on the first communication bus unit. The functional module to be verified is pre-configured in the chiplet unit of the FPGA prototype verification system.

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