Chip selection method, device and storage medium

Abstract

The application discloses a chip selection method and device and a storage medium, relates to the technical field of data processing, and discloses a chip selection method, which comprises the following steps: receiving a chip selection demand input by a user based on natural language, extracting chip entity information from the chip selection demand; performing information retrieval in a chip data structured database and a chip manual vectorization database based on the chip entity information and the chip selection demand, and obtaining retrieval results; inputting the retrieval results, the chip selection demand and the chip entity information into a chip selection analyzer, and outputting corresponding chip selection results. Through the combination of structured retrieval and vectorized retrieval, the application improves the retrieval accuracy and matching effect of chip selection, reduces the cost of manual participation, and realizes efficient, accurate and automatic chip selection.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a chip selection method, device and storage medium. Background Technology

[0002] Traditional chip selection techniques primarily rely on structured parameter retrieval based on predefined fields. This approach requires users to manually convert natural language requirements into precise parameter indicators or follow fixed search syntax. It lacks an automatic semantic parsing and intent mapping mechanism for unstructured descriptions and cannot directly convert user selection intent into multi-dimensional constraint search logic. This makes it difficult for the search process to cover implicit scenario features, resulting in a low degree of fit between chip selection results and actual application requirements.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a chip selection method, device and storage medium, which aims to solve the technical problem that traditional chip selection technology cannot perform semantic parsing of natural language requirements, resulting in low adaptability between chip selection and application scenarios.

[0005] To achieve the above objectives, embodiments of this application provide a chip selection method, the chip selection method comprising: Receive chip selection requirements from users based on natural language input, and extract chip entity information from the chip selection requirements; Based on the chip entity information and the chip selection requirements, information retrieval is performed in the chip data structured database and the chip manual vectorized database to obtain the retrieval results. The search results, chip selection requirements, and chip entity information are input into the chip selection analyzer, which outputs the corresponding chip selection results.

[0006] In one embodiment, the step of receiving a user's chip selection request based on natural language input and extracting chip entity information from the chip selection request includes: By combining preset contextual learning examples, chip type descriptions, performance parameter descriptions, and prompts, the chip selection requirements are input into the large language model to obtain a set of chip entities; Anomaly detection is performed on the set of chip entities. If the anomaly detection passes, the set of chip entities is output as the chip entity information.

[0007] In one embodiment, the step of performing information retrieval in a structured chip data database and a vectorized chip manual database based on the chip entity information and the chip selection requirements to obtain retrieval results includes: Based on the chip entity information, a structured search is performed in the chip data structured database to determine the candidate chip set and the number of candidate chips; When the number of candidate chips exceeds the target screening quantity, based on the chip selection requirements and the candidate chip set, a vector search is performed in the chip manual vectorization database to determine the chip summary document corresponding to each candidate chip in the candidate chip set. Based on the chip selection requirements, the chip summary documents corresponding to each candidate chip are quantitatively scored to obtain the semantic relevance score of each chip summary document. The search results are generated based on the candidate chip set, the chip summary document corresponding to each candidate chip, and the corresponding semantic relevance score.

[0008] In one embodiment, the step of performing information retrieval in a structured chip data database and a vectorized chip manual database based on the chip entity information and the chip selection requirements to obtain retrieval results includes: Based on the number of chip entities contained in the chip entity information, a corresponding number of retrieval processes are initiated to perform the information retrieval in parallel. Once all the aforementioned retrieval processes have been completed, the abnormal feedback information generated during the retrieval process is summarized to obtain the abnormal information prompt text; The abnormal information prompt text, the candidate chip set, the chip summary document corresponding to each candidate chip, and the semantic relevance score are used together as the search results.

[0009] In one embodiment, before the step of performing vector retrieval in the chip manual vectorization database based on the chip selection requirements and the candidate chip set to determine the chip summary document corresponding to each candidate chip in the candidate chip set, the chip selection method further includes: Obtain the chip manual summary document, and divide the chip manual summary document into blocks to obtain multiple summary document blocks; Perform vectorization processing on each of the abstract document blocks to generate a abstract document vector corresponding to each of the abstract document blocks, and assign a corresponding abstract document number and block number to each of the abstract document blocks; Extract the chip name and summary document storage address corresponding to each summary document block, determine the summary document number, the block number, the chip name, and the chip summary document storage address as metadata, and associate the metadata with the summary document vector to construct the chip manual vectorized database.

[0010] In one embodiment, the step of performing vector retrieval in the chip manual vectorization database based on the chip selection requirements and the candidate chip set to determine the chip summary document corresponding to each candidate chip in the candidate chip set includes: Based on the candidate chip set, the summary document blocks and summary document vectors corresponding to each candidate chip are selected from the chip manual vectorization database to generate a document vector list. The chip selection requirements are converted into query vectors, and the target number of filters and weight parameters are determined. The selected document index set is initialized to an empty set, and the unselected document index set is all document indexes corresponding to the document vector list. Calculate the similarity between each of the summary document vectors in the document vector list and the query vector to obtain the relevance score between each summary document block and the chip selection requirements; For each document index in the set of unselected document indexes, obtain the summary document vector and the relevance score corresponding to the current document index; If the selected document index set is not empty, then calculate the maximum similarity between the current document index and all selected summary document vectors in the selected document index set, and use the maximum similarity as the redundancy of the current document index; Based on the relevance score and redundancy corresponding to the current document index, and in conjunction with the weight parameters, the maximum marginal relevance algorithm score of the summary document vector corresponding to the current document index is calculated. Obtain the target document index with the highest score of the maximum marginal relevance algorithm from the set of unselected document indexes; The target document index is added to the selected document index set and removed from the unselected document index set until the number of indexes in the selected document index set reaches the target filtering number, or the unselected document index set is empty; Based on the selected document index set, the corresponding summary document block is matched in the chip manual vectorization database to obtain the summary document corresponding to each candidate chip in the candidate chip set.

[0011] In one embodiment, after the step of performing a structured search in the chip data structured database based on the chip entity information to determine the candidate chip set and the number of candidate chips, the chip selection method further includes: When the number of candidate chips is less than or equal to the target screening number, the set of candidate chips is used as the search result.

[0012] In one embodiment, the step of inputting the search results, the chip selection requirements, and the chip entity information into the chip selection analyzer and outputting the corresponding chip selection results includes: Based on the chip entity information, the chip selection scenario is determined, and according to the chip selection scenario, the corresponding target scenario prompt word template is matched from the prompt word template library; The chip selection requirements, the target scenario prompt word template, and the search results are input into the large language model, and the chip selection results are output.

[0013] This application embodiment also provides a chip selection device, the chip selection device including: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip selection method as described above.

[0014] This application embodiment also provides a storage medium, which is a computer-readable storage medium, and stores a computer program thereon. When the computer program is executed by a processor, it implements the steps of the chip selection method described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application addresses the issue of traditional chip selection relying on specialized input formats by receiving chip selection requests from users using natural language input and extracting chip entity information. This lowers the barrier to entry for users, allowing even non-professionals to easily initiate chip selection requests. Simultaneously, it accurately captures core selection-related information, providing precise data for subsequent searches. By performing information retrieval in both a structured chip data database and a vectorized chip manual database based on the extracted chip entity information and the original chip selection request, it achieves dual retrieval of both structured and unstructured documents. This ensures accurate extraction of core data such as chip parameters while comprehensively acquiring detailed information from the chip manual, avoiding information omissions caused by searching only a single database. The system enhances the comprehensiveness and accuracy of search results. Furthermore, by inputting search results, chip selection requirements, and chip entity information into the chip selection analyzer and outputting selection results, it achieves fully automated integration of the entire process from requirement input and information retrieval to selection output. This eliminates the need for manual intervention in the retrieval and analysis process, significantly improving chip selection efficiency. In addition, the entire process uses natural language interaction as the entry point, dual-database collaborative retrieval as the core, and the selection analyzer as the output terminal, constructing a highly efficient, accurate, and convenient automated chip selection system. This effectively solves the technical problems of traditional chip selection processes being cumbersome, requiring high levels of user expertise, having incomplete retrieval, and being inefficient, achieving automation, efficiency, and accuracy in chip selection. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating Embodiment 2 of the chip selection method of this application; Figure 2 This is a schematic block diagram of the entity recognizer provided in Embodiment 2 of the chip selection method of this application; Figure 3 This is a schematic diagram of the multi-level retrieval mechanism for single-chip retrieval provided in Embodiment 2 of the chip selection method of this application; Figure 4 A schematic diagram illustrating the process of building a vectorized database of chip manuals provided in Embodiment 2 of the chip selection method of this application; Figure 5 This is a schematic diagram of the overall process for the chip selection method in Embodiment 2 of this application; Figure 6 This is a flowchart illustrating Embodiment 3 of the chip selection method of this application; Figure 7 This is a flowchart illustrating Embodiment 4 of the chip selection method of this application; Figure 8 This is a schematic diagram of the scorer provided in Embodiment 4 of the chip selection method of this application; Figure 9 This is a schematic diagram of the chip selection device in the hardware operating environment involved in the chip selection method in this application embodiment.

[0017] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0019] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0020] Traditional chip selection techniques primarily rely on structured parameter retrieval based on predefined fields. This approach requires users to manually convert natural language requirements into precise parameter indicators or follow fixed search syntax. It lacks an automatic semantic parsing and intent mapping mechanism for unstructured descriptions and cannot directly convert user selection intent into multi-dimensional constraint search logic. This makes it difficult for the search process to cover implicit scenario features, resulting in a low degree of fit between chip selection results and actual application requirements.

[0021] Specifically, current chip selection technologies generally rely on structured input modes, which cannot directly parse chip selection needs expressed by users in natural language. For non-professional users, they need to learn parameter definitions and search rules before they can start the selection process, resulting in high operational complexity. For professional users, natural language requirements need to be manually converted into structured parameters, increasing operational steps and time costs, thus limiting the user coverage of selection tools and resulting in poor usability. At the same time, current chip selection technologies use fixed search processes, which are difficult to cover complex scenarios such as multi-chip collaborative selection and semantic-guided selection (such as prioritizing cost-effective RF transceivers). When faced with such needs, users need to manually break down their requirements and switch search modes multiple times, lacking targeted search logic for different chip selection scenarios, resulting in insufficient scenario adaptability. Furthermore, current chip selection retrieval mechanisms rely on single-dimensional filtering, which can easily lead to significant discrepancies between selection results and actual needs. Filtering based solely on structured parameters may retain redundant chips that meet the parameter requirements but are unsuitable for certain scenarios (e.g., chips that only meet the "frequency range 400-1700MHz" requirement but lack high-temperature environment adaptability). Relying solely on simple semantic matching may overlook key hard parameters (e.g., chips that only meet the semantic requirement of "low noise" but fail to meet the hard parameter requirement of "noise figure ≤ 1.8dB"). In addition, current chip selection technologies suffer from low data storage and retrieval efficiency. Structured and unstructured data are independent, and cross-database filtering increases data processing time. Moreover, multi-chip selection uses a serial retrieval mode, requiring sequential retrieval by chip type, with overall processing time increasing linearly with the number of chip types. Finally, current chip selection technologies only return chip manuals or parameter lists, lacking in-depth analysis based on user's natural language input regarding chip selection needs. Users still need to manually judge the suitability of chip selection results to their needs, failing to provide effective decision support.

[0022] In view of the above problems, this application proposes a chip selection method, which involves receiving chip selection requirements from users based on natural language input, extracting chip entity information from the chip selection requirements, performing information retrieval in a chip data structured database and a chip manual vectorized database based on the chip entity information and the chip selection requirements, respectively, to obtain retrieval results, and inputting the retrieval results, the chip selection requirements, and the chip entity information into a chip selection analyzer to output the corresponding chip selection results.

[0023] This application provides a solution that receives chip selection requests from users based on natural language input and extracts chip entity information from them. This eliminates the reliance on professional input formats in traditional chip selection, lowers the operational threshold for users, and allows non-professional users to easily initiate chip selection requests. Simultaneously, it accurately captures core selection-related information, providing precise basis for subsequent searches. By performing information retrieval in both a structured chip data database and a vectorized chip manual database based on the extracted chip entity information and the original chip selection request, it achieves dual retrieval of structured data and unstructured documents. This ensures accurate extraction of core data such as chip parameters while comprehensively obtaining detailed information from the chip manual, avoiding the limitations of searching a single database. This system addresses information omissions and improves the comprehensiveness and accuracy of search results. Furthermore, by inputting search results, chip selection requirements, and chip entity information into the chip selection analyzer and outputting selection results, it achieves fully automated integration from requirement input and information retrieval to selection output. No manual intervention is required in the retrieval and analysis process, significantly improving chip selection efficiency. In addition, the entire process uses natural language interaction as the entry point, dual-database collaborative retrieval as the core, and the selection analyzer as the output terminal, constructing a highly efficient, accurate, and convenient automated chip selection system. This effectively solves the technical problems of traditional chip selection processes being cumbersome, requiring high levels of user expertise, having incomplete retrieval, and being inefficient, achieving automation, efficiency, and accuracy in chip selection.

[0024] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a server, computer, or mobile terminal, or an electronic device, chip selection device, or chip selection system capable of performing the above functions. The following description uses a chip selection system as an example to illustrate this embodiment and the subsequent embodiments.

[0025] First Embodiment This embodiment provides a chip selection system, which includes an entity recognizer, a single-chip retrieval unit, an anomaly information processor, and a chip selection analyzer. It also incorporates a structured chip data database and a vectorized chip manual database to address the technical problems in current chip selection technologies, such as high operational barriers, weak scenario adaptability, low selection accuracy, low selection processing efficiency, and weak decision support capabilities.

[0026] Specifically, the entity recognizer receives chip selection requests from users based on natural language input. Using a large language model combined with contextual learning examples, chip type descriptions, performance parameter descriptions, and preset prompts, it extracts key information such as chip name, chip type, company name, and performance parameters from the chip selection request, transforming the unstructured natural language request into standardized chip entity information. Simultaneously, it performs anomaly detection on the output of the large language model, such as determining whether the set of chip entities output by the large language model is non-empty, or removing invalid data with format errors or missing parameters. This provides standardized retrieval criteria for subsequent searches, reduces ambiguity in natural language understanding, and improves retrieval efficiency and accuracy.

[0027] The single-chip searcher is used to perform multi-level parallel searches in a structured database of chip data and a vectorized database of chip manuals, based on chip entity information and chip selection requirements. The single-chip retrieval tool first filters structured parameters through a chip data structured database to quickly identify a set of candidate chips that meet the explicit parameter requirements. When the number of candidate chips in the set exceeds the preset target number, the chip selection requirements are further vectorized. Using the candidate chip set as the search scope, semantic similarity retrieval is performed in the chip manual vectorized database to locate chip summary documents that semantically match the user's needs. Simultaneously, based on the number of chip entities in the chip entity information, a corresponding number of independent retrieval processes are adaptively launched to complete multi-chip synchronous retrieval in parallel, shortening the overall processing time and balancing accurate parameter matching with implicit semantic understanding, thereby improving the comprehensiveness and relevance of the selection results. Then, the obtained chip summary documents are subjected to multi-dimensional quantitative scoring. Based on the number of chip summary documents to be scored, a corresponding number of scorer interfaces are activated. Each scorer interface is responsible for scoring one chip summary document. The scorer performs multi-dimensional quantitative scoring from dimensions such as core parameter matching degree, application scenario adaptability, and semantic requirement relevance, and performs weighted calculations to ensure that the scoring process is efficient and accurate, further correcting possible biases in semantic retrieval and ensuring the reliability of the final selection results.

[0028] An anomaly information processor monitors the entire execution status of the entity recognizer and single-chip retrieval unit. During the entity recognition phase, if an empty chip entity set is detected, or during the retrieval phase, if data matching fails or the retrieval result is empty, an anomaly information recording mechanism is triggered, generating an anomaly information log containing the anomaly type, the stage or time of occurrence, and corresponding related information. During the retrieval phase, after all retrieval processes have completed and retrieved results, the anomaly feedback information in the anomaly information log is extracted synchronously, generating an anomaly information prompt text. This text is then correlated and summarized with the retrieval results to obtain the final retrieval result, ensuring the stability and traceability of the retrieval process and providing anomaly reference for subsequent selection analysis.

[0029] The chip selection analyzer receives aggregated search results (including anomaly alert text), chip selection requirements, and chip entity information. Specifically, it first determines whether the current scenario is a single-chip or multi-chip selection based on the number of chip entities in the chip entity information. Then, it matches the corresponding target scenario alert word template from a pre-defined alert word template library. Combining the aggregated search results and chip selection requirements, it generates chip selection results using a large language model. These results include parameter comparisons of each chip, compatibility analysis with chip selection requirements, parameter compatibility between different chips, feasibility and connectivity compatibility analysis, risk warnings, and alternative solutions. Simultaneously, the large language model also marks existing matching risk points in the output chip selection results and provides corresponding solutions, offering users intuitive decision support and enhancing the scenario adaptability and practicality of the selection results.

[0030] This embodiment, through the aforementioned multi-module collaborative system architecture, achieves full-process automation from natural language requirement input to professional chip selection result output, effectively solving the technical problems existing in current chip selection technology, such as high operation threshold, weak scenario adaptability, low selection accuracy, low processing efficiency, and insufficient decision support capabilities.

[0031] Second Embodiment Based on the chip selection system architecture of the first embodiment described above, this application also provides a chip selection method, referring to... Figure 1 The chip selection method includes steps S10 to S30: Step S10: Receive the chip selection requirements from the user based on natural language input, and extract chip entity information from the chip selection requirements.

[0032] It should be noted that chip selection requirements are unstructured information expressed by the user in natural language, used to convey their chip selection intent. This information can be input in the form of text, images, documents, etc. Chip entity information is structured key information extracted from the chip selection requirements, including chip name, chip type, company name, and performance parameters.

[0033] In this embodiment, the chip entity information is in dictionary form, as shown in Table 1. It stores chip name, chip type, company name and performance parameter information, where the parameter values ​​in the performance parameters need to be converted into corresponding ranges.

[0034] Table 1. Description and Examples of Chip Entity Information

[0035] Because user-input natural language requirements are flexible and lack a standardized format, they cannot be directly processed by structured databases. Therefore, an entity recognizer is used to extract key information such as chip name, chip type, company name, and performance parameters from chip selection requirements and convert them into a standard structured format (i.e., chip entity information). This forms search conditions that can be directly executed by the structured database, effectively avoiding the problem of mismatch between unstructured requirements and structured search conditions, and improving the efficiency and accuracy of subsequent structured filtering and data retrieval.

[0036] In this embodiment, step S10 further includes steps S110 to S120: Step S110: Combining the preset context learning examples, chip type descriptions, performance parameter descriptions, and prompts, input the chip selection requirements into the large language model to obtain a set of chip entities.

[0037] Step S120: Perform anomaly detection on the chip entity set. If the anomaly detection passes, output the chip entity set as the chip entity information.

[0038] The specific implementation logic of the entity recognizer in this embodiment is as follows: Figure 2 As shown, Figure 2 This is a block diagram illustrating the principle of an entity recognizer. Specifically: This embodiment pre-constructs examples of chip selection requirements and their corresponding sets of chip entities as context learning examples for a large language model. It also guides the large language model to extract key information such as chip name, company name, chip type, and performance parameters from the chip selection requirements through a designed prompt. After the user inputs their chip selection requirements, the requirements, along with the chip type description, performance parameter description, context learning example, and prompt, are input into the large language model to obtain the chip entity set. After obtaining the chip entity set, anomaly detection is performed, such as checking if the chip entity set is empty. The chip entity set that passes the detection is used as the final output chip entity information.

[0039] This implementation transforms unstructured natural language requirements into standardized structured entity information, providing a unified and standardized retrieval basis for subsequent retrieval processes and reducing ambiguity in natural language understanding.

[0040] It should be noted that the context learning examples are formed by human experts analyzing chip selection requirement examples in various scenarios, annotating and writing corresponding chip entity sets, and then pairing the chip selection requirement examples with the corresponding chip entity sets as context learning examples for the large language model.

[0041] As an example, the prompt word "Prompt" is as follows: "You are a chip selection requirement entity recognition assistant."

[0042] Please identify the required chip name, company name, chip type, and performance parameters based on your chip selection requirements. If the chip selection requirements are combined (i.e., involve multiple chips), then you need to group and identify them by chip type.

[0043] I will provide you with the chip type descriptions, performance parameters, and examples you need for reference.

[0044] Your task is to output each type of chip as an entity, in dictionary form; if multiple types of chips are identified, output them as a set. Furthermore, the chip type description is a list containing all available chip types, as shown in Table 2, employing a two-level classification mechanism. The purpose of this chip type classification is not to provide a rigorous scientific classification of RF chips, but rather to manage the complex categories of RF chips in a simple and feasible manner. The chip type output by the entity identifier is the chip type identified from the user's input chip selection requirements and falling within the range listed in Table 2.

[0045] Table 2 Secondary Classification Table of Chip Types

[0046] Furthermore, the performance parameter description is a list containing all filterable chip performance parameters, as shown in Table 3. The performance parameter dictionary output by the entity recognizer contains the performance parameters and their corresponding value ranges identified from the user's input chip selection requirements, and only recognizes the performance parameters listed in Table 3.

[0047] Table 3 Key Value Description Table for Performance Parameter Dictionary

[0048] Step S20: Based on the chip entity information and the chip selection requirements, perform information retrieval in the chip data structured database and the chip manual vectorized database respectively to obtain the retrieval results.

[0049] It should be noted that the chip data structured database is a pre-built structured database used to store structured data such as chip name, chip model, chip type, and performance parameters, supporting precise matching and fast filtering. The chip manual vectorized database is a vector knowledge base built based on the vectorization of the summary documents of the chip datasheet, used to implement natural language queries.

[0050] While traditional structured databases can achieve precise matching of chip names and performance parameters, they struggle to understand the implicit semantics expressed in natural language in users' chip selection needs (such as suitability for high-temperature industrial environments, radiation resistance, and cost-effectiveness). This application, by constructing a vectorized chip manual database, can vectorize natural language selection requirements and quickly locate the chip summary document with the highest semantic relevance through vector similarity calculation. This overcomes the limitation of structured databases in semantic matching, thus better meeting chip selection needs expressed in natural language.

[0051] In this embodiment, step S20 includes steps S210 to S240: Step S210: Based on the chip entity information, perform a structured search in the chip data structured database to determine the candidate chip set and the number of candidate chips.

[0052] Step S220: When the number of candidate chips is greater than the target screening number, based on the chip selection requirements and the candidate chip set, perform vector retrieval in the chip manual vectorization database to determine the chip summary document corresponding to each candidate chip in the candidate chip set.

[0053] Step S230: Based on the chip selection requirements, the chip summary documents corresponding to each candidate chip are quantitatively scored to obtain the semantic relevance score of each chip summary document.

[0054] Step S240: Based on the candidate chip set, the chip summary document corresponding to each candidate chip, and the corresponding semantic relevance score, generate the search results.

[0055] User chip selection requirements input in natural language typically include both explicit entity requirements (such as chip type, performance parameters, etc.) and implicit semantic demands. Relying solely on filtering from structured databases or searching from vectorized databases is insufficient to balance search efficiency and comprehensiveness, failing to fully meet the needs for efficient, comprehensive, and accurate chip selection in natural language input scenarios. Therefore, the single-chip searcher designed in this embodiment employs a multi-level search process to achieve multi-level matching of chip selection requirements.

[0056] Specifically, the process begins with structured filtering. Based on the chip entity information output by the entity recognizer, chips that meet the explicit entity requirements are quickly matched from the structured database to obtain a set of candidate chips, thereby improving the basic efficiency of the retrieval. Next, semantic matching is performed. After vectorizing the chip selection requirements, semantic association is performed between the requirements and the corresponding chip document vectors within the candidate chip set. This further determines the degree of matching between each candidate chip and the user's chip selection requirements at the semantic level, and extracts the corresponding chip summary documents, thus compensating for the shortcomings of structured filtering in capturing implicit semantics. Finally, a large language model is used to deeply analyze the scenario intent and potential needs in the chip selection requirements, and the chip summary documents corresponding to each candidate chip in the candidate chip set are quantitatively scored to ensure that the retrieval results accurately respond to the user's complete chip selection needs.

[0057] As a possible implementation, step S210 is followed by: when the number of candidate chips is less than or equal to the target screening number, the candidate chip set is used as the retrieval result.

[0058] As an example, please refer to Figure 3 The multi-level retrieval mechanism for single-chip retrieval specifically includes the following steps: First, a primary structured filter is performed, which quickly filters data from the chip data structured database based on chip entity information, reducing the amount of data retrieved subsequently. The chip entity information includes multiple chip entities, specifically chip name, chip type, company name, and performance parameters. The structured filtering process is as follows: First, chip name matching is performed. If the chip name in the chip entity information is not empty, an exact match is performed directly in the chip data structured database. If the match is successful, the search result is output directly; if the match fails, the exception information processor is invoked. If the match is successful, company name filtering is performed. If the company name in the chip entity information is not empty, the chip data structured database is filtered by company name, eliminating chips from non-target manufacturers. If no chip data is found after filtering, the exception information processor is invoked. If chips are found after filtering, chip type filtering is performed. If the chip type in the chip entity information is not empty, chips of non-target types are eliminated. If no data is found after filtering, the exception information processor is invoked. If chips are found after filtering, performance parameter filtering is performed. Based on the range restrictions of the performance parameters in the chip entity information, range filtering is performed on the chips, eliminating chips whose parameter values ​​do not intersect. If no data is found after filtering, the exception information processor is invoked. If chips are found after filtering, a candidate chip set is generated.

[0059] The first-level structured filtering can only filter explicit entity information such as chip name, company name, chip type, and performance parameters. It ignores the implicit semantic information in the user's chip selection requirements input in natural language, such as non-parametric requirements like suitability for high-temperature environments or radiation resistance. The initially selected candidate chips may only meet hard parameter specifications but not the implicit requirements of actual application scenarios. Since these non-parametric requirements are usually recorded in the original chip manual, the next step is to perform a second-level semantic matching. This embodiment uses text vectorization technology to map the user's input chip selection requirements to a high-dimensional vector space. Based on distance metrics (such as cosine similarity) in the high-dimensional vector space, it measures the relevance between the user's chip selection requirements and the chip summary document, thereby achieving semantic matching.

[0060] The specific semantic matching process is as follows: If the number of candidate chips in the candidate chip set is less than or equal to the target screening quantity top-K, the candidate chip set is directly used as the search result, and the chip summary document corresponding to each candidate chip in the candidate chip set is obtained; if the number of candidate chips is greater than the target screening quantity top-K, vector retrieval and sorting are performed first. The chip selection requirement text is vectorized and input into the chip manual vectorization database (referred to as the vector library). Based on the chip number of the candidate chip, the corresponding vector subset is first selected from the vector library to determine the chip summary document corresponding to each candidate chip. Then, the relevance and diversity of the search results are balanced by the MMR maximum marginal relevance algorithm to obtain the top-K relevant vectors (i.e., summary document vectors), and the chip summary document corresponding to each candidate chip is obtained.

[0061] Finally, to comprehensively evaluate the matching degree between each candidate chip and the user's selection needs, a three-level quantitative score is performed on the chip summary document corresponding to each candidate chip to generate a semantic relevance score that can accurately represent the degree of chip matching. The chip summary document can be screened based on the semantic relevance score, and chip summary documents with a semantic relevance score not lower than a preset score threshold (e.g., ≥6 points) can be retained as valid document output.

[0062] It should be noted that traditional vector retrieval algorithms are prone to homogenization or omission of search results, making it difficult to balance the relevance and diversity of search results. This application, however, employs the MMR (Maximum Marginal Relevance) algorithm, which introduces weight parameters... Balancing the relevance of chip summary documents with chip selection requirements, as well as the redundancy among chip summary documents, and based on the selection of corresponding vector subsets based on chip numbers, it can retain chips that are highly semantically consistent with chip selection requirements, and at the same time, it can select candidate chips with complementary functions and differentiated characteristics by suppressing redundant documents, thus effectively balancing the relevance and diversity of search results.

[0063] As another feasible implementation, steps S2201 to S2203 are included before step S220: Step S2201: Obtain the chip manual summary document, and divide the chip manual summary document into blocks to obtain multiple summary document blocks.

[0064] Step S2202: Perform vectorization processing on each of the abstract document blocks to generate abstract document vectors corresponding to each abstract document block, and assign corresponding abstract document number and block number to each abstract document block.

[0065] Step S2203: Extract the chip name and summary document storage address corresponding to each summary document block, determine the summary document number, the block number, the chip name and the chip summary document storage address as metadata, and associate the metadata with the summary document vector to construct the chip manual vectorized database.

[0066] In this embodiment, the process of building the chip manual vectorized database is as follows: Figure 4 As shown, specifically: First, a Markdown chunker is used to divide the chip manual summary document into several chunks based on the first-level headings, while preserving the semantic structure of the original chip summary document to ensure the logical coherence of the chunked text.

[0067] Secondly, vectorization processing is performed on each summary document block to generate a summary document vector corresponding to each summary document block. At the same time, a unique block number and a corresponding summary document number are assigned to each summary document block. Meanwhile, chip number, chip name, and summary document storage address are extracted from the chip data structured database and used together with the block number and the summary document number to which the summary document block belongs as metadata. This metadata is then associated and bound to the corresponding summary document block to achieve a one-to-one correspondence between metadata and document blocks.

[0068] Subsequently, the original text content of the summary document block (i.e., the chip summary document), the corresponding summary document vector, and the associated metadata information are stored in the vector library. The text content, metadata, and summary document vector of each summary document block are associated with each other through block numbering. Through the above processing, the construction of the chip manual vectorized database is finally completed.

[0069] Furthermore, when vectorizing the summary document blocks, the vectorization process can be implemented using an open-source text embeddings model, specifically including the following steps: First, the original text content of the summary document block is preprocessed to remove HTML tags, extra spaces, and invisible characters, and a truncation method is used to ensure that the text length does not exceed the maximum input limit of the Embeddings model. Then, the pre-trained Embeddings model weights and the corresponding tokenizer are loaded. The tokenizer converts the text content of the summary document block into a token sequence for text formatting. If the text length is less than the maximum input limit of the Embeddings model, the tokenizer adds padding tokens to the end of the token sequence. The formatted token sequence is then input into the Embeddings model for inference, and the model outputs the activation values ​​of each layer, including contextual embedding information. Finally, the vectors of all tokens in the token sequence are average-pooled to generate a fixed-length vector, and an attention mask is used to eliminate the influence of padding tokens, resulting in the final summary document vector.

[0070] Furthermore, step S20 also includes steps S250 to S270: Step S250: Based on the number of chip entities contained in the chip entity information, start a corresponding number of retrieval processes to perform the information retrieval in parallel.

[0071] Step S260: After all the search processes have been completed, the abnormal feedback information generated during the search process is summarized to obtain the abnormal information prompt text.

[0072] Step S270: The abnormal information prompt text, the candidate chip set, the chip summary document corresponding to each candidate chip, and the semantic relevance score are used together as the search results.

[0073] Users' chip selection needs vary across scenarios, including single-chip selection and multi-chip selection ( requiring matching multiple chip types simultaneously). If a serial search mode is used, the search process must be executed sequentially for each chip entity when dealing with multi-chip selection needs, significantly increasing overall time and reducing chip selection efficiency. Therefore, this embodiment adaptively launches a corresponding number of independent search processes based on the number of chip entities contained in the chip entity information. These processes are executed synchronously in parallel to obtain a set of candidate chips, greatly shortening the processing time for multi-chip selection scenarios. Simultaneously, it is compatible with both single-chip (single-process) and multi-chip (multi-process) scenarios, improving search efficiency and enhancing the system's adaptability to diverse selection needs.

[0074] Furthermore, to ensure the stability and traceability of the retrieval process, this embodiment also employs an anomaly information processor to monitor the entire retrieval process. Specifically, the anomaly information processor performs the following processing: after all retrieval processes in the single-chip retrieval unit have completed, it checks the trigger status of the anomaly information processor. If the anomaly information processor is detected to be triggered or invoked, it extracts anomaly feedback information from the corresponding anomaly information log to form an anomaly information prompt text, facilitating risk labeling of anomaly chips during the subsequent chip selection analysis phase; if no triggering or invocation is detected, the anomaly information prompt text remains empty.

[0075] Finally, the abnormal information prompt text, the retrieved candidate chip set, the chip summary document corresponding to each candidate chip, and the semantic relevance score that characterizes the degree of chip matching are integrated to form a complete search result, providing comprehensive and accurate data support for subsequent chip selection analysis.

[0076] As an example, the triggering mechanism and behavior of the exception information handler are shown in Table 4.

[0077] Table 4. Triggering Mechanism and Behavior of Exception Information Handlers

[0078] This embodiment combines structured retrieval with semantic retrieval from a vector library, ensuring the reliability of parameter matching while also recognizing the implicit scene intent and potential needs in natural language, thereby improving the comprehensiveness and relevance of the retrieval results.

[0079] Step S30: Input the search results, the chip selection requirements, and the chip entity information into the chip selection analyzer, and output the corresponding chip selection results.

[0080] It should be noted that the chip selection analyzer is a functional module used to analyze the summarized search results (including abnormal information prompts) and the user's chip selection requirements in natural language, and generate the chip selection results. It can use a large language model to achieve scenario-based analysis and generate chip selection analysis reports.

[0081] In this embodiment, step S30 includes steps S310 to S320: Step S310: Determine the chip selection scenario based on the chip entity information, and match the corresponding target scenario prompt word template from the prompt word template library according to the chip selection scenario.

[0082] Step S320: Input the chip selection requirements, the target scenario prompt word template, and the search results into the large language model, and output the chip selection results.

[0083] In practical chip selection, there are significant differences in the analysis logic, output requirements, and evaluation dimensions between single-chip selection and multi-chip collaborative selection. Using a uniform set of prompts makes it difficult to adapt to the selection analysis needs of different scenarios, easily leading to inaccurate and unrelevant output. Therefore, this embodiment improves the parsing and output performance of the large language model through scenario-based prompt matching.

[0084] This embodiment first determines whether the current scenario is a single-chip selection scenario or a multi-chip selection scenario based on the chip entity information output by the entity recognizer. If the number of chip entities in the chip entity information is greater than or equal to 2, it indicates that a multi-chip selection scenario has been input. Then, the chip selection analyzer matches the corresponding target scenario prompt word template from the preset prompt word template library, so that the large language model can perform structured analysis and comprehensive evaluation of the chip selection requirements and search results according to the analysis logic and output specifications of the corresponding scenario, thereby generating chip selection results that fit the actual chip selection requirements.

[0085] As an example, the scenario prompt template for a single-chip selection scenario is as follows: "Given the user's selection requirements, please complete the following tasks based on the provided search results: 1. Compare the core parameters of each chip in tabular form and mark the degree of matching with the chip selection requirements; 2. Analyze the technical advantages and disadvantages of each chip, and explain its suitability in conjunction with the application scenarios in the user's selection requirements." As an example, the scenario prompt template for a multi-chip selection scenario is as follows: "Users need to match multiple types of chips. Please perform the following tasks based on chip selection requirements and search results: 1. List the core parameters and matching scores of each type of chip; 2. Focus on analyzing the electrical characteristic compatibility, timing synchronization feasibility, and hardware connection adaptability between different chips; 3. Propose solutions for existing matching risk points." Furthermore, the user's chip selection requirements, the matched target scenario prompt word template, and the summarized search results are all used as input information and fed into the large language model. The large language model performs comprehensive analysis and generation based on the above input content to obtain the final chip selection result and push it to the user, thus completing the entire chip selection process.

[0086] This embodiment combines search results with scenario-based analysis, and uses a large language model to complete professional selection analysis and conclusion output. This solves the problems of traditional chip selection results being too scattered, lacking intuitive analysis and scenario adaptation explanations, and reduces the understanding cost and operation difficulty for users in chip selection.

[0087] In summary, this application constructs an automated chip selection process from natural language requirement parsing to final selection result output by combining entity recognition, parallel retrieval, multi-level screening, and scenario-based selection analysis. It can simultaneously take into account explicit parameter matching and implicit semantic understanding, effectively improving the efficiency and accuracy of multi-chip parallel retrieval. Finally, it achieves professional and scenario-based selection analysis and conclusion output through a large language model, solving the technical problems existing in current chip selection technology, such as high operation threshold, weak scenario adaptability, low selection accuracy, low selection processing efficiency, and weak decision support capabilities.

[0088] For example, to help understand the implementation flow of the chip selection method obtained by combining this embodiment with the first embodiment described above, please refer to... Figure 5 , Figure 5 A schematic diagram of the overall process for chip selection is provided, specifically: First, the system obtains the user's chip selection requirements expressed in natural language and inputs them into an entity recognizer to extract chip entity information from the requirements. Then, based on the number of recognized chip entities, a corresponding number of single-chip retrievers are activated. Each single-chip retriever accesses the structured chip data database and the vectorized chip manual database in parallel to perform information retrieval and obtain a set of candidate chips and their corresponding chip summary documents.

[0089] Next, the retrieval process is monitored by an anomaly information processor. If the anomaly information processor is detected to be triggered, anomaly feedback information is extracted from the anomaly information log and anomaly information prompt text is generated. If there is no anomaly, the retrieval results are directly summarized, and the candidate chip set, chip summary document and anomaly information prompt text (if any) are integrated.

[0090] Finally, the summarized search results are input into the chip selection analyzer, which combines chip selection requirements, scenario prompt word templates, and a large language model to complete a comprehensive analysis and selection analysis, and finally outputs the chip selection results.

[0091] Third Embodiment Based on the second embodiment of this application, in the third embodiment of this application, the content that is the same as or similar to the second embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 6 In the chip selection method, step S220 includes steps S2210 to S2290: Step S2210: Based on the candidate chip set, filter out the summary document blocks and summary document vectors corresponding to each candidate chip from the chip manual vectorization database, and generate a document vector list.

[0092] Step S2220: Convert the chip selection requirements into query vectors, determine the target number of filters and weight parameters, initialize the selected document index set to an empty set, and the unselected document index set to all document indexes corresponding to the document vector list.

[0093] Step S2230: Calculate the similarity between each of the summary document vectors in the document vector list and the query vector to obtain the relevance score between each summary document block and the chip selection requirements.

[0094] Step S2240: For each document index in the set of unselected document indexes, obtain the summary document vector and the relevance score corresponding to the current document index.

[0095] Step S2250: If the selected document index set is not empty, calculate the maximum similarity between the current document index and all selected summary document vectors in the selected document index set, and use the maximum similarity as the redundancy of the current document index.

[0096] Step S2260: Based on the relevance score and redundancy corresponding to the current document index, and in conjunction with the weight parameters, calculate the maximum marginal relevance algorithm score of the summary document vector corresponding to the current document index.

[0097] Step S2270: Obtain the target document index with the highest score of the maximum marginal relevance algorithm in the set of unselected document indexes.

[0098] Step S2280: Add the target document index to the selected document index set and remove the target document index from the unselected document index set until the number of indexes in the selected document index set reaches the target filtering number, or the unselected document index set is empty.

[0099] Step S2290: Based on the selected document index set, match the corresponding summary document block in the chip manual vectorization database to obtain the summary document corresponding to each candidate chip in the candidate chip set.

[0100] This embodiment achieves accurate vector retrieval based on the Maximum Marginal Relevance (MMR) algorithm through the specific execution of steps S2210~S2290 described above. Its core execution logic is as follows: Before performing vector retrieval, this embodiment first selects the summary document blocks and their corresponding summary document vectors corresponding to each candidate chip from the chip manual vectorization database based on the candidate chip set, and constructs a document vector list accordingly. At the same time, the chip selection requirements are vectorized to generate a query vector Q for similarity matching. In addition, the top-K target screening quantity is obtained as the chip screening threshold to limit the number of relevant chip summary documents obtained in the final screening.

[0101] Then, input and initialization operations are performed, including importing the document vector list. Query vector Q, top-K number of target filters, and weights (Default 0.5); Simultaneously initialize the selected document index set to an empty set, i.e. The unselected document index set consists of all document indexes corresponding to the document vector list, preparing for subsequent retrieval and filtering. (The index corresponds to the document vector list order).

[0102] After initialization, the document-query similarity formula is used to calculate the similarity between all summary document vectors in the document vector list and the query vector Q in batches. This yields a relevance score for each summary document block corresponding to the chip selection requirements, and all relevance scores are stored for later use, providing foundational data support for subsequent MMR score calculations. The document-query similarity formula is as follows:

[0103] in It is a summary document vector The kth component, It is the first of the query vector Q Each component.

[0104] Then, an iterative filtering process is initiated, targeting each document index in the set of unselected document indexes. First, the summary document vector corresponding to the document index and the previously stored relevance score are extracted. If the selected document index set is not empty, the redundancy corresponding to the document index is calculated using the document-selected document maximum similarity formula. Specifically, the cosine similarity between the summary document vector of the current document to be evaluated and all summary document vectors in the selected document set is calculated, and the maximum value is taken as the redundancy of the summary document vector corresponding to the current document index. The corresponding document-selected document maximum similarity calculation formula is as follows:

[0105]

[0106] If the selected document index set is empty, the redundancy of that document index is set to 0. Then, the relevance score, redundancy, and weight parameters are substituted into the MMR score formula to calculate the MMR score for that document index. The MMR score formula is:

[0107] in, Q represents the currently unselected documents to be evaluated (converted to summary document vectors); Q represents the query vector (with the same dimensions as the summary document vectors); S represents the set of filtered documents (in vector form); λ∈[0,1] represents the weight parameter (default 0.5), where a larger λ emphasizes relevance and a smaller λ emphasizes diversity. For vectors and Cosine similarity; The similarity between the document to be evaluated and the most similar document selected (measures redundancy).

[0108] After the MMR score is calculated, the target document index with the highest MMR score in the unselected document index set is selected and added to the selected document index set. The target document index is then removed from the unselected document index set. The above iterative filtering process continues until the number of indexes in the selected document index set reaches the target filtering number top-K, or the unselected document index set is empty.

[0109] Finally, based on the selected document index set, the corresponding summary document blocks are matched in the chip manual vectorized database to obtain the summary documents corresponding to each candidate chip in the candidate chip set, thus completing the entire vector retrieval process. This effectively balances the relevance and diversity of the retrieval results, ensuring that the retrieval results not only meet the chip selection requirements but also avoid homogenization, providing high-quality summary document support for subsequent quantitative scoring.

[0110] Fourth embodiment Based on the above embodiments of this application, in the fourth embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 7 In the chip selection method, step S230 includes steps S2310 to S2330: Step S2310: Based on the number of chip digest documents to be scored, start the corresponding number of scorer interfaces, each of which is responsible for processing the scoring task of one chip digest document.

[0111] Step S2320: Based on preset scoring prompts, input the chip selection requirements, the scoring prompts, and the chip summary document into the large language model.

[0112] Step S2330: The chip summary document is scored from multiple preset scoring dimensions using the large language model, and the scores of each scoring dimension are weighted according to preset weights to obtain the semantic relevance score corresponding to each chip summary document.

[0113] In this embodiment, to improve scoring efficiency, the number of scorer interfaces is adaptively activated based on the number of chip summary documents to be scored. Each scorer interface independently undertakes the scoring task of one chip summary document, effectively shortening the overall scoring time through parallel processing. Subsequently, preset scoring prompts are constructed to guide and constrain the large language model, enabling it to conduct a comprehensive and standardized scoring of the chip summary documents from multiple dimensions, including core parameter matching, application scenario adaptability, and semantic requirement fit. Finally, the user-input chip selection requirements, the preset scoring prompts, and the chip summary documents to be scored are input into the large language model. The large language model outputs the specific scores for each scoring dimension, and then weights and sums the scores of each dimension according to preset weight ratios (e.g., 20%, 40%, 40%) to obtain the semantic relevance score for each chip summary document, providing accurate data support for subsequent chip selection analysis.

[0114] Furthermore, after obtaining the semantic relevance scores of each chip summary document, the chip summary documents can be filtered according to a preset scoring threshold. Chip summary documents with semantic relevance scores not lower than the preset scoring threshold (e.g., ≥6 points) can be retained as valid documents to eliminate redundant documents with low matching degree, thus providing a more accurate and efficient data foundation for subsequent chip selection analysis.

[0115] As an example, the rating prompts are as follows: "You are a chip summary document scoring assistant."

[0116] Please assign a score to the chip summary document based on the chip selection requirements.

[0117] You must evaluate based on the following three dimensions: 1. Evaluate the matching degree of core parameters from two aspects: parameter compliance and parameter redundancy. Score the parameters on a scale of 0-10 and explain the reasons. 2. Please determine whether the chip is suitable for the scenario, explain the advantages of its application scenario adaptability in combination with the specific requirements of the scenario, score it on 0-10 and explain the basis; 3. Please determine whether the chip fits the implicit meaning of the chip selection problem (e.g., 'prioritizing cost-effectiveness'), score it on 0-10, and explain the basis for your assessment. For example, to help understand the implementation process of the chip selection method in this embodiment, please refer to... Figure 8 , Figure 8 A block diagram of a scorer is provided, specifically: The scorer takes the chip summary document to be scored, the user's chip selection requirements, and preset scoring prompts as input. The above information is fed into a large language model, which outputs corresponding scores from multiple scoring dimensions, such as core parameter matching degree, application scenario adaptability, and semantic requirement fit, based on the prompt constraints. Then, the scores of multiple scoring dimensions are weighted according to preset weight ratios (e.g., core parameter matching degree 20%, application scenario adaptability 40%, semantic requirement fit 40%) to finally obtain the comprehensive score of each chip summary document, that is, the semantic relevance score, which provides a quantitative basis for subsequent chip selection and screening.

[0118] This application provides a chip selection device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip selection method in the above embodiment 1.

[0119] The following is for reference. Figure 9 The diagram illustrates a structural schematic of a chip selection device suitable for implementing embodiments of this application. The chip selection device in the embodiments of this application may include various hardware and software components for implementing the chip selection method. Figure 9 The chip selection device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0120] like Figure 9As shown, the chip selection device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the chip selection device. The processing unit 1001, the ROM 1002, and the RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the chip selection device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows chip selection devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0121] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0122] The chip selection device provided in this application, employing the chip selection method described in the above embodiments, can solve the technical problem that traditional chip selection technologies cannot perform semantic parsing of natural language requirements, resulting in poor adaptability between chip selection and application scenarios. Compared with the prior art, the beneficial effects of the chip selection device provided in this application are the same as those of the chip selection method provided in the above embodiments, and other technical features of this chip selection device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0123] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0125] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the chip selection method in the above embodiments.

[0126] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, radio frequency (RF), etc., or any suitable combination thereof.

[0127] The aforementioned computer-readable storage medium may be included in the chip selection device; or it may exist independently and not be assembled into the chip selection device.

[0128] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the chip selection device, the chip selection device causes the following: to receive a chip selection requirement input by a user based on natural language, and to extract chip entity information from the chip selection requirement; to perform information retrieval in a chip data structured database and a chip manual vectorized database based on the chip entity information and the chip selection requirement, respectively, and to obtain retrieval results; and to input the retrieval results, the chip selection requirement, and the chip entity information into a chip selection analyzer, and to output the corresponding chip selection result.

[0129] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0131] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0132] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described chip selection method. This solves the technical problem that traditional chip selection technologies cannot perform semantic parsing of natural language requirements, resulting in poor adaptability between chip selection and application scenarios. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the chip selection method provided in the above embodiments, and will not be repeated here.

[0133] This application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the chip selection method described above.

[0134] The computer program product provided in this application can solve the technical problem that traditional chip selection technology cannot perform semantic parsing of natural language requirements, resulting in poor adaptability between chip selection and application scenarios. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the chip selection method provided in the above embodiments, and will not be repeated here.

[0135] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent scope of this application.

[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0138] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip selection method, characterized in that, The chip selection method includes: Receive chip selection requirements from users based on natural language input, and extract chip entity information from the chip selection requirements; Based on the chip entity information and the chip selection requirements, information retrieval is performed in the chip data structured database and the chip manual vectorized database to obtain the retrieval results. The search results, chip selection requirements, and chip entity information are input into the chip selection analyzer, which outputs the corresponding chip selection results.

2. The chip selection method as described in claim 1, characterized in that, The step of receiving the user's chip selection requirements based on natural language input and extracting chip entity information from the chip selection requirements includes: By combining preset contextual learning examples, chip type descriptions, performance parameter descriptions, and prompts, the chip selection requirements are input into the large language model to obtain a set of chip entities; Anomaly detection is performed on the chip entity set. If the anomaly detection passes, the chip entity set is output as the chip entity information.

3. The chip selection method as described in claim 1, characterized in that, The steps of performing information retrieval in the chip data structured database and the chip manual vectorized database based on the chip entity information and the chip selection requirements to obtain the retrieval results include: Based on the chip entity information, a structured search is performed in the chip data structured database to determine the candidate chip set and the number of candidate chips; When the number of candidate chips exceeds the target screening quantity, based on the chip selection requirements and the candidate chip set, a vector search is performed in the chip manual vectorization database to determine the chip summary document corresponding to each candidate chip in the candidate chip set. Based on the chip selection requirements, the chip summary documents corresponding to each candidate chip are quantitatively scored to obtain the semantic relevance score of each chip summary document. The search results are generated based on the candidate chip set, the chip summary document corresponding to each candidate chip, and the corresponding semantic relevance score.

4. The chip selection method as described in claim 3, characterized in that, The steps of performing information retrieval in the chip data structured database and the chip manual vectorized database based on the chip entity information and the chip selection requirements to obtain the retrieval results include: Based on the number of chip entities contained in the chip entity information, a corresponding number of retrieval processes are initiated to perform the information retrieval in parallel. Once all the aforementioned retrieval processes have been completed, the abnormal feedback information generated during the retrieval process is summarized to obtain the abnormal information prompt text; The abnormal information prompt text, the candidate chip set, the chip summary document corresponding to each candidate chip, and the semantic relevance score are used together as the search results.

5. The chip selection method as described in claim 3, characterized in that, Before the step of performing vector retrieval in the chip manual vectorization database based on the chip selection requirements and the candidate chip set to determine the chip summary document corresponding to each candidate chip in the candidate chip set, the chip selection method further includes: Obtain the chip manual summary document, and divide the chip manual summary document into blocks to obtain multiple summary document blocks; Perform vectorization processing on each of the abstract document blocks to generate a abstract document vector corresponding to each of the abstract document blocks, and assign a corresponding abstract document number and block number to each of the abstract document blocks; Extract the chip name and summary document storage address corresponding to each summary document block, determine the summary document number, the block number, the chip name, and the chip summary document storage address as metadata, and associate the metadata with the summary document vector to construct the chip manual vectorized database.

6. The chip selection method as described in claim 3, characterized in that, The step of determining the chip summary document corresponding to each candidate chip in the candidate chip set by performing vector retrieval in the chip manual vectorization database based on the chip selection requirements and the candidate chip set includes: Based on the candidate chip set, the summary document blocks and summary document vectors corresponding to each candidate chip are selected from the chip manual vectorization database to generate a document vector list. The chip selection requirements are converted into query vectors, and the target number of filters and weight parameters are determined. The selected document index set is initialized to an empty set, and the unselected document index set is all document indexes corresponding to the document vector list. Calculate the similarity between each of the summary document vectors in the document vector list and the query vector to obtain the relevance score between each summary document block and the chip selection requirements; For each document index in the set of unselected document indexes, obtain the summary document vector and the relevance score corresponding to the current document index; If the selected document index set is not empty, then calculate the maximum similarity between the current document index and all selected summary document vectors in the selected document index set, and use the maximum similarity as the redundancy of the current document index; Based on the relevance score and redundancy corresponding to the current document index, and in conjunction with the weight parameters, the maximum marginal relevance algorithm score of the summary document vector corresponding to the current document index is calculated. Obtain the target document index with the highest score of the maximum marginal relevance algorithm from the set of unselected document indexes; The target document index is added to the selected document index set and removed from the unselected document index set until the number of indexes in the selected document index set reaches the target filtering number, or the unselected document index set is empty; Based on the selected document index set, the corresponding summary document block is matched in the chip manual vectorization database to obtain the summary document corresponding to each candidate chip in the candidate chip set.

7. The chip selection method as described in claim 3, characterized in that, After the step of performing a structured search in the chip data structured database based on the chip entity information to determine the candidate chip set and the number of candidate chips, the chip selection method further includes: When the number of candidate chips is less than or equal to the target screening number, the set of candidate chips is used as the search result.

8. The chip selection method as described in claim 1, characterized in that, The step of inputting the search results, the chip selection requirements, and the chip entity information into the chip selection analyzer and outputting the corresponding chip selection results includes: Based on the chip entity information, the chip selection scenario is determined, and according to the chip selection scenario, the corresponding target scenario prompt word template is matched from the prompt word template library; The chip selection requirements, the target scenario prompt word template, and the search results are input into the large language model, and the chip selection results are output.

9. A chip selection device, characterized in that, The chip selection device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip selection method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the chip selection method as described in any one of claims 1 to 8.

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