Method and apparatus for thermal state delamination recognition of power semiconductor device packages

Abstract

The application provides a power semiconductor device package thermal state layering recognition method and device, relates to the reliability analysis field of a power semiconductor device, and comprises the following steps: applying an electrothermal excitation signal containing a plurality of frequency components to a to-be-tested power semiconductor device, and acquiring a junction temperature transient response of the to-be-tested power semiconductor device; based on the electrothermal excitation signal containing a plurality of frequency components and the junction temperature transient response, a thermal impedance frequency spectrum reflecting spatial distribution differences is constructed; based on the difference between the measured thermal impedance frequency spectrum and a reference thermal impedance frequency spectrum, the local thermal parameter increment of each layer in the package heat dissipation path is separated out through an inversion algorithm, and the local thermal parameter increment is used for layering recognition of the package thermal state. The application utilizes the frequency dependence characteristics of a thermal diffusion path to decouple and map a frequency domain mixed response back to a spatial domain, so that quantitative layering positioning and rapid nondestructive evaluation of defects in a package heat dissipation structure are realized.

Description

Technical Field

[0001] This application relates to the field of reliability analysis, and more specifically, to a method and apparatus for identifying the thermal state layering of power semiconductor device packages. Background Technology

[0002] Currently, the heat dissipation performance of power semiconductor devices is determined by the multi-layered heat conduction paths within their packages. Abnormal interface thermal resistance in any layer can lead to increased junction temperature and shortened lifespan. Existing technologies typically employ the steady-state thermal resistance method, calculating the total thermal resistance by measuring the junction temperature and dissipated power under steady-state conditions. However, the steady-state thermal resistance method has fundamental limitations: First, the total thermal resistance is the sum of the thermal resistances of each layer, making it impossible to distinguish which physical layer the increase in thermal resistance originates from, thus failing to guide process improvements. Second, steady-state testing discards the frequency-dependent characteristics derived from thermal capacity, which is a key feature for diagnosing delamination and voids. Furthermore, local hot spots caused by voids are averaged out in steady-state measurements, making it difficult to detect small-area voids. Finally, steady-state testing requires waiting for thermal equilibrium, resulting in long testing times. Existing solutions suffer from the inability to locate defects within the package layer by layer and the loss of thermal capacity spatial resolution information, leading to insensitivity to transient local defects and low testing efficiency. Summary of the Invention

[0003] The purpose of this application is to provide a method and apparatus for identifying the thermal state layering of power semiconductor device packages, so as to solve the above-mentioned technical problems.

[0004] A method for layered identification of thermal state of a power semiconductor device package includes: applying an electrothermal excitation signal containing multiple frequency components to the power semiconductor device under test and acquiring the junction temperature transient response of the power semiconductor device under test; constructing a thermal impedance spectrum reflecting spatial distribution differences based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response; separating the local thermal parameter increments of each layer in the package heat dissipation path through an inversion algorithm based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum, and performing layered identification of the thermal state of the package based on the local thermal parameter increments.

[0005] The above scheme constructs a thermal impedance spectrum that reflects spatial distribution differences by applying an electrothermal excitation containing multiple frequency components and obtaining the junction temperature response. Then, based on the spectral differences, it inverts and separates the local thermal parameter increments of each layer. By utilizing the frequency dependence characteristics of the thermal diffusion path, it decouples the frequency domain mixed response into a single spatial domain increment, realizing the quantitative layered positioning of the thermal state of the package and overcoming the limitation that traditional single-value thermal resistance cannot locate defect layers.

[0006] As one implementation, the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response are subjected to frequency domain transformation, and the thermal impedance spectrum is determined based on the ratio of the frequency domain components.

[0007] The above scheme extracts the frequency domain components of excitation and response through frequency domain transformation, accurately reflecting the transmission characteristics of the thermal system at different frequencies, and providing a solid mathematical foundation for subsequent hierarchical inversion based on spectral differences.

[0008] In one implementation, the thermal impedance spectrum is a complex number, containing amplitude and phase information. The amplitude information is determined by the ratio of the amplitude of the frequency domain component of the junction temperature transient response to the amplitude of the frequency domain component of the electrothermal excitation signal containing multiple frequency components. This reflects the superposition effect of thermal resistance of each layer in the package heat dissipation path. In the low-frequency band, the thermal resistance of the heat dissipation layer far from the chip dominates the contribution to the amplitude. As the frequency increases, the proportion of the thermal resistance contribution of the layer closer to the chip in the amplitude gradually increases. The phase information is determined by the phase difference between the frequency domain component of the junction temperature transient response and the frequency domain component of the electrothermal excitation signal containing multiple frequency components. This reflects the response hysteresis caused by the thermal capacitance of each layer. The thermal capacitance of the layer closer to the chip produces significant phase hysteresis in the high-frequency band, the thermal capacitance of the layer far from the chip produces phase hysteresis in the low-frequency band, and the thermal capacitance of the middle layer produces phase hysteresis in the mid-frequency band. The changing trends of the amplitude and phase information in different frequency bands together constitute the frequency domain characteristics reflecting the spatial distribution differences of the package heat dissipation path.

[0009] The above scheme explores the complex characteristics of the thermal resistance spectrum, maps the amplitude and phase to the thermal resistance superposition effect and thermal capacity response hysteresis respectively, and reveals the layer contribution law of its variation with frequency. This makes the spectrum not only contain total thermal resistance information, but also contain rich spatial distribution characteristics, which greatly improves the resolution and accuracy of layer identification.

[0010] In one implementation, the electrothermal excitation signal containing multiple frequency components is a square wave pulse sequence with a constant duty cycle.

[0011] The above scheme uses a square wave pulse sequence with a constant duty cycle as excitation. The square wave has rich harmonic components in the frequency domain, which can cover a wide frequency band in a single test, thus improving excitation efficiency and the continuity of spectrum construction.

[0012] In one implementation, the frequency range of the electrothermal excitation signal containing multiple frequency components covers at least three orders of magnitude, with multiple frequency points selected at logarithmic intervals from the low-frequency band to the high-frequency band. The low-frequency band is sensitive to identifying thermal parameters of the heat dissipation layer far from the chip, and changes in the thermal impedance spectrum of the low-frequency band mainly reflect anomalies in the thermal parameters of the heat dissipation interface and system-level thermal parameters. The mid-frequency band is sensitive to identifying thermal parameters of the package intermediate layer, and changes in the thermal impedance spectrum of the mid-frequency band mainly reflect degradation of the copper frame and the package intermediate layer. The high-frequency band is sensitive to identifying thermal parameters of the solder layer close to the chip, and changes in the thermal impedance spectrum of the high-frequency band mainly reflect anomalies in the thermal parameters of the chip solder layer.

[0013] The above scheme ensures sufficient frequency band sensitivity from the heat dissipation interface far from the chip to the solder layer close to the chip by setting a frequency range covering at least three orders of magnitude and selecting frequency points at logarithmic intervals. This allows anomalies in the thermal parameters of each layer to be accurately captured in the corresponding frequency band, enhancing the tomographic capability of inversion separation.

[0014] As one implementation method, a sensitivity matrix is ​​established between the change in thermal impedance and the increment of local thermal parameters of each layer, and a least squares problem with regularization constraints is solved to separate the increment of local thermal parameters of each layer.

[0015] The above scheme establishes a linear correlation between the frequency domain mixed response and the spatial domain single-layer increment by establishing a sensitivity matrix, and introduces regularization constraints to solve the least squares problem, which effectively suppresses the influence of measurement noise on the inversion results and ensures the stability and physical rationality of decoupling each layer increment from high-dimensional spectral data.

[0016] In one implementation, the regularization constraint is a smoothness constraint. This smoothness constraint introduces a continuity penalty term between the local thermal parameter increments of adjacent layers when solving the least squares problem with regularization constraints. This continuity penalty term imposes a constraint on the difference between the thermal parameter increments of adjacent layers in the package heat dissipation path, requiring the difference to satisfy a smooth transition condition rather than abrupt jumps. This suppresses the influence of measurement noise on the inversion results and improves the identification accuracy of the local thermal parameter increments of each layer. The smoothness constraint ensures that the separated local thermal parameter increments of each layer conform to the physical laws of heat conduction, avoiding locally abrupt solutions that do not conform to physical meaning, thereby improving the reliability of the layer identification results.

[0017] The above scheme introduces smoothness constraints and continuity penalty terms to force a smooth transition in the incremental thermal parameters of adjacent layers, eliminating abrupt solutions that do not conform to the physical laws of heat conduction. While suppressing noise, it ensures the physical meaning of the inversion results and significantly improves the reliability of layer identification.

[0018] As one implementation, the package heat dissipation path is discretized into a multilayer thermal resistance-thermal capacity network to establish the sensitivity matrix.

[0019] The above scheme discretizes the continuous heat dissipation path into a multi-layer thermal resistance-thermal capacity network, providing a clear physical model framework for establishing the sensitivity matrix. This makes the mapping relationship between the frequency domain response and the spatial layer clearer, facilitating the numerical solution of the inversion algorithm.

[0020] As one implementation method, the packaging defect type is determined based on the magnitude of the local thermal parameter increment and the frequency band characteristics of the thermal impedance spectrum; wherein, when the local thermal parameter increment corresponding to the layer close to the chip is greater than a preset threshold and the thermal impedance phase lag of the corresponding frequency band is abnormal, it is determined to be a void or delamination defect of that layer; when the local thermal parameter increment corresponding to the intermediate packaging layer is dominant and the thermal impedance amplitude of the corresponding frequency band jumps, it is determined to be a degradation defect of the intermediate packaging layer; when the local thermal parameter increment corresponding to the heat dissipation interface far from the chip is dominant, it is determined to be a poor contact defect of the heat dissipation interface.

[0021] The above scheme establishes a mapping rule between layer-frequency band-defect type by combining the magnitude of the local thermal parameter increment with the spectral characteristics of a specific frequency band (such as phase lag and amplitude jump), thereby achieving accurate classification and judgment of typical defects such as voids, delamination, degradation, and poor contact.

[0022] In one implementation, the reference thermal impedance spectrum includes the standard thermal impedance spectrum of a healthy device and the defect sensitivity spectrum obtained by simulating typical packaging defects.

[0023] The above scheme provides a comprehensive comparison benchmark for measured spectra by constructing a benchmark library that includes health standard spectrum and defect sensitivity spectrum. It can not only identify deviations from the relative health state, but also directly match typical defect characteristics, thereby improving the coverage and accuracy of defect diagnosis.

[0024] As one implementation method, the junction temperature transient response is obtained by measuring changes in temperature-sensitive electrical parameters inside the power semiconductor device.

[0025] The above solution utilizes the internal temperature-sensitive electrical parameters of the device as an embedded sensor to obtain the junction temperature response, eliminating the need for external thermal imagers or vibration sensors. This achieves purely electrical measurement, greatly simplifying the testing equipment and improving the convenience of non-destructive evaluation.

[0026] In one implementation, the temperature-sensitive electrical parameter is measured by injecting a detection current with an amplitude much smaller than the excitation current within the measurement window after the electrothermal excitation signal containing multiple frequency components is turned off. The amplitude of the detection current is set to be much smaller than the excitation current that generates the electrothermal excitation signal containing multiple frequency components, and the injection time of the detection current is extremely short to avoid introducing additional self-heating effects that could affect the measurement accuracy of the junction temperature transient response. A differential measurement method is used to eliminate the influence of line resistance on the measurement results of the temperature-sensitive electrical parameter. The differential measurement method samples the values ​​of the temperature-sensitive electrical parameter under different operating conditions and takes the difference to cancel the common-mode influence of line resistance. The measurement results of the temperature-sensitive electrical parameter in multiple excitation cycles are synchronously averaged to improve the signal-to-noise ratio, and a stable average junction temperature response waveform at each frequency is obtained to construct the thermal impedance spectrum.

[0027] The above scheme avoids self-heating interference by injecting an extremely short and small detection current during the excitation shutdown window; it also eliminates the common-mode influence of line resistance by combining differential measurement and improves the signal-to-noise ratio through synchronous averaging, thus ensuring high-precision and high-stability acquisition of junction temperature transient response and providing high-quality raw data for spectrum construction.

[0028] Furthermore, the present invention also provides a power semiconductor device package thermal state layer identification device, comprising: an excitation application module configured to apply an electrothermal excitation signal containing multiple frequency components to the power semiconductor device under test; a response acquisition module configured to acquire the junction temperature transient response of the power semiconductor device under test; a spectrum construction module configured to construct a thermal impedance spectrum reflecting spatial distribution differences based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response; and an inversion separation module configured to separate the local thermal parameter increments of each layer in the package heat dissipation path through an inversion algorithm based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum, so as to realize the layer identification of the package thermal state.

[0029] The above-mentioned device scheme, through the coordinated cooperation of various modules, fully realizes the hierarchical identification process of multi-frequency excitation application, junction temperature response acquisition, thermal impedance spectrum construction and inversion separation, providing a reliable hardware carrier for the execution of the method and ensuring the automation and engineering implementation of hierarchical identification.

[0030] In one implementation, the excitation application module includes a programmable pulse source, the response acquisition module includes a temperature-sensitive electrical parameter detection unit, and the spectrum construction module and the inversion separation module are integrated into a data processing unit.

[0031] The above scheme achieves flexible multi-frequency excitation generation through a programmable pulse source, high-precision junction temperature acquisition through a temperature-sensitive electrical parameter detection unit, and centralized spectrum construction and inversion calculation through a data processing unit, thus realizing a reasonable division of labor and efficient integration of software and hardware functions.

[0032] In one implementation, the temperature-sensitive electrical parameter detection unit includes a precision constant current source and a high common-mode rejection ratio differential amplifier.

[0033] The above solution provides a stable, minute detection current through a precision constant current source, and combines it with a high common-mode rejection ratio differential amplifier to extract weak changes in electrical parameters and suppress line interference, thus ensuring the accuracy and anti-interference capability of junction temperature response acquisition. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic flowchart illustrating a method for identifying the thermal state layering of a power semiconductor device package, provided in an embodiment of this application; Figure 2 A schematic diagram of a power semiconductor device package thermal state layering identification device provided in this application embodiment; Figure 3 This is a flowchart illustrating another method for identifying the thermal state layering of a power semiconductor device package, provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0037] like Figure 1 As shown, this embodiment provides a method for layered identification of the thermal state of power semiconductor device packages. The core inventive concept of this method lies in utilizing the frequency-dependent characteristics of the thermal diffusion path to map the frequency domain response back to the spatial domain for layered localization, thereby overcoming the limitation of traditional steady-state thermal resistance testing in locating internal defects within the package layer by layer. This method mainly includes the following three core steps: Step S110: Apply an electrothermal excitation signal containing multiple frequency components to the power semiconductor device under test, and obtain the junction temperature transient response of the power semiconductor device under test.

[0038] Specifically, this step involves injecting a power signal containing multiple frequency components into the device to excite the thermal response of its internal multi-layered heat dissipation structure. It should be understood that the electrothermal excitation signal containing multiple frequency components described here is not a continuous excitation of a single frequency, but rather a composite signal capable of covering a wide range of frequency points in the frequency domain, such as a square wave pulse sequence or other waveforms with rich harmonic characteristics, which will be described in detail in subsequent embodiments. The process of obtaining the junction temperature transient response captures the dynamic curve of the device's internal temperature changing over time under multi-frequency heat flow impact. This step breaks through the limitation of traditional steady-state testing, which only focuses on the final thermal equilibrium state, and preserves transient dynamic information during the heat conduction process.

[0039] Step S120: Based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response, a thermal impedance spectrum reflecting spatial distribution differences is constructed.

[0040] Specifically, this step converts the time-domain excitation and response signals to the frequency domain. By comparing the mathematical relationship between thermal excitation and junction temperature response at different frequencies, a thermal impedance spectrum is constructed. Steady-state thermal resistance essentially measures only a scalar value under thermal equilibrium conditions. It simply adds up the thermal resistances of each layer within the package, from the chip to the environment, completely losing the crucial physical quantity of thermal capacity and the frequency dependence of thermal impedance. Thermal capacity represents the ability of each layer to absorb and release heat; the combination of thermal capacity and thermal resistance at different layers determines the time constant of heat diffusion. Steady-state testing discards this time constant information, essentially using a one-dimensional scalar to describe a high-dimensional distributed parameter system, inevitably losing spatial resolution. The thermal impedance spectrum constructed in this embodiment not only includes the superposition effect of thermal resistance but also the response hysteresis and frequency attenuation characteristics caused by thermal capacity. These frequency-dependent information are strongly bound to the spatial location of each physical layer within the package. Therefore, the thermal impedance spectrum essentially maps the spatial distribution differences within the package, which are difficult to observe directly, to easily measurable and analytical spectral features in the frequency domain.

[0041] Step S130: Based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum, the local thermal parameter increments of each layer in the package heat dissipation path are separated by the inversion algorithm, and the layered identification of the package thermal state is performed based on the local thermal parameter increments.

[0042] Specifically, this step decouples the mixed spectral differences in the frequency domain and restores them to the changes in thermal parameters of each single layer in the spatial domain through mathematical inversion. Since the measured spectrum is a mixed response resulting from the combined effects of changes in thermal parameters across layers, direct observation of the spectrum makes it difficult to accurately quantify the degree of degradation at a specific layer. The role of the inversion algorithm is to establish an inverse mapping relationship between the frequency domain response and the spatial domain layer parameters, peeling away the local thermal parameter increments of each layer from the mixed spectral differences. For example, when voids appear in the chip solder layer, although some frequency bands will show anomalies, only through inversion separation can the specific increment of the thermal resistance of that solder layer be quantitatively calculated, excluding possible interference from other layers. The reason why this combination of multi-frequency excitation and spectral inversion can decouple the mixed frequency domain response into single-layer increments in the spatial domain is fundamentally due to the different penetration depths of heat waves of different frequencies in a multi-layer structure—high-frequency heat waves attenuate quickly and only sense layers close to the chip; low-frequency heat waves penetrate deeply and can reach heat dissipation interfaces far from the chip. The inversion algorithm utilizes this natural correspondence between frequency and spatial location to achieve spatial decoupling similar to tomography. It should be understood that the inversion algorithm described in this embodiment can be any mathematical optimization algorithm capable of achieving the aforementioned decoupling function. Subsequent embodiments will provide a specific example of least-squares inversion with regularization constraints, but the inversion algorithm should not be limited to this single specific form.

[0043] Through the coordinated operation of steps S110 to S130 above, this embodiment establishes a complete causal chain backbone from acquiring transient response through multi-frequency excitation, to constructing spectrum to extract spatial distribution features, and then to inversion separation to achieve tomographic localization, providing attachment points for all subsequent advanced branches. The scheme of this embodiment is only illustrative and not restrictive. Any technical details variation that can realize the core concept of multi-frequency excitation-spectrum construction-inversion separation should be covered within the protection scope of this invention.

[0044] In some embodiments, a frequency domain transformation can be performed on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response, and the thermal impedance spectrum can be determined based on the ratio of the frequency domain components. Specifically, the essence of frequency domain transformation is to decompose the complex waveform that varies with time in the time domain into a series of superimposed sine waves of different frequencies. Through this transformation, the originally intertwined transient thermal excitation and transient temperature response are resolved into their respective frequency domain components at specific frequencies. Subsequently, by performing a ratio calculation between the frequency domain components of the junction temperature transient response and the frequency domain components of the electrothermal excitation signal, the transfer characteristics determined purely by the device package heat dissipation structure itself can be extracted, thereby constructing the thermal impedance spectrum. It should be understood that the frequency domain transformation here can be implemented using a general Fourier transform algorithm or other time-frequency conversion methods, and its core purpose is to extract frequency-dependent information, rather than being limited to a specific mathematical transformation formula.

[0045] Furthermore, the thermal impedance spectrum is a complex number, containing both amplitude and phase information.

[0046] It's crucial to explain why the thermal impedance spectrum can be a complex number encompassing both amplitude and phase, rather than a single scalar: the packaged heat dissipation path is a distributed parameter system composed of multiple layers of interwoven thermal resistance and thermal capacitance. Thermal resistance determines the magnitude of the steady-state temperature rise, while thermal capacitance determines the lag time of transient heat diffusion. Using only the amplitude as a single characteristic only reflects the superposition effect of thermal resistance, losing the time delay information introduced by thermal capacitance. This degenerates into an incomplete description, failing to achieve accurate spatial decoupling. Therefore, amplitude and phase together constitute the frequency domain characteristics, and neither is dispensable.

[0047] Among them, the amplitude information is determined by the ratio of the amplitude of the frequency domain component of the junction temperature transient response to the amplitude of the frequency domain component of the electrothermal excitation signal containing multiple frequency components. It reflects the superposition effect of the thermal resistance of each layer in the heat dissipation path of the package. In the low frequency band, the thermal resistance of the heat dissipation layer far from the chip has a dominant contribution to the amplitude. As the frequency increases, the proportion of the thermal resistance of the layer closer to the chip in the amplitude gradually increases.

[0048] Phase information is determined by the phase difference between the frequency domain component of the junction temperature transient response and the frequency domain component of the electrothermal excitation signal containing multiple frequency components. It reflects the response hysteresis caused by the thermal capacitance of each layer. The thermal capacitance of the layer closer to the chip produces significant phase hysteresis in the high frequency band, the thermal capacitance of the layer farther from the chip produces phase hysteresis in the low frequency band, and the thermal capacitance of the middle layer produces phase hysteresis in the mid frequency band.

[0049] The variation trends of amplitude and phase information in different frequency bands together constitute frequency domain characteristics that reflect the differences in the spatial distribution of heat dissipation paths in the package.

[0050] The revelation of the physical meaning of this complex spectrum establishes a very strong defensive depth: low-frequency heat waves penetrate deeply, reaching heat dissipation interfaces far from the chip. Therefore, the large heat capacity at these points causes significant phase lag in the low-frequency band, and their enormous thermal resistance dominates the low-frequency amplitude. High-frequency heat waves attenuate extremely quickly, remaining only in the shallow area near the chip. Therefore, the small heat capacity near the junction, such as the chip solder layer, produces significant phase lag in the high-frequency band, and the proportion of its thermal resistance contribution to the amplitude gradually increases with frequency. The mid-frequency band mainly senses the thermal state of the intermediate layers of the package. This layered contribution pattern of amplitude and phase with frequency strongly binds spectral characteristics to spatial layers, providing a high-resolution analytical dimension for subsequent inversion and separation.

[0051] In selecting the excitation signal, the electrothermal excitation signal containing multiple frequency components is a square wave pulse sequence with a constant duty cycle.

[0052] The reason for using a square wave pulse sequence with a constant duty cycle is that square wave signals possess extremely rich harmonic components in the frequency domain, enabling them to simultaneously cover a wide frequency band in a single test sequence. Unlike a single sine wave, this eliminates the need for slow frequency sweeping point by point, greatly improving excitation efficiency and the continuity of spectrum construction. Simultaneously, the constant duty cycle ensures that the energy distribution of each frequency component exhibits consistent regularity, avoiding additional spectral distortion introduced by duty cycle jumps. It should be understood that while this embodiment preferably uses a square wave pulse sequence, other composite waveforms with wideband harmonic characteristics can also be used in other embodiments, as long as they provide sufficiently rich multi-frequency components in the frequency domain.

[0053] To ensure sufficient frequency sensitivity in each layer, the frequency range of the electrothermal excitation signal containing multiple frequency components covers at least three orders of magnitude, with multiple frequency points selected at logarithmic intervals from low frequency to high frequency.

[0054] The low-frequency band is sensitive to identifying the thermal parameters of the heat dissipation layer far from the chip, and the changes in the thermal impedance spectrum in the low-frequency band mainly reflect the abnormalities of the heat dissipation interface and system-level thermal parameters; the mid-frequency band is sensitive to identifying the thermal parameters of the package intermediate layer, and the changes in the thermal impedance spectrum in the mid-frequency band mainly reflect the degradation of the copper frame and the package intermediate layer; the high-frequency band is sensitive to identifying the thermal parameters of the solder layer close to the chip, and the changes in the thermal impedance spectrum in the high-frequency band mainly reflect the abnormalities of the thermal parameters of the chip solder layer.

[0055] The thermal time constant of the package, from the chip solder layer to the external heat dissipation interface, spans a wide range, potentially from microseconds to seconds. If the frequency range is too narrow, it will be impossible to simultaneously detect shallow local defects and deep heat dissipation anomalies. Selecting frequency points at logarithmic intervals ensures that each layer's corresponding frequency band receives uniform and sufficiently dense sampling points across a broad frequency domain spanning multiple time constants. This avoids the spectral characteristics of a certain layer being missed due to sparse frequency points, thus ensuring that the inversion algorithm can extract complete sensitivity information for each single layer from the entire frequency band.

[0056] In some embodiments, a sensitivity matrix can be established between the change in thermal impedance and the increments of local thermal parameters in each layer. A least-squares problem with regularization constraints is then solved to separate the increments of local thermal parameters in each layer. Specifically, the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum is a mixed response resulting from the superposition of small changes in the thermal parameters of multiple layers in the packaged heat dissipation path. The sensitivity matrix serves to establish a linearized correlation mapping between this highly coupled mixed response in the frequency domain and the increments of local thermal parameters in each single layer in the spatial domain. By constructing this matrix, the inversion algorithm can clearly identify which layer(s) of parameters contributes to the difference in a specific frequency band of the spectrum. However, since the measured spectrum data inevitably contains measurement noise, and the sensitivity matrix itself may have ill-conditioned characteristics, directly solving this inverse problem can easily lead to severe oscillations in the solution, causing the separated increments of local thermal parameters to deviate from the true values. Therefore, regularization constraints can be introduced to solve the least squares problem. By imposing reasonable restrictions on the search space of the solution, the interference of noise on the inversion results can be effectively suppressed, ensuring the stability and physical rationality of decoupling the increments of each layer from the high-dimensional spectral data. It should be understood that the regularization constraints described here are not the only algorithmic choice, but their core purpose is to provide additional prior information for solving the inverse problem to stabilize the solution structure.

[0057] Furthermore, the regularization constraint is a smoothness constraint.

[0058] Heat conduction is essentially a physical process that follows the laws of spatial continuity. The diffusion of heat within a multilayered encapsulation structure gradually decreases, and the thermal parameters between adjacent physical layers necessarily exhibit a smooth transition relationship. When a layer degrades or develops a defect, the anomaly in its thermal parameters tends to diffuse to adjacent layers to a certain extent, rather than presenting an isolated, abrupt jump in space. If the inversion algorithm allows for abrupt solutions, it might, in order to forcibly fit certain noise spikes in the spectrum, produce absurd results such as a surge in thermal resistance in an intermediate layer while the thermal resistance of its adjacent upper and lower layers remains unchanged. This clearly violates the fundamental physical laws of heat conduction. Therefore, smoothness constraints introduce a continuity penalty term between the local thermal parameter increments of adjacent layers when solving least squares problems with regularization constraints. This continuity penalty term constrains the difference in thermal parameter increments between adjacent layers in the encapsulation heat dissipation path, requiring the difference to satisfy a smooth transition condition rather than an abrupt jump. This suppresses the influence of measurement noise on the inversion results and improves the identification accuracy of the local thermal parameter increments of each layer.

[0059] By penalizing the incremental difference between adjacent layers, the smoothness constraint injects physical laws as prior knowledge into the mathematical optimization process, eliminating abrupt solutions that, although mathematically minimizing the residuals, are physically unacceptable, thereby significantly improving the reliability of the hierarchical identification results.

[0060] To provide a clear physical model framework for establishing the sensitivity matrix, the package heat dissipation path is discretized into a multi-layer thermal resistance-thermal capacity network. Specifically, the continuous heat diffusion path from the chip to the environment within the package can be mathematically represented as a trapezoidal network composed of multiple cascaded thermal resistances and thermal capacitives. Each level of thermal resistance represents the obstruction of heat flow at the corresponding physical layer, and each level of thermal capacity represents the time delay characteristics of heat storage and release at that layer. Through this discretization, the originally abstract distributed parameter system is transformed into a concrete lumped parameter network, allowing the mapping relationship between the frequency domain response and spatial layers to be expressed using explicit circuit topology equations. Based on this multi-layer thermal resistance-thermal capacity network, the thermal resistance or thermal capacity parameters of a single layer can be changed one by one through simulation perturbation or differential calculation to observe the degree of influence on the thermal impedance spectrum at each frequency point, thereby systematically deriving the value of each element in the sensitivity matrix. This discretization model not only provides a solid physical basis for the numerical solution of the inversion algorithm, but also enables the final separated local thermal parameter increments to directly correspond to specific physical layers such as the chip solder layer, copper frame, and molding compound, achieving a closed loop from mathematical solution to physical diagnosis. It should be understood that the number of discretization layers can be flexibly set according to the actual structural complexity of the device package. More layers result in higher spatial resolution, but also increase the complexity of the inversion calculation, requiring a balance between identification accuracy and computational efficiency. The sensitivity matrix establishment and regularization solution logic described in this embodiment are interpretive, not restrictive; any equivalent algorithm framework capable of achieving frequency domain decoupling and spatial tomographic localization should be included.

[0061] In some embodiments, the specific encapsulation defect type determination is further elaborated on how to determine the specific encapsulation defect type based on the local thermal parameter increments separated by inversion, and the composition of the reference thermal impedance spectrum on which the determination depends.

[0062] This paper proposes a packaging defect type determination mechanism based on the magnitude of local thermal parameter increments and the frequency band characteristics of thermal impedance spectra. Specifically, traditional defect diagnosis often relies solely on the absolute value of the total thermal resistance or the thermal resistance increment of a specific layer to determine the presence of anomalies. This single-dimensional approach carries a significant risk of misjudgment. For example, when poor contact at the heat dissipation interface far from the chip leads to an increase in total thermal resistance, the layers closer to the chip may also exhibit a certain increase in thermal resistance due to heat accumulation caused by impaired heat flow. If only the magnitude of the increment is considered, it is easy to misjudge deep-layer poor contact as shallow-layer voids. Therefore, this embodiment establishes a binary binding determination mechanism based on parameter increments and spectral characteristics. It not only considers the magnitude of the increment but also combines spectral characteristics of specific frequency bands, such as phase lag or amplitude jumps, thereby achieving accurate defect classification.

[0063] When the increase in local thermal parameters of a layer close to the chip is greater than a preset threshold and the thermal impedance phase lag of the corresponding frequency band is abnormal, it is determined to be a void or delamination defect in that layer.

[0064] Voids or delamination defects essentially introduce air gaps into the originally tightly contacted solid interfaces. Air has extremely low thermal conductivity, leading to a significant increase in thermal resistance. Therefore, the increase in local thermal parameters inevitably exceeds a preset threshold. Simultaneously, the introduction of air gaps cuts off the direct heat conduction path, forcing heat to flow and diffuse around the defect edges. This flow effect greatly increases the thermal capacity time constant of that local region, manifesting as a severe hysteresis in the thermal response. Since layers closer to the chip correspond to high-frequency bands, this hysteresis caused by flow is particularly anomalous and severe in the thermal impedance phase at high frequencies. Only when both the incremental threshold condition and the high-frequency phase hysteresis condition are met can a void or delamination be diagnosed, ruling out interference from other layer thermal resistance conduction anomalies.

[0065] When the increase in local thermal parameters corresponding to the encapsulation intermediate layer dominates and the thermal impedance amplitude of the corresponding frequency band jumps, it is determined to be a degradation defect of the encapsulation intermediate layer.

[0066] In encapsulation interlayers, such as copper frames or molding compounds, degradation typically manifests as microscopic damage to the material's lattice structure or the formation of interfacial oxide layers. While this degradation increases thermal resistance, making the local thermal parameter increment at this layer dominate the total increment, it does not create a complete air blockage like voids, thus exhibiting less pronounced phase hysteresis. However, abrupt changes in thermal resistance at degraded layers lead to strong impedance mismatch and reflection as heat flows through the layer. This reflection is directly reflected in the frequency spectrum as discontinuous jumps in the corresponding mid-frequency thermal impedance amplitude. Therefore, the binary association between incremental dominance and amplitude jumps is a key fingerprint for identifying interlayer material degradation.

[0067] When the increase in local thermal parameters at the heat dissipation interface far from the chip dominates, it is determined to be a defect of poor contact at the heat dissipation interface.

[0068] At heat dissipation interfaces far from the chip, such as thermal grease layers or heat sink contact surfaces, poor contact typically manifests as large-area macroscopic poor adhesion. This defect primarily increases macroscopic thermal resistance, causing local thermal parameter increments in the low-frequency band to dominate. Since poor contact does not significantly alter the local heat capacity distribution structure, and the resolution of phase changes in the low-frequency band is relatively weak, the single-dimensional characteristic of low-frequency local thermal parameter increment dominance is sufficient for diagnostic specificity in the determination of this type of defect, without the need for additional complex spectral distortion conditions. It should be understood that the above three determination rules are only examples of typical defects. In practical engineering applications, more layer-frequency-defect type mapping rules can be established based on the packaging structure characteristics of different devices to cover other failure modes such as bond wire detachment and substrate cracks.

[0069] To provide a comprehensive benchmark, the benchmark thermal impedance spectrum includes the standard thermal impedance spectrum of healthy devices and the defect sensitivity spectrum obtained by simulating typical packaging defects. Specifically, the standard thermal impedance spectrum of healthy devices is established by repeatedly executing the test method of this invention on a large number of devices with intact packaging structures, extracting the statistical average value and confidence interval of their thermal impedance spectra. This standard spectrum represents the frequency domain response baseline of the device in a state without any degradation. The defect sensitivity spectrum is obtained by artificially introducing typical defects (such as solder layer voids with different area ratios, interface oxide layers of different thicknesses, etc.) at specific layers of the packaging model using finite element simulation software, and calculating the change in thermal impedance spectrum relative to the healthy state. This simulation-generated sensitivity spectrum not only includes the quantitative mapping relationship between defect size and spectral distortion, but also covers extreme defect samples that are difficult to obtain on actual production lines but have high diagnostic value. The healthy standard spectrum and the defect sensitivity spectrum together constitute a multi-dimensional benchmark database, enabling the measured spectrum to not only identify deviations from the healthy state, but also to directly match and compare with typical defect characteristics, greatly improving the coverage and quantitative accuracy of defect diagnosis. The determination rules and benchmark library construction methods described in this embodiment are only interpretive and not restrictive. Any equivalent logic that can achieve binary binding determination of incremental and spectral features should be included.

[0070] In some embodiments, further details are provided on how to acquire this critical transient response with high precision and high interference resistance.

[0071] The transient response of the junction temperature is obtained by measuring changes in temperature-sensitive electrical parameters within power semiconductor devices. Specifically, power semiconductor devices contain various electrical parameters that are highly sensitive to temperature, such as the forward voltage drop of the body diode in a MOSFET and the collector-emitter saturation voltage drop in an IGBT. These parameters exhibit an approximately linear relationship with junction temperature, thus serving as miniature temperature sensors embedded within the chip. By measuring the dynamic changes of these temperature-sensitive electrical parameters under electrothermal excitation and converting them into junction temperature change curves using pre-calibrated temperature coefficients, a purely electrical, non-destructive evaluation can be achieved. This method completely eliminates the limitations of traditional testing methods that rely on external infrared thermal imagers or thermocouples, requiring no damage to the packaging structure or disassembly of the heat sink, greatly simplifying the testing setup and improving the convenience of online evaluation. It should be understood that although different types of devices may employ different temperature-sensitive electrical parameters, their core logic is to utilize the device's own physical characteristics as a sensing medium; any internal electrical parameter that can reflect transient changes in junction temperature should be covered within the scope of this invention.

[0072] To ensure sufficient accuracy and stability of the junction temperature transient response obtained through temperature-sensitive electrical parameters, this embodiment further provides three key measurement details, constructing a complete defense depth from hardware operation to signal processing.

[0073] First, the temperature-sensitive electrical parameters are measured by injecting a detection current with an amplitude much smaller than the excitation current into the measurement window after the electrothermal excitation signal containing multiple frequency components is turned off.

[0074] The most critical source of interference when measuring junction temperature response is the additional self-heating effect introduced by the measurement process itself. If the detection current is large or continuously injected, it will generate additional Joule heat inside the chip, causing an additional temperature rise in the junction temperature at the moment of measurement that is not caused by the excitation. This self-heating effect will be directly superimposed on the true transient response curve, distorting the measured junction temperature waveform and consequently causing distortion of the subsequently constructed thermal impedance spectrum. Therefore, in this embodiment, the amplitude of the detection current is set to be much smaller than the excitation current that generates the electrothermal excitation signal containing multiple frequency components, and the injection time of the detection current is extremely short, in order to avoid introducing additional self-heating effects that affect the measurement accuracy of the junction temperature transient response.

[0075] For example, the excitation current is typically in the ampere range to simulate actual operating power consumption, while the sense current is strictly controlled in the milliampere or even microampere range, injected only momentarily within an extremely short cooling window after the excitation is turned off to read electrical parameters. The self-heating generated by this tiny and extremely short sense current is negligible, thus ensuring the purity of the junction temperature response.

[0076] Secondly, a differential measurement method is used to eliminate the influence of line resistance on the measurement results of the temperature-sensitive electrical parameters.

[0077] Specifically, in actual test circuits, line resistance, including contact resistance and wire resistance, is unavoidable between device pins and test fixtures. When the detection current flows through these line resistances, an additional voltage drop is generated. This voltage drop is superimposed in series with the voltage drop generated by internal temperature-sensitive electrical parameters (such as the forward voltage drop of a body diode) and is collected by the measuring instrument. Since the value of line resistance often varies with ambient temperature and contact force, this common-mode interference, if not eliminated, will severely mask weak junction temperature change signals. Differential measurement methods compensate for the common-mode effect of line resistance by sampling the values ​​of temperature-sensitive electrical parameters under different operating conditions and taking the difference.

[0078] For example, the same minute detection current can be injected and the voltage sampled in both the cold state before excitation is applied and the hot state after excitation is turned off. Since the line resistance remains almost constant within a very short measurement interval, the resulting voltage drop is the same common-mode component in both samples. By subtracting the cold-state sample value from the hot-state sample value, the common-mode voltage drop across the line resistance is completely canceled out, and the difference reflects only the change in temperature-sensitive electrical parameters caused purely by junction temperature variations. This differential logic eliminates external interference at the underlying signal extraction mechanism, ensuring the accurate extraction of weak junction temperature signals.

[0079] Finally, the measurement results of the temperature-sensitive electrical parameters in multiple excitation cycles are synchronously averaged to improve the signal-to-noise ratio, and a stable average junction temperature response waveform at each frequency is obtained to construct the thermal impedance spectrum.

[0080] In real-world industrial testing environments, random interference such as electromagnetic interference, power supply ripple, and device switching noise are ubiquitous. Junction temperature response waveforms measured in a single cycle often exhibit numerous spikes and extremely low signal-to-noise ratios (SNR). If frequency domain transformation is directly performed on such low-quality single-cycle waveforms to construct the spectrum, the noise spectrum will severely mask the true thermal impedance characteristics, causing the inversion separation algorithm to fail to converge or yield absurd solutions. Synchronous averaging technology leverages the fundamental difference in statistical characteristics between random noise and periodic signals: the true thermal response is a deterministic signal that strictly repeats with the excitation cycle, while random noise is irregular between cycles. By strictly aligning and synchronously averaging the measurement results across multiple excitation cycles, the deterministic signal is linearly superimposed and enhanced, while the random noise, due to its irregularity, cancels each other out during the superposition process, tending towards zero. As the number of averaging cycles increases, the SNR increases by a square root multiple, ultimately obtaining an extremely smooth and stable average junction temperature response waveform at each frequency, providing a high-quality data foundation for subsequently constructing a high-resolution thermal impedance spectrum.

[0081] It should be understood that the three key measurement details mentioned above are not isolated, but constitute a progressive precision assurance system: the minute detection current avoids self-heating interference and ensures signal purity; differential measurement eliminates line resistance and ensures signal authenticity; and synchronous averaging suppresses random noise and ensures signal stability. This system tightly binds functional limitations to the underlying hardware. For example, the stable provision of the minute detection current relies on a precision constant current source, and the extraction of weak differential signals relies on a differential amplifier with a high common-mode rejection ratio. These hardware carriers will be further detailed in subsequent device embodiments. The measurement details described in this embodiment are illustrative only and not restrictive. Any equivalent measurement strategy that can achieve the avoidance of self-heating, elimination of common-mode interference, and improvement of signal-to-noise ratio should be included.

[0082] like Figure 2 As shown, this embodiment provides a power semiconductor device packaging thermal state layer identification device, which provides a specific hardware carrier mapping for the aforementioned method embodiment, binding functional modules to visible physical hardware.

[0083] The device comprises four core functional modules: an excitation application module 201, a response acquisition module 202, a spectrum construction module 203, and an inversion separation module 204. The excitation application module 201 is configured to apply an electrothermal excitation signal containing multiple frequency components to the power semiconductor device under test (PSD), directly corresponding to and executing the excitation application action in step S110. The response acquisition module 202 is configured to acquire the junction temperature transient response of the PSD, corresponding to and executing the response acquisition action in step S110. The spectrum construction module 203 is configured to construct a thermal impedance spectrum reflecting spatial distribution differences based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response, corresponding to and executing step S120. The inversion separation module 204 is configured to separate the local thermal parameter increments of each layer in the package heat dissipation path based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum using an inversion algorithm, thereby achieving layered identification of the package thermal state, corresponding to and executing step S130. Through the coordinated operation of these four modules, the device fully realizes the entire process of hierarchical identification, from multi-frequency excitation application, high-precision junction temperature acquisition, spectrum construction to inversion separation, and translates abstract algorithm logic into operable hardware execution actions.

[0084] To more clearly illustrate the technical solution and engineering feasibility of the present invention, the following example uses the detection of solder layer voids in a typical TO-220 packaged power MOSFET, combined with the method and device architecture of the aforementioned embodiments, as follows: Figure 3 As shown, the complete operational results are demonstrated from excitation application, junction temperature measurement, spectrum construction, inversion separation to defect determination.

[0085] Step S301: Apply a multi-frequency electrothermal excitation signal.

[0086] An excitation application module containing a programmable pulse source is used to apply electrothermal excitation signals containing multiple frequency components to two devices under test.

[0087] Specifically, this embodiment uses a square wave pulse sequence with a constant duty cycle as the excitation waveform. Its frequency range covers at least three orders of magnitude from extremely low to high frequencies, and multiple frequency points are selected at logarithmic intervals to ensure sufficient frequency band sensitivity from the heat dissipation interface far from the chip to the solder layer close to the chip. The pulse amplitude is set to a preset proportion of the device's rated current to excite a sufficient thermal response signal while avoiding excessive self-heating damage to the device.

[0088] Step S302: Obtain the junction temperature transient response.

[0089] During the application of the excitation signal and within the measurement window after it is turned off, a temperature-sensitive electrical parameter detection unit containing a precision constant current source and a high common-mode rejection ratio differential amplifier is used to obtain the junction temperature transient response by measuring the changes in the temperature-sensitive electrical parameters inside the device.

[0090] Specifically, this embodiment utilizes the approximately linear relationship between the forward voltage drop of the MOSFET body diode and the junction temperature as an embedded temperature sensor. During the extremely short cooling time after the square wave pulse excitation is turned off, a tiny detection current with an amplitude much smaller than the excitation current is injected to avoid additional self-heating effects. A differential measurement method is used to sample and take the difference under different operating conditions to eliminate the common-mode influence of the line resistance. The measurement results in multiple excitation cycles are synchronously averaged to improve the signal-to-noise ratio, and finally a stable and pure average junction temperature response waveform at each frequency is obtained.

[0091] Step S303: Construct the thermal impedance spectrum.

[0092] The acquired time-domain excitation signal and the average junction temperature response waveform are sent to the data processing unit, where they undergo frequency domain transformation. The thermal impedance spectrum is determined based on the ratio of the frequency components. Since the thermal impedance spectrum is a complex number containing amplitude and phase information, the data processing unit extracts the amplitude and phase data at each frequency point to plot the complete thermal impedance spectrum curve.

[0093] By comparing the thermal impedance spectra of healthy devices and voided devices, significant differences in frequency characteristics can be observed: in the extremely low frequency band, the amplitude and phase differences between the two are very small, indicating that the heat dissipation interface and system-level thermal parameters far from the chip are not significantly changed by the local voids in the solder layer; while in the mid-to-high frequency band, the thermal impedance amplitude of the voided device is significantly higher than that of the healthy device, and the phase lag is significantly increased. The microscopic physical mechanism of this phenomenon is that the voids in the solder layer cut off the direct conduction path of local heat flow, forcing heat to diffuse around the defect edge, which greatly increases the thermal resistance superposition effect and thermal capacity response lag near the chip layer. High-frequency heat waves attenuate quickly and penetrate shallowly, and have extremely high sensitivity to such shallow local anomalies near the chip, thus exhibiting severe distortion in the mid-to-high frequency spectrum.

[0094] Step S304: Invert and separate the local thermal parameter increments of each layer.

[0095] Based on the difference between the measured thermal impedance spectrum and the pre-established reference thermal impedance spectrum, the data processing unit uses an inversion algorithm to separate the local thermal parameter increments of each layer in the package heat dissipation path.

[0096] Specifically, the heat dissipation path of the package is discretized into a multi-layer thermal resistance-thermal capacity network to establish a sensitivity matrix. This matrix establishes a linear relationship between the observed mixed spectrum differences in the frequency domain and the local thermal parameter increments of each single layer in the spatial domain. When solving the least squares problem with regularization constraints, a smoothness constraint is introduced, namely a continuity penalty term between the local thermal parameter increments of adjacent layers. This requires the difference to meet the smooth transition condition rather than abrupt jumps, thereby suppressing measurement noise and ensuring that the inversion results conform to the spatial continuity physical laws of heat conduction. For void devices, the local thermal parameter increments corresponding to the chip solder layer are significantly larger than the increments of other layers (such as the copper frame, molding compound, etc.), and this increment exceeds the preset health judgment threshold; while the increments of other layers are all within the normal fluctuation range.

[0097] Step S305: Determine the type of packaging defect and output a report.

[0098] The packaging defect type is determined based on the magnitude of the local thermal parameter increment and the frequency band characteristics of the thermal impedance spectrum. Since the local thermal parameter increment corresponding to the solder layer near the chip exceeds a preset threshold, and the corresponding high-frequency thermal impedance phase lag is abnormal, this embodiment confirms the presence of voids or delamination defects in this layer based on the binary bonding determination rule. The data processing unit ultimately outputs a complete defect diagnosis report. The report not only includes a bar chart comparison of the local thermal parameter increments of each layer and the defect type determination conclusion, but also, based on the specific value of the solder layer thermal resistance increment and combined with the thermal model of the device under specified switching frequency and load conditions, predicts the dynamic junction temperature fluctuation amplitude and remaining thermal cycle life of the defective device, indicating that its predicted remaining life is approximately a lower percentage of that of a healthy device, highlighting the risk.

[0099] It should be understood that the TO-220 packaged MOSFET solder layer void detection described in this embodiment is only a specific application scenario for verifying the feasibility of the solution. Any person skilled in the art can easily conceive of extending this method to the detection of other package forms, other device types or other defect modes within the scope of the technology disclosed in this invention. These changes or substitutions should all be covered within the protection scope of this invention.

[0100] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for identifying the thermal state layering of a power semiconductor device package, characterized in that, include: An electrothermal excitation signal containing multiple frequency components is applied to the power semiconductor device under test, and the junction temperature transient response of the power semiconductor device under test is obtained. Based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response, a thermal impedance spectrum reflecting spatial distribution differences is constructed. Based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum, the local thermal parameter increments of each layer in the package heat dissipation path are separated by an inversion algorithm, and the layered identification of the package thermal state is performed based on the local thermal parameter increments.

2. The method for identifying the thermal state layering of power semiconductor device packages according to claim 1, characterized in that, The electrothermal excitation signal containing multiple frequency components and the junction temperature transient response are subjected to frequency domain transformation, and the thermal impedance spectrum is determined based on the ratio of the frequency domain components.

3. The method for identifying the thermal state layering of power semiconductor device packages according to claim 2, characterized in that, The thermal impedance spectrum is a complex number, containing amplitude and phase information; The amplitude information is determined by the ratio of the amplitude of the frequency domain component of the junction temperature transient response to the amplitude of the frequency domain component of the electrothermal excitation signal containing multiple frequency components. It reflects the superposition effect of the thermal resistance of each layer in the package heat dissipation path. In the low frequency band, the thermal resistance of the heat dissipation layer far from the chip has a dominant contribution to the amplitude. As the frequency increases, the proportion of the thermal resistance of the layer closer to the chip in the amplitude gradually increases. The phase information is determined by the phase difference between the frequency domain component of the junction temperature transient response and the frequency domain component of the electrothermal excitation signal containing multiple frequency components. It reflects the response hysteresis caused by the thermal capacity of each layer. The thermal capacity of the layer closer to the chip produces significant phase hysteresis in the high frequency band, the thermal capacity of the layer farther from the chip produces phase hysteresis in the low frequency band, and the thermal capacity of the middle layer produces phase hysteresis in the mid frequency band. The variation trends of the amplitude and phase information in different frequency bands together constitute frequency domain features that reflect the spatial distribution differences of the heat dissipation path of the package.

4. The method for identifying the thermal state layering of power semiconductor device packages according to claim 2, characterized in that, The electrothermal excitation signal containing multiple frequency components is a square wave pulse sequence with a constant duty cycle.

5. The method for identifying the thermal state layering of power semiconductor device packages according to claim 4, characterized in that, The frequency range of the electrothermal excitation signal containing multiple frequency components covers at least three orders of magnitude, and multiple frequency points are selected at logarithmic intervals from the low frequency band to the high frequency band. The low-frequency band is sensitive to the thermal parameters of the heat dissipation layer far from the chip, and the thermal impedance spectrum change in the low-frequency band mainly reflects the abnormality of the heat dissipation interface and system-level thermal parameters. The mid-frequency band has a high sensitivity to the thermal parameters of the package intermediate layer, and the change in the thermal impedance spectrum of the mid-frequency band mainly reflects the degradation of the copper frame and the package intermediate layer. The high-frequency band has a high sensitivity to identifying the thermal parameters of the solder layer near the chip, and the change in the thermal impedance spectrum of the high-frequency band mainly reflects the abnormality of the thermal parameters of the chip solder layer.

6. The method for identifying the thermal state layering of power semiconductor device packages according to claim 1, characterized in that, A sensitivity matrix is ​​established between the change in thermal impedance and the increment of local thermal parameters of each layer. A least squares problem with regularization constraints is solved to separate the increment of local thermal parameters of each layer.

7. The method for identifying the thermal state layering of power semiconductor device packages according to claim 6, characterized in that, The regularization constraint is a smoothness constraint; The smoothness constraint introduces a continuity penalty term between the local thermal parameter increments of adjacent layers when solving the least squares problem with regularization constraints. The continuity penalty term imposes a constraint on the difference of thermal parameter increments of adjacent layers in the package heat dissipation path, requiring the difference to meet the smooth transition condition rather than abrupt jump, so as to suppress the influence of measurement noise on the inversion results and improve the identification accuracy of local thermal parameter increments of each layer. The smoothness constraint ensures that the increments of local thermal parameters of each separated layer conform to the physical laws of heat conduction, avoiding local abrupt solutions that do not conform to physical meaning, thereby improving the reliability of the layer identification results.

8. The method for identifying the thermal state layering of power semiconductor device packages according to claim 6, characterized in that, The heat dissipation path of the package is discretized into a multi-layer thermal resistance-thermal capacity network to establish the sensitivity matrix.

9. The method for identifying the thermal state layering of power semiconductor device packages according to claim 1, characterized in that, The type of encapsulation defect is determined based on the magnitude of the local thermal parameter increment and the frequency band characteristics of the thermal impedance spectrum. When the local thermal parameter increment of the layer closest to the chip is greater than the preset threshold and the thermal impedance phase lag of the corresponding frequency band is abnormal, it is determined to be a void or delamination defect in that layer. When the local thermal parameter increment of the encapsulation intermediate layer is dominant and the thermal impedance amplitude of the corresponding frequency band jumps, it is determined to be a degradation defect of the encapsulation intermediate layer. When the increase in local thermal parameters at the heat dissipation interface far from the chip dominates, it is determined to be a defect of poor contact at the heat dissipation interface.

10. A device for identifying the thermal state layering of a power semiconductor device package, characterized in that, include: The excitation application module is configured to apply an electrothermal excitation signal containing multiple frequency components to the power semiconductor device under test; The response acquisition module is configured to acquire the junction temperature transient response of the power semiconductor device under test; The spectrum construction module is configured to construct a thermal impedance spectrum reflecting spatial distribution differences based on the electrothermal excitation signal containing multiple frequency components and the junction temperature transient response; The inversion separation module is configured to separate the local thermal parameter increments of each layer in the package heat dissipation path based on the difference between the measured thermal impedance spectrum and the reference thermal impedance spectrum, so as to realize the layered identification of the thermal state of the package.

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