A printed circuit board parallel wiring method, device and computer equipment

Abstract

The application relates to the technical field of electronic design automation, and discloses a printed circuit board parallel wiring method and device and computer equipment. The method is applied to wiring of multiple to-be-wired networks of a printed circuit board. Each to-be-wired network comprises multiple end points. The method comprises the following steps: acquiring end point information of the multiple to-be-wired networks; constructing a conflict graph between the multiple to-be-wired networks based on the end point information, wherein the conflict graph is used to represent a dependency relationship between the to-be-wired networks in a parallel wiring process; dividing the multiple to-be-wired networks into multiple wiring stages with a determined sequence based on the conflict graph and an initial wiring sequence of the multiple to-be-wired networks which is preconfigured; and wiring the multiple to-be-wired networks according to the sequence of the multiple wiring stages. While ensuring wiring efficiency, the wiring stages and the wiring sequence determined based on the conflict graph do not require repeated locking and unlocking operations, effectively avoiding thread blocking caused by the operations, and thus significantly improving overall wiring efficiency.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a method, apparatus, and computer equipment for parallel routing of printed circuit boards. Background Technology

[0002] In the field of EDA (Electronic Design Automation), routing algorithms, as a core component of physical implementation, directly determine the efficiency and quality of chip design and PCB routing. With the continuous expansion of chip scale and increasing design complexity, multi-threaded parallel technology has become the main technical path to improve routing performance. However, in the actual engineering implementation of multi-threaded parallel routing algorithms, constraints from underlying mechanisms such as thread scheduling, resource coordination, and execution consistency lead to many typical bottlenecks that restrict algorithm performance and stability, severely weakening the engineering practicality and horizontal scalability of parallel routing strategies.

[0003] First, when multiple parallel threads concurrently access and modify the global routing resource graph, high-frequency locking and unlocking operations are likely to occur, leading to a large number of thread blockages and waiting, significantly reducing the overall efficiency of parallel routing. Therefore, shared resource conflicts and lock contention become one of the main problems of parallel routing. Second, setting too many or too dense global synchronization points in the parallel execution process can easily disrupt the pipelined and continuous nature of parallel execution, significantly reducing the scalability of the algorithm. Therefore, excessively fine-grained stage synchronization is also one of the main problems of parallel routing. Furthermore, in related technologies, parallel routers are prone to inconsistent output results under different thread scheduling conditions such as hardware environment and runtime, leading to an exponential increase in the complexity of regression testing and functional debugging. This problem is particularly severe for commercial EDA tools with stringent requirements for stability and reproducibility.

[0004] In summary, how to reduce shared resource conflicts and lock contention during EDA parallel routing, how to construct an appropriate synchronization granularity, and how to ensure the consistency of output results under arbitrary operating environments and thread scheduling conditions have become urgent technical problems to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a method, apparatus and computer device for parallel routing of printed circuit boards to solve the technical problems of how to construct an appropriate synchronization granularity and how to ensure the consistency of output results under any operating environment and thread scheduling conditions.

[0006] In a first aspect, the present invention provides a parallel routing method for a printed circuit board, applied to routing multiple networks to be routed on a printed circuit board, each network to be routed including multiple endpoints, the method comprising: Obtain endpoint information for multiple networks to be wired; Based on endpoint information, a conflict graph is constructed between multiple networks to be routed. The conflict graph is used to represent the dependencies between networks to be routed during parallel routing. Based on the conflict diagram and the pre-configured initial routing sequence of multiple networks to be routed, the multiple networks to be routed are divided into multiple routing stages with a defined order. Multiple networks to be wired are wired in sequence according to multiple wiring stages.

[0007] This invention provides a parallel routing method for printed circuit boards. By constructing a conflict graph to characterize the routing dependencies between various networks, and based on the conflict graph and the initial routing order, multiple networks to be routed are divided into multiple routing stages. Multiple networks in each routing stage can be routed in parallel. While ensuring routing efficiency, the routing stages and order determined by the conflict graph eliminate the need for repeated locking and unlocking operations, effectively avoiding thread blocking and significantly improving overall routing efficiency. Furthermore, the determination of the conflict relationships and initial routing order of multiple networks allows for a more reasonable granularity of routing stages compared to the stage synchronization granularity in related technologies. This ensures consistency in the output results of multiple routing operations, effectively improving the adaptability of this invention's routing method to different hardware environments and guaranteeing the stability and reproducibility of the routing process.

[0008] In some alternative implementations, a collision graph is constructed between multiple networks to be cabled, based on endpoint information, including: Based on the endpoint information of each network to be wired, determine the wiring range of the network to be wired; If the routing ranges of two networks to be routed overlap, it is determined that the two networks to be routed have a dependency relationship. In the conflict graph, the dependency relationship is represented by the initial routing order of the two networks to be routed. Among them, the network to be routed with the later initial routing order has a dependency relationship on the network to be routed with the earlier initial routing order. Based on the initial routing order and the dependency determination results among multiple networks to be routed, a conflict graph among multiple networks to be routed is constructed.

[0009] The parallel routing method for printed circuit boards of the present invention constructs a conflict graph by analyzing the overlap of routing ranges between networks to be routed, fully reflecting the dependencies between the networks to be routed, and constructing a conflict graph that can effectively assist in the configuration of routing task strategies, thereby effectively simplifying the complexity of routing.

[0010] In some optional implementations, based on a conflict graph and a pre-configured initial routing order of multiple networks to be routed, the multiple networks to be routed are divided into multiple routing stages with a defined order, including: The network to be routed that has no dependency on any network to be routed in the conflict graph is assigned to the first routing stage, and the dependency on the network to be routed in the first routing stage is deleted from the conflict graph, and the conflict graph is updated. In the updated conflict graph, the networks to be routed that have no dependency on any network to be routed are assigned to the second routing stage, and the dependencies on the networks to be routed in the second routing stage are deleted from the updated conflict graph. The conflict graph is then updated. The process involves dividing the network into multiple routing phases and updating the conflict graph until all networks to be routed are assigned to the appropriate routing phase.

[0011] In some alternative implementations, multiple networks to be routed are routed in sequence according to multiple routing stages, including: Following the sequence from the first routing stage to the last routing stage, after completing the routing operations for all networks to be routed in the current routing stage, the routing operations for the networks to be routed in the next routing stage are initiated.

[0012] In some alternative implementations, multiple networks to be routed are routed in sequence according to multiple routing stages, including: For multiple networks to be routed in the same routing phase, according to the load balancing distribution strategy, the multiple networks to be routed are divided into multiple cores of multiple systems that perform routing operations, and multiple cores route the multiple networks to be routed in parallel in the same routing phase.

[0013] In some optional implementations, based on a load balancing distribution strategy, multiple networks to be cabled are divided among multiple cores of multiple systems performing cabling operations, including: The first-fit algorithm with decreasing utilization is used to assign each network to be routed to the first core that satisfies the current load being below the load threshold, based on the estimated routing time of the network to be routed, thus obtaining the initial allocation result; Based on the initial allocation results, the multiple networks to be wired are sequentially allocated to the core with the lowest current load, according to the ascending order of the initial wiring sequence of the multiple networks to be wired.

[0014] In some alternative implementations, multiple cores perform parallel routing of multiple networks to be routed in the same routing phase, including: For each network to be wired, an iterative congestion negotiation wiring algorithm is used for wiring. On each core, routing tasks are executed using an earliest deadline-first scheduling strategy.

[0015] In some alternative implementations, after routing multiple networks to be routed in sequence according to multiple routing stages, the method further includes: If there are multiple unrouted networks on the printed circuit board that have failed to be routed, then based on the routing results of the multiple unrouted networks in the previous round, the conflict graph is reconstructed, the routing stage is reconfigured, and based on the new routing stage, the multiple unrouted networks are rerouted until all the multiple unrouted networks on the printed circuit board are successfully routed or the routing round reaches the set number of rounds. If all the networks to be routed on the printed circuit board are successfully routed or the number of routing rounds reaches the set number of rounds, then routing is stopped.

[0016] Secondly, the present invention provides a parallel routing apparatus for a printed circuit board, used for routing multiple networks to be routed on a printed circuit board, each network to be routed including multiple endpoints, the apparatus comprising: The information acquisition module is used to acquire endpoint information of multiple networks to be wired; The conflict graph module is used to construct a conflict graph between multiple networks to be routed based on endpoint information. The conflict graph is used to represent the dependencies between networks to be routed during parallel routing. The phase division module is used to divide multiple networks to be routed into multiple routing phases with a defined order based on the conflict diagram and the pre-configured initial routing sequence of multiple networks to be routed. The cabling module is used to cable multiple networks in sequence according to multiple cabling stages.

[0017] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the printed circuit board parallel routing method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a parallel routing method for printed circuit boards according to an embodiment of the present invention. Figure 2 This is a schematic flowchart of another parallel routing method for printed circuit boards according to an embodiment of the present invention; Figure 3 This is a structural block diagram of a parallel wiring device for printed circuit boards according to an embodiment of the present invention; Figure 4This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention proposes a parallel routing method, apparatus, and computer device for printed circuit boards. The parallel routing method of this invention adopts a serial-parallel equivalent multi-core parallel FPGA routing approach, and combines scheduling theory, load balancing algorithm, and multi-core parallel mechanism to achieve an efficient and controllable consistent routing process.

[0022] According to an embodiment of the present invention, a method for parallel routing of printed circuit boards is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0023] This embodiment provides a parallel routing method for printed circuit boards, applied to routing multiple networks to be routed on a printed circuit board, each network including multiple endpoints. Figure 1 This is a flowchart of a parallel routing method for printed circuit boards according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain endpoint information for multiple networks to be wired.

[0024] In some alternative implementations, for printed circuit board (PCB) designs using multi-pin chips with complex functions, such as FPGAs, automatic routing is often used after the schematic design is completed. The routing process involves multiple networks, and there may be issues such as overlapping routing areas between these networks. For example, network A to be routed involves routing between m endpoints, and network B to be routed involves routing between n endpoints. If the smallest region containing the m endpoints of network A intersects with the smallest region containing the n endpoints of network B, then during the routing of networks A and B, it is necessary to avoid routing intersections in the intersecting region. This can be solved by using loops or routing the two networks to different layers.

[0025] Therefore, the cabling process first needs to obtain endpoint information for multiple networks to be cabled. Endpoint information may include endpoint numbers and coordinates.

[0026] Step S102: Based on endpoint information, construct a conflict graph between multiple networks to be routed. The conflict graph is used to characterize the dependencies between networks to be routed during parallel routing.

[0027] For example, in FPGA routing, each net connects multiple pins, and its available routing paths are confined to a minimum bounding box. To ensure no resource conflicts occur during parallel routing, it is necessary to first determine whether there is spatial overlap between any two nets. Nets that do not overlap spatially can be routed in parallel. Nets that overlap spatially are considered to have conflicts and should be avoided in parallel routing.

[0028] Here, we can assume network n i The minimum bounding box is b i = (x i y i w i h i ), that is, network n i The coordinates of the lower left corner are (x i y i ), width is w i The height is h i A collision graph can be represented by G' = (V', E'). Here, V' represents the set of all networks to be routed, and n... i Let n represent the i-th network of V'. j Let V' represent the j-th network in V'. E' represents the dependencies between the networks to be routed, which can be represented by directed edges e. ij This indicates a dependency between the minimum bounding regions of the i-th network and the j-th network. Here, i < j, and i and j are the network numbers of the two networks to be wired. ij This indicates that the routing of the i-th network depends on the routing of the j-th network.

[0029] Step S103: Based on the conflict diagram and the pre-configured initial routing sequence of multiple networks to be routed, the multiple networks to be routed are divided into multiple routing stages with a defined order.

[0030] In some alternative implementations, the initial routing order of the network to be routed can be configured according to actual needs. For example, the initial routing order can be configured to be in ascending order of network number, or the number of endpoints of each network to be routed can be obtained and the initial routing order can be configured to be in descending order of the number of endpoints of the network to be routed.

[0031] Here, networks that have no dependency on any other network in the set of networks to be routed can be assigned to the first routing stage. Then, among the networks to be routed outside the first routing stage, networks that only depend on the networks to be routed in the first routing stage are searched, and these networks are assigned to the second routing stage. Further, among the networks to be routed outside the first and second routing stages, networks that only depend on the networks to be routed in the first and second routing stages are searched, and these networks are assigned to the third routing stage. This process is iterated until all networks to be routed are assigned to the appropriate routing stage.

[0032] Step S104: Routing is performed on multiple networks to be routed in the order of multiple routing stages.

[0033] In some optional implementations, the multiple networks in the first routing stage are independent of each other and also independent of the networks to be routed in other routing stages. Therefore, the multiple networks to be routed in the first routing stage can be routed in parallel. Furthermore, after the routing of the multiple networks to be routed in the first routing stage is completed, the multiple networks in the second routing stage are also independent of the networks to be routed in other routing stages that have not yet been routed. At this point, the multiple networks to be routed in the second routing stage can be routed in parallel. Thus, following the sequence of multiple routing stages, starting from the first routing stage, after completing the parallel routing of the multiple networks to be routed in one routing stage, the parallel routing of the multiple networks to be routed in the next routing stage adjacent to this routing stage is initiated. This continues until the routing of the networks to be routed in all routing stages is completed.

[0034] This invention provides a parallel routing method for printed circuit boards. By constructing a conflict graph to characterize the routing dependencies between various networks, and based on the conflict graph and the initial routing order, multiple networks to be routed are divided into multiple routing stages. Multiple networks in each routing stage can be routed in parallel. While ensuring routing efficiency, the routing stages and order determined by the conflict graph eliminate the need for repeated locking and unlocking operations, effectively avoiding thread blocking and significantly improving overall routing efficiency. Furthermore, the determination of the conflict relationships and initial routing order of multiple networks allows for a more reasonable granularity of routing stages compared to the stage synchronization granularity in related technologies. This ensures consistency in the output results of multiple routing operations, effectively improving the adaptability of this invention's routing method to different hardware environments and guaranteeing the stability and reproducibility of the routing process.

[0035] This embodiment provides a parallel routing method for printed circuit boards, applied to routing multiple networks to be routed on a printed circuit board, each network including multiple endpoints. Figure 2 This is a flowchart of a parallel routing method for printed circuit boards according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain endpoint information for multiple networks to be wired.

[0036] Please refer to the above for details. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0037] Step S202: Based on endpoint information, construct a conflict graph between multiple networks to be routed. The conflict graph is used to characterize the dependencies between networks to be routed during parallel routing.

[0038] In some alternative implementations, step S202 may include: Step S2021: Determine the cabling range of the network to be cabled based on the endpoint information of each network to be cabled.

[0039] Specifically, each network to be routed includes multiple endpoints. Endpoint information can include the coordinates of each endpoint. During the routing process, each network connects multiple endpoints, and its available routing paths are restricted to a minimum bounding area. This minimum bounding area is the routing range of the network to be routed. The minimum bounding area can be determined by the coordinates of the multiple endpoints.

[0040] Step S2022: If the routing ranges of two networks to be routed overlap, it is determined that the two networks to be routed have a dependency relationship. In the conflict graph, the dependency relationship is represented based on the initial routing order of the two networks to be routed. The network to be routed with the later initial routing order has a dependency relationship on the network to be routed with the earlier initial routing order.

[0041] You can refer to this. Figure 1 Step S102 of the illustrated embodiment represents the dependency between two networks to be routed in the form of directed edges, for example, e ij This indicates that the wiring of the i-th network is dependent on the wiring of the j-th network.

[0042] Step S2023: Based on the initial routing sequence and the dependency determination results between multiple networks to be routed, construct a conflict graph between multiple networks to be routed.

[0043] Specifically, overlapping routing ranges between any two networks to be routed indicate a dependency relationship between them. Specifically, the dependency relationship is that the network routed later in the initial routing order depends on the completion of routing by the network routed earlier in the initial routing order. Once the dependencies between any two networks to be routed are determined, a conflict graph can be constructed from these dependencies, containing multiple directed edges. Each node in the conflict graph represents a network to be routed. If a dependency exists between two networks, the network routed earlier in the initial routing order can be used as the starting point, and the network routed later in the initial routing order can be used as the starting and ending point, forming a directed edge. This completes the construction of the conflict graph between multiple networks to be routed.

[0044] The parallel routing method for printed circuit boards of the present invention constructs a conflict graph by analyzing the overlap of routing ranges between networks to be routed, fully reflecting the dependencies between the networks to be routed, and constructing a conflict graph that can effectively assist in the configuration of routing task strategies, thereby effectively simplifying the complexity of routing.

[0045] Please refer to the above for other details. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0046] Step S203: Based on the conflict diagram and the pre-configured initial routing order of multiple networks to be routed, the multiple networks to be routed are divided into multiple routing stages with a defined order.

[0047] In some alternative implementations, step S203 may include: Step S2031: Assign the network to be routed in the conflict graph that has no dependency on any network to be routed to the first routing stage, delete the dependency on the network to be routed in the first routing stage in the conflict graph, and update the conflict graph.

[0048] In some alternative implementations, in order to securely route in parallel on a platform with a multi-core system, all networks to be routed must be divided into several routing stages, within which multiple networks to be routed are independent of each other and can be routed in parallel. The stages are then executed sequentially according to their dependency order.

[0049] Here, a phase scheduling algorithm based on topology sorting can be used. First, the phases are initialized by initializing the wiring phase set M={} and the wiring phase index k=1. The wiring phase index k=1 indicates that the wiring phases can be numbered starting from 1. Next, all nodes with an in-degree of 0 can be found in the conflict graph G' to form the wiring phase p. kIn this context, a node with an in-degree of 0 is a network that has no dependency on any other network to be routed. For example, after initializing and deleting the dependencies of the networks to be routed in the first routing stage in the conflict graph, and setting the routing stage index k=1, all networks to be routed with an in-degree of 0 and no dependency on any other network to be routed are found and assigned to the first routing stage p1.

[0050] Furthermore, nodes in p1 and their outgoing edges in the conflict graph can be deleted, which means deleting all networks in the conflict graph that have been assigned to the first routing stage, and removing the dependencies on the networks in the first routing stage.

[0051] Algorithmically, p1 is added to the wiring stage set M={}, and k is increased by 1.

[0052] Step S2032: In the updated conflict graph, the networks to be routed that have no dependency on any network to be routed are assigned to the second routing stage, and the dependencies on the networks to be routed in the second routing stage are deleted from the updated conflict graph, and the conflict graph is updated.

[0053] Step S2032 can be referred to step S2031 above, and will not be repeated here.

[0054] Step S2033: Sequentially divide multiple routing stages and update the conflict graph until all networks to be routed are assigned to the appropriate routing stages.

[0055] In some alternative implementations, multiple networks to be routed in the set V' of all networks to be routed can be sequentially assigned to the first routing stage p1, the second routing stage p2, ..., the kth routing stage p1. k until V' is empty.

[0056] Based on steps S2031 to S2033 above, during the process of allocating the cabling stages in the stage scheduling of the cabling network, each node and edge of the conflict graph is visited at most once. The time complexity of the algorithm is O(|V'| + |E'|), which effectively improves the efficiency of the stage scheduling algorithm, and the algorithm has theoretical optimality.

[0057] Please refer to the above for other details. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0058] Step S204: Routing is performed on multiple networks to be routed in the order of multiple routing stages.

[0059] In some alternative implementations, step S204 may include: Step a1: Following the order from the first routing stage to the last routing stage, after completing the routing operations for all networks to be routed in the current routing stage, start the routing operations for the networks to be routed in the next routing stage.

[0060] In some alternative implementations, due to the dependency on routing resources, strict serial synchronization between different stages must be ensured. After routing is completed in each stage, the scheduling controller can be notified via message queues such as MPI (Message Passing Interface) to allow the start of the next routing stage. Thus, the synchronization mechanism ensures that the final routing result of all networks to be routed is consistent with the final routing result of a completely serial router, i.e., it satisfies the serial-parallel equivalence requirement.

[0061] In some alternative implementations, step S204 may include: Step b1: For multiple networks to be routed in the same routing phase, according to the load balancing distribution strategy, the multiple networks to be routed are divided into multiple cores of multiple systems that perform routing operations, and the multiple cores route the multiple networks to be routed in the same routing phase in parallel.

[0062] In some alternative implementations, for each routing stage p k The set of networks to be wired is S = {s1,..., s}. a} is partitioned into a multi-core system C={c1, ..., c2} b} on, where s 1、…、 s a These represent the networks to be wired, numbered 1, ..., a, respectively. c1, ..., c b These represent the processor core numbers configured in the hardware environment performing the wiring operation. Here, a two-stage load balancing strategy, LBAP (Load-Balance-Aware Partitioning), can be used.

[0063] In some alternative implementations, step b1 includes: Step b11: Using the first-fit algorithm with decreasing utilization, each network to be routed is assigned to the first core that satisfies the current load being below the load threshold, based on the estimated routing time of the network to be routed, thus obtaining the initial allocation result.

[0064] Specifically, FFDU (First Fit Decreasing Utilization) can be used for initial allocation. The network to be cabled is then allocated according to the estimated cabling time r. iThe networks are sorted in descending order. The estimated routing time can be based on the routing time of the previous round, or it can be determined based on at least one of the number of endpoints and the minimum enclosing area size of the network. Furthermore, they are allocated sequentially according to the First Fit algorithm. Each network s... i Assign to the first core that meets the requirement that the current load does not exceed the core load threshold. j .

[0065] If all networks to be wired are allocated to meet the total load If so, it is determined that it can be scheduled.

[0066] Among them, core utilization rate k i =r i / d i r i This represents the estimated cabling time for the network to be cabled, d. i The preset duration is indicated by n, the number of networks to be wired is indicated by n, and the number of processor cores is indicated by b.

[0067] Step b12: Based on the initial allocation results, the multiple networks to be routed are sequentially allocated to the core with the lowest current load in ascending order of their initial routing sequence.

[0068] In some alternative implementations, WFIU (Worst Fit Increasing Utilization) can be used to redistribute and optimize the initial allocation results.

[0069] Specifically, based on the initial allocation results, the network to be routed is reordered in ascending order of the initial routing sequence, and the network to be routed is sequentially allocated to the core with the lowest current load to reduce the standard deviation of the core load. This effectively reduces the load imbalance among multiple cores.

[0070] The standard deviation of the core load here is: ; in, The standard deviation of core load is represented by b, where b represents the number of processor cores, and k represents the number of cores. i Let μ be the core utilization of core i, and μ be the average value. The reallocation in step b12 continues until... It will not descend further.

[0071] This ensures the schedulability of cabling across multiple cores while maximizing core utilization efficiency.

[0072] In some alternative implementations, step b1, "parallel routing of multiple networks to be routed in the same routing phase by multiple cores," may include: Step b13: For each network to be routed, the iterative congestion negotiation routing algorithm is used to perform routing.

[0073] Specifically, for each network to be routed, the core uses the classic Pathfinder (Iterative Congestion Negotiation Route Algorithm) to route the network. After completing the routing of the current network to be routed, the routing resource status is updated and fed back to the stage controller.

[0074] If there are issues such as resource conflicts or unreachable paths, and the cabling fails, a rollback operation for the current cabling stage will be triggered, and the cabling for that stage will be retried.

[0075] Step b14: On each core, the routing task is executed using the earliest deadline priority scheduling strategy.

[0076] On each core, routing tasks are executed using the EDF (Earliest Deadline First) scheduling strategy.

[0077] Please refer to the above for other details of step S204. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0078] Step S205: If there are multiple unrouted networks on the printed circuit board that have failed to be routed, then based on the routing results of the multiple unrouted networks in the previous round, the conflict graph is reconstructed, the routing stage is reconfigured, and based on the new routing stage, the multiple unrouted networks are rerouted until all multiple unrouted networks on the printed circuit board are successfully routed or the routing round reaches the set round.

[0079] Specifically, during the routing process, although the dependencies between multiple networks to be routed have been fully considered and a conflict graph based on the dependencies between multiple networks to be routed has been constructed, there are still many factors that affect the routing results in the actual routing process, and there are still problems such as routing failure at a certain routing stage. This invention adopts a negotiation-based Rip-up and Reroute algorithm to resolve local conflicts through multiple rounds of iterative routing.

[0080] Specifically, based on the routing results of multiple networks to be routed in the previous round, the above steps S201 to S204 can be re-executed to rebuild the conflict graph, reconfigure the routing phase, and reroute multiple networks to be routed based on the new routing phase.

[0081] In each round of routing, the conflict graph needs to be reconstructed, phase scheduling needs to be performed, LBAP and in-core EDF scheduling strategies need to be reused for phase routing, and unroutable networks need to be identified and marked as retry targets for the next round to achieve conflict detection and resource rollback.

[0082] Step S206: If all the multiple networks to be routed on the printed circuit board are successfully routed or the number of routing rounds reaches the set number of rounds, then the routing is stopped.

[0083] If all the networks to be routed on the printed circuit board are successfully routed, routing can be stopped and the current routing result can be used.

[0084] If the routing rounds reach the set number, there may be design problems such as schematic errors or other non-routing issues such as incorrect component selection. In such cases, there is no need to continue routing, and a routing failure message can be returned.

[0085] Therefore, the entire process is highly modular and scalable, making it easy to deploy on FPGA designs and platforms of different scales.

[0086] Furthermore, to improve routing efficiency while maintaining serial-parallel equivalence, this invention introduces a feedback-guided scheduling (FGS) mechanism based on historical routing information. This is a dynamic stage reconfiguration mechanism that dynamically adjusts the routing stage and priority of each network to be routed by analyzing the routing performance of each network in previous iterations, thereby improving the parallel efficiency and scheduling flexibility within the routing stage.

[0087] Specifically, firstly, during each round of cabling, the system will collect the following operational feedback metrics from all networks involved in the cabling: Routing Time: Records network n i CPU time from startup to wiring completion; Path Failures: The number of times the network was canceled and retried due to collisions during the Rip-up & Reroute process; History Retry Count: The cumulative number of times the network has been retried or had its cabling delayed in the past few rounds; Path length change rate (ΔLength): Records the trend of path length change in recent iterations to determine whether it has entered a stable convergence state.

[0088] All the above indicators will be smoothed using a sliding window or exponentially weighted average to avoid single-round fluctuations causing the feedback mechanism to overreact to the data indicators.

[0089] This invention employs a dynamic stage reconstruction algorithm. Using the aforementioned metrics, the scheduler optimizes and adjusts the current stage division. Specifically, the following basic decision rules can be adopted: If the number of path failures in the network to be cabled exceeds the failure threshold, it will be moved to the next stage to avoid further interference with the cabling of other networks in the current stage. The failure threshold can be set according to actual needs. For example, the failure threshold can be set to 3 times. If the routing time of a network to be routed is significantly higher than the average routing time of all networks in the routing stage to which it belongs—for example, if the routing time of a network to be routed is more than twice the average routing time of all networks in the routing stage to which it belongs—the scheduler may attempt to advance the routing of that network to a previous stage. It should be noted that advancing the routing stage of any network to be routed must not introduce dependency conflicts. If the path length change rate ΔLength of the network to be routed fluctuates drastically in multiple iterations, it indicates that the path of the network to be routed is unstable. In this case, the cost factor of the route can be increased to encourage the network to avoid the path of the high-congestion area. The illustrative pseudocode is as follows: for net in current_stage: if net.failure_count>threshold: delay_to_next_stage(net) elif net.runtime>avg_runtime * 2: promote_to_earlier_stage(net) elif net.Δlength_var>var_threshold: adjust_routing_cost(net) The adjusted cabling phase will update the topology sorting based on the original conflict graph to ensure that the scheduling order is valid.

[0090] Therefore, the present invention adopts the above-mentioned feedback mechanism, which takes into account the scheduling flexibility and convergence efficiency of multiple networks to be routed. Without sacrificing the consistency of parallel and serial routing results, it effectively reduces the impact of high failure networks to be routed on the progress of the entire routing stage. This feedback mechanism is the key enhancement scheme of the serial-parallel equivalent model of the present invention.

[0091] Meanwhile, to ensure serial-to-parallel equivalence and maintain consistency between parallel routing results and serial routers, the feedback mechanism of this invention only allows inter-stage adjustments without introducing new scheduling dependencies. After stage adjustments, the system re-verifies the conflict graph to ensure that all migration operations do not violate the constraints of dependencies in the original conflict graph, thereby fully preserving serial-to-parallel equivalence.

[0092] This invention, based on the existing serial-parallel equivalent parallel routing architecture, introduces a strict dependency verification mechanism in dynamic scheduling adjustments to ensure that the results are completely consistent with serial routing. This facilitates regression verification and fault reproduction in engineering deployment, thereby maintaining serial-parallel equivalence and enhancing routing repeatability. Furthermore, through a feedback mechanism, it proactively identifies high-failure and high-time-consuming networks, relocating them from the current parallel stage. This avoids single-point bottlenecks affecting the overall concurrency progress, significantly reducing synchronization blocking time and effectively improving the parallel efficiency and convergence speed of the routing stage. Further, through feedback indicators such as path failure count and path volatility, this mechanism achieves early detection and dynamic adjustment of high-risk networks, reducing the probability of conflict rollback and adaptive scheduling to reduce resource contention conflicts. Compared to static stage scheduling methods, the feedback mechanism effectively improves the system's adaptability to uncertainties such as congestion distribution and uneven network complexity, exhibiting stronger controllability in complex designs. This gives the printed circuit board parallel routing method of this invention algorithm-level robustness and stability improvement. Furthermore, the feedback mechanism, as an enhancement to the scheduler module, can be embedded into existing parallel routing processes without affecting the main structure of the routing engine, preserving platform compatibility and modular implementation capabilities. This makes the parallel routing method for printed circuit boards of the present invention highly portable in engineering and valuable for industrial applications.

[0093] This embodiment also provides a parallel routing device for printed circuit boards, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0094] This embodiment provides a parallel routing device for printed circuit boards, used for routing multiple networks to be routed on a printed circuit board. Each network to be routed includes multiple endpoints, such as... Figure 3 As shown, it includes: The information acquisition module 301 is used to acquire endpoint information of multiple networks to be wired; The conflict graph module 302 is used to construct a conflict graph between multiple networks to be routed based on endpoint information. The conflict graph is used to characterize the dependencies between networks to be routed during parallel routing. The phase division module 303 is used to divide multiple networks to be routed into multiple routing phases with a defined order based on the conflict diagram and the initial routing sequence of multiple networks to be routed in a pre-configured manner. The cabling module 304 is used to cable multiple networks to be cabled in sequence according to multiple cabling stages.

[0095] In some alternative implementations, the collision graph module 302 includes: The range determination unit is used to determine the cabling range of the network to be cabled based on the endpoint information of each network to be cabled. The dependency determination unit is used to determine that there is a dependency relationship between two networks to be routed if the routing ranges of the two networks to be routed overlap. In the conflict graph, the dependency relationship is represented based on the initial routing order of the two networks to be routed. The network to be routed with the later initial routing order has a dependency relationship on the network to be routed with the earlier initial routing order. The conflict construction unit is used to construct a conflict graph between multiple networks to be routed, based on the initial routing order and the dependency determination results between multiple networks to be routed.

[0096] In some optional implementations, the phase division module 303 includes: The initial stage unit is used to assign the networks to be routed that have no dependency on any network to be routed in the conflict graph to the first routing stage, delete the dependencies on the networks to be routed in the first routing stage in the conflict graph, and update the conflict graph. The update phase unit is used to assign the networks to be routed that have no dependency on any network to be routed in the updated conflict graph to the second routing phase, and delete the dependencies on the networks to be routed in the second routing phase in the updated conflict graph, and update the conflict graph. The iterative update unit is used to sequentially divide multiple routing stages and update the conflict graph until all networks to be routed are divided into the appropriate routing stages.

[0097] In some alternative implementations, the wiring module 304 includes: The stage control unit is used to initiate the routing operation of the network to be routed in the next routing stage after completing the routing operation of all networks to be routed in the current routing stage, in the order from the first routing stage to the last routing stage.

[0098] In some alternative implementations, the stage control unit includes: The load balancing strategy subunit is used to divide multiple networks to be routed in the same routing phase into multiple cores of multiple systems that perform routing operations, based on a load balancing allocation strategy. The multiple cores then route the multiple networks to be routed in the same routing phase in parallel.

[0099] In some optional implementations, the load balancing strategy subunit divides multiple networks to be cabled into multiple cores of multiple systems performing cabling operations according to a load balancing allocation strategy, including: The first-fit algorithm with decreasing utilization is used to assign each network to be routed to the first core that satisfies the current load being below the load threshold, based on the estimated routing time of the network to be routed, thus obtaining the initial allocation result; Based on the initial allocation results, the multiple networks to be wired are sequentially allocated to the core with the lowest current load, according to the ascending order of the initial wiring sequence of the multiple networks to be wired.

[0100] In some optional implementations, the load balancing strategy subunit consists of multiple cores routing multiple networks to be routed in parallel during the same routing phase, including: For each network to be wired, an iterative congestion negotiation wiring algorithm is used for wiring. On each core, routing tasks are executed using an earliest deadline-first scheduling strategy.

[0101] In some alternative embodiments, the apparatus further includes: The rerouting module is used to reconstruct the conflict graph and reconfigure the routing stages after routing multiple networks to be routed in the order of multiple routing stages. If there are any networks to be routed that failed to be routed on the printed circuit board, the module will reroute the network to be routed based on the routing results of the previous round, and reroute the network to be routed based on the new routing stages until all networks to be routed on the printed circuit board are successfully routed or the routing round reaches the set number of rounds. The stop routing module is used to stop routing if multiple networks to be routed on the printed circuit board are successfully routed or the routing rounds reach a set number of rounds.

[0102] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0103] In this embodiment, the printed circuit board parallel routing device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0104] This invention also provides a computer device having the above-described features. Figure 4 The printed circuit board parallel wiring device shown.

[0105] Please see Figure 4 , Figure 4This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.

[0106] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0107] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0108] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0109] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0110] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0111] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0112] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0113] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended technical solutions.

Claims

1. A method for parallel routing on a printed circuit board, characterized in that, The method is applied to routing multiple networks to be routed on the printed circuit board, each of the networks to be routed including multiple endpoints, and includes: Obtain endpoint information for multiple networks to be wired; Based on the endpoint information, a conflict graph is constructed between multiple networks to be routed. The conflict graph is used to characterize the dependencies between the networks to be routed during parallel routing. Based on the conflict diagram and the pre-configured initial routing order of the multiple networks to be routed, the multiple networks to be routed are divided into multiple routing stages with a defined order; Multiple networks to be wired are wired in sequence according to the multiple wiring stages described above.

2. The method according to claim 1, characterized in that, The step of constructing a conflict graph among multiple networks to be cabled based on the endpoint information includes: The cabling range of each network to be cabled is determined based on the endpoint information of each network to be cabled. If the routing ranges of two networks to be routed overlap, it is determined that the two networks to be routed have a dependency relationship. The dependency relationship is represented in the conflict graph based on the initial routing order of the two networks to be routed, wherein the network to be routed with a later initial routing order has a dependency relationship on the network to be routed with a earlier initial routing order. Based on the initial routing order and the dependency determination results between multiple networks to be routed, a conflict graph is constructed between the multiple networks to be routed.

3. The method according to claim 1, characterized in that, The method, based on the conflict diagram and a pre-configured initial routing order of the multiple networks to be routed, divides the multiple networks to be routed into multiple routing stages with a defined order, including: The network to be routed that has no dependency on any network to be routed in the conflict graph is assigned to the first routing stage, and the dependency on the network to be routed in the first routing stage in the conflict graph is deleted, and the conflict graph is updated. In the updated conflict graph, the networks to be routed that have no dependency on any network to be routed are assigned to the second routing stage, and the dependencies on the networks to be routed in the second routing stage are deleted from the updated conflict graph, and the conflict graph is updated. The process involves dividing the network into multiple routing phases and updating the conflict graph until all networks to be routed are assigned to the appropriate routing phase.

4. The method according to claim 1, characterized in that, The step of routing multiple networks to be routed in sequence according to the multiple routing stages includes: Following the sequence from the first routing stage to the last routing stage, after completing the routing operations for all networks to be routed in the current routing stage, the routing operations for the networks to be routed in the next routing stage are initiated.

5. The method according to claim 1, characterized in that, The step of routing multiple networks to be routed in sequence according to the multiple routing stages includes: For multiple networks to be routed in the same routing phase, according to the load balancing distribution strategy, the multiple networks to be routed are divided into multiple cores of multiple systems that perform routing operations, and multiple cores route the multiple networks to be routed in parallel in the same routing phase.

6. The method according to claim 5, characterized in that, The step of dividing the multiple networks to be cabled into multiple cores of multiple systems performing cabling operations according to a load balancing allocation strategy includes: The first-fit algorithm with decreasing utilization is used to assign each network to be routed to the first core that satisfies the current load being below the load threshold, based on the estimated routing time of the network to be routed, thus obtaining the initial allocation result; Based on the initial allocation results, the multiple networks to be wired are sequentially allocated to the core with the lowest current load, according to the ascending order of the initial wiring sequence of the multiple networks to be wired.

7. The method according to claim 5, characterized in that, Parallel routing of multiple networks to be routed in the same routing phase by multiple cores, including: For each network to be wired, an iterative congestion negotiation wiring algorithm is used for wiring. On each core, routing tasks are executed using an earliest deadline-first scheduling strategy.

8. The method according to claim 1, characterized in that, After routing the multiple networks to be routed in the order of the multiple routing stages, the method further includes: If there are multiple networks to be routed on the printed circuit board that have failed to be routed, then based on the routing results of the multiple networks to be routed in the previous round, the conflict graph is reconstructed, the routing stage is reconfigured, and based on the new routing stage, the multiple networks to be routed are rerouted until all the multiple networks to be routed on the printed circuit board are successfully routed or the routing round reaches the set number of rounds. If all the multiple networks to be routed on the printed circuit board are successfully routed or the number of routing rounds reaches the set number of rounds, then the routing is stopped.

9. A parallel wiring device for printed circuit boards, characterized in that, An apparatus for routing multiple networks to be routed on a printed circuit board, each network to be routed including multiple endpoints, the apparatus comprising: An information acquisition module is used to acquire endpoint information of multiple networks to be wired; The conflict graph module is used to construct a conflict graph between multiple networks to be routed based on the endpoint information. The conflict graph is used to characterize the dependencies between the networks to be routed during parallel routing. The phase division module is used to divide the multiple networks to be routed into multiple routing phases with a defined order based on the conflict diagram and the pre-configured initial routing order of the multiple networks to be routed; The cabling module is used to cable multiple networks to be cabled in sequence according to the multiple cabling stages.

10. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the printed circuit board parallel routing method according to any one of claims 1 to 8.

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