Display panel and display device

Abstract

The application relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a pixel circuit, a signal line, a first reset signal line, a second reset signal line, a third reset signal line, a first bias signal line and a second bias signal line. The pixel circuit comprises a first reset transistor, a second reset transistor and a bias transistor. The first reset signal line and the second reset signal line are electrically connected with the first reset transistor respectively. The third reset signal line is electrically connected with the second reset transistor. The first bias signal line and the second bias signal line are electrically connected with the bias transistor respectively. The first reset signal line, the third reset signal line and the first bias signal line continuously extend along a first direction and are arranged along a second direction. The first direction intersects with the second direction. The second reset signal line and the second bias signal line continuously extend along the second direction and are arranged along the first direction. The application can improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display panels have been widely used in people's production and daily life. To better meet people's needs, adjustments can be made to the display panel, such as adjusting some of the wiring, thereby improving the overall effect of the display panel. Summary of the Invention

[0003] This application provides a display panel and display device that can realize a grid design of signal lines, thereby reducing the impedance of the signal lines, thereby reducing the voltage drop of the signal lines and improving the uniformity of the display.

[0004] In a first aspect, embodiments of this application provide a display panel, including:

[0005] The pixel circuit includes a first reset transistor, a second reset transistor, and a bias transistor;

[0006] The signal lines include a first reset signal line and a second reset signal line electrically connected to the first reset transistor, a third reset signal line electrically connected to the second reset transistor, and a first bias signal line and a second bias signal line electrically connected to the bias transistor.

[0007] The first reset signal line, the third reset signal line, and the first bias signal line extend continuously along a first direction and are arranged along a second direction; the first direction intersects the second direction.

[0008] The second reset signal line and the second bias signal line extend continuously along the second direction and are arranged along the first direction, respectively.

[0009] Secondly, embodiments of this application also provide a display device, which includes the display panel provided in the first aspect.

[0010] The display panel and display device provided in this application embodiment provide a first reset signal to the first reset transistor in the pixel circuit through a first signal line, thereby supporting the display of the display panel. Furthermore, by providing a first reset signal line extending along a first direction and arranged along a second direction, and a second reset signal line extending along the second direction and arranged along the first direction, the first and second reset signal lines form a grid structure. In addition, by making the first reset signal line continuous in the first direction and the second reset signal line continuous in the second direction, a full-screen grid structure can be formed, which can reduce the overall impedance of the first signal line, thereby reducing the power consumption of the first signal line and improving the signal transmission stability of the first signal line, which is beneficial to improving the display uniformity and other display effects of the display panel. Similarly, by setting bias signal lines to provide bias signals to the bias transistors in the pixel circuit, support is provided for the display panel's display. Furthermore, by setting the bias signal lines to include a first bias signal line extending along a first direction and arranged along a second direction, and a second bias signal line extending along the second direction and arranged along the first direction, the first and second bias signal lines form a grid structure. Moreover, by setting the first bias signal line to be continuous in the first direction and the second bias signal line to be continuous in the second direction, a full-screen grid structure can be formed, reducing the overall impedance of the first signal line, thereby reducing the power consumption of the bias signal line and improving the signal transmission stability of the bias signal line, which is beneficial for improving the display uniformity and other display effects of the display panel. Additionally, by setting a third reset signal line to provide a second reset signal to the second reset transistor in the pixel circuit, support is provided for the display panel's display. Furthermore, by setting the third reset signal line to extend continuously along the first direction and arranged along the second direction, the occupation of signal lines in the first direction can be reduced while ensuring the display function of the display panel, which helps to achieve miniaturization of the display panel design. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment;

[0012] Figure 2 A schematic diagram of a pixel circuit and a light-emitting element provided in one embodiment;

[0013] Figure 3 This is a schematic diagram of the film layer structure of a display panel provided in one embodiment;

[0014] Figure 4 This is a schematic diagram of the layout structure of a display panel provided in one embodiment;

[0015] Figure 5 for Figure 4 The diagram shows a schematic diagram of the layout structure of the first semiconductor layer in the display panel.

[0016] Figure 6 for Figure 4 The diagram shows the layout structure of the first conductive layer in the display panel.

[0017] Figure 7 for Figure 4 The diagram shows a schematic diagram of the layout structure of the first sub-gate conductive layer in the display panel.

[0018] Figure 8 for Figure 4 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0019] Figure 9 for Figure 4 The diagram shows a schematic diagram of the layout structure of the second sub-gate conductive layer in the display panel.

[0020] Figure 10 for Figure 4 The diagram shows the layout structure of the second conductive layer in the display panel.

[0021] Figure 11 A schematic diagram of the layout structure of a display panel provided for another embodiment;

[0022] Figure 12 for Figure 11 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0023] Figure 13 A schematic diagram of the layout structure of a display panel provided in yet another embodiment;

[0024] Figure 14 for Figure 13 The diagram shows the layout structure of the first conductive layer in the display panel.

[0025] Figure 15 for Figure 13 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0026] Figure 16 A schematic diagram of the layout structure of a display panel provided in another embodiment;

[0027] Figure 17 for Figure 16 The diagram shows the layout structure of the first conductive layer in the display panel.

[0028] Figure 18 A schematic diagram of the layout structure of a display panel provided for another embodiment;

[0029] Figure 19 A schematic diagram of the layout structure of a display panel provided in yet another embodiment;

[0030] Figure 20 for Figure 19 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0031] Figure 21 for Figure 19 The diagram shows the layout structure of the second conductive layer in the display panel.

[0032] Figure 22 A schematic diagram of the layout structure of a display panel provided in another embodiment;

[0033] Figure 23 A schematic diagram of the layout structure of a display panel provided for another embodiment;

[0034] Figure 24 A schematic diagram of the layout structure of a display panel provided in yet another embodiment;

[0035] Figure 25 for Figure 24 The diagram shows a schematic diagram of the layout structure of the first semiconductor layer in the display panel.

[0036] Figure 26 for Figure 24 The diagram shows the layout structure of the first conductive layer in the display panel.

[0037] Figure 27 for Figure 24 The diagram shows a schematic diagram of the layout structure of the first sub-gate conductive layer in the display panel.

[0038] Figure 28 for Figure 24 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0039] Figure 29 for Figure 24 The diagram shows a schematic diagram of the layout structure of the second sub-gate conductive layer in the display panel.

[0040] Figure 30 for Figure 24 The diagram shows the layout structure of the second conductive layer in the display panel.

[0041] Figure 31 A schematic diagram of the layout structure of a display panel provided in another embodiment;

[0042] Figure 32 for Figure 31 The diagram shows the layout structure of the first conductive layer in the display panel.

[0043] Figure 33 for Figure 31 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0044] Figure 34 A schematic diagram of the layout structure of a display panel provided for another embodiment;

[0045] Figure 35 for Figure 34 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0046] Figure 36 for Figure 34 The diagram shows the layout structure of the second conductive layer in the display panel.

[0047] Figure 37 A schematic diagram of the layout structure of a display panel provided in yet another embodiment;

[0048] Figure 38 for Figure 37 The diagram shows a schematic diagram of the layout structure of the second semiconductor layer in the display panel.

[0049] Figure 39 for Figure 37 The diagram shows the layout structure of the second conductive layer in the display panel.

[0050] Figure 40 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0054] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0055] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0056] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0057] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0058] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0059] This application provides a display panel and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0060] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of the pixel circuit 10 and the light-emitting element provided in the embodiments of this application. Figure 3 This is a schematic diagram of the film layer structure of the display panel provided in the embodiments of this application. Figures 4 to 39 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of this application. Wherein, Figures 4 to 23 This application provides a schematic diagram of a layout structure in which pixel circuits in a display panel are arranged in a mirror image. Figures 5 to 10 They are respectively Figure 4 The diagram shows a layout structure of the first semiconductor layer, the first conductive layer, the first sub-gate conductive layer, the second semiconductor layer, the second sub-gate conductive layer, and the second conductive layer in the display panel. Figure 12 for Figure 11The diagram shows a schematic of the layout structure of the second semiconductor layer in the display panel. Figure 14 and Figure 15 They are respectively Figure 13 The diagram shows a schematic layout of the first conductive layer and the second semiconductor layer in the display panel. Figure 17 for Figure 16 The diagram shows a schematic of the layout structure of the second semiconductor layer in the display panel. Figure 20 and Figure 21 They are respectively Figure 19 The diagram shows a schematic layout of the second semiconductor layer and the second conductive layer in the display panel. Figures 24 to 39 This is a schematic diagram of a layout structure for a display panel in which the pixel circuit adopts a non-mirror design, as provided in an embodiment of this application. Figures 25 to 30 They are respectively Figure 24 The diagram shows a layout structure of the first semiconductor layer, the first conductive layer, the first sub-gate conductive layer, the second semiconductor layer, the second sub-gate conductive layer, and the second conductive layer in the display panel. Figure 33 and Figure 32 They are respectively Figure 31 The diagram shows a schematic layout of the first conductive layer and the second semiconductor layer in the display panel. Figure 35 and Figure 36 They are respectively Figure 34 The diagram shows a schematic layout of the second semiconductor layer and the second conductive layer in the display panel. Figure 39 and Figure 38 They are respectively Figure 37 The diagram shows a schematic layout of the second semiconductor layer and the second conductive layer in the display panel.

[0061] like Figure 1 and Figure 2 As shown, in some embodiments, a display panel is provided, which includes pixel circuitry 10 and signal lines. Pixel circuitry 10 includes a first reset transistor, a second reset transistor, and a bias transistor T8. Signal lines include a first reset signal line 211 and a second reset signal line 212 electrically connected to the first reset transistor, a third reset signal line 221 electrically connected to the second reset transistor, and a first bias signal line 231 and a second bias signal line 232 electrically connected to the bias transistor T8. The first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 extend continuously along a first direction and are arranged along a second direction. The second reset signal line 212 and the second bias signal line 232 extend continuously along the second direction and are arranged along the first direction. The first direction intersects the second direction.

[0062] For ease of explanation, in this embodiment, the first reset signal line 211, the second reset signal line 212, and the third reset signal line 221 are collectively referred to as reset signal lines. Each reset signal line may include the first signal line 21 and the third reset signal line 221. The first signal line 21 may include the electrically connected first reset signal line 211 and the second reset signal line 212. Furthermore, the first reset signal line 211 and the second reset signal line 212 are respectively insulated from the third reset signal line 221.

[0063] like Figure 1 As shown, in some embodiments, there can be multiple first reset signal lines 211, second reset signal lines 212, and third reset signal lines 221. The multiple first reset signal lines 211 and multiple third reset signal lines 221 can extend continuously along a first direction and be arranged along a second direction, respectively. The multiple second reset signal lines 212 can extend continuously along the second direction and be arranged along the first direction, respectively. There can be multiple intersection points between the multiple first reset signal lines 211 and multiple second reset signal lines 212. The first reset signal lines 211 and second reset signal lines 212 can be electrically connected at at least some of their intersection points. Each first reset signal line 211 can be electrically connected to at least one second reset signal line 212, and each second reset signal line 212 can be electrically connected to at least one first reset signal line 211.

[0064] For ease of explanation, in this embodiment, the first bias signal line 231 and the second bias signal line 232 are collectively referred to as bias signal line 23. That is, bias signal line 23 includes the electrically connected first bias signal line 231 and second bias signal line 232. The bias signal line 23 is insulated from the reset signal line; specifically, the first bias signal line 231 is insulated from the first reset signal line 211, the second reset signal line 212, and the third reset signal line 221, and the second bias signal line 232 is insulated from the first reset signal line 211, the second reset signal line 212, and the third reset signal line 221, respectively.

[0065] like Figure 1As shown, in some embodiments, there can be multiple first bias signal lines 231 and second bias signal lines 232. The multiple first bias signal lines 231 can extend continuously along a first direction and be arranged along a second direction, and the multiple second bias signal lines 232 can extend continuously along the second direction and be arranged along the first direction. There can be multiple intersection points between the multiple first bias signal lines 231 and the multiple second bias signal lines 232, and the first bias signal lines 231 and the second bias signal lines 232 can be electrically connected at at least some of their intersection points. Each first bias signal line 231 can be electrically connected to at least one second bias signal line 232, and each second bias signal line 232 can be electrically connected to at least one first bias signal line 231.

[0066] The continuous extension of a signal line along a first direction can be understood as the signal line extending along the first direction and being continuous in the first direction. Similarly, the continuous extension of a signal line along a second direction can be understood as the signal line extending along the second direction and being continuous in the second direction. Specifically, the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 are continuous in the first direction, and the second reset signal line 212 and the second bias signal line 232 are continuous in the second direction.

[0067] In some embodiments, the first direction is perpendicular to the second direction. For example, with Figure 1 As shown, the first direction can be the column direction or the Y-axis direction, and the second direction can be the row direction or the X-axis direction. In some embodiments, the angle between the first direction and the second direction can be greater than 0 and less than 90 degrees.

[0068] Understandably, the signal lines are used to provide voltage and / or current signals to the pixel circuit 10. The pixel circuit 10 can be electrically connected to the light-emitting element D in the display panel, and the pixel circuit 10 can be used to drive the light-emitting element D to emit light, thereby causing the display panel to display. In some embodiments, the display panel includes an array of pixel circuits 10 and light-emitting elements D, and the pixel circuit 10 drives the corresponding light-emitting element D to emit light according to a target brightness, so that the display panel displays a target image.

[0069] The first signal line 21 is electrically connected to the first terminal of the first reset transistor in the pixel circuit 10 and is used to provide a first reset signal. The third reset signal line 221 is electrically connected to the first terminal of the second reset transistor in the pixel circuit 10 and is used to provide a second reset signal. The bias signal line 23 is electrically connected to the second terminal of the bias transistor T8 in the pixel circuit 10 and is used to provide a bias signal DVH.

[0070] like Figure 2As shown, in some embodiments, one of the first reset transistor and the second reset transistor can be the gate reset transistor T5 in the pixel circuit 10, and the other can be the anode reset transistor T7 in the pixel circuit 10. The gate reset transistor T5 is used to reset the gate 101 of the driving transistor T3 in the pixel circuit 10, and the anode reset transistor T7 is used to reset the anode RE of the light-emitting element D in the pixel circuit 10. For ease of understanding, this application uses the gate reset transistor T5 as the first reset transistor and the anode reset transistor T7 as the second reset transistor, that is, the first reset signal line 211 and the second reset signal line 212 provide the first reset signal VREF2 for the gate reset transistor T5, and the third reset signal line 221 provides the second reset signal VREF1 for the anode reset transistor T7 as an example for illustration.

[0071] like Figure 2 As shown, in some embodiments, the pixel circuit 10 includes a driving transistor T3, an anode reset transistor T7, a gate reset transistor T5, and a bias transistor T8. The first terminal of the anode reset transistor T7 is electrically connected to the first reset signal line 211, and the second terminal of the anode reset transistor T7 is electrically connected to the anode RE of the light-emitting element D. The first terminal of the gate reset transistor T5 is electrically connected to the third reset signal line 221, and the second terminal of the gate reset transistor T5 is electrically connected to the gate 101 of the driving transistor T3. The first terminal of the bias transistor T8 is electrically connected to the first terminal of the driving transistor T3, and the second terminal of the bias transistor T8 is electrically connected to the first bias signal line 231. In some embodiments, the pixel circuit 10 further includes a data writing transistor T2, a threshold compensation transistor T4, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a capacitor C. The first terminal of the data writing transistor T2 is electrically connected to the second terminal of the first light-emitting control transistor T1 and the first terminal of the driving transistor T3, respectively. The first terminal of the first light-emitting control transistor T1 is electrically connected to the first terminal of the capacitor C. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the threshold compensation transistor T4 and the second terminal of the driving transistor T3, respectively. The second terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal of the anode reset transistor T7 and the anode RE of the light-emitting element D, respectively. The first terminal of the threshold compensation transistor T4 is electrically connected to the second terminal of the gate reset transistor T5, the gate 101 of the driving transistor T3, and the second terminal of the capacitor C, respectively. One of the first and second terminals of the transistor is the source 103, and the other is the drain 104.

[0072] like Figures 6 to 9As shown, in some embodiments, the signal lines may further include scan signal lines, data signal lines, power signal lines, and light emission control signal lines 25. The scan signal lines may extend continuously along a second direction and be arranged along a first direction. The scan signal lines may include a first scan signal line 241, a second scan signal line 242, a third scan signal line 243, and a fourth scan signal line 244. The power signal lines may include a first power signal line 26 and a second power signal line. The first scan signal line 241 may be electrically connected to the gate 101 of the gate reset transistor T5 and can be used to provide a first scan signal S1N. The second scan signal line 242 may be electrically connected to the gate 101 of the threshold compensation transistor T4 and can be used to provide a second scan signal S2N. The third scan signal line 243 may be electrically connected to the gate 101 of the data write transistor T2 and can be used to provide a third scan signal SP. The fourth scan signal line 244 may be electrically connected to the gate 101 of the anode reset transistor T7 and the gate 101 of the bias transistor T8, respectively, and can be used to provide a fourth scan signal SPX. The first power signal line 26 can be electrically connected to the first electrode of the first light-emitting control transistor T1 and can be used to provide the first power signal PVDD. The second power signal line can be electrically connected to the cathode of the light-emitting element D and can be used to provide the second power signal PVSS. The data signal line can be electrically connected to the second electrode of the data writing transistor T2 and can be used to provide the data signal DATA. The light-emitting control signal line 25 can extend continuously along the second direction and be arranged along the first direction, and can be electrically connected to the gate 101 of the first light-emitting control transistor T1 and the gate 101 of the second light-emitting control transistor T6 respectively, and can be used to provide the light-emitting control signal Emit.

[0073] like Figure 2 and Figure 3 As shown, in some embodiments, the pixel circuit 10 may include multiple thin-film transistors, which may include silicon thin-film transistors 111 and oxide thin-film transistors 112. The silicon thin-film transistors 111 include, but are not limited to, low-temperature polycrystalline silicon (LTPS) thin-film transistors, and the oxide thin-film transistors 112 include, but are not limited to, IGZO (Indium Gallium Zinc Oxide) thin-film transistors. In some embodiments, the threshold compensation transistor T4 and the gate reset transistor T5 may both be oxide transistors, and the driving transistor T3, data writing transistor T2, anode reset transistor T7, first light-emitting control transistor T1, second light-emitting control transistor T6, and bias transistor T8 in the pixel circuit 10 may all be silicon transistors.

[0074] It should be noted that the pixel circuit 10 described above is an example of 8T1C, where T represents a transistor and C represents a capacitor C. The pixel circuit 10 can also have other structures, such as 8T2C, 9T1C, 9T2C, etc., and can be adapted to meet specific requirements.

[0075] The display panel provided in this application embodiment provides a first reset signal VREF2 to the first reset transistor in the pixel circuit 10 through a first signal line 21, thereby supporting the display of the display panel. Furthermore, by providing a first reset signal line 211 extending in a first direction and arranged in a second direction, and a second reset signal line 212 extending in the second direction and arranged in the first direction, the first reset signal line 211 and the second reset signal line 212 form a grid structure. In addition, by making the first reset signal line 211 continuous in the first direction and the second reset signal line 212 continuous in the second direction, a full-screen grid structure can be formed, which can reduce the overall impedance of the first signal line 21, thereby reducing the power consumption of the first signal line 21 and improving the signal transmission stability of the first signal line 21, which is beneficial to improving the display uniformity and other display effects of the display panel. Similarly, by setting the bias signal line 23 to provide a bias signal DVH to the bias transistor T8 in the pixel circuit 10, support is provided for the display of the display panel. Furthermore, by setting the bias signal line 23 to include a first bias signal line 231 extending along a first direction and arranged along a second direction, and a second bias signal line 232 extending along a second direction and arranged along a first direction, the first bias signal line 231 and the second bias signal line 232 form a grid structure. In addition, by setting the first bias signal line 231 to be continuous in the first direction and the second bias signal line 232 to be continuous in the second direction, a full-screen grid structure can be formed, which can reduce the overall impedance of the first signal line 21, thereby reducing the power consumption of the bias signal line 23 and improving the signal transmission stability of the bias signal line 23, which is beneficial to improving the display uniformity and other display effects of the display panel. In addition, by setting the third reset signal line 221 to provide the second reset signal VREF1 to the second reset transistor in the pixel circuit 10, support is provided for the display of the display panel; and by setting the third reset signal line 221 to extend continuously along the first direction and be arranged along the second direction, the occupation of the signal line in the first direction can be reduced while ensuring the display function of the display panel, which helps to realize the miniaturization design of the display panel.

[0076] like Figures 8 to 23As shown, in some embodiments, the display panel includes pixel pairs, each pixel pair including two adjacent pixel circuits 10 arranged along a second direction. The display panel may include multiple pixel pairs arranged in an array, i.e., multiple pixel pairs may be arranged along a first direction and a second direction. Each pixel pair includes an electrode portion 110, which includes a channel layer 102 interconnecting two second reset transistors in the pixel pair. The electrode portion 110 is electrically connected to the first electrode and the third reset signal line 221 of the two second reset transistors in the pixel pair, respectively. The electrode portion 110 can be understood as an integrated structure of the channel layer 102 of the two second reset transistors in the pixel pair. The electrode portion 110 enables a shared connection between the first electrode of the two second reset transistors and the first electrode of the third reset signal line 221. That is, the first electrodes (source 103 or drain 104) of both second reset transistors are electrically connected to the electrode portion 110, thereby enabling the electrical connection between the first electrodes of the two second reset transistors and the third reset signal line 221 through the electrode portion 110, thus eliminating the need to separately provide a connection line between each second reset transistor and the third reset signal line 221. This design not only simplifies the wiring structure of the pixel circuit 10, reduces the number of signal lines, and lowers the wiring difficulty and manufacturing cost, but also ensures the synchronization of the reset signals received by the two second reset transistors, avoiding inconsistent resets of the two pixel circuits 10 due to signal delay or difference, thereby improving the uniformity of the displayed image.

[0077] like Figure 22 and Figure 23 As shown, in some embodiments, at least one third reset signal line 221 is provided for each two adjacent pixel columns. Each pixel column includes multiple pixel circuits 10 arranged sequentially along a first direction. For example, each two adjacent pixel columns are provided with one third reset signal line 221, and the two adjacent pixel columns are electrically connected to the corresponding third reset signal line 221 via electrode portions 110. Thus, two adjacent columns of pixel circuits 10 can share one third reset signal line 221, reducing the number of third reset signal lines 221 and further increasing the area occupied by the signal line in the second direction, which helps to achieve miniaturization. In another example, at least two third reset signal lines 221 can be provided for each two adjacent pixel columns, for example, two third reset signal lines 221 can be provided for each two adjacent pixel columns, which helps to meet the display panel requirements of high resolution and high signal transmission. In practical applications, the quantity relationship between the third reset signal lines 221 and the pixel columns can be flexibly configured.

[0078] like Figures 4 to 23As shown, in some embodiments, the two second reset transistors in a pixel pair are mirror images of each other along a first direction. The two second reset transistors in the pixel pair are symmetrically distributed with the first direction as the axis of mirror symmetry. For example, in a pixel pair, the gate 101, source 103, and drain 104 of one second reset transistor are oriented in a flipped symmetrical manner with the corresponding electrode orientation of the other second reset transistor along the first direction, and the line connecting the centers of the two transistors is perpendicular to the first direction. This mirror image arrangement optimizes the layout space of the pixel circuit 10, making the transistor arrangement more compact and regular, reducing the area occupied by the pixels, and creating conditions for increasing pixel density. The third reset signal line 221 can be positioned close to the electrode portion 110 of the pixel pair, which helps to achieve electrical connection between the third reset signal line 221 and the electrode portion 110, reducing the layout difficulty between the pixel circuit 10 and the signal line.

[0079] like Figures 4 to 23 As shown, in some embodiments, the two pixel circuits 10 in a pixel pair are mirror images of each other along a first direction, that is, the two pixel circuits 10 are symmetrically distributed with the first direction as the axis of mirror symmetry. The same structure in the two pixel circuits 10 is mirrored along the first direction; that is, the first reset transistor, the second reset transistor, and the bias transistor T8 in one pixel circuit 10 are symmetrically distributed with their corresponding transistors in the other pixel circuit 10. This achieves a regularized layout of the pixel circuits 10, improves the uniformity and process compatibility of the display panel, and reduces wiring crosstalk and signal interference, thus improving the operational stability of the pixel circuits 10. Furthermore, in some embodiments, the pixel circuits 10 arranged along the first direction are arranged in the same manner. That is, each pixel circuit 10 in the display panel can be mirrored along the column direction and arranged in the same manner along the row direction. For ease of description, this application simply refers to this arrangement as a mirrored arrangement. This reduces wiring difficulty and helps to achieve miniaturization and thinning.

[0080] like Figures 24 to 39 As shown, in some embodiments, the pixel circuits 10 arranged along the second direction are arranged in the same manner. Further, in some embodiments, the pixel circuits 10 arranged along the first direction are arranged in the same manner. That is, all pixel circuits 10 in the display panel are arranged in the same manner. This reduces the difficulty of arranging the pixel circuits 10 and improves the uniformity of the display panel.

[0081] like Figure 1 , Figures 4 to 39As shown, in some embodiments, the display panel includes at least one signal line group 200 arranged along a second direction. The signal line group 200 includes at least one first reset signal line 211, at least one third reset signal line 221, and at least one first bias signal line 231 arranged along the second direction. For example, the signal line group 200 includes three signal lines: a first reset signal line 211, a third reset signal line 221, and a first bias signal line 231, each arranged along the second direction. This regular arrangement of the three signal lines in the signal line group 200 simplifies the signal line layout, facilitates modular management of the signal lines, and is convenient for manufacturing processes and signal control. The number of signal lines in the signal line group 200 can be 3, 4, 5, 6, or other values ​​greater than 6. Within the same signal line group 200, the number of the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 can be 1, 2, 3, or other suitable numbers, respectively. The number of various signal lines in the signal line group 200 can be the same or different. Furthermore, the arrangement of signal lines in signal line group 200 can be adaptively adjusted according to factors such as the arrangement of pixel circuit 10 and the number of signal lines. In practice, the number of various signal lines and the arrangement of signal lines in signal line group 200 can be flexibly set according to requirements.

[0082] like Figure 1 , Figures 4 to 39 As shown, in some embodiments, the display panel includes at least one pixel group arranged along a second direction, and the pixel group includes at least three pixel columns arranged sequentially along the second direction. This grouping design enables modular management of the pixel structure, facilitating manufacturing and signal control. Each signal line group 200 corresponds to one pixel group. That is, one pixel group corresponds to one signal line group 200, meaning the number of pixel columns in the pixel group is the same as the number of signal lines in the signal line group 200. For example, the number of pixel columns in the pixel group and the number of signal lines in the signal line group 200 are both 3, 4, 5, 6, or other values ​​greater than 6. Thus, one set of signal lines can drive one pixel group, enabling precise zoning control of signals, avoiding signal crosstalk between different pixel groups, and improving display performance. Any signal line in the signal line group 200 corresponds to one pixel column. That is, one pixel column corresponds to one signal line. For example, the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 are respectively positioned close to their corresponding pixel columns. With such a pixel column arrangement for the signal lines, there is sufficient space between each signal line to provide insulation between different types of signal lines, thereby supporting the deployment of different types of signal lines in the same film layer and helping to achieve thinner designs.

[0083] like Figure 1 , Figures 4 to 39As shown, in some embodiments, each pixel row may be provided with a second reset signal line 212 and a second bias signal line 232, which may be arranged along a first direction. Each second reset signal line 212 may be electrically connected to the corresponding pixel row, and each second bias signal line 232 may be electrically connected to the corresponding pixel row. The pixel row includes multiple pixel circuits 10 arranged along a second direction. This ensures electrical connection between the first signal line 21 and the bias signal line 23 and each pixel circuit 10 in the display panel, thereby ensuring the provision of a first reset signal VREF2 and a bias signal DVH to each pixel circuit 10, and thus achieving display control.

[0084] like Figures 4 to 39 As shown, in some embodiments, the number of pixel columns in a pixel group is N0. In the same signal line group 200, the number of first reset signal lines 211 is N1, the number of third reset signal lines 221 is N2, and the number of first bias signal lines 231 is N3. Wherein, N1 + N2 + N3 = N0, N2 ≥ N1, N2 ≥ N3, and N1, N2, and N3 are all positive integers. That is, in the same signal line group 200, the number of first reset signal lines 211, third reset signal lines 221, and first bias signal lines 231 is at least one, and the total number of each signal line is the same as the number of pixel columns in the pixel group. Furthermore, the number of third reset signal lines 221 is greater than or equal to the number of first reset signal lines 211, and the number of third reset signal lines 221 is greater than or equal to the number of first bias signal lines 231. That is, the percentage of the third reset signal line 221 is set to the highest to ensure that the second reset signal VREF1 is provided to each pixel circuit 10 in the display panel, thereby ensuring the display.

[0085] like Figures 4 to 23As shown, in some embodiments, the first reset signal line 211 can be electrically connected to a corresponding pixel column, the third reset signal line 221 can be electrically connected to at least one pixel column in the corresponding signal line group 200, and the first bias signal line 231 can be electrically connected to a corresponding pixel column. In the pixel group and its corresponding signal line group 200, the first reset signal line 211 can be electrically connected to the corresponding pixel column, and the remaining pixel columns can be electrically connected to the second reset signal line 212, thereby achieving electrical connection between each pixel column and the first signal line 21; the first bias signal line 231 can be electrically connected to the corresponding pixel column, and the remaining pixel columns can be electrically connected to the second bias signal line 232, thereby achieving electrical connection between each pixel column and the bias signal line 23; the third reset signal line 221 can be electrically connected to at least one pixel column, thereby achieving electrical connection between each pixel column and the third reset signal line 221. It is understandable that by setting the first reset signal line 211 to be electrically connected to a pixel column, and each pixel row to be electrically connected to a second reset signal line 212, the electrical connection between each pixel circuit 10 and the first signal line 21 is achieved, thereby satisfying the input requirements of each pixel column for the first reset signal VREF2. Similarly, by setting the first bias signal line 231 to be electrically connected to a pixel column, and each pixel row to be electrically connected to a second bias signal line 232, the electrical connection between each pixel circuit 10 and the bias signal line 23 is achieved, thereby satisfying the input requirements of each pixel column for the bias signal DVH. Furthermore, the third reset signal line 221 is electrically connected to at least one pixel column to satisfy the input requirements of each pixel column for the second reset signal VREF1.

[0086] like Figure 22 and Figure 23As shown, in some embodiments, N2 ≥ N0 / 2. That is, the number of third reset signal lines 221 in signal line group 200 is greater than or equal to half the number of pixel columns in pixel group, and the total number of first reset signal lines 211 and first bias signal DVH is less than or equal to half the number of pixel columns in pixel group. Thus, by setting the number of third reset signal lines 221 in signal line group 200 to be no less than half the number of pixel columns in pixel group, and each third reset signal line 221 electrically connected to at least one pixel column, it is ensured that each pixel circuit 10 is electrically connected to the third reset signal line 221, thereby ensuring that a second reset signal VREF1 is provided to each pixel circuit 10 to realize the display function. Further, in some embodiments, adjacent two third reset signal lines 221 are separated by a first reset signal line 211 or a first bias signal line 231. That is, a first reset signal line 211 or a first bias signal line 231 is provided between adjacent two third reset signal lines 221. This spacing arrangement ensures that each pixel circuit 10 is electrically connected to the third reset signal line 221, while optimizing the overall wiring layout of the signal line group 200, making the distribution of various signal lines more uniform, making full use of the wiring space of the display panel, and reducing the difficulty of manufacturing process.

[0087] like Figures 4 to 23 As shown, in some embodiments, the display panel includes pixel pairs, and each pixel pair includes an electrode portion 110. In the pixel group and the corresponding signal line group 200, each third reset signal line 221 is electrically connected to two adjacent pixel columns via the electrode portion 110 of the pixel pair. The two adjacent pixel columns include multiple pixel pairs arranged along a first direction. Each adjacent pixel column may have a corresponding third reset signal line 221, and each third reset signal line 221 is electrically connected to the electrode portion 110 of each pixel pair in the corresponding two adjacent pixel columns. This allows the first electrode of each second reset transistor in the two pixel columns to be electrically connected to the same third reset signal line 221, thereby enabling the adjacent pixel columns to share the third reset signal line 221. Furthermore, while meeting the input requirements of each pixel circuit 10 for the second reset signal VREF1, there is no need to additionally provide a reset signal line extending along the second direction, arranged along the first direction, and providing the second reset signal VREF1. This reduces the area occupied by the signal line in the first direction, contributing to miniaturization and thinning.

[0088] like Figures 4 to 21As shown, in some embodiments, the number of pixel columns in a pixel group is N0, and the number of third reset signal lines 221 in the signal line group 200 is N2. Where 1 ≤ N2 < N0 / 2. That is, the number of third reset signal lines 221 in the signal line group 200 is greater than or equal to 1, and less than the total number of signal line groups 200, or half the number of pixel columns in the pixel group. The total number of first reset signal lines 211 and first bias signal lines 231 is greater than half the number of pixel columns in the pixel group. For example, N0 = 3, N1 = N2 = N3 = 1, that is, the signal line group 200 includes three signal lines: one first reset signal line 211, one third reset signal line 221, and one first bias signal DVH.

[0089] like Figures 4 to 21 , Figures 24 to 39 As shown, in some embodiments, the display panel further includes a fourth reset signal line 222 extending along a second direction and arranged along a first direction. Exemplarily, the number of fourth reset signal lines 222 may be the same as the number of pixel rows. The fourth reset signal line 222 is electrically connected to the third reset signal line 221 and the second reset transistor, respectively. The fourth reset signal line 222 may be electrically connected to the first electrode of the second reset transistor to provide a second reset signal VREF1. For ease of description, in this embodiment, the third reset signal line 221 and the fourth reset signal line 222 are collectively referred to as the second signal line 22. That is, the second signal line 22 includes the electrically connected third reset signal line 221 and the fourth reset signal line 222. The fourth reset signal line 222 is insulated from the first reset signal line 211, the second reset signal line 212, the third bias signal line 23, and the fourth bias signal line 23, respectively.

[0090] In this embodiment, a fourth reset signal line 222 extending along the second direction and arranged along the first direction is provided. This fourth reset signal line 222 electrically connects to the pixel circuit 10, thereby providing a second reset signal VREF1 to each pixel circuit 10 in the display panel, ensuring display functionality. Furthermore, the third reset signal line 221 and the fourth reset signal line 222 form a mesh structure, which reduces the overall impedance of the second signal line 22, thereby reducing the power consumption of the bias signal line 23 and improving the signal transmission stability of the second signal line 22. This is beneficial for improving the display uniformity and other display effects of the display panel.

[0091] It is understandable that when the pixel circuits 10 are arranged in a mirror image and the number of third reset signal lines 221 is less than half the number of pixel columns, each third reset signal line 221 electrically connects two adjacent pixel columns. This results in some pixel columns being unable to be electrically connected to the third reset signal lines 221, thus failing to meet the input requirements of the pixel circuits 10 for the second reset signal VREF1. Alternatively, when the pixel circuits 10 are arranged in the same way, each third reset signal line 221 electrically connects to one pixel column, again resulting in some pixel columns being unable to be electrically connected to the third reset signal lines 221. To address this, this application can provide a fourth reset signal line 222, combined with the third reset signal line 221, to achieve electrical connection with the second reset transistors of each pixel circuit 10 in the display panel. This allows the second reset signal VREF1 to be provided to each pixel circuit 10 in the display panel, thereby ensuring the display function. Among them, the pixel circuit 10 that is not directly electrically connected to the third reset signal line 221 can be electrically connected to the fourth reset signal line 222, thereby realizing the electrical connection between each pixel circuit 10 and the second signal line 22, so as to provide the second reset signal VREF1 for each pixel circuit 10.

[0092] like Figures 4 to 21 , Figures 24 to 39 As shown, in some embodiments, each pixel row may be provided with a second reset signal line 212, a fourth reset signal line 222, and a second bias signal line 232. The second reset signal line 212, the fourth reset signal line 222, and the second bias signal line 232 may be arranged regularly along a second direction, and the specific arrangement order can be flexibly set according to the specific structure of the pixel circuit 10. For example, the second reset signal line 212 is positioned near the first reset transistor in the pixel circuit 10, the fourth reset signal line 222 is positioned near the second reset transistor in the pixel circuit 10, and the second bias signal line 232 is positioned near the bias transistor T8 in the pixel circuit 10. The fourth reset signal line 222 may be electrically connected to the first electrode of the second reset transistor in at least a portion of the second reset transistors in the corresponding pixel row of the pixel circuit 10. In this way, the electrical connection between the first signal line 21, the second signal line 22, and the bias signal line 23 and each pixel circuit 10 in the display panel can be guaranteed, thereby ensuring that the first reset signal VREF2, the second reset signal VREF1, and the bias signal DVH are provided to each pixel circuit 10, and thus realizing display control.

[0093] like Figure 11 , Figure 12 , Figure 16 , Figure 17 , Figure 19 , Figure 29 , Figure 37 and Figure 38As shown, in some embodiments, the fourth reset signal line 222 extends continuously along the second direction, meaning the fourth reset signal line 222 is continuous in the second direction. Thus, the fourth reset signal line 222 can form a full-screen grid structure with the third reset signal line 221, further improving the uniformity of the display panel. There can be multiple fourth reset signal lines 222 and multiple third reset signal lines 221, and multiple intersection points between them. The fourth reset signal lines 222 and third reset signal lines 221 can be electrically connected at at least some of their intersection points. Each fourth reset signal line 222 can be electrically connected to at least one third reset signal line, and each third reset signal line 221 can be electrically connected to at least one fourth reset signal line 222. The fourth reset signal line 222 can be electrically connected to at least a portion of the first terminals of the second reset transistors in the corresponding pixel row. The fourth reset signal line 222 can be electrically connected to the first terminals of the third reset signal line 221 and the second reset transistors respectively through through-holes.

[0094] like Figure 4 , Figure 8 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 24 , Figure 28 , Figure 31 , Figure 32 , Figure 34 and Figure 35 As shown, in some embodiments, the fourth reset signal line 222 includes a plurality of signal segments 2221 extending and arranged along the second direction. That is, the fourth reset signal line 222 is discontinuous and interrupted in the second direction. Specifically, the fourth reset signal line 222 includes a plurality of discontinuous signal segments 2221. Each signal segment 2221 is electrically connected to a third reset signal line 221 and a second reset transistor, respectively. A signal segment 2221 may intersect with at least one third reset signal line 221, and the signal segment 2221 may be electrically connected to the third reset signal line 221 at the intersection. A signal segment 2221 may be electrically connected to the first electrode of a portion of the second reset transistors in the pixel row. Thus, the signal segments 2221 and the third reset signal line 221 form a grid structure, which can improve the uniformity of the display panel. Furthermore, the signal segments 2221 can reduce wiring difficulty and the space occupied by signal lines, contributing to miniaturization and thinning.

[0095] like Figures 3 to 39As shown, in some embodiments, the display panel includes a first semiconductor layer POLY, a first conductive layer M1, a first sub-gate conductive layer MC, a second semiconductor layer IGZO, a second sub-gate conductive layer MG, and a second conductive layer M2, which are sequentially stacked. The material of the first semiconductor layer may include silicon. The material of the second semiconductor layer may include an oxide semiconductor material. The materials of the first conductive layer M1, the first sub-gate conductive layer MC, the second sub-gate conductive layer MG, and the second conductive layer M2 may all include metallic materials. In some embodiments, the display panel may further include a light-shielding conductive layer M0 located on the side of the first semiconductor layer POLY opposite to the first conductive layer M1 and a substrate 113. In some embodiments, the light-shielding conductive layer M0 may include a light-shielding layer 114.

[0096] like Figure 3 As shown, in some embodiments, the pixel circuit 10 may include multiple thin-film transistors and a capacitor C. The multiple thin-film transistors may include a silicon thin-film transistor 111 and an oxide thin-film transistor 112. The silicon thin-film transistor 111 includes a gate 101, a channel layer 102, a source 103, and a drain 104. The gate 101 of the silicon thin-film transistor 111 is located in a first conductive layer, the channel layer 102 of the silicon thin-film transistor 111 is located in a first semiconductor layer POLY, and the source 103 and drain 104 of the silicon thin-film transistor 111 are both located in a second conductive layer M2. The oxide thin-film transistor 112 includes a gate 101, a channel layer 102, a source 103, and a drain 104. The gate 101 of the oxide thin-film transistor 112 includes a first sub-gate 1011 and a second sub-gate 1012. The first sub-gate 1011 is located in a first sub-gate conductive layer MC, and the second sub-gate 1012 is located in a second sub-gate conductive layer MG. The channel layer 102 of the oxide thin-film transistor 112 is located in a second semiconductor layer IGZO. The source 103 and drain 104 of the oxide thin-film transistor 112 are both located in the second conductive layer M2. The capacitor C may include a first electrode C1 and a second electrode C2, with the first electrode C1 located in the first conductive layer M1 and the second electrode C2 located in the first sub-gate conductive layer MC.

[0097] like Figures 3 to 39 As shown, in some embodiments, the first reset signal line 211 and the second reset signal line 212 are disposed in different layers. In some embodiments, the first reset signal line 211 is located in the second conductive layer M2, and the second reset signal line 212 is located in the first sub-gate conductive layer MC. In this way, by disposing the first reset signal line 211 and the second reset signal line 212, which have different extension directions and arrangement directions, in different film layers, the wiring difficulty of the same film layer can be reduced.

[0098] like Figures 3 to 39As shown, in some embodiments, the first bias signal line 231 and the second bias signal line 232 are disposed in different layers. In some embodiments, the first bias signal line 231 is located in the second conductive layer M2, and the second bias signal line 232 is located in the second sub-gate conductive layer MG. In this way, by disposing the first bias signal line 231 and the second bias signal line 232, which have different extension directions and arrangement directions, in different film layers, the wiring difficulty of the same film layer can be reduced.

[0099] like Figures 3 to 39 As shown, in some embodiments, the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 are disposed in the same layer. In some embodiments, the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 are all located in the second conductive layer M2. Thus, by disposing the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231, which have the same extension direction and arrangement direction, in the same film layer, the number of film layers in the display panel can be reduced, which helps to achieve thinner design.

[0100] like Figures 3 to 39 As shown, in some embodiments, the second reset signal line 212 and the second bias signal line 232 are disposed in different layers. In some embodiments, the second reset signal line 212 is located in the first sub-gate conductive layer MC, and the second bias signal line 232 is located in the second sub-gate conductive layer MG. Thus, disposing the mutually insulated second reset signal line 212 and the second bias signal line 232 in different film layers helps reduce the wiring difficulty of multiple signal lines, reduces crosstalk between different signal lines, and thereby improves the display effect.

[0101] like Figure 21 As shown, in some embodiments, the fourth reset signal line 222 and the third reset signal line 221 are disposed in the same layer. In some embodiments, both the fourth reset signal line 222 and the third reset signal line 221 are located in the second conductive layer M2. Thus, by disposing the electrically connected fourth reset signal line 222 and the third reset signal line 221 in the same film layer, the connection complexity between signal lines can be reduced, and the number of film layers in the display panel can be reduced, which helps to achieve thinner designs.

[0102] like Figure 8 , Figure 12 , Figure 20 , Figure 28 , Figure 35 and Figure 38As shown, in some embodiments, the fourth reset signal line 222 is disposed on the same layer as the channel layer 102 of the second reset transistor. Thus, the fourth reset signal line 222 is electrically connected to the channel layer 102 of the second reset transistor, which is on the same film layer, achieving electrical connection between the fourth reset signal line 222 and the first electrode of the second reset transistor, reducing the difficulty of layout. For example, the second reset transistor can be an oxide thin-film transistor 112, meaning the fourth reset signal line 222 can be disposed on the same layer as the channel layer 102 of the oxide thin-film transistor 112. In some embodiments, both the fourth reset signal line 222 and the channel layer 102 of the oxide thin-film transistor 112 are located on the second semiconductor layer IGZO.

[0103] like Figure 14 , Figure 17 , Figure 32 As shown, in some embodiments, the fourth reset signal line 222 is disposed in a different layer from the first reset signal line 211, the second reset signal line 212, the third reset signal line 221, the first bias signal line 231, and the second bias signal line 232. In some embodiments, the fourth reset signal line 222 is located in the first conductive layer M1, the first reset signal line 211, the third reset signal line 221, and the first bias signal line 231 are all located in the second conductive layer M2, the second reset signal line 212 is located in the first sub-gate conductive layer MC, and the second bias signal line 232 is located in the second sub-gate conductive layer MG. Thus, by placing the fourth reset signal line 222 in different layers from the other three reset signal lines and the bias signal line 23, the area occupied by the signal lines can be reduced, and the difficulty of laying out multiple signal lines can be lowered.

[0104] like Figures 4 to 39 As shown, in some embodiments, the fourth reset signal line 222 is located in at least one of the second semiconductor layer IGZO, the first conductive layer M1, and the second conductive layer M2. The fourth reset signal line 222 can be electrically connected to the first electrode of the second reset transistor and the third reset signal line 221 via vias, respectively. For example, the fourth reset signal line 222 is located in the first conductive layer M1, and the fourth reset signal line 222 can be electrically connected to the first electrode of the second reset transistor via a via, wherein the via can electrically connect the first conductive layer M1 and the second conductive layer M2.

[0105] like Figures 4 to 21As shown, in some embodiments, the signal line group 200 includes a first reset signal line 211, a third reset signal line 221, a first bias signal line 231, and a third reset signal line 221 arranged sequentially along a second direction. For ease of description, this arrangement is referred to as a first vertical arrangement. That is, the signal line group 200 includes six signal lines, including two first reset signal lines 211, two third reset signal lines 221, and two first bias signal lines 231, meaning the number of third reset signal lines 221 is less than half the number of lines in the signal line group 200. Correspondingly, the pixel group includes six pixel columns, i.e., N0=6, N1=2, N2=2, and N3=2.

[0106] like Figure 22 As shown, in some embodiments, the signal line group 200 includes a first reset signal line 211, a third reset signal line 221, a first bias signal line 231, a third reset signal line 221, a first reset signal line 211, and a third reset signal line 221 arranged sequentially along a second direction. For ease of description, this arrangement is referred to as the second vertical arrangement. That is, the signal line group 200 includes six signal lines, including two first reset signal lines 211, three third reset signal lines 221, and one first bias signal line 231, meaning the number of third reset signal lines 221 is half the number of signal lines in the signal line group 200. Correspondingly, the pixel group includes six pixel columns, i.e., N0=6, N1=2, N2=3, and N3=1.

[0107] like Figure 23 As shown, in some embodiments, the signal line group 200 includes a first reset signal line 211, a third reset signal line 221, a first bias signal line 231, a third reset signal line 221, a first bias signal line 231, and a third reset signal line 221 arranged sequentially along a second direction. For ease of description, this arrangement is referred to as a third vertical arrangement. That is, the signal line group 200 includes six signal lines, including one first reset signal line 211, three third reset signal lines 221, and two first bias signal lines 231, meaning the number of third reset signal lines 221 is half the number of signal lines in the signal line group 200. Correspondingly, the pixel group includes six pixel columns, i.e., N0=6, N1=1, N2=3, and N3=2.

[0108] like Figures 24 to 33As shown, in some embodiments, the signal line group 200 includes a third reset signal line 221, a first bias signal line 231, and a first reset signal line 211 arranged along a second direction. For ease of description, this arrangement is referred to as a fourth longitudinal arrangement. That is, the signal line group 200 includes three signal lines: one first reset signal line 211, one third reset signal line 221, and one first bias signal line 231, meaning the number of third reset signal lines 221 is less than half the number of lines in the signal line group 200. Correspondingly, the pixel group includes three pixel columns: N0=3, N1=1, N2=1, and N3=1.

[0109] like Figures 34 to 36 As shown, in some embodiments, the signal line group 200 includes a third reset signal line 221, a first reset signal line 211, a third reset signal line 221, a third reset signal line 221, and a first bias signal line 231 arranged sequentially along the second direction. For ease of description, this arrangement is referred to as the fifth vertical arrangement. That is, the signal line group 200 includes six signal lines, including one first reset signal line 211, four third reset signal lines 221, and one first bias signal line 231, meaning the number of third reset signal lines 221 exceeds half the number of signal lines in the signal line group 200. Correspondingly, the pixel group includes six pixel columns, i.e., N0=6, N1=1, N2=4, and N3=1.

[0110] like Figures 37 to 39 As shown, in some embodiments, the signal line group 200 includes a third reset signal line 221, a first reset signal line 211, a third reset signal line 221, a first reset signal line 211, a third reset signal line 221, and a first bias signal line 231 arranged along a second direction. For ease of description, this arrangement is referred to as the sixth vertical arrangement. That is, the signal line group 200 includes six signal lines, including two first reset signal lines 211, two third reset signal lines 221, and two first bias signal lines 231, meaning the number of third reset signal lines 221 is less than half the number of signal line groups 200. Correspondingly, the pixel group includes six pixel columns, i.e., N0=6, N1=3, N2=2, and N3=1.

[0111] If the pixel circuits 10 in the display panel are arranged in a mirror configuration, i.e., the display panel includes pixel pairs and the pixel pairs include electrode portions 110, and if the third reset signal line 221 in the signal line group 200 exceeds half of the total number of signal lines in the signal line group 200, such as if the signal line group 200 adopts the above-mentioned second vertical arrangement, third vertical arrangement, fourth vertical arrangement or fifth vertical arrangement, the third reset signal line 221 can be electrically connected to the electrode portion 110, so that the third reset signal line 221 is electrically connected to the first pole of the second reset transistor in each pixel circuit 10, thereby satisfying the input requirements of each pixel circuit 10 for the second reset signal VREF1. Furthermore, by combining the second reset signal line 212 and the second bias signal line 232, the input requirements of each pixel circuit 10 for the first reset signal VREF2 and the bias signal DVH can be met, thereby ensuring the display function. This type of display panel does not require an additional fourth reset signal line 222, which reduces the occupation of signal lines and helps to achieve miniaturization and thinness. Moreover, the first signal line 21 and the bias signal line 23 form a full-screen grid structure, which can reduce impedance and improve the display effect.

[0112] The pixel circuits 10 in the display panel are arranged in a mirror image, and the third reset signal line 221 in the signal line group 200 is less than half the total number of signal lines in the signal line group 200, such as when the signal line group 200 adopts the first or sixth vertical arrangement described above; or, the pixel circuits 10 in the display panel are arranged in a non-mirror image, such as the same arrangement. For any of the above vertical arrangements, in addition to the first reset signal VREF2, the second reset signal line 212, the third reset signal line 221, the first bias signal line 231, and the second bias signal line 232, the display panel also provides a fourth reset signal line 222. That is, the third reset signal line 221 and the fourth reset signal line 222 are used together to achieve electrical connection with each pixel circuit 10, thereby providing the second reset signal VREF1 to each pixel circuit 10. In this regard, the following describes the setting method of the fourth reset signal line 222, taking the pixel circuits 10 as a mirror image and the signal line group 200 as the fourth vertical arrangement described above as an example.

[0113] For example, such as Figure 4 , Figure 7 , Figure 24 , Figure 28 , Figure 34 and Figure 35As shown, the fourth reset signal line 222 may be located in the second semiconductor layer IGZO. The fourth reset signal line 222 may include a plurality of signal segments 2221 extending and arranged along the second direction. Each signal segment 2221 may be electrically connected to the first pole of the second reset transistor in at least two pixel circuits 10 arranged continuously along the second direction. Each signal segment 2221 is electrically connected to the corresponding third reset signal line 221, so that the third reset signal line 221 and each signal segment 2221 can provide a second reset signal VREF1 to each pixel circuit 10.

[0114] Another example, such as Figure 11 , Figure 12 , Figures 18 to 20 , Figure 37 and Figure 38 As shown, the fourth reset signal line 222 can be located in the second semiconductor layer IGZO. The fourth reset signal line 222 can extend continuously along the second direction. The fourth reset signal line 222 is connected to the first pole of each second reset transistor in a pixel row. The fourth reset signal line 222 is electrically connected to the third reset signal line 221, thereby realizing the electrical connection between each pixel circuit 10 and the second signal line 22. In turn, the third reset signal line 221 and the fourth reset signal line 222 can provide the second reset signal VREF1 to each pixel circuit 10.

[0115] Another example is, such as Figure 13 , Figure 14 , Figure 31 and Figure 32 As shown, the fourth reset signal line 222 may be located in the first conductive layer M1. The fourth reset signal line 222 may include a plurality of signal segments 2221 extending and arranged along the second direction. Each signal segment 2221 is electrically connected to the first pole of the second reset transistor in at least two pixel circuits 10 arranged continuously along the second direction through a via. Each signal segment 2221 is electrically connected to the corresponding third reset signal line 221, so that the third reset signal line 221 and each signal segment 2221 can provide a second reset signal VREF1 to each pixel circuit 10. The via is electrically connected to the first conductive layer M1 and the second conductive layer M2.

[0116] Another example, such as Figures 16 to 18 As shown, the fourth reset signal line 222 can be located in the first conductive layer M1. The fourth reset signal line 222 can extend continuously along the second direction. The fourth reset signal line 222 can be electrically connected to the first pole of at least two second reset transistors in a pixel row through a via. The fourth reset signal line 222 is electrically connected to the third reset signal line 221, so that the second reset signal VREF1 can be provided to each pixel circuit 10 through the third reset signal line 221 and the fourth reset signal line 222.

[0117] Another example, such as Figure 16 and Figure 17 As shown, the fourth reset signal line 222 can be located between the second semiconductor layer IGZO and the first conductive layer M1. The fourth reset signal line 222 can extend continuously along the second direction. The fourth reset signal line 222 is electrically connected to the third reset signal line 221, so that the second reset signal VREF1 can be provided to each pixel circuit 10 through the third reset signal line 221 and the fourth reset signal line 222.

[0118] Another example is, such as Figures 19 to 21 As shown, the fourth reset signal line 222 can be located in the second semiconductor layer IGZO and the second conductive layer M2. The fourth reset signal line 222 located in the second semiconductor layer can extend continuously along the second direction. The fourth reset signal line 222 located in the second conductive layer can include a plurality of signal segments 2221 arranged and extending along the second direction. The fourth reset signal line 222 is electrically connected to the third reset signal line 221, so that the second reset signal VREF1 can be provided to each pixel circuit 10 through the third reset signal line 221 and the fourth reset signal line 222.

[0119] It should be noted that the above is only an illustrative example. In practice, the film layer and shape (continuous or intermittent) where the fourth reset signal line 222 is located can be flexibly set according to specific circumstances. The signal line group 200 in the display panel can adopt any of the above-mentioned vertical arrangements. The second reset signal line 212, the fourth reset signal line 222 (if present), and the second bias signal line 232 can each be set to correspond to a pixel row and arranged along the first direction, so as to electrically connect to each pixel circuit 10 through the first signal line 21 and the bias signal line 23 respectively, thereby ensuring the display.

[0120] Based on the same concept, this application also provides a display device. Figure 40 This is a schematic diagram of the structure of the display device 2000 provided in the embodiments of this application, as shown below. Figure 40 As shown, the display device 2000 includes the display panel 1000 in any of the above embodiments. Exemplarily, as... Figure 40 As shown, the display device 2000 includes a display panel 1000. Therefore, the display device 2000 also has the beneficial effects of the display panel 1000 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 1000 above, and will not be repeated below.

[0121] The display device 2000 provided in this application embodiment can be... Figure 40The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0122] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: The pixel circuit includes a first reset transistor, a second reset transistor, and a bias transistor; The signal lines include a first reset signal line and a second reset signal line electrically connected to the first reset transistor, a third reset signal line electrically connected to the second reset transistor, and a first bias signal line and a second bias signal line electrically connected to the bias transistor. The first reset signal line, the third reset signal line, and the first bias signal line extend continuously along a first direction and are arranged along a second direction, respectively. The first direction intersects with the second direction; The second reset signal line and the second bias signal line extend continuously along the second direction and are arranged along the first direction, respectively.

2. The display panel according to claim 1, characterized in that, The display panel includes pixel pairs, and each pixel pair includes two adjacent pixel circuits arranged along the second direction; wherein... The pixel pair includes an electrode portion, which includes a channel layer in which two second reset transistors in the pixel pair are interconnected. The electrode portion is electrically connected to the first electrode of the two second reset transistors in the pixel pair and the third reset signal line, respectively.

3. The display panel according to claim 2, characterized in that, At least one third reset signal line is provided for each two adjacent pixel columns.

4. The display panel according to claim 2, characterized in that, The two second reset transistors in the pixel pair are arranged in a mirror image along the first direction.

5. The display panel according to claim 4, characterized in that, The two pixel circuits in the pixel pair are arranged in a mirror image along the first direction.

6. The display panel according to claim 1, characterized in that, The display panel includes at least one signal line group arranged along the second direction, the signal line group including at least one first reset signal line, at least one third reset signal line, and at least one first bias signal line arranged along the second direction.

7. The display panel according to claim 6, characterized in that, The display panel includes at least one pixel group arranged along the second direction, and the pixel group includes at least three pixel columns arranged sequentially along the second direction; wherein each signal line group corresponds to one pixel group, and any signal line in the signal line group corresponds to one pixel column.

8. The display panel according to claim 7, characterized in that, The number of pixel columns in the pixel group is N0; in the same signal line group, the number of the first reset signal lines is N1, the number of the third reset signal lines is N2, and the number of the first bias signal lines is N3; wherein, N1+N2+N3=N0, N2≥N1, N2≥N3, and N1, N2, and N3 are all positive integers.

9. The display panel according to claim 8, characterized in that, N2≥N0 / 2, and the two adjacent third reset signal lines are separated by the first reset signal line or the first bias signal line.

10. The display panel according to claim 9, characterized in that, The display panel includes pixel pairs; in the pixel group and the corresponding signal line group, each of the third reset signal lines is electrically connected to two adjacent pixel columns through the electrode portion of the pixel pair.

11. The display panel according to claim 10, characterized in that, The signal line group includes: The first reset signal line, the third reset signal line, the first bias signal line, the third reset signal line, the first reset signal line, and the third reset signal line are arranged sequentially along the second direction; or, The first reset signal line, the third reset signal line, the first bias signal line, the third reset signal line, the first bias signal line, and the third reset signal line are arranged sequentially along the second direction.

12. The display panel according to claim 7, characterized in that, The number of pixel columns in the pixel group is N0, and the number of third reset signal lines in the signal line group is N2, where 1≤N2<N0 / 2.

13. The display panel according to claim 1, characterized in that, The pixel circuits arranged along the second direction are in the same layout.

14. The display panel according to claim 1, characterized in that, The display panel further includes a fourth reset signal line that extends along the second direction and is arranged along the first direction; The fourth reset signal line is electrically connected to the third reset signal line and the second reset transistor, respectively.

15. The display panel according to claim 14, characterized in that, The fourth reset signal line extends continuously along the second direction.

16. The display panel according to claim 14, characterized in that, The fourth reset signal line includes a plurality of signal segments extending along the second direction and arranged along the second direction, and the signal segments are electrically connected to the third reset signal line and the second reset transistor, respectively.

17. The display panel according to claim 14, characterized in that, The display panel includes at least one group of signal lines arranged along the second direction, the group of signal lines including at least one first reset signal line, at least one third reset signal line, and at least one first bias signal line arranged along the second direction; wherein, The signal line group includes the third reset signal line, the first reset signal line, the third reset signal line, the first reset signal line, the third reset signal line, the first reset signal line, and the first bias signal line arranged sequentially along the second direction; or, The signal line group includes the third reset signal line, the first bias signal line, and the first reset signal line arranged sequentially along the second direction; or... The signal line group includes the third reset signal line, the third reset signal line, the first reset signal line, the third reset signal line, and the first bias signal line arranged sequentially along the second direction; or, The signal line group includes the first reset signal line, the third reset signal line, the first bias signal line, the third reset signal line, the first reset signal line, and the first bias signal line arranged sequentially along the second direction.

18. The display panel according to claim 14, characterized in that, The fourth reset signal line is disposed on the same layer as the third reset signal line.

19. The display panel according to claim 14, characterized in that, The fourth reset signal line is disposed on the same layer as the channel layer of the second reset transistor.

20. The display panel according to claim 14, characterized in that, The fourth reset signal line is disposed on a different layer from the first reset signal line, the second reset signal line, the third reset signal line, the first bias signal line, and the second bias signal line.

21. The display panel according to claim 14, characterized in that, The display panel includes a first semiconductor layer, a first conductive layer, a first sub-gate conductive layer, a second semiconductor layer, a second sub-gate conductive layer, and a second conductive layer, which are sequentially stacked; wherein... The first reset signal line, the third reset signal line, and the first bias signal line are respectively located in the second conductive layer; The second reset signal line is located in the second semiconductor layer; The second bias signal line is located in the second sub-gate conductive layer; The fourth reset signal line is located at at least one of the second semiconductor layer, the first conductive layer, and the second conductive layer.

22. The display panel according to claim 1, characterized in that, The pixel circuit also includes a driving transistor and a light-emitting element; wherein... The first terminal of the first reset transistor is electrically connected to the first reset signal line, and the second terminal of the first reset transistor is electrically connected to the anode of the light-emitting element. The first terminal of the second reset transistor is electrically connected to the third reset signal line, and the second terminal of the second reset transistor is electrically connected to the gate of the driving transistor. The first terminal of the bias transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the bias transistor is electrically connected to the first bias signal line.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 22.

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