Method of operation of a semiconductor memory device
By employing a dual sequencer structure in the semiconductor memory device to control the order and time interval of the writing program, the interference problem between memory blocks is solved, achieving high-speed operation and high efficiency.
CN122201366APending Publication Date: 2026-06-12KIOXIA CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-06-18
- Publication Date
- 2026-06-12
AI Technical Summary
⚠Technical Problem
Existing semiconductor memory devices suffer from inefficiency when writing programs, especially due to interference between write instruction sets of multiple memory blocks, which affects the device's operating speed.
⚗Method used
A dual sequencer structure is adopted, consisting of a first sequencer and a second sequencer, which are used for different storage planes. By controlling the order and time interval of the writing process, interference between memory blocks is avoided, thereby improving writing efficiency.
🎯Benefits of technology
This enables high-speed operation of the memory device, reduces interference between write programs, and improves overall operating efficiency.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122201366A_ABST
Abstract
Embodiments provide a method for operating a semiconductor storage device that operates at high speed. The semiconductor storage device of the embodiments includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer operable to write a program, and a second sequencer operable to write a program.
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