Storage device and method of operating a storage controller

Abstract

A storage device includes a non-volatile memory device and a storage controller. The non-volatile memory device includes at least one memory block including a plurality of cell strings. The at least one memory block is divided into a plurality of sub-blocks arranged in one direction. The storage controller includes a recycling register, identifies the plurality of sub-blocks as a selected sub-block including a selected word line and at least one unselected sub-block adjacent to the selected sub-block based on an access address, adaptively determines K target word lines of the selected sub-block and the at least one unselected sub-block based on a program progress state of each of the selected sub-block and the at least one unselected sub-block, and sequentially performs a reliability verification operation on the K target word lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0182199, filed on December 10, 2024, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor memory devices, and more specifically to memory devices and methods of operating memory controllers. Background Technology

[0004] Semiconductor memory devices used for storing data can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices (such as dynamic random access memory (DRAM) devices) are typically configured to store data by charging or discharging capacitors in memory cells, and the stored data is lost when power is off. Non-volatile memory devices (such as flash memory devices) retain the stored data even when power is off. Volatile memory devices are widely used as main memory in various devices, while non-volatile memory devices are widely used to store program code and / or data in various electronic devices such as computers and mobile devices.

[0005] Flash memory devices are widely used as high-capacity storage media. Due to the physical characteristics of flash memory devices and / or various environmental factors, errors can occur in the data stored in them. Data errors can be corrected using individual error correction schemes. However, when an error occurs that exceeds the correction limit of an individual error correction scheme, such data may be lost. In this case, the reliability of the data stored in flash memory devices may be affected. Summary of the Invention

[0006] Some example embodiments may provide storage devices with enhanced reliability and enhanced performance.

[0007] Some example embodiments may provide a method of operating a memory controller configured to control a non-volatile memory device with enhanced reliability and performance.

[0008] According to an example embodiment, a storage device includes a non-volatile memory device and a storage controller. The non-volatile memory device includes at least one memory block comprising a plurality of cell strings, wherein each of the plurality of cell strings includes a string select transistor, a plurality of memory cells, and a ground select transistor, which are connected in series and arranged in one direction between a bit line and a common source line. The at least one memory block is divided into a plurality of sub-blocks arranged in one direction. The storage controller includes a reclamation register that identifies a selected sub-block including a selected word line and at least one unselected sub-block adjacent to the selected sub-block based on an access address, adaptively determines K target word lines of the selected sub-block and at least one unselected sub-block based on the programming progress state of each of the selected sub-block and at least one unselected sub-block, and sequentially performs reliability verification operations on the K target word lines.

[0009] According to an example embodiment, a method for operating a memory controller to control a non-volatile memory device is provided. The non-volatile memory device includes at least one memory block comprising a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells, and a ground select transistor, which are connected in series and arranged in one direction between a bit line and a common source line, and the at least one memory block is divided into a plurality of sub-blocks arranged in one direction. According to the method, the plurality of sub-blocks are identified based on access addresses as a selected sub-block including a selected word line and at least one unselected sub-block adjacent to the selected sub-block; K target word lines of the selected sub-block and at least one unselected sub-block are adaptively determined based on the programming progress state of each of the selected sub-block and at least one unselected sub-block; and a reliability verification operation is sequentially performed on the K target word lines.

[0010] According to an example embodiment, a storage device includes a non-volatile memory device and a storage controller. The non-volatile memory device includes at least one memory block comprising a plurality of memory cells. The at least one memory block includes a plurality of sub-blocks. The storage controller identifies the plurality of sub-blocks as a selected sub-block including a selected word line and at least one unselected sub-block adjacent to the selected sub-block based on access addresses. Based on the programming progress state of each of the selected sub-blocks and the at least one unselected sub-block, the storage controller adaptively determines K target word lines for the selected sub-blocks and the at least one unselected sub-block, where K is an integer greater than two, and sequentially performs reliability verification operations on the K target word lines. The storage controller includes a reclamation register, a reliability manager, an error correction code (ECC), and a processor. The reliability manager performs reliability verification operations based on a read interference level monitoring scheme. The ECC engine detects and corrects errors in read data by performing ECC decoding on read data read by the reliability manager. The processor controls the reliability manager and the ECC engine. Based on an error count in the read data that is greater than a reference error count, the processor registers the corresponding sub-block in the reclamation register as a reclamation sub-block.

[0011] Therefore, the storage device and the method for operating the storage controller according to the example embodiment can designate at least one word line from the word lines of an unselected sub-block that is sensitive to read interference, in addition to the target word lines among the word lines of the selected sub-block that are sensitive to read interference, as additional target word lines. A reliability verification operation can be performed on the target word lines and the additional target word lines, and a recycling operation can be performed based on the result of the reliability verification operation. Therefore, the reliability and performance of the storage device can be enhanced. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating a method of operating a memory controller to control a non-volatile memory device according to an example embodiment.

[0014] Figure 2A and Figure 2B This illustrates an example embodiment. Figure 1 The flowchart shows the operation of adaptively determining K target word lines.

[0015] Figure 3 This illustrates an example embodiment in Figure 1 A flowchart illustrating an example of sequentially performing reliability verification operations.

[0016] Figure 4 This shows a memory block divided into sub-blocks and target word lines for the sub-blocks.

[0017] Figure 5A and Figure 5B Each of the example embodiments is shown separately. Figure 3 Examples of operations.

[0018] Figure 6 Examples of open sub-blocks, closed sub-blocks, and erase sub-blocks according to an example embodiment are shown.

[0019] Figure 7 It is a graph showing the changes in the distribution of memory cells obtained through repeated read operations.

[0020] Figure 8 This is a block diagram illustrating a storage device according to an example embodiment.

[0021] Figure 9 This illustrates an example embodiment. Figure 8 A block diagram of an example storage controller in a storage device.

[0022] Figure 10 This illustrates an example embodiment. Figure 8 A block diagram of an example of a non-volatile memory device in a storage device.

[0023] Figure 11 Schematic illustration according to an example embodiment Figure 10 The structure of non-volatile memory devices.

[0024] Figure 12 This illustrates an example embodiment. Figure 10 A block diagram of an example memory cell array in a non-volatile memory device.

[0025] Figure 13 This illustrates an example embodiment. Figure 12 A circuit diagram of one of the memory blocks.

[0026] Figure 14 Show Figure 13 An example of the structure of a string of cells in a memory block.

[0027] Figure 15 This illustrates an example embodiment. Figure 10 A block diagram of the control circuitry in a non-volatile memory device.

[0028] Figure 16 This illustrates an example embodiment. Figure 10 A block diagram of an example voltage generator in a non-volatile memory device.

[0029] Figure 17 According to the example embodiment Figure 10A schematic diagram showing the connection between the memory cell array and the page buffer circuit.

[0030] Figure 18A , Figure 18B and Figure 18C The positions of the boundary word lines for programming progress states based on selected and unselected sub-blocks, according to the example embodiment, are shown respectively.

[0031] Figure 19 The location of the boundary word line is shown according to an example embodiment of the programming progress state based on selected and unselected sub-blocks.

[0032] Figure 20 The location of the boundary word line is shown according to an example embodiment of the programming progress state based on selected and unselected sub-blocks.

[0033] Figure 21 It is used to describe Figure 13 A diagram illustrating the operational characteristics and reliability verification operations of the memory block.

[0034] Figure 22 An example embodiment is shown. Figure 8 Example of a connection between a storage controller and a non-volatile memory device in a storage device.

[0035] Figure 23 This is a block diagram illustrating a storage device according to an example embodiment. Detailed Implementation

[0036] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments.

[0037] Figure 1 This is a flowchart illustrating a method of operating a memory controller to control a non-volatile memory device according to an example embodiment.

[0038] Figure 1 The operation memory controller is shown (reference). Figure 8 50) to control a non-volatile storage device comprising at least one memory block (see reference 50) Figure 8 The method of (100) in the example includes at least one memory block comprising a plurality of cell strings, wherein each cell string includes a string select transistor, a plurality of memory cells, and a ground select transistor connected in series in a vertical direction between a bit line and a common source line. According to an example embodiment, the non-volatile memory device may include a three-dimensional NAND flash memory device or a vertical NAND flash memory device. The common source line may be in the substrate, and the vertical direction may be perpendicular to the substrate. The vertical direction may be referred to as a direction.

[0039] Reference Figure 1The storage controller 50 divides the multiple cell strings into multiple sub-blocks arranged in the vertical direction (operation S110). Each of the multiple sub-blocks is smaller than the physical block of the non-volatile memory device.

[0040] The storage controller 50 performs programming operations on at least a portion of the multiple sub-blocks (operation S130).

[0041] The storage controller 50 can trigger a reliability verification operation (operation S150). The reliability verification operation may be referred to as a reliability operation and may be performed based on a read interference level monitoring scheme.

[0042] In an example embodiment, the memory controller 50 can perform a read operation on at least one of the target word lines using a read interference level monitoring scheme, and can perform a recycling operation when the error count in the read data is greater than a reference error count. In an example embodiment, the read interference level monitoring scheme can be performed based on an on-chip valley search (OVS) algorithm. For example, the memory controller 50 can determine an optimal read voltage level, a bidirectional offset of the optimal read voltage level relative to the initial read voltage level, and can determine recycling based on the offset.

[0043] For example, when the read count associated with a specific memory block reaches a predetermined time period, the storage controller 50 may trigger a reliability verification operation for the specific memory block. For example, when the read count associated with a specific memory block reaches a reference read count, the storage controller 50 may trigger a reliability verification operation for the specific memory block.

[0044] The storage controller 50 can identify multiple sub-blocks based on the access address as a selected sub-block including the selected word line and at least one unselected sub-block (operation S170).

[0045] The storage controller 50 can adaptively determine K target word lines for the selected sub-blocks and at least one unselected sub-block based on the programming progress status of each of the selected sub-blocks and at least one unselected sub-block (operation S200). A reliability verification operation will be performed on the K target word lines. Here, K can be an integer greater than 2.

[0046] In an example embodiment, the programming progress state of each of the selected sub-block and the at least one unselected sub-block includes an open state, a closed state, and an erase state. An open state indicates that each of the selected sub-block and the at least one unselected sub-block includes at least one erased word line; a closed state indicates that each of the selected sub-block and the at least one unselected sub-block includes only programmed word lines; and an erase state indicates that each of the selected sub-block and the at least one unselected sub-block includes only erased word lines. The selected word line can be specified by an access address.

[0047] The memory controller 50 can sequentially perform reliability verification operations (operation S400) on the K target word lines. In an example embodiment, the reliability verification operation can instruct the reading of data from a memory cell connected to at least one of the K target word lines, as well as the detection and correction of errors in the read data.

[0048] When the error count detected in the memory cell of the first target word line coupled to the selected sub-block is greater than the reference error count during the reliability verification operation of the K target word lines, the memory controller 50 may skip the reliability verification operation of the second target word line of the selected sub-block, and may perform a reliability verification operation on at least one target word line of the unselected sub-block.

[0049] Based on the results of the reliability verification operation, the storage controller 50 may selectively register sub-blocks containing word lines with error counts greater than a reference error count as reclaimable sub-blocks in the reclaim register (operation S500). In an example embodiment, the storage controller 50 may perform a reclaim operation on the reclaimable sub-blocks instead of registering them in the reclaim register.

[0050] Figure 2A and Figure 2B This illustrates an example embodiment. Figure 1 The flowchart shows the operation of adaptively determining K target word lines.

[0051] Figure 2A Operation of S200a and Figure 2B The operation S200b can correspond to Figure 1 Operation S200 in the middle.

[0052] exist Figure 2A and Figure 2B In this context, assuming a physical block is divided into two sub-blocks, however... Figure 2A Operation of S200a and Figure 2B Operation S200b can be applied to situations where a physical block is divided into three or more sub-blocks.

[0053] Reference Figure 2Aand Figure 2B In order to adaptively determine the K target word lines (operations S200a and S200b), the storage controller 50 determines whether the selected sub-block is in a closed state or an open state (operation S210).

[0054] When the selected sub-block is in a closed state (closed in S210), the storage controller 50 determines whether the unselected sub-block is in a closed state, an erased state, or an open state (operation S220).

[0055] When the unselected sub-block is in a closed state (closed in S220), the storage controller 50 can determine (i) the adjacent word line AWL of the first word line of the selected sub-block that is adjacent to the selected word line (operation S231), (ii) the first weak word line WWL1 of the first word line that is adjacent to the unselected sub-block (operation S233), and (iii) the second weak word line WWL2 of the second word line of the unselected sub-block that is adjacent to the selected sub-block (operation S235) as K target word lines.

[0056] When the unselected sub-block is in the erase state (erasure in S220), the storage controller 50 can determine (i) the adjacent word line AWL of the first word line of the selected sub-block that is adjacent to the selected word line (operation S241), (ii) the first weak word line WWL1 of the first word line that is adjacent to the unselected sub-block (operation S243), (iii) the boundary word line BWL of the second word line of the unselected sub-block that is adjacent to at least one programmed word line (operation S245), and (iv) the second weak word line WWL2 of the second word line that is adjacent to the selected sub-block (operation S247) as K target word lines.

[0057] When the unselected subblock is in an open state (open in S220), the storage controller 50 can determine (i) the adjacent word line AWL of the first word line of the selected subblock that is adjacent to the selected word line (operation S251), (ii) the first weak word line WWL1 of the first word line that is adjacent to the unselected subblock (operation S253), (iii) the boundary word line BWL of the second word line of the unselected subblock that is adjacent to at least one programmed word line (operation S255), and (iv) the second weak word line WWL2 of the second word line that is adjacent to the selected subblock (operation S257) as K target word lines.

[0058] When the selected sub-block is in an open state (open in S210), the storage controller 50 determines whether the unselected sub-block is in a closed state, an erased state, or an open state (operation S320).

[0059] When the unselected sub-block is in a closed state (closed in S320), the storage controller 50 can determine the following as K target word lines: (i) the boundary word line BWL of the first word line of the selected sub-block that is adjacent to at least one programming word line (operation S331), (ii) the adjacent word line AWL of the first word line of the selected sub-block that is adjacent to the selected word line (operation S333), (iii) the first weak word line WWL1 of the first word line that is adjacent to the unselected sub-block (operation S335), and (iv) the second weak word line WWL2 of the second word line of the unselected sub-block that is adjacent to the selected sub-block (operation S337).

[0060] When the unselected sub-block is in the erase state (erasure in S320), the storage controller 50 can determine the following as K target word lines: (i) the first boundary word line BWL1 of the first word line of the selected sub-block that is adjacent to at least one first programming word line (operation S341), (ii) the adjacent word line AWL of the first word line of the selected sub-block that is adjacent to the selected word line (operation S343), (iii) the first weak word line WWL1 of the first word line that is adjacent to the unselected sub-block (operation S345), (iv) the second boundary word line BWL2 of the second word line of the unselected sub-block that is adjacent to at least one second programming word line (operation S347), and (v) the second weak word line WWL2 of the second word line that is adjacent to the selected sub-block (operation S349).

[0061] When the unselected sub-block is in an open state (open in S320), the storage controller 50 can determine the following as K target word lines: (i) the first boundary word line BWL1 of the first word line of the selected sub-block that is adjacent to at least one first programming word line (operation S351), (ii) the adjacent word line AWL of the first word line of the selected sub-block that is adjacent to the selected word line (operation S353), (iii) the first weak word line WWL1 of the first word line that is adjacent to the unselected sub-block (operation S355), (iv) the second boundary word line BWL2 of the second word line of the unselected sub-block that is adjacent to at least one second programming word line (operation S357), and (v) the second weak word line WWL2 of the second word line that is adjacent to the selected sub-block (operation S359).

[0062] exist Figure 2A and Figure 2BIn a read operation, a voltage is applied to the adjacent word line (AWL). The adjacent word line AWL can be significantly affected by read interference and can be the target of reliability verification operations. The location of the adjacent word line AWL can vary based on the voltage level applied to the word line during the read operation. For example, when the voltage level of the read voltage applied to an unselected word line is greater than the voltage level of the read voltage applied to a selected word line, one or more word lines adjacent to the selected word line can be considered adjacent word lines, and reliability verification operations can be performed on these adjacent word lines. Conversely, when the voltage level of the read voltage applied to an unselected word line is equal to or less than the voltage level of the read voltage applied to the selected word line, one or more word lines adjacent to the selected word line can be excluded from the target word lines of the reliability verification operation.

[0063] exist Figure 2A and Figure 2B In this context, the weak word line (WWL) can be the target of a reliability verification operation because the WWL can be significantly affected by read interference due to differences in the aperture spacing of the physical configuration of sub-blocks. In an example embodiment, depending on the manufacturing process of the non-volatile memory device, the weak word line may include multiple weak word lines. The reliability verification operation can be performed on all of the multiple weak word lines, or it can be performed on one of the multiple weak word lines randomly selected. The weak word line may be referred to as a sub-target word line.

[0064] exist Figure 2A and Figure 2B In this context, the boundary word line (BWL) can be the target of reliability verification operations because, due to its physical proximity to the programming word line, the BWL can be significantly affected by read interference.

[0065] Furthermore, when a physical block is divided into three or more sub-blocks, the storage controller 50 can adaptively determine target word lines based on the programming progress status of the selected sub-blocks and one or more unselected sub-blocks, and can sequentially perform reliability verification operations on at least one target word line of the selected sub-blocks and at least one target word line of each of the one or more unselected sub-blocks. In this case, the number of target word lines can vary based on a combination of the programming progress status of the selected sub-blocks, the programming progress status of the first unselected sub-blocks, and the programming progress status of the second unselected sub-blocks.

[0066] Figure 3 This illustrates an example embodiment in Figure 1 A flowchart illustrating an example of sequentially performing reliability verification operations.

[0067] Reference Figure 3In order to sequentially perform reliability verification operations (operation S400), the storage controller 50 can select the Nth target word line from the K target word lines (operation S410). Here, N can be 1. The storage controller 50 can perform a reliability verification operation on the Nth target word line (operation S420) and determine whether to reclaim the Nth target word line based on the error count obtained through the reliability verification operation (operation S430).

[0068] When it is determined that the Nth target word line will not be reclaimed (No in S430), the storage controller 50 determines whether N is greater than K (operation S440). When N is less than K (No in S440), the storage controller 50 increments N by 1 (N = N + 1) and repeats operations S420, S430, and S440.

[0069] When it is determined that the Nth target word line is reclaimed (Yes in S430), the storage controller 50 can register the selected sub-blocks including the Nth target word line and determine the corresponding sub-blocks as reclaimed sub-blocks (S470). When the (N+1)th target word line is included in the selected sub-blocks including the Nth target word line, the reliability verification operation for the (N+1)th target word line can be skipped, and the reliability verification operation can be performed on the (N+2)th target word line of the unselected sub-blocks.

[0070] When N is greater than K (as in S440), the storage controller 50 can terminate the reliability verification operation (S450).

[0071] Figure 4 This shows a memory block divided into sub-blocks and target word lines for the sub-blocks.

[0072] Reference Figure 4 A physical memory block can be divided into a first sub-block SBa and a second sub-block SBb. The first sub-block SBa can be a selected sub-block, and the second sub-block SBb can be an unselected sub-block. The first sub-block SBa can be stacked on top of the second sub-block SBb in a substrate.

[0073] Figure 4 Table TB shows the target word lines for which reliability verification operations are to be performed in the first subblock SBa and the second subblock SBb. The first target word line (N=1) can be the adjacent word line AWL in the first subblock SBa that is adjacent to the selected word line, the second target word line (N=2) can be the first weak word line WWL1 in the first word line of the first subblock SBa that is physically adjacent to the second subblock SBb, and the third target word line (N=3) can be the second weak word line WWL2 in the second word line of the second subblock SBb that is physically adjacent to the first subblock SBa.

[0074] The number of target word lines in the first subblock SBa and the second subblock SBb to which reliability verification operations are to be performed can vary based on the programming progress status of each of the first subblock SBa and the second subblock SBb.

[0075] Figure 5A and Figure 5B Each of the example embodiments is shown separately. Figure 3 Examples of operations.

[0076] Reference Figure 4 and Figure 5A The storage controller 50 can set the adjacent word line AWL in the first sub-block SBBa that is adjacent to the selected word line as the first target word line (N = 1) (operation S411), perform a reliability verification operation on the adjacent word line AWL in the first sub-block SBBa (operation S421), and determine whether to reclaim the adjacent word line AWL in the first sub-block SBBa based on the result of the reliability verification operation (operation S430). When it is determined to reclaim the adjacent word line AWL in the first sub-block SBBa (yes in S430), the first sub-block SBBa is reclaimed (operation S471). The reliability verification operation on the first weak word line WWL1 in the first word line of the first sub-block SBBa that is physically adjacent to the second sub-block SBb can be skipped, and the second weak word line WWL2 in the second word line of the second sub-block SBb that is physically adjacent to the first sub-block SBBa can be set as the next target word line (N = 3).

[0077] Reference Figure 4 and Figure 5B The storage controller 50 can set the adjacent word line AWL in the first sub-block SBA that is adjacent to the selected word line as the first target word line (N = 1) (operation S411), perform a reliability verification operation on the adjacent word line AWL in the first sub-block SBA (operation S421), and determine whether to reclaim the adjacent word line AWL in the first sub-block SBA based on the result of the reliability verification operation (operation S430). When it is determined that the adjacent word line AWL in the first sub-block SBA will not be reclaimed (No in S430), it can determine whether N is greater than K (operation S440), and when N is equal to or less than K (No in S440), the first weak word line WWL1 in the first word line of the first sub-block SBA that is physically adjacent to the second sub-block SBb can be set as the next target word line (N = 2).

[0078] Figure 6 Examples of open sub-blocks, closed sub-blocks, and erase sub-blocks according to an example embodiment are shown.

[0079] Reference Figure 6A subblock can be identified as an open subblock OP_SB when it includes at least one erased page (erase word line). An open subblock OP_SB can include at least one erased page (erase word line) and at least one valid page (programming word line).

[0080] A subblock can be identified as a closed subblock CL_SB when it contains only valid pages (programming word lines) and no erased pages (erase word lines). A subblock can be identified as an erased subblock ER_SB when it contains only erased pages (erase word lines).

[0081] That is, each of the selected and unselected sub-blocks according to the example embodiment may be in an open state, a closed state, or an erased state based on the programming progress state of each of the selected and unselected sub-blocks.

[0082] Figure 7 It is a graph showing the changes in the distribution of memory cells obtained through repeated read operations.

[0083] Reference Figure 7 In the attached figure, reference numeral 21 corresponds to the initial memory cell distribution based on the threshold voltage, with the horizontal axis indicating the threshold voltage "Vth" and the vertical axis indicating the number of memory cells. For example, when the memory cells are multi-level cells programmed with three bits, the memory cells can be in one of the following states: erase state E, first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6, and seventh programming state P7.

[0084] To read programming data from a memory cell, the non-volatile memory device 100 may use multiple read voltages VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, and VRD7, as well as a read pass voltage VPASS. For example, to read programming data from a memory cell coupled to a selected word line, the non-volatile memory device 100 may sequentially apply one or more of the read voltages VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, and VRD7 to the selected word line, and may apply the read pass voltage VPASS to an unselected word line. The voltage level of the read pass voltage VPASS may be greater than the voltage level of each of the read voltages VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, and VRD7.

[0085] Figure 23 corresponds to the memory cell distribution obtained by the change caused by repeated read operations, with the horizontal axis indicating the threshold voltage "Vth" and the vertical axis indicating the number of memory cells. During a read operation, because one or more of the read voltages VRD1, VRD2, VRD3, VRD4, VRD5, VRD6, and VRD7 are applied to the selected word line, and the read voltage VPASS is applied to the unselected word line, the distribution of memory cells coupled to the unselected word line of the selected and unselected sub-blocks may expand, and therefore the error count may increase.

[0086] However, in the method of operating the storage controller according to the example embodiment, in addition to the target word lines among the word lines of the selected sub-blocks that are sensitive to read interference, the storage controller 50 may also designate at least one word line among the word lines of the unselected sub-blocks that are sensitive to read interference as an additional target word line. A reliability verification operation can be performed on the target word lines and the additional target word lines, and a recycling operation can be performed based on the result of the reliability verification operation. Therefore, the storage controller 50 can enhance reliability and performance.

[0087] Figure 8 This is a block diagram illustrating a storage device according to an example embodiment.

[0088] Reference Figure 8 The storage device (i.e., memory system) 10 may include a storage controller 50 and a non-volatile memory device 100.

[0089] In the example embodiment, each of the memory controller 50 and the non-volatile memory device 100 may be provided as a chip, a package, or a module. Alternatively, the memory controller 50 and the non-volatile memory device 100 may be packaged in one of a variety of packages.

[0090] The non-volatile memory device 100 can perform erase, program, or write operations under the control of the memory controller 50. The non-volatile memory device 100 receives commands (signals) CMD, addresses (signals) ADDR, and data from the memory controller 50 via input / output lines to perform these operations. Additionally, the non-volatile memory device 100 can receive control signals CTRL from the memory controller 50 via control lines. Furthermore, the non-volatile memory device 100 can receive power PWR from the memory controller 50 via power lines.

[0091] Figure 9 This illustrates an example embodiment. Figure 8 A block diagram of an example storage controller in a storage device.

[0092] Reference Figure 9The storage controller 50 may include a processor 60, an error correction code (ECC) engine 70, an on-chip memory 80, an advanced encryption standard (AES) engine 90, a host interface 92, a ROM 94, a reliability manager 96, a recycling register 97, and a memory interface 98 connected via a bus 55.

[0093] Processor 60 can control the overall operation of storage controller 50. Processor 60 can control ECC engine 70, on-chip memory 80, AES engine 90, host interface 92, ROM 94, reliability manager 96, recycling register 97, and memory interface 98. Processor 60 may include one or more cores (e.g., homogeneous multi-core or heterogeneous multi-core). Processor 60 may be or include at least one of, for example, a central processing unit (CPU), image signal processing unit (ISP), digital signal processing unit (DSP), graphics processing unit (GPU), vision processing unit (VPU), and neural processing unit (NPU). Processor 60 can execute various applications loaded onto on-chip memory 80 (e.g., flash translation layer (FTL) 81 and firmware).

[0094] The on-chip memory 80 can store various application programs that can be executed by the processor 60. The on-chip memory 80 can operate as a cache memory adjacent to the processor 60. The on-chip memory 80 can store commands, addresses, and data to be processed by the processor 60, or it can store the processing results of the processor 60. The on-chip memory 80 can be a storage medium or working memory, including, for example, latches, registers, static random access memory (SRAM), dynamic random access memory (DRAM), thyristor random access memory (TRAM), tightly coupled memory (TCM), etc.

[0095] Processor 60 can execute FTL 81 loaded onto on-chip memory 80. FTL 81 can be loaded onto on-chip memory 80 as firmware or a program stored in non-volatile memory device 100. FTL 81 can manage the mapping between logical addresses provided from the host and physical addresses of non-volatile memory device 100, and can include an address mapping table manager that manages and updates the address mapping table. FTL 81 can further perform garbage collection operations, wear leveling operations, and the aforementioned address mapping. FTL 81 can be executed by processor 60 to address one or more of the following aspects of non-volatile memory device 100: impossibility of rewriting or in-situ writing, memory cell lifetime, finite number of program-erase (PE) cycles, and erase speed slower than write speed.

[0096] The memory cells of the non-volatile memory device 100 may have physical characteristics where the threshold voltage distribution varies due to factors such as programming elapsed time, temperature, programming interference, and read interference. For example, due to the aforementioned reasons, the data stored in the non-volatile memory device 100 may become corrupted.

[0097] The storage controller 50 can utilize various error correction techniques to correct such errors. For example, the storage controller 50 may include an ECC engine 70. The ECC engine 70 can correct errors occurring in the data stored in the non-volatile memory device 100. The ECC engine 70 may include an ECC encoder 71 and an ECC decoder 73. The ECC encoder 71 can perform ECC encoding operations on the data to be stored in the non-volatile memory device 100. The ECC decoder 73 can perform ECC decoding operations on the data read from the non-volatile memory device 100 during normal read operations and reliability verification operations, and can provide the processor 60 and / or the reliability manager 96 with the address of the word line where the relevant error count is greater than the reference error count based on the result of the ECC decoding.

[0098] ROM 94 can store various information in the firmware, which is required for the operation of storage controller 50.

[0099] The AES engine 90 can perform at least one of encryption and decryption operations on data input to the storage controller 50 using a symmetric key algorithm. Although not shown in detail, the AES engine 90 may include an encryption module and a decryption module. For example, the encryption and decryption modules can be implemented as separate modules. As another example, a single module capable of performing both encryption and decryption operations can be implemented in the AES engine 90.

[0100] Storage controller 50 can communicate with a host via host interface 92. For example, host interface 92 may include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), High-Speed ​​PCI, Advanced Technology Accessory (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), Mobile Industry Processor Interface (MIPI), High-Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), etc. Storage controller 50 can communicate with non-volatile memory device 100 via memory interface 98.

[0101] The Reliability Manager 96 can perform reliability verification operations on target word lines of selected and unselected sub-blocks and manage these operations. (See reference...) Figure 1The reliability manager 96 can perform and / or manage reliability verification operations by using a read interference level monitoring scheme or an OVS algorithm.

[0102] When the error count obtained through the reliability verification operation is greater than the reference error count, the reliability manager 96 can directly or through the processor 60 register the corresponding sub-block in the recycling register as a recycling sub-block.

[0103] Figure 10 This illustrates an example embodiment. Figure 8 A block diagram of an example of a non-volatile memory device in a storage device.

[0104] Reference Figure 10 The non-volatile memory device 100 may include a memory cell array 200 and peripheral circuitry 300. The peripheral circuitry 300 may include an address decoder 430, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, and a voltage generator 500.

[0105] The memory cell array 200 can be coupled to the address decoder 430 via the serial select line SSL, multiple word lines WL, and the ground select line GSL. Additionally, the memory cell array 200 can be coupled to the page buffer circuit 410 via multiple bit lines BL. The memory cell array 200 may include multiple non-volatile memory cells coupled to multiple word lines WL and multiple bit lines BL.

[0106] In some example embodiments, the memory cell array 200 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional (or vertical) structure. In this case, the memory cell array 200 may include vertically oriented vertical cell strings, such that at least one memory cell is located above another memory cell.

[0107] The control circuit 450 can receive command (signal) CMD and address (signal) ADDR from the memory controller 50, and control the erase cycle, programming cycle, and read operation of the non-volatile memory device 200 based on the command signal CMD and the address signal ADDR. The programming cycle may include programming operations and programming verification operations. The erase cycle may include erase operations and erase verification operations. The read operation may include normal read operations and reliability verification operations.

[0108] For example, control circuit 450 can generate control signal CTL based on command signal CMD to control voltage generator 500, and can generate page buffer control signal PCTL to control page buffer circuit 410. Control circuit 450 can generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 450 can provide row address R_ADDR to address decoder 430 and column address C_ADDR to data I / O circuit 420. Address signal ADDR or row address R_ADDR can be referred to as access address.

[0109] Address decoder 430 can be coupled to memory cell array 200 via serial select line SSL, multiple word lines WL, and ground select line GSL. During programming or reading operations, address decoder 430 can determine one of the multiple word lines WL as the selected word line based on row address R_ADDR, and determine the remaining multiple word lines WL as unselected word lines.

[0110] Voltage generator 500 can generate the word line voltage VWL required for the operation of non-volatile memory device 200 based on control signal CTL. Voltage generator 500 can receive power PWR from memory controller 50. Word line voltage VWL can be applied to multiple word lines WL via address decoder 430.

[0111] For example, during an erase operation, voltage generator 500 can apply an erase voltage to the channel of the cell string of the memory block and can apply a ground voltage to the word line of the sub-block to be erased. During an erase verification operation, voltage generator 500 can apply an erase verification voltage to the word line of the sub-block to be erased, or apply the erase verification voltage sequentially to the word lines based on the word lines.

[0112] For example, during programming operations, voltage generator 500 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Additionally, during programming verification operations, voltage generator 500 can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line.

[0113] Page buffer circuit 410 can be coupled to memory cell array 200 via multiple bit lines BL. Page buffer circuit 410 may include multiple page buffers. Page buffer circuit 410 can temporarily store data to be programmed in a selected page or data read from a selected page.

[0114] Data I / O circuit 420 can be coupled to page buffer circuit 410 via multiple data lines DL. During programming operations, data I / O circuit 420 can receive programming data from memory controller 50 and provide programming data DATA to page buffer circuit 410 based on the column address C_ADDR received from control circuit 450. During read operations, data I / O circuit 420 can provide read data DATA stored in page buffer circuit 410 to memory controller 50 based on the column address C_ADDR received from control circuit 450.

[0115] Figure 11 Schematic illustration according to an example embodiment Figure 10 The structure of non-volatile memory devices.

[0116] Reference Figure 11 The non-volatile memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in the vertical direction VD. The second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD, and therefore, the second semiconductor layer L2 may be close to the substrate.

[0117] In the example embodiment, Figure 10 The memory cell array 200 can be formed (or provided) on the first semiconductor layer L1. Figure 10 The peripheral circuitry 300 can be formed (or provided) on the second semiconductor layer L2. Therefore, the non-volatile memory device 100 can have a structure where the memory cell array 200 is located on the peripheral circuitry 300, i.e., a cell-on-periphery (COP) structure. The COP structure can effectively reduce the horizontal area and improve the integration density of the non-volatile memory device 100.

[0118] In an example embodiment, the second semiconductor layer L2 may include a substrate, and peripheral circuitry 300 may be formed in the second semiconductor layer L2 by forming transistors and metal patterns for wiring the transistors on the substrate. After the peripheral circuitry 300 is formed on the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 200 may be formed, and metal patterns for connecting word lines WL and bit lines BL of the memory cell array 200 to the peripheral circuitry 300 formed in the second semiconductor layer L2 may be formed. For example, word lines WL may extend in a first horizontal direction HD1, and bit lines BL may extend in a second horizontal direction HD2.

[0119] As the number of memory cell levels in the memory cell array 200 increases with the development of semiconductor technology, that is, as the number of stacked word lines WL increases, the area of ​​the memory cell array 200 decreases, and therefore, the area of ​​the peripheral circuitry 300 also decreases. According to an embodiment, in order to reduce the area occupied by the page buffer circuit 410, the page buffer circuit 410 may have a structure in which the page buffer cells and cache latches are separated from each other, and the sensing nodes included in each page buffer cell can be jointly connected to a combined sensing node.

[0120] Figure 12 This illustrates an example embodiment. Figure 10 A block diagram of an example memory cell array in a non-volatile memory device.

[0121] Reference Figure 12 The memory cell array 200 may include multiple memory blocks BLK1 to BLKz. Here, z is a natural number greater than two. Memory blocks BLK1 to BLKz extend along a first horizontal direction HD1, a second horizontal direction HD2, and a vertical direction VD. In some example embodiments, memory blocks BLK1 to BLKz are... Figure 10 The address decoder 430 selects the memory block BLK corresponding to the block address from memory blocks BLK1 to BLKz.

[0122] The first horizontal direction HD1 and the second horizontal direction HD2 intersect each other and are substantially parallel to the upper surface of the substrate, and the vertical direction VD is substantially perpendicular to the upper surface of the substrate.

[0123] Figure 13 This illustrates an example embodiment. Figure 12 A circuit diagram of one of the memory blocks.

[0124] Figure 13 The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. Here, i can be one of 1 to z. For example, multiple strings of memory cells included in the memory block BLKi can be formed in a vertical direction VD perpendicular to the substrate SUB.

[0125] Reference Figure 13The memory block BLKi may include multiple (memory) cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 (hereinafter referred to as NS11 to NS33) coupled between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9, MC10, MC11, and MC12 (hereinafter referred to as MC1 to MC12), and a ground select transistor GST.

[0126] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3 (hereinafter referred to as SSL1 to SSL3). Multiple memory cells MC1 to MC12 can be connected to the corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, WL9, WL10, WL11, and WL12 (hereinafter referred to as WL1 to WL12). The ground select transistor GST can be connected to the corresponding ground select lines CSL1, CSL2, and GSL3 (hereinafter referred to as GSL1 to GSL3). The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0127] Word lines with the same height (e.g., word line WL1) can be connected together, and ground select lines GSL1 to GSL3 and serial select lines SSL1 to SSL3 can be separated.

[0128] According to some embodiments, the memory block BLKi can be divided into multiple sub-blocks indicated by representative sub-blocks SB1, SB2, and SB3, each sub-block being smaller than the memory block BLKi. For example... Figure 13 As shown, sub-blocks SB1, SB2, and SB3 can be divided along the word line direction. In some embodiments, sub-blocks SB1, SB2, and SB3 can be divided based on bit lines or string select lines. Sub-blocks SB1, SB2, and SB3 in memory block BLKi can be erased independently of the reference used to divide memory block BLKi into sub-blocks.

[0129] For example, among the memory cells included in memory block BLKi, subblock SB1 includes memory cells coupled to word lines WL1, WL2, WL3, and WL4; subblock SB2 includes memory cells coupled to word lines WL5, WL6, WL7, and WL8; and subblock SB3 includes memory cells coupled to word lines WL9, WL10, WL11, and WL12. Memory cells included in subblock SB1 can be selected and erased independently of the remaining subblocks SB2 and SB3, and vice versa. One or more of subblocks SB1, SB2, and SB3 can be selected and erased simultaneously or at different times. Figure 11 The address decoder 430 in the memory can provide bias for erasing memory cells on a sub-block basis.

[0130] Figure 14 Show Figure 13 An example of the structure of a string of cells in a memory block.

[0131] Reference Figure 13 and Figure 14 The post PL is disposed on the substrate SUB, such that the post PL extends in a direction perpendicular to the substrate SUB to contact the substrate SUB. Figure 14 Each of the ground select line GSL, word lines WL1 to WL12, and string select line SSL shown can be formed of a conductive material (e.g., a metallic material) parallel to the substrate SUB. The pillar PL can be in contact with the substrate SUB via the conductive material forming the string select line SSL1, word lines WL1 to WL12, and ground select line GSL1. Subblock SB1 may include memory cells coupled to word lines WL1, WL2, WL3, and WL4. Subblock SB3 may include memory cells coupled to word lines WL9, WL10, WL11, and WL12.

[0132] Figure 14 The diagram also shows a cross-sectional view taken along line EE'. In some example embodiments, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylinder BD. The air gap AG may be defined within the body BD.

[0133] The body BD may include P-type silicon and may be the region where the channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A barrier insulating layer BI may be disposed between the first word line WL1 and the pillar PL. The body BD, tunnel insulating layer TI, charge trapping layer CT, barrier insulating layer BI, and first word line WL1 may constitute or be included in a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistor SST, ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0134] Figure 15 This illustrates an example embodiment. Figure 10 A block diagram of the control circuitry in a non-volatile memory device.

[0135] Reference Figure 15 The control circuit 450 may include a command decoder 460, an address buffer 470, a control signal generator 480, and a status signal generator 485.

[0136] Command decoder 460 can decode command CMD and provide the decoded command D_CMD to control signal generator 480 and status signal generator 485.

[0137] Address buffer 470 can receive address (signal) ADDR, provide row address R_ADDR to address decoder 430, and provide column address C_ADDR to data I / O circuit 420.

[0138] The control signal generator 480 can receive the decoding command D_CMD, generate the control signal CTL based on the operation guided by the decoding command D_CMD, provide the control signal CTL to the voltage generator 500, generate the page buffer control signal PCTL, and provide the page buffer control signal PCTL to the page buffer circuit 410.

[0139] The status signal generator 485 can receive the decoding command D_CMD, monitor the operation indicated by the decoding command D_CMD, and change the status signal nR / B to a ready state or a busy state based on whether the operation indicated by the decoding command D_CMD has been completed.

[0140] Figure 16 This illustrates an example embodiment. Figure 10 A block diagram of an example voltage generator in a non-volatile memory device.

[0141] refer to Figure 16The voltage generator 500 may include a high-voltage HV generator 510 and a low-voltage LV generator 520. The voltage generator 500 may also include a negative-voltage NV generator 530.

[0142] The high-voltage generator 510 can respond to the first control signal CTL1 and generate the programming voltage PGM, the programming pass voltage VPPASS, the verification pass voltage VVPASS, the read pass voltage VRPASS, and the erase voltage VERS according to the operation guided by the command CMD. The programming pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS can be included in the pass voltage VPASS.

[0143] The programming voltage VPGM can be applied to the selected word line, the programming pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS can be applied to the unselected word line, and the erase voltage VERS can be applied to the channel of the cell string. The first control signal CTL1 may include multiple bits indicating the operation directed by the decoding command D_CMD.

[0144] The low voltage generator 520 can respond to the second control signal CTL2 to generate the programming verification voltage VPV, the read voltage VRD, and the erase verification voltages VEV1 and VEV2 according to the operation indicated by the command CMD.

[0145] The programming verification voltage VPV, read voltage VRD, and erase verification voltages VEV1 and VEV2 can be applied to the word lines of the selected sub-block according to the operation of the non-volatile memory device 100. The second control signal CTL2 may include multiple bits indicating the operation directed by the decoding command D_CMD.

[0146] The negative voltage generator 530 can respond to a third control signal CTL3 to generate a first negative voltage VNEG1 and a second negative voltage VNEG2 with negative levels according to the operation guided by the command CMD. The third control signal CTL3 may include multiple bits indicating the operation guided by the decoding command D_CMD. The first negative voltage VNEG1 and the second negative voltage VNEG2 can be used for programming operations.

[0147] Figure 17 According to the example embodiment Figure 10 A schematic diagram showing the connection between the memory cell array and the page buffer circuit.

[0148] Reference Figure 17The memory cell array 200 may include first to nth cell strings NS1, NS2, NS3, ..., NSn. Each of the first to nth cell strings NS1, NS2, NS3, ..., NSn may include a ground selection transistor GST connected to the ground selection line GSL, a plurality of memory cells MC connected to the first to mth word lines WL1, ..., WLm respectively, and a string selection transistor SST connected to the string selection line SSL. The ground selection transistor GST, the plurality of memory cells MC, and the string selection transistor SST may be connected in series with each other. In this case, n may be an integer greater than three, and m may be a positive integer.

[0149] Page buffer circuit 410 may include first to nth page buffer units PBU1, PBU2, PBU3, ..., PBUn. First page buffer unit PB1 may be connected to first unit string NS1 via first bit line BL1, and nth page buffer unit PBUn may be connected to nth unit string NSn via nth bit line BLn. In this case, n may be a positive integer. For example, n may be 8, and page buffer circuit 410 may have an eight-level page buffer unit structure (or, first page buffer unit PBU1, second page buffer unit PBU2, third page buffer unit PBU3, ..., nth page buffer unit PBUn) arranged in a line. For example, first to nth page buffer units PBU1, PBU2, PBU3, ..., PBUn may be arranged in a row along the extension direction of first to nth bit lines BL1, BL2, BL3, ..., BLn.

[0150] Page buffer circuit 410 may further include first cache latches to nth cache latches CL1, CL2, CL3, ..., CLn, respectively, corresponding to the first page buffer unit to the nth page buffer unit PBU1, PBU2, PBU3, ..., PBUn. For example, page buffer circuit 410 may have an eight-level cache latch structure or a structure in which the first cache latches to the nth cache latches CL1, CL2, CL3, ..., CLn are arranged in a single line. For example, the first cache latches to the nth cache latches CL1, CL2, CL3, ..., CLn may be arranged in a single line along the extension direction of the first bit line to the nth bit line BL1, BL2, BL3, ..., BLn.

[0151] The sensing nodes of each of the first page buffer units to the nth page buffer units PBU1, PBU2, PBU3, ..., PBUn can be jointly connected to the combined sensing node SOC. Additionally, the first cache latches to the nth cache latches CL1, CL2, CL3, ..., CLn can be jointly connected to the combined sensing node SOC. Therefore, the first page buffer units to the nth page buffer units PBU1, PBU2, PBU3, ..., PBUn can be connected to the first cache latches to the nth cache latches CL1, CL2, CL3, ..., CLn via the combined sensing node SOC.

[0152] Figure 18A , Figure 18B and Figure 18C The positions of the boundary word lines based on the programming progress status of selected and unselected sub-blocks, according to the example embodiment, are shown respectively.

[0153] Boundary word lines can be word lines that are physically adjacent to programming word lines.

[0154] exist Figure 18A , Figure 18B and Figure 18C In each of the above, it is assumed that a particular memory block is divided into a first sub-block SBa and a second sub-block SBb, the first sub-block SBa being the selected sub-block and the second sub-block SBb being the unselected sub-block, and the first sub-block SBa being stacked on top of the second sub-block SBb in the vertical direction VD.

[0155] Reference Figure 18A When the first subblock SBa and the second subblock SBb are in the closed state (e.g., the programming state) as indicated by reference numeral 611 in the figure, there is no boundary word line BWL.

[0156] Additionally, when the first sub-block SBa and the second sub-block SBb, as shown by reference numeral 613 in the attached figure, are in the erase state, there is no boundary word line BWL.

[0157] Additionally, as shown by reference numeral 615 in the attached figure, when the first sub-block SBBa is in a closed state and the second sub-block SBb is in an erased state, the word line in the second word line of the second sub-block SBb that is physically adjacent to the programming word line of the first sub-block SBBa can correspond to the boundary word line BWL. That is, the uppermost word line in the second word line of the second sub-block SBb can correspond to the boundary word line BWL.

[0158] refer to Figure 18BWhen the first sub-block SBBa is in the erase state and the second sub-block SBb is in the closed state, as shown by reference numeral 621 in the attached figure, the word line in the first word line of the first sub-block SBBa that is physically adjacent to the programming word line of the second sub-block SBb can correspond to the boundary word line BWL. That is, the lowest word line in the first word line of the first sub-block SBBa can correspond to the boundary word line BWL.

[0159] Additionally, as shown by reference numeral 623 in the attached figure, when the first sub-block SBA is in an open state (e.g., a portion of the first word line of the first sub-block SBA is programmed) and the second sub-block SBb is in an erase state, the erase word line physically adjacent to the programming word line of the first sub-block SBA can correspond to the boundary word line BWL. That is, the uppermost erase word line among the erase word lines of the first sub-block SBA can correspond to the boundary word line BWL.

[0160] Furthermore, as shown by reference numeral 625 in the attached figure, when the first sub-block SBB is in the erase state and the second sub-block SBb is in the open state, the erase word lines in the second sub-block SBb that are physically adjacent to the programming word lines, and the word lines in the first word lines of the first sub-block SBB that are physically adjacent to the programming word lines of the second sub-block SBb, can correspond to the boundary word lines (BWL). That is, the uppermost erase word line in the second sub-block SBb and the lowermost word line in the first word lines of the first sub-block SBB can correspond to the boundary word lines (BWL).

[0161] Furthermore, as shown by reference numeral 627 in the attached figure, when the first sub-block SBBa is in the open state and the second sub-block SBb is in the erase state, the erase word lines in the first sub-block SBBa that are physically adjacent to the programming word lines of the first sub-block SBBa, and the word lines in the second word lines of the second sub-block SBb that are physically adjacent to the programming word lines of the first sub-block SBBa, can correspond to the boundary word lines (BWL). That is, the lowest erase word line in the erase word lines of the first sub-block SBBa and the highest word line in the second word lines of the second sub-block SBb can correspond to the boundary word lines (BWL).

[0162] exist Figure 18B In the accompanying drawings, reference numerals 623 and 625 correspond to the T2B programming scheme, where programming operations are performed from the top word line to the bottom word line of the sub-block, while reference numeral 627 corresponds to the B2T programming scheme, where programming operations are performed from the bottom word line to the top word line of the sub-block. That is, the position of the boundary word line (BWL) can vary based on the programming order.

[0163] refer to Figure 18CWhen the first sub-block SBA is in an open state (e.g., a portion of the first word line of the first sub-block SBA is programmed) and the second sub-block SBb is in a closed state (as shown by reference numeral 631 in the figure), the erase word lines in the first sub-block SBA that are physically adjacent to the programming word lines of the first sub-block SBA and the erase word lines that are physically adjacent to the programming word lines of the second sub-block SBb can correspond to boundary word lines (BWL). That is, the uppermost and lowermost erase word lines in the erase word lines of the first sub-block SBA can correspond to boundary word lines (BWL).

[0164] When the first subblock SBBa is in a closed state and the second subblock SBb is in an open state (e.g., a portion of the second word line of the second subblock SBb is programmed), as shown by reference numeral 633, the erase word line in the erase word line of the second subblock SBb that is physically adjacent to the programming word line of the second subblock SBb can correspond to the boundary word line BWL. That is, the uppermost erase word line among the erase word lines of the second subblock SBb can correspond to the boundary word line BWL.

[0165] When the first sub-block SBa and the second sub-block SBb are in an open state (e.g., a portion of the first word line of the first sub-block SBa is programmed and a portion of the second word line of the second sub-block SBb is programmed), as shown by reference numeral 635, the erase word lines in the first sub-block SBa that are physically adjacent to the programming word lines of the first sub-block SBa and the erase word lines in the second sub-block SBb that are physically adjacent to the programming word lines of the second sub-block SBb can correspond to boundary word lines (BWL). That is, the uppermost erase word line in the first sub-block SBa and the uppermost erase word line in the second sub-block SBb can correspond to boundary word lines (BWL).

[0166] Figure 19 The location of the boundary word line is shown according to an example embodiment, based on the programming progress status of selected and unselected sub-blocks.

[0167] exist Figure 19 In this context, it is assumed that a specific memory block is divided into a first sub-block SBa, a second sub-block SBb, and a third sub-block SBc. The first sub-block SBa is stacked on the second sub-block SBb in the vertical direction VD, and the second sub-block SBb is stacked on the third sub-block SBc in the vertical direction VD.

[0168] refer to Figure 19When the first sub-block SBa and the third sub-block SBc are in the erase state and the second sub-block SBb is in the closed state, as shown by reference numeral 641 in the attached figure, the word lines in the first word lines of the first sub-block SBa that are physically adjacent to the programming word lines of the second sub-block SBb, and the word lines in the third word lines of the third sub-block SBc that are physically adjacent to the programming word lines of the second sub-block SBb, can correspond to the boundary word lines BWL. That is, the lowest word line in the first word lines of the first sub-block SBa and the highest word line in the third word lines of the third sub-block SBc can correspond to the boundary word lines BWL.

[0169] Figure 20 The location of the boundary word line is shown according to an example embodiment, based on the programming progress status of selected and unselected sub-blocks.

[0170] exist Figure 20 In this context, it is assumed that a specific memory block is divided into a first sub-block SBa, a second sub-block SBb, a third sub-block SBc, and a fourth sub-block SBd. The first sub-block SBa is stacked on the second sub-block SBb in the vertical direction VD, the second sub-block SBb is stacked on the third sub-block SBc in the vertical direction VD, and the third sub-block SBc is stacked on the fourth sub-block SBd in the vertical direction VD.

[0171] See Figure 20 When the first sub-block SBa and the third sub-block SBc are in a closed state, and the second sub-block SBb and the fourth sub-block SBd are in an erased state, as shown by reference numeral 651 in the attached figure, the word lines in the second word line of the second sub-block SBb that are physically adjacent to the programming word lines of the first sub-block SBa, the word lines in the second word line of the second sub-block SBb that are physically adjacent to the programming word lines of the third sub-block SBc, and the word lines in the fourth word line of the fourth sub-block SBd that are physically adjacent to the programming word lines of the third sub-block SBc can correspond to the boundary word lines BWL. That is, the uppermost and lowermost word lines in the second word line of the second sub-block SBb, and the uppermost word line in the fourth word line of the fourth sub-block SBd can correspond to the boundary word lines BWL.

[0172] When a specific memory block is divided into three or more sub-blocks (as referenced) Figure 19 and 20 When the selected sub-block is selected, the storage controller 50 or the reliability manager 96 can designate the adjacent word lines and weak word lines of the selected sub-block and the adjacent word lines and weak word lines of each unselected sub-block as target word lines, and can perform reliability verification operations on the target word lines in the order from the selected sub-block to the unselected sub-block.

[0173] Figure 21 It is used to describe Figure 13 A diagram illustrating the operational characteristics and reliability verification operations of the memory block.

[0174] exist Figure 21 In the graph portion, the horizontal axis represents the read count of memory block BLKi, and the vertical axis represents the number of error bits occurring in memory block BLKi (e.g., error count). In an embodiment, the read count may indicate the number of read operations performed on memory block BLKi.

[0175] In the embodiments described below, for ease of description, it may be assumed that the ratio of read counts to error bits for memory block BLKi is linear. However, this disclosure is not limited thereto. For example, depending on the physical characteristics and / or degradation state of memory block BLKi, the ratio of actual read counts to actual error bits may be non-linear, but is not limited thereto. Additionally, it is assumed that memory block BLKi is divided into sub-blocks SBa and SBb.

[0176] Additionally, the number of error bits detected by the reliability verification operation of the memory block BLKi (e.g., error count) can be referred to as "error information". For example, the memory controller 50 can perform a reliability verification operation on the memory block BLKi to obtain error information indicating the number of error bits included in the memory block BLKi, but is not limited thereto.

[0177] Furthermore, it can be assumed that the reliability manager 96 of the storage controller 50 performs reliability verification operations on the memory block BLKi at given intervals (e.g., uniform intervals). However, this disclosure is not limited thereto. For example, depending on the operating state of the storage device 10, the reliability verification operations on the memory block BLKi can be performed non-periodically. As an example, the reliability verification operations on the memory block BLKi can be performed at arbitrary or random intervals. In this case, the average value of any interval may correspond to a given interval, but is not limited thereto.

[0178] refer to Figure 9 and Figure 21 The storage controller 50 can repeatedly execute the read operation EXE on the memory block BLKi, thus increasing the read count of the memory block BLKi. In this case, the error bits (e.g., the error count) of the memory block BLKi may increase due to read interference associated with the repeatedly executed read operations.

[0179] To ensure the reliability of the data stored in memory block BLKi, the storage controller 50 or the reliability manager 96 can perform reliability verification operations at given intervals. For example, when the number of read operations on memory block BLKi has been repeated matches the 0th read count RC0, the storage controller 50 or the reliability manager 96 can perform a reliability (verification) operation on memory block BLKi. In this case, the 0th error information EB0 of memory block BLKi can be obtained.

[0180] Furthermore, when the number of read operations on the first memory block BLKi has been repeated to the first read count RC1 to the tenth read count RC10 of the first memory block BLKi, the storage controller 50 or the reliability manager 96 can perform a reliability verification operation. When a reliability verification operation is performed at each of the first read count RC1 to the tenth read count RC10, the first error information EB1 to the tenth error information EB10 of the memory block BLKi can be obtained respectively.

[0181] In an embodiment, a reliability verification operation performed at the tenth read count RC10 of memory block BLKi can determine that memory block BLKi includes error bits corresponding to the tenth error information EB10. In this case, the number of error bits corresponding to the tenth error information EB10 may correspond to a level exceeding the recycling reference level of memory block BLK1, at which point the block can be recycled. Thus, the reliability manager 96 can correct errors in the data stored in memory block BLKi and can program the corrected data into another memory block. This series of operations described above can be referred to as a "recycling operation".

[0182] As described above, the reliability manager 96 can determine the error level of the memory block BLKi by performing a reliability verification operation on the memory block BLKi at given intervals; when the error level (e.g., error count) of the memory block BLKi or the sub-block SBa exceeds (e.g., is greater than) a preset threshold (e.g., reference error count), the reliability manager 96 can perform a recycling operation on the memory block BLKi or the sub-block SBa.

[0183] Therefore, in addition to the target word lines among the word lines of the selected sub-blocks that are sensitive to read interference, the storage device according to the example embodiment can also designate at least one word line among the word lines of the unselected sub-blocks that are sensitive to read interference as an additional target word line. A reliability verification operation can be performed on the target word lines and the additional target word lines, and a recycling operation can be performed based on the result of the reliability verification operation. Therefore, the storage device can enhance reliability and performance.

[0184] Figure 22 An example embodiment is shown. Figure 8 Example of a connection between a storage controller and a non-volatile memory device in a storage device.

[0185] Reference Figure 22 The storage device 10a may include a non-volatile memory device 100 and a storage controller 50. Figure 22 The interface between the non-volatile memory device 100 and the memory controller 50 is shown in detail.

[0186] The non-volatile memory device 100 may include first to eighth pins P11, P12, P13, P14, P15, P16, P17 and P18, interface circuitry 105, control circuitry 450, and memory cell array 200. Interface circuitry 105 may be referred to as the first interface circuit or memory interface circuit.

[0187] Interface circuit 105 can receive a chip enable signal nCE from memory controller 50 via first pin P11. Interface circuit 105 can send signals to and receive signals from memory controller 50 via second to eighth pins P12 to P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), interface circuit 105 can send signals to and receive signals from memory controller 50 via second to eighth pins P12 to P18.

[0188] Interface circuit 105 can receive command latch enable signal CLE, address latch enable signal ALE, and write enable signal nWE from memory controller 50 via pins P12 to P14. Interface circuit 105 can receive data signal DQ from memory controller 50 via pin P17, or can send data signal DQ to memory controller 50. Command CMD, address ADDR, and data DTA can be sent via data signal DQ. For example, data signal DQ can be sent via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals DQ.

[0189] Interface circuit 105 can obtain command CMD from data signal DQ received in the enable portion (e.g., high state) of command latch enable signal CLE based on the switching time of write enable signal nWE. Interface circuit 105 can obtain address ADDR from data signal DQ received in the enable portion (e.g., high state) of address latch enable signal ALE based on the switching time of write enable signal nWE.

[0190] In some example embodiments, the write enable signal nWE can be held statically (e.g., high or low) and can toggle between high and low. For example, the write enable signal nWE can be toggled during the transmission of command CMD or address ADDR. Therefore, interface circuitry 105 can obtain command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0191] Interface circuit 105 can receive the read enable signal nRE from memory controller 50 via pin 5 P15. Interface circuit 105 can receive the data strobe signal DQS from memory controller 50 via pin 6 P16, or it can send the data strobe signal DQS to memory controller 50.

[0192] In the data output operation of the non-volatile memory device 100, the interface circuit 105 may receive a read enable signal nRE switched via pin 5 P15 before outputting data DTA. The interface circuit 105 may generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, the interface circuit 105 may generate the data strobe signal DQS based on the switching start time of the read enable signal nRE, and the data strobe signal DQS may begin switching after a predetermined delay (e.g., tDQSRE). The interface circuit 105 may transmit a data signal DQ including the data DTA based on the switching time of the data strobe signal DQS. Therefore, the data DTA may be aligned with the switching time of the data strobe signal DQS and may be sent to the memory controller 50.

[0193] In the data input operation of the non-volatile memory device 100, when a data signal DQ including data DTA is received from the memory controller 50, the interface circuit 105 can receive a switched data strobe signal DQS and the data DTA from the memory controller 50. The interface circuit 105 can obtain the data DTA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the interface circuit 105 can sample the data signal DQ at the rising and falling edges of the data strobe signal DQS and obtain the data DTA.

[0194] Interface circuit 105 can send a ready / busy signal (e.g., a status signal) nR / B to memory controller 50 via pin 8 P18. Interface circuit 105 can send status information of non-volatile memory device 100 to memory controller 50 via the ready / busy signal nR / B. When non-volatile memory device 100 is in a busy state (e.g., when an operation is being performed on non-volatile memory device 100), interface circuit 105 can send the ready / busy signal nR / B indicating the busy state to memory controller 50. When non-volatile memory device 100 is in a ready state (e.g., when no operation is being performed on non-volatile memory device 100 or an operation has completed), interface circuit 105 can send the ready / busy signal nR / B indicating the ready state to memory controller 50.

[0195] Control circuit 450 can control all operations of non-volatile memory device 100. Control circuit 450 can receive commands (CMD) and addresses (ADDR) obtained from interface circuit 105. Control circuit 450 can generate control signals for controlling other components of non-volatile memory device 100 in response to the received commands (CMD) and addresses (ADDR). For example, control circuit 450 can generate various control signals for programming data DTA to or reading data DTA from memory cell array 200.

[0196] The memory cell array 200 can store the data DTA obtained from the interface circuit 105 under the control of the control circuit 450. The memory cell array 200 can output the stored data DTA to the interface circuit 105 under the control of the control circuit 480.

[0197] The memory cell array 200 may include multiple non-volatile memory cells.

[0198] The storage controller 50 may include first to eighth pins P21, P22, P23, P24, P25, P26, P27, and P28, as well as interface circuitry 99. Interface circuitry 99 may be referred to as a second interface circuit or a controller interface circuit. Interface circuitry 99 may correspond to... Figure 9 The memory interface 98 in the memory. The first pin P21 to the eighth pin P28 can respectively correspond to the first pin P11 to the eighth pin P18 of the non-volatile memory device 100.

[0199] Interface circuit 99 can send the chip enable signal nCE to non-volatile memory device 100 via the first pin P21. Interface circuit 99 can send signals to and receive signals from non-volatile memory device 100 selected by chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0200] Interface circuit 99 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to non-volatile memory device 100 via pins P22 to P24. Interface circuit 99 can send the data signal DQ to or receive the data signal DQ from non-volatile memory device 100 via pin P27.

[0201] Interface circuit 99 can send a data signal DQ, including command CMD or address ADDR, together with a switchable write enable signal nWE to the non-volatile memory device 100. Interface circuit 99 can also send the data signal DQ, including command CMD, to the non-volatile memory device 100 by sending a command latch enable signal CLE with an enabled state. Furthermore, interface circuit 99 can send the data signal DQ, including address ADDR, to the non-volatile memory device 100 by sending an address latch enable signal ALE with an enabled state.

[0202] Interface circuit 99 can send the read enable signal nRE to non-volatile memory device 100 via pin 5 P25. Interface circuit 99 can receive the data strobe signal DQS from non-volatile memory device 100 or send the data strobe signal DQS to non-volatile memory device 100 via pin 6 P26.

[0203] Interface circuit 99 can receive a ready / busy signal nR / B from non-volatile memory device 100 via pin 8 P28. Interface circuit 99 can determine the status information of non-volatile memory device 100 based on the ready / busy signal nR / B.

[0204] Figure 23 This is a block diagram illustrating a storage device according to an example embodiment.

[0205] refer to Figure 23 The storage device 800 may include a storage controller 810 and a storage medium 820. The storage device 800 may support multiple media channels CHN1, CHN2, ..., CHNp (hereinafter referred to as CHN1 to CHNp), and the storage medium 820 may be connected to the storage controller 810 through multiple media channels CHN1 to CHNp.

[0206] Storage medium 820 may include multiple non-volatile memory devices NVM11, NVM12, ..., NVM1t, NVM21, NVM22, ..., NVM2t, NVMp1, NVMp2, ..., NVMpt. For example, non-volatile memory devices NVM11 to NVMpt may correspond to... Figure 1Non-volatile memory device 100. Each of the non-volatile memory devices NVM11 to NVMpt can be connected to one of a plurality of media channels CHN1 to CHNp via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1t can be connected to the first media channel CHN1 via paths W11, W12, ..., W1t; non-volatile memory devices NVM21 to NVM2t can be connected to the second media channel CHN2 via paths W21, W22, ..., W2t; and non-volatile memory devices NVMp1 to NVMpt can be connected to the p-th media channel CHNp via paths Wp1, Wp2, ..., Wpt. In some example embodiments, each of the non-volatile memory devices NVM11 to NVMpt can be implemented as any memory cell that can be operated according to individual commands from the memory controller 810. For example, each of the non-volatile memory devices NVM11 to NVMpt can be implemented as a chip or die, but the example embodiments are not limited thereto.

[0207] Each of the non-volatile memory devices NVM11 to NVMpt can correspond to Figure 10 The non-volatile memory device 100. Therefore, each of the non-volatile memory devices NVM11 to NVMpt may include a memory cell array comprising at least one memory block, and the at least one memory block may be divided into multiple sub-blocks. Therefore, in addition to the target word lines among the word lines of the selected sub-blocks that are sensitive to read interference, the memory controller 810 may also designate at least one word line among the word lines of unselected sub-blocks that are sensitive to read interference as additional target word lines, perform reliability verification operations on the target word lines and the additional target word lines, and perform a recycling operation based on the result of the reliability verification operations. Therefore, the memory controller 810 can enhance reliability and performance.

[0208] The storage controller 810 can send signals to and receive signals from the storage medium 820 through multiple media channels CHN1 to CHNp. For example, the storage controller 810 can correspond to... Figure 9 The memory controller 50 is located in the storage medium 820. For example, the storage controller 810 can send commands CMDa, CMDb, ..., CMDp, addresses ADDRa, ADDRb, ..., ADDRp, and data DTAa, DTAb, ..., DTAp to the storage medium 820 via media channels CHN1 to CHNp, or it can receive DTAa to DTAp from the storage medium 820.

[0209] The storage controller 810 can select one of the non-volatile memories NVM11 to NVMpt connected to each of the media channels CHN1 to CHNp by using one of the corresponding media channels CHN1 to CHNp, and can send signals to and receive signals from the selected non-volatile memory device.

[0210] The storage controller 810 can send signals to and receive signals from the storage medium 820 in parallel through different media channels.

[0211] The storage controller 810 can communicate with external hosts via the Universal Flash Memory (UFS) standard.

[0212] The non-volatile memory device or storage device according to the example embodiments can be packaged using various package types or package configurations.

[0213] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: A non-volatile memory device comprising: at least one memory block including a plurality of cell strings, wherein each of the plurality of cell strings includes a string select transistor, a plurality of memory cells, and a ground select transistor connected in series and arranged in one direction between a bit line and a common source line, the at least one memory block being divided into a plurality of sub-blocks arranged in the one direction; and A storage controller, including a recycling register, wherein the storage controller is configured to: Based on the access address, the plurality of sub-blocks are identified as a selected sub-block including the selected word line and at least one unselected sub-block adjacent to the selected sub-block; Based on the programming progress status of each of the selected sub-blocks and the at least one unselected sub-block, K target word lines of the selected sub-blocks and the at least one unselected sub-block are adaptively determined, where K is an integer greater than 2; and Reliability verification operations are performed sequentially on the K target word lines.

2. The storage device according to claim 1, in, The reliability verification operation indicates the operation of reading data from a memory cell connected to at least one of the K target word lines and detecting and correcting errors in the read data. The programming progress state of each of the selected sub-block and the at least one unselected sub-block includes an open state, a closed state, and an erase state. The open state indicates that each of the selected sub-block and the at least one unselected sub-block includes at least one erase word line; the closed state indicates that each of the selected sub-block and the at least one unselected sub-block includes only programming word lines; and the erase state indicates that each of the selected sub-block and the at least one unselected sub-block includes only erase word lines. The selected sub-block includes the selected word line specified by the access address.

3. The storage device according to claim 2, wherein, Based on the fact that the selected sub-block is in the closed state and the unselected sub-block is in the closed state. The storage controller is configured to identify (i) an adjacent word line of the first word line of the selected sub-block that is adjacent to the selected word line, (ii) a first sub-target word line of the first word line that is adjacent to the unselected sub-block, and (iii) a second sub-target word line of the second word line of the unselected sub-block that is adjacent to the selected sub-block as the K target word lines.

4. The storage device according to claim 3, wherein, Based on the fact that the error count obtained through the reliability verification operation on the adjacent word lines is greater than the reference error count, the storage controller is configured to: The selected sub-block is registered in the reclaim register as a reclaimed sub-block; Skip the reliability verification operation for the first sub-target word line; and Perform the reliability verification operation on the second sub-target word line.

5. The storage device according to claim 2, wherein, Based on the selected sub-block being in the closed state and the unselected sub-block being in the erased state, or based on the selected sub-block being in the closed state and the unselected sub-block being in the open state. The storage controller is configured to identify (i) an adjacent word line of the first word line of the selected sub-block that is adjacent to the selected word line, (ii) a first sub-target word line of the first word line that is adjacent to the unselected sub-block, (iii) a boundary word line of the second word line of the unselected sub-block that is adjacent to at least one programming word line, and (iv) a second sub-target word line of the second word line that is adjacent to the selected sub-block as the K target word lines.

6. The storage device according to claim 5, wherein, Based on the fact that the error count obtained through the reliability verification operation on the boundary word line is greater than the reference error count, the storage controller is configured to: The unselected sub-blocks are registered in the reclaim register as reclaimed sub-blocks; as well as Skip the reliability verification operation for the second sub-target word line.

7. The storage device according to claim 2, wherein, Based on the fact that the selected sub-block is in the open state and the unselected sub-block is in the closed state. The storage controller is configured to identify (i) a boundary word line among the first word lines of the selected sub-block that is adjacent to at least one programming word line, (ii) an adjacent word line among the first word lines of the selected sub-block that is adjacent to the selected word line, (iii) a first sub-target word line among the first word lines that is adjacent to the unselected sub-block, and (iv) a second sub-target word line among the second word lines of the unselected sub-block that is adjacent to the selected sub-block as the K target word lines.

8. The storage device according to claim 7, wherein, Based on the fact that the error count obtained through the reliability verification operation on the boundary word line is greater than the reference error count, the storage controller is configured to: The selected sub-block is registered in the reclaim register as a reclaimed sub-block; Skip the reliability verification operation for the adjacent word line and the first sub-target word line; and Perform the reliability verification operation on the second sub-target word line.

9. The storage device according to claim 2, wherein, Based on the selected sub-block being in the open state and the unselected sub-block being in the erase state, or based on the selected sub-block being in the open state and the unselected sub-block being in the open state, The storage controller is configured to determine the following as the K target word lines: (i) a first boundary word line among the first word lines of the selected sub-block that is adjacent to at least one first programming word line; (ii) an adjacent word line among the first word lines of the selected sub-block that is adjacent to the selected word line; (iii) a first sub-target word line among the first word lines that is adjacent to the unselected sub-block; (iv) a second boundary word line among the second word lines of the unselected sub-block that is adjacent to at least one second programming word line; and (v) a second sub-target word line among the second word lines that is adjacent to the selected sub-block.

10. The storage device according to claim 9, wherein, Based on the fact that the error count obtained through the reliability verification operation on the first boundary word line is greater than the reference error count, the storage controller is configured to: The selected sub-block is registered in the reclaim register as a reclaimed sub-block; Skip the reliability verification operation for the adjacent word line and the first sub-target word line; as well as The reliability verification operation is performed on the second boundary word line and the second sub-target word line.

11. The storage device according to claim 1, wherein, The storage controller includes: The reliability manager is configured to perform the reliability verification operation based on the read interference level monitoring scheme; An error correction code (ECC) engine is configured to detect and correct errors in the read data by performing ECC decoding on the read data read by the reliability manager; A memory interface is configured to communicate with the non-volatile memory device; and The processor is configured to control the reliability manager, the ECC engine, and the memory interface. Wherein, based on the fact that the error count in the read data is greater than the reference error count, the processor is configured to register the corresponding sub-block in the recycling register as a recycling sub-block, or to perform a recycling operation on the corresponding sub-block.

12. The storage device according to claim 1, further comprising: A voltage generator is configured to generate a read voltage, a read pass voltage, and an erase voltage based on control signals; The address decoder is configured to provide the read voltage and the read pass voltage to the selected sub-block and the unselected sub-block based on the access address; and The control circuit is configured to perform the reliability verification by controlling the voltage generator and the address decoder under the control of the storage controller.

13. A method of operating a memory controller, the memory controller being configured to control a non-volatile memory device, the non-volatile memory device comprising at least one memory block, the at least one memory block comprising a plurality of cell strings, wherein, Each of the plurality of cell strings includes a string select transistor connected in series and arranged in one direction between a bit line and a common source line, a plurality of memory cells, and a ground select transistor, wherein the at least one memory block is divided into a plurality of sub-blocks arranged in the one direction, and the method includes: Based on the access address, the plurality of sub-blocks are identified as a selected sub-block including the selected word line and at least one unselected sub-block adjacent to the selected sub-block; Based on the programming progress status of each of the selected sub-blocks and the at least one unselected sub-block, K target word lines of the selected sub-blocks and the at least one unselected sub-block are adaptively determined, where K is an integer greater than 2; and Reliability verification operations are performed sequentially on the K target word lines.

14. The method according to claim 13, in, The reliability verification operation indicates the operation of reading data from a memory cell connected to at least one of the K target word lines and detecting and correcting errors in the read data. The programming progress state of each of the selected sub-block and the at least one unselected sub-block includes an open state, a closed state, and an erase state. The open state indicates that each of the selected sub-block and the at least one unselected sub-block includes at least one erase word line; the closed state indicates that each of the selected sub-block and the at least one unselected sub-block includes only programming word lines; and the erase state indicates that each of the selected sub-block and the at least one unselected sub-block includes only erase word lines. The selected sub-block includes the selected word line specified by the access address.

15. The method according to claim 14, wherein, Based on the fact that the selected sub-block is in the closed state and the unselected sub-block is in the closed state. The K target word lines include (i) the adjacent word lines of the first word lines of the selected sub-block that are adjacent to the selected word line, (ii) the first sub-target word lines of the first word lines that are adjacent to the unselected sub-block, and (iii) the second sub-target word lines of the second word lines of the unselected sub-block that are adjacent to the selected sub-block.

16. The method according to claim 15, wherein, Based on the fact that the error count obtained through the reliability verification operation on the adjacent word lines is greater than the reference error count, the reliability verification operation is performed sequentially, including: The selected sub-block is registered in the reclaim register of the storage controller as a reclaimed sub-block; Skip the reliability verification operation for the first sub-target word line; and Perform the reliability verification operation on the second sub-target word line.

17. The method of claim 14, wherein, Based on the selected sub-block being in the closed state and the unselected sub-block being in the erased state, or based on the selected sub-block being in the closed state and the unselected sub-block being in the open state. The K target word lines include: (i) an adjacent word line among the first word lines of the selected sub-block that is adjacent to the selected word line; (ii) a first sub-target word line among the first word lines that is adjacent to the unselected sub-block; (iii) a boundary word line among the second word lines of the unselected sub-block that is adjacent to at least one programming word line; and (iv) a second sub-target word line among the second word lines that is adjacent to the selected sub-block.

18. The method according to claim 14, wherein, Based on the fact that the selected sub-block is in the open state and the unselected sub-block is in the closed state. The K target word lines include (i) a boundary word line among the first word lines of the selected sub-block that is adjacent to at least one programming word line; (ii) an adjacent word line among the first word lines of the selected sub-block that is adjacent to the selected word line; (iii) a first sub-target word line among the first word lines that is adjacent to the unselected sub-block; and (iv) a second sub-target word line among the second word lines of the unselected sub-block that is adjacent to the selected sub-block.

19. The method of claim 14, wherein, Based on the selected sub-block being in the open state and the unselected sub-block being in the erase state, or based on the selected sub-block being in the open state and the unselected sub-block being in the open state. The K target word lines include: (i) a first boundary word line among the first word lines of the selected sub-block that is adjacent to at least one first programming word line; (ii) an adjacent word line among the first word lines of the selected sub-block that is adjacent to the selected word line; (iii) a first sub-target word line among the first word lines that is adjacent to the unselected sub-block; (iv) a second boundary word line among the second word lines of the unselected sub-block that is adjacent to at least one second programming word line; and (v) a second sub-target word line among the second word lines of the unselected sub-block that is adjacent to the selected sub-block.

20. A storage device, comprising: A non-volatile memory device comprising: at least one memory block including a plurality of memory cells, said at least one memory block including a plurality of sub-blocks; and The storage controller is configured as follows: Based on the access address, the plurality of sub-blocks are identified as a selected sub-block including the selected word line and at least one unselected sub-block adjacent to the selected sub-block; Based on the programming progress status of each of the selected sub-blocks and the at least one unselected sub-block, K target word lines of the selected sub-blocks and the at least one unselected sub-block are adaptively determined, where K is an integer greater than 2; and Sequentially perform reliability verification operations on the K target word lines, and The storage controller includes: Reclaim registers; The reliability manager is configured to perform the reliability verification operation based on the read interference level monitoring scheme; An error correction code (ECC) engine is configured to detect and correct errors in read data by performing ECC decoding on the read data read by the reliability manager; and The processor is configured to control the reliability manager and the ECC engine. Wherein, based on the fact that the error count in the read data is greater than the reference error count, the processor is configured to register the corresponding sub-block in the recycling register as a recycling sub-block.

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