A refresh management method of a phase change memory and a storage system

Abstract

The application discloses a refresh management method of a phase change memory and a storage system. The method comprises the following steps: determining a first target storage unit in a plurality of storage units, and determining a first transmission line in a plurality of transmission lines, determining a plurality of second target storage units in the plurality of storage units; the second target storage units comprise at least one of adjacent units and remote units; the adjacent units are adjacent to the first target storage unit; the remote units are coupled with the first transmission line; and the remote units and the first target storage unit are respectively the first storage unit and the last storage unit on the first transmission line; updating the current write string interference times of each second target storage unit respectively to obtain updated write string interference times; screening the storage units with the updated write string interference times greater than a preset number threshold from the plurality of second target storage units to obtain third target storage units; and performing a refresh operation on the third target storage units.

Description

Technical Field

[0001] This application relates to the field of phase-change memory technology, specifically to a refresh management method and storage system for phase-change memory. Background Technology

[0002] Phase-change memory (PCM) comprises transmission lines and memory cells coupled between the transmission lines. The memory cells utilize the resistance changes of the phase-change material between different phases to store data. Write operations of PCM include: applying a medium-width, low-amplitude current pulse signal to the memory cell through the transmission lines, which switches the memory cell from the RESET state (amorphous, high-resistance state) to the SET state (crystalline, low-resistance state); applying a short, strong current pulse signal to the memory cell through the transmission lines, which switches the memory cell from the SET state to the RESET state. Different data can be written to the RESET and SET states.

[0003] To ensure that storage cells can record data more stably, a refresh operation is required: the data in the storage cell is read out and then rewritten. This refresh operation can promptly correct minor changes caused by crosstalk, preventing these changes from accumulating and ultimately causing storage cell failure, thus helping to extend the overall lifespan of the memory.

[0004] In related technologies, multiple memory cells perform refresh operations at different numbers of times. Memory cells that perform more refresh operations have lower performance, while memory cells that perform fewer refresh operations have higher performance. The performance of each memory cell is inconsistent. Memory cells that perform more refresh operations may fail prematurely due to overuse, affecting the overall working performance of the phase-change memory. Summary of the Invention

[0005] A refresh management method and storage system for phase-change memory are provided to solve the problem of inconsistent refresh counts among different storage cells.

[0006] A first aspect provides a refresh management method for a phase-change memory (PCM), the method being applied to a PCM, the PCM including a memory cell array and multiple transmission lines, the memory cell array including multiple memory cells arranged in an array, the multiple memory cells being coupled between the multiple transmission lines; the method includes: A first target storage cell is determined among the plurality of storage cells, and a first transmission line is determined among the plurality of transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. A plurality of second target storage cells are determined among the plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to the first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; The current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count; From a plurality of second target storage units, storage units whose updated write crosstalk impact count is greater than a preset threshold number are selected to obtain third target storage units; A refresh operation is performed on the third target storage unit.

[0007] In some embodiments, the transmission line includes word lines and bit lines; the first transmission line includes a first word line and a first bit line; Determining a plurality of second target storage cells among the plurality of said storage cells includes: In the word line and the bit line, the first word line and the first bit line coupled to the first target memory cell are obtained, and the first word line address corresponding to the first word line and the first bit line address corresponding to the first bit line are determined. Based on the first word line address, determine the second word line address and the third word line address; Based on the first bit line address, determine the second bit line address and the third bit line address; By combining the second word line address, the third word line address, the second bit line address, the third bit line address, the first word line address, and the first bit line address, an address set is obtained; The storage units associated with the address set are determined to obtain multiple second target storage units.

[0008] In some embodiments, determining the second word line address and the third word line address based on the first word line address includes: When the first word line address is equal to the minimum word line address, the first word line address is incremented by 1 to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The maximum word line address is determined to obtain the third word line address; the third word line indicated by the third word line address is the last word line in the transmission line; the third word line is coupled to the remote unit.

[0009] In some embodiments, determining the second word line address and the third word line address based on the first word line address includes: If the first word line address is equal to the maximum word line address, subtract 1 from the first word line address to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The minimum word line address is determined to obtain the third word line address; the third word line indicated by the third word line address is the first word line in the transmission line; the third word line is coupled to the remote unit.

[0010] In some embodiments, determining the second word line address and the third word line address based on the first word line address includes: If the first word line address is not equal to the minimum word line address and not equal to the maximum word line address, the first word line address is incremented by 1 to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The first word line address is subtracted by 1 to obtain the third word line address; the third word line indicated by the third word line address is adjacent to the first word line; the third word line is coupled to the adjacent unit.

[0011] In some embodiments, determining the second bit line address and the third bit line address based on the first bit line address includes: When the first bit line address is equal to the minimum bit line address, the first bit line address is incremented by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The maximum bit line address is determined to obtain the third bit line address; the third bit line indicated by the third bit line address is the last bit line in the transmission line; the third bit line is coupled to the remote unit.

[0012] In some embodiments, determining the second bit line address and the third bit line address based on the first bit line address includes: When the first bit line address is equal to the maximum bit line address, the first bit line address is subtracted by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The minimum bit line address is determined to obtain the third bit line address; the third bit line indicated by the third bit line address is the first bit line in the transmission line; the third bit line is coupled to the remote unit.

[0013] In some embodiments, determining the second bit line address and the third bit line address based on the first bit line address includes: If the first bit line address is not equal to the minimum bit line address and not equal to the maximum bit line address, the first bit line address is incremented by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The first bit line address is subtracted by 1 to obtain the third bit line address; the third bit line indicated by the third bit line address is adjacent to the first bit line; the third bit line is coupled to the adjacent cell.

[0014] In some embodiments, the address set includes: a first address, a second address, a third address, and a fourth address; The first address includes the first word line address and the second bit line address; The second address includes the first word line address and the third bit line address; The third address includes the second word line address and the first bit line address; The fourth address includes the third word line address and the first bit line address.

[0015] In some embodiments, the current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count, including: Increment the current write crosstalk impact count for each of the second target storage units by 1 to obtain the updated write crosstalk impact count.

[0016] Secondly, a storage system is provided, comprising: A phase-change memory includes a memory cell array and multiple transmission lines. The memory cell array includes multiple memory cells arranged in an array, and the multiple memory cells are coupled between the multiple transmission lines. The controller is coupled to the phase-change memory; the controller is configured to: A first target storage cell is determined among the plurality of storage cells, and a first transmission line is determined among the plurality of transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. A plurality of second target storage cells are determined among the plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to the first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; The current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count; From a plurality of second target storage units, storage units whose updated write crosstalk impact count is greater than a preset threshold number are selected to obtain third target storage units; A refresh operation is performed on the third target storage unit.

[0017] The beneficial effects of this application are as follows: Based on the refresh management method of phase change memory provided in the embodiments of this application, an equal number of second target memory units are allocated to the first target memory unit. The number of second target memory units affected by the write operation of the first target memory unit is equal. This makes the number of refresh operations performed by each memory unit tend to be the same constant value for the memory unit array, realizing wear leveling management of phase change memory, ensuring that the number of refreshes of each memory unit is equal, the performance of each memory unit is consistent, and avoiding premature failure of some memory units due to multiple refreshes. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of refresh management in related technologies; Figure 2 This is a flowchart illustrating the refresh management method for a phase-change memory provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a phase-change memory provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram showing the locations of the first target storage unit and the second target storage unit provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram showing the locations of the first target storage unit and the second target storage unit provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the threshold voltage provided by an exemplary embodiment of this disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0023] In related technologies, write operations (especially amorphization processes) involve applying high-current pulses to the target memory cell (aggressor) to heat the phase change material and rapidly cool it. These high-current pulses not only affect the aggressor but can also cause crosstalk to surrounding memory cells (victims) near the aggressor. The heat generated by the write operation diffuses from the aggressor to the victim, causing the victim's temperature to rise and its electrical properties and physical structure to change. This may render the victim unable to read data, leading to data loss and reduced operational stability of the phase change memory. To reduce the impact of crosstalk, a refresh operation is required on the victim whenever the crosstalk accumulates to a certain level: the data in the victim is read out and rewritten. The refresh operation ensures that the phase state of the victim is correctly restored to its proper state (crystalline or amorphous). Even if the phase state changes slightly due to crosstalk, the rewrite operation can correct this. Through the reheating and cooling process, the residual thermal effects of previous write operations can be eliminated, ensuring that the material properties of the victim return to normal. Refresh operations can promptly correct minor changes caused by crosstalk, preventing these changes from accumulating and eventually causing memory cell failure, thus helping to extend the overall lifespan of the memory.

[0024] In related technologies, each write operation (especially the amorphization process) will cause some damage to the phase change material. Therefore, it is necessary to manage the wear leveling of the phase change memory. By reasonably allocating the number of times the memory cells are used, the number of times each memory cell is used (the number of write operations) is equal, so as to avoid some memory cells from failing prematurely due to overuse.

[0025] See related technologies. Figure 1As shown, multiple storage cells are arranged in an array. If storage cell A1 is the victim, then its surrounding storage cells B1 and B2 are aggressors. When storage cells B1 and B2 perform write operations, they will cause crosstalk to storage cell A1. If storage cell A2 is the victim, then its surrounding storage cells B3, B4, and B5 are aggressors. When storage cells B3, B4, and B5 perform write operations, they will cause crosstalk to storage cell A2. If storage cell A3 is the victim, then its surrounding storage cells B6, B7, B8, and B9 are aggressors. When storage cells B6, B7, B8, and B9 perform write operations, they will cause crosstalk to storage cell A3. Storage cell A3 is most susceptible to crosstalk from its surroundings and is refreshed the most times. Storage cell A1 is least susceptible to crosstalk from its surroundings and is refreshed the least times. Under ideal conditions, within the same time period, storage cell A1 is refreshed 2N times (N is a positive integer), storage cell A2 is refreshed 3N times, and storage cell A3 is refreshed 4N times. Therefore, due to the different locations of the storage cells, the degree of crosstalk they experience varies, resulting in different refresh counts. Storage cells near the edges (especially near corners) are less likely to be refreshed, while those in the middle are more likely to be refreshed. This leads to unequal refresh counts (write operations) for each storage cell, resulting in different wear levels and thus different performance. Storage cells in the middle are more prone to premature failure due to multiple refreshes.

[0026] This application provides a refresh management method for a phase-change memory (PCM). The PCM includes a memory cell array and multiple transmission lines. The memory cell array includes multiple memory cells arranged in an array, and the multiple memory cells are coupled between the multiple transmission lines. (See also...) Figure 2 As shown, the method includes: S101: A first target storage cell is determined among multiple storage cells, and a first transmission line is determined among multiple transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. S102: Determine a plurality of second target storage cells among a plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to the first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; S103: Update the current write crosstalk impact count for each second target memory unit to obtain the updated write crosstalk impact count; S104: From multiple second target storage units, select storage units whose updated write crosstalk impact count is greater than a preset threshold number to obtain the third target storage unit; S105: Perform a refresh operation on the third target storage unit.

[0027] In some embodiments, the remote unit is the first storage unit on the first transmission line, and the first target storage unit is the last storage unit on the first transmission line. Alternatively, the remote unit is the last storage unit on the first transmission line, and the first target storage unit is the first storage unit on the first transmission line.

[0028] In some embodiments, the plurality of second target storage units includes two adjacent units and two remote units. In other embodiments, the plurality of second target storage units includes three adjacent units and one remote unit. In still other embodiments, the plurality of second target storage units includes four adjacent units.

[0029] Through the above embodiments, an equal number of second target storage units are allocated to the first target storage unit. The number of second target storage units affected by the write operation of the first target storage unit is equal. This makes the number of refresh operations performed by each storage unit in the storage unit array tend to be the same constant value, realizing wear leveling management of the phase change memory, ensuring that the refresh count of each storage unit is equal, the performance of each storage unit is consistent, and avoiding premature failure of some storage units due to multiple refreshes.

[0030] The refresh management method of phase-change memory and phase-change memory will be explained in detail below with reference to the accompanying drawings.

[0031] In some embodiments, Figure 3This represents a phase-change memory (PCM). A PCM includes a memory cell array and multiple transmission lines. The memory cell array comprises multiple arrayed memory cells coupled to the multiple transmission lines. The multiple transmission lines include multiple word lines and multiple bit lines. Each memory cell is coupled between one word line and one bit line. The multiple word lines are: WL0, WL1, and WL2, where WL0 is the first word line, WL1 is the second word line, and WL2 is the third word line. The multiple bit lines are: BL0, BL1, and BL2, where BL0 is the first bit line, BL1 is the second bit line, and BL2 is the third bit line. Memory cell a is coupled between WL0 and BL0. Memory cell b is coupled between WL0 and BL1. Memory cell c is coupled between WL1 and BL0. WL0 has a word line address wl0, WL1 has a word line address wl1, and WL2 has a word line address wl2. BL0 has a bitline address bl0, BL1 has a bitline address bl1, and BL2 has a bitline address bl2. When locating a memory cell, it is only necessary to obtain the word line and bit line coupled to that memory cell, and then further obtain the word line address and the bit line address to locate the unique memory cell. For example, knowing wl0 and bl0 is sufficient to locate memory cell a; knowing wl0 and bl1 is sufficient to locate memory cell b.

[0032] In some embodiments, each storage cell is configured with a counter to count the number of write crosstalk events.

[0033] In some embodiments, the first target memory cell is a memory cell that has just completed a write operation. The first target memory cell acts as an aggressor, causing crosstalk to nearby memory cells. The first target memory cell is coupled to a first transmission line. The first transmission line includes a first word line and a first bit line, and the first memory cell is coupled between the first word line and the first bit line.

[0034] In some embodiments, determining a plurality of second target storage units among a plurality of storage units specifically includes: S1: In word lines and bit lines, obtain the first word line and the first bit line coupled to the first target memory cell, and determine the first word line address corresponding to the first word line and the first bit line address corresponding to the first bit line. S2: Determine the second and third word line addresses based on the first word line address; S3: Determine the second and third line addresses based on the first line address; S4: Combine the second word line address, the third word line address, the second bit line address, the third bit line address, the first word line address, and the first bit line address to obtain the address set; S5: Determine the storage units associated with the address set to obtain multiple second target storage units.

[0035] In some embodiments, determining the second word line address and the third word line address based on the first word line address specifically includes: S1: When the first word line address is equal to the minimum word line address, add 1 to the first word line address to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; S2: Determine the maximum word line address to obtain the third word line address; the third word line indicated by the third word line address is the last word line in the transmission line; the third word line is coupled to the remote unit.

[0036] In some embodiments, determining the second and third line addresses based on the first line address specifically includes: S1: When the address of the first bit line is not equal to the address of the minimum bit line and not equal to the address of the maximum bit line, add 1 to the address of the first bit line to get the address of the second bit line; the second bit line indicated by the address of the second bit line is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. S2: Subtract 1 from the first bit address to obtain the third bit address; the third bit address indicates the third bit and is adjacent to the first bit; the third bit is coupled to the adjacent cell.

[0037] In some embodiments, the address set includes: a first address, a second address, a third address, and a fourth address; the first address includes a first word line address and a second bit line address; the second address includes a first word line address and a third bit line address; the third address includes a second word line address and a first bit line address; the fourth address includes a third word line address and a first bit line address. The first word line corresponds to the first word line address. The second word line corresponds to the second word line address. The third word line corresponds to the third word line address. The first bit line corresponds to the first bit line address. The second bit line corresponds to the second bit line address. The third bit line corresponds to the third bit line address.

[0038] Specifically, the number of second target memory units is four. The first second target memory unit is coupled between the first word line and the second bit line; the second second target memory unit is coupled between the first word line and the third bit line; the third second target memory unit is coupled between the second word line and the first bit line; and the fourth second target memory unit is coupled between the third word line and the first bit line. Therefore, the second target memory units can be associated with each other through the address set.

[0039] In some embodiments, the current write crosstalk impact count for each second target storage unit is updated to obtain an updated write crosstalk impact count. Specifically, this includes incrementing the current write crosstalk impact count for each second target storage unit by 1. The initial value of the current write crosstalk impact count is equal to 0. If a storage unit is identified as a second target storage unit, its current write crosstalk impact count is incremented by 1 to obtain an updated write crosstalk impact count.

[0040] In some embodiments, see Figure 4 As shown, the minimum word line address is set to wl0, the maximum word line address to wl14, the minimum bit line address to bl0, and the maximum bit line address to bl16. The first word line is WL0, and the last word line is WL14. The first bit line is BL0, and the last bit line is BL16. Using memory cell A4 as the first target memory cell, the first word line address is wl0, and the first bit line address is bl7. The first word line address equals the minimum word line address. Increasing the first word line address wl0 by 1 gives wl1, which is the second word line address. The maximum word line address wl14 is used as the third word line address.

[0041] Continue reading Figure 4 As shown, when the first bit address bl7 is not equal to the minimum bit address bl0 and not equal to the maximum bit address bl16, the first bit address bl7 is incremented by 1 to obtain the second bit address bl8; the first bit address bl7 is decremented by 1 to obtain the third bit address bl6. Then, an address set is constructed, which includes: the first address, the second address, the third address, and the fourth address. First address = (first word line address wl0, second bit line address bl8); Second address = (first word line address wl0, third bit line address bl6); Third address = (Second word line address wl1, First word line address bl7); Fourth address = (Third word line address wl14, First word line address bl7).

[0042] Continue reading Figure 4As shown, the second target storage unit B11 can be determined through the first address, the second target storage unit B10 through the second address, the second target storage unit B12 through the third address, and the second target storage unit B13 through the fourth address. In this embodiment, the first word line is WL0, the second word line is WL1, the third word line is WL14, the first bit line is BL7, the second bit line is BL8, and the third bit line is BL6. A4 is the first storage unit on BL7, and B13 is the last storage unit on BL7. B10, B11, and B12 are adjacent units. There are no other storage units between the adjacent units and the first target storage unit A4. The heat generated by the first target storage unit A4 will directly interfere with the adjacent units. B13 belongs to the remote unit. Although the heat generated by the target storage unit A4 will not directly crosstalk to the remote unit, this embodiment treats the first word line and the last word line as adjacent word lines for media management, so that each first target storage unit is configured with 4 second target storage units. That is, the number of second target storage units = the number of adjacent units + the number of remote units = 4. Each first target storage unit will affect the write crosstalk impact number of the 4 second target storage units. The current write crosstalk impact number of each second target storage unit is updated to obtain the updated write crosstalk impact number. From the multiple second target storage units, the storage units with the updated write crosstalk impact number greater than the preset threshold number are selected to obtain the third target storage units. The third target storage units are refreshed. The refresh operation includes reading the data in the third target storage unit and then rewriting it.

[0043] In some embodiments, the preset number of times threshold is an integer between 100 and 1000, such as 100 times, 200 times, or 500 times.

[0044] In some embodiments, determining the second word line address and the third word line address based on the first word line address specifically includes: S1: If the first word line address is not equal to the minimum word line address and not equal to the maximum word line address, add 1 to the first word line address to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; S2: Subtract 1 from the address of the first word line to obtain the address of the third word line; the third word line indicated by the address of the third word line is adjacent to the first word line; the third word line is coupled to the adjacent cell.

[0045] In some embodiments, determining the second and third line addresses based on the first line address specifically includes: S1: When the address of the first bit line is equal to the address of the smallest bit line, add 1 to the address of the first bit line to get the address of the second bit line; the second bit line indicated by the address of the second bit line is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. S2: Determine the maximum bit line address to obtain the third bit line address; the third bit line indicated by the third bit line address is the last bit line in the transmission line; the third bit line is coupled to the remote unit.

[0046] In some embodiments, see Figure 4 As shown, if memory cell A2 is taken as the first target memory cell, then the first word line address is equal to wl11, and the first word line address is equal to bl0. Since the first word line address is neither equal to the minimum word line address nor equal to the maximum word line address, we add 1 to the first word line address wl11 to get wl12, which is the second word line address. Then, we subtract 1 from the first word line address wl11 to get wl10, which is the third word line address.

[0047] Continue reading Figure 4 As shown, when the first bit address bl0 equals the minimum bit address, the first bit address bl0 is incremented by 1 to obtain the second bit address bl1; the maximum bit address bl16 is determined to obtain the third bit address. Then, an address set is constructed, which includes: the first address, the second address, the third address, and the fourth address. First address = (first word line address wl11, second bit line address bl1); Second address = (first word line address wl11, third bit line address bl16). Third address = (Second word line address wl12, First word line address bl0); Fourth address = (Third word line address wl10, First word line address bl0).

[0048] Continue reading Figure 4As shown, the second target storage unit B4 can be determined by the first address, the second target storage unit B14 by the second address, the second target storage unit B5 by the third address, and the second target storage unit B3 by the fourth address. In this embodiment, the first word line is WL11, the second word line is WL12, the third word line is WL10, the first bit line is BL0, the second bit line is BL1, and the third bit line is BL16. A2 is the first storage unit on WL11, and B14 is the last storage unit on WL11. B3, B4, and B5 are adjacent units, and B14 is a far-end unit. Although the heat generated by target storage cell A2 does not directly crosstalk to the remote cell, this embodiment treats the first bit line and the last bit line as adjacent bit lines for media management, so that each first target storage cell is configured with four second target storage cells. Each first target storage cell affects the write crosstalk impact number of the four second target storage cells. The current write crosstalk impact number of each second target storage cell is updated to obtain the updated write crosstalk impact number. From the multiple second target storage cells, the storage cells with the updated write crosstalk impact number greater than a preset threshold are selected to obtain the third target storage cell. The third target storage cell is refreshed. In some embodiments, determining the second word line address and the third word line address based on the first word line address specifically includes: S1: If the first word line address is equal to the maximum word line address, subtract 1 from the first word line address to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; S2: Determine the minimum word line address to obtain the third word line address; the third word line indicated by the third word line address is the first word line in the transmission line; the third word line is coupled to the remote unit.

[0049] In some embodiments, determining the second and third line addresses based on the first line address specifically includes: S1: When the first bit line address is equal to the maximum bit line address, subtract 1 from the first bit line address to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. S2: Determine the minimum bit line address to obtain the third bit line address; the third bit line indicated by the third bit line address is the first bit line in the transmission line; the third bit line is coupled to the remote unit.

[0050] In some embodiments, see Figure 4As shown, if memory cell A5 is taken as the first target memory cell, then the first word line address is equal to wl14, and the first word line address is equal to bl16. If the first word line address is equal to the maximum word line address, subtract 1 from the first word line address wl14 to obtain the second word line address wl13; determine the minimum word line address to obtain the third word line address wl0.

[0051] Continue reading Figure 4 As shown, when the first bit address equals the maximum bit address, the first bit address is subtracted by 1 to obtain the second bit address bl15; the minimum bit address is determined to obtain the third bit address bl0. Then, an address set is constructed, which includes: the first address, the second address, the third address, and the fourth address; First address = (first word line address wl14, second bit line address bl15); Second address = (first word line address wl14, third bit line address bl0); Third address = (Second word line address wl13, first word line address bl16); Fourth address = (Third word line address wl0, First word line address bl16).

[0052] Continue reading Figure 4 As shown, the second target storage unit B16 can be determined through the first address, the second target storage unit B18 through the second address, the second target storage unit B15 through the third address, and the second target storage unit B17 through the fourth address. In this embodiment, the first word line is WL14, the second word line is WL13, the third word line is WL0, the first bit line is BL16, the second bit line is BL15, and the third bit line is BL0. B18 is the first storage unit on WL14, and A5 is the last storage unit on WL14. B17 is the first storage unit on BL16, and A5 is the last storage unit on BL16. B15 and B16 are adjacent units, and B17 and B18 are distant units. Although the heat generated by target storage cell A2 does not directly crosstalk to the remote cell, this embodiment treats the first bit line and the last bit line as adjacent bit lines for media management, and treats the first word line and the last word line as adjacent word lines for media management, so that each first target storage cell is configured with four second target storage cells, and each first target storage cell affects the write crosstalk impact number of the four second target storage cells; the current write crosstalk impact number of each second target storage cell is updated to obtain the updated write crosstalk impact number; from the multiple second target storage cells, the storage cells whose updated write crosstalk impact number is greater than a preset threshold number are selected to obtain the third target storage cell; and a refresh operation is performed on the third target storage cell.

[0053] In some embodiments, see Figure 5 As shown, if memory cell A1 is taken as the first target memory cell, then the first word line address is equal to wl0, and the first bit line address is equal to bl0. When the first word line address is equal to the minimum word line address, the first word line address wl0 is incremented by 1 to obtain the second word line address wl1; the maximum word line address is then determined to obtain the third word line address wl14.

[0054] Continue reading Figure 5 As shown, when the first bit address equals the minimum bit address, the first bit address is incremented by 1 to obtain the second bit address bl1; the maximum bit address is determined to obtain the third bit address bl16. Then, an address set is constructed, which includes: the first address, the second address, the third address, and the fourth address. First address = (first word line address wl0, second bit line address bl1); Second address = (first word line address wl0, third bit line address bl16); Third address = (Second word line address wl1, First word line address bl0); Fourth address = (Third word line address wl14, First word line address bl0).

[0055] Continue reading Figure 5 As shown, the second target storage unit B1 can be determined by the first address, the second target storage unit B17 by the second address, the second target storage unit B2 by the third address, and the second target storage unit B18 by the fourth address. In this embodiment, the first word line is WL0, the second word line is WL1, the third word line is WL14, the first bit line is BL0, the second bit line is BL1, and the third bit line is BL16. A1 is the first storage unit on WL0, and B17 is the last storage unit on WL0. A1 is the first storage unit on BL0, and B18 is the last storage unit on BL0. B2 and B1 are adjacent units, and B17 and B18 are distant units. After determining B1, B2, B17, and B18 as the second target storage units, the current write crosstalk impact count of each second target storage unit is updated to obtain the updated write crosstalk impact count. From the multiple second target storage units, the storage units whose updated write crosstalk impact count is greater than the preset threshold are selected to obtain the third target storage units. The third target storage units are then refreshed.

[0056] In some embodiments, see Figure 5As shown, if memory cell A3 is used as the first target memory cell, then the first word line address is equal to wl6, and the first bit line address is equal to bl7. If the first word line address is not equal to either the minimum or maximum word line address, increment the first word line address wl6 by 1 to obtain the second word line address wl7; decrement the first word line address wl6 by 1 to obtain the third word line address wl5. If the first bit line address is not equal to either the minimum or maximum bit line address, increment the first bit line address bl7 by 1 to obtain the second bit line address bl8; decrement the first bit line address bl7 by 1 to obtain the third bit line address bl6. Then, construct an address set, which includes the first address, the second address, the third address, and the fourth address. First address = (first word line address wl6, second bit line address bl8); Second address = (first word line address wl6, third bit line address bl6); Third address = (Second word line address wl7, First word line address bl7); Fourth address = (Third word line address wl5, First word line address bl7).

[0057] Continue reading Figure 5 As shown, the second target storage unit B8 can be determined through the first address, the second target storage unit B7 through the second address, the second target storage unit B9 through the third address, and the second target storage unit B6 through the fourth address. In this embodiment, the first word line is WL6, the second word line is WL7, the third word line is WL5, the first bit line is BL7, the second bit line is BL8, and the third bit line is BL6. B6, B7, B8, and B9 are adjacent units; there are no far-end units in this embodiment. After determining B6, B7, B8, and B9 as the second target storage units, the current write crosstalk impact count for each second target storage unit is updated to obtain the updated write crosstalk impact count. From the multiple second target storage units, the storage units whose updated write crosstalk impact count is greater than a preset threshold are selected to obtain the third target storage unit. A refresh operation is then performed on the third target storage unit.

[0058] Based on the above embodiments, four second target storage units are configured for the first target storage unit. After the first target storage unit performs a write operation, it updates the current write crosstalk impact count of these four second target storage units to obtain the updated write crosstalk impact count. For the storage unit array, the probability of the "write crosstalk impact count" of each storage unit being updated is the same. Therefore, the number of refresh operations performed by each storage unit tends to be the same constant value, realizing wear leveling management of the phase change memory, ensuring that the refresh count of each storage unit is equal, the performance of each storage unit is consistent, improving the service life of the storage unit, reducing the difficulty of media management, avoiding premature failure of some storage units due to multiple refreshes, and ensuring the working performance of the phase change memory.

[0059] In some embodiments, see Figure 6 As shown, Set Vt represents the SET threshold voltage for switching a memory cell from the RESET state to the SET state, and Reset Vt represents the RESET threshold voltage for switching a memory cell from the SET state to the RESET state. BOL (beginning of life) represents the performance parameters of the memory cell in its initial state (i.e., just manufactured or in a brand new, unused state). EOL (end of life) represents the performance parameters of the memory cell after multiple read and write operations. As the memory cell is read and written multiple times, Set Vt changes from BOL1 to EOL1, and Reset Vt changes from BOL2 to EOL2. During a read operation, a read voltage Vread needs to be applied, which is greater than Set Vt and less than Reset Vt. Vread changes from Vread(BOL) to Vread(EOL). If multiple memory cells are not worn out, and the EOL1 and EOL2 of each memory cell are different, it is impossible to use the same Vread(EOL) to read all memory cells. Based on the refresh management method of phase change memory provided in the embodiments of this application, it can be ensured that the refresh count of each memory cell is equal. Therefore, the EOL1 and EOL2 of each memory cell are almost the same, and the same Vread (EOL) can be used to read all memory cells.

[0060] This application provides a storage system, including: A phase-change memory includes a memory cell array and multiple transmission lines. The memory cell array includes multiple memory cells arranged in an array, and the multiple memory cells are coupled between multiple transmission lines. The controller is coupled to the phase-change memory; the controller is configured as follows: A first target storage cell is determined among multiple storage cells, and a first transmission line is determined among multiple transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. A plurality of second target storage cells are determined among a plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to a first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; The current write crosstalk impact count for each second target storage unit is updated to obtain the updated write crosstalk impact count; From multiple second target storage units, storage units whose updated write crosstalk impact count is greater than a preset threshold are selected to obtain the third target storage unit; Perform a refresh operation on the third target storage unit.

[0061] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0062] The refresh management method and storage system of phase-change memory provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A refresh management method for a phase-change memory, characterized in that, The method is applied to a phase-change memory, which includes a memory cell array and multiple transmission lines. The memory cell array includes multiple memory cells arranged in an array, and the multiple memory cells are coupled between the multiple transmission lines. The method includes: A first target storage cell is determined among the plurality of storage cells, and a first transmission line is determined among the plurality of transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. A plurality of second target storage cells are determined among the plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to the first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; The current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count; From a plurality of second target storage units, storage units whose updated write crosstalk impact count is greater than a preset threshold number are selected to obtain third target storage units; A refresh operation is performed on the third target storage unit.

2. The method according to claim 1, characterized in that, The transmission lines include word lines and bit lines; The first transmission line includes a first word line and a first bit line; Determining a plurality of second target storage cells among the plurality of said storage cells includes: In the word line and the bit line, the first word line and the first bit line coupled to the first target memory cell are obtained, and the first word line address corresponding to the first word line and the first bit line address corresponding to the first bit line are determined. Based on the first word line address, determine the second word line address and the third word line address; Based on the first bit line address, determine the second bit line address and the third bit line address; By combining the second word line address, the third word line address, the second bit line address, the third bit line address, the first word line address, and the first bit line address, an address set is obtained; The storage units associated with the address set are determined to obtain multiple second target storage units.

3. The method according to claim 2, characterized in that, Based on the first word line address, the second and third word line addresses are determined, including: When the first word line address is equal to the minimum word line address, the first word line address is incremented by 1 to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The maximum word line address is determined to obtain the third word line address; the third word line indicated by the third word line address is the last word line in the transmission line; the third word line is coupled to the remote unit.

4. The method according to claim 2, characterized in that, Based on the first word line address, the second and third word line addresses are determined, including: If the first word line address is equal to the maximum word line address, subtract 1 from the first word line address to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The minimum word line address is determined to obtain the third word line address; the third word line indicated by the third word line address is the first word line in the transmission line; the third word line is coupled to the remote unit.

5. The method according to claim 2, characterized in that, Based on the first word line address, the second and third word line addresses are determined, including: If the first word line address is not equal to the minimum word line address and not equal to the maximum word line address, the first word line address is incremented by 1 to obtain the second word line address; the second word line indicated by the second word line address is adjacent to the first word line; the second word line is coupled to the adjacent cell; The first word line address is subtracted by 1 to obtain the third word line address; the third word line indicated by the third word line address is adjacent to the first word line; the third word line is coupled to the adjacent unit.

6. The method according to claim 2, characterized in that, Based on the first bit line address, the second bit line address and the third bit line address are determined, including: When the first bit line address is equal to the minimum bit line address, the first bit line address is incremented by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The maximum bit line address is determined to obtain the third bit line address; the third bit line indicated by the third bit line address is the last bit line in the transmission line; the third bit line is coupled to the remote unit.

7. The method according to claim 2, characterized in that, Based on the first bit line address, the second bit line address and the third bit line address are determined, including: When the first bit line address is equal to the maximum bit line address, the first bit line address is subtracted by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The minimum bit line address is determined to obtain the third bit line address; the third bit line indicated by the third bit line address is the first bit line in the transmission line; the third bit line is coupled to the remote unit.

8. The method according to claim 2, characterized in that, Based on the first bit line address, the second bit line address and the third bit line address are determined, including: If the first bit line address is not equal to the minimum bit line address and not equal to the maximum bit line address, the first bit line address is incremented by 1 to obtain the second bit line address; the second bit line indicated by the second bit line address is adjacent to the first bit line; the second bit line is coupled to the adjacent cell. The first bit line address is subtracted by 1 to obtain the third bit line address; the third bit line indicated by the third bit line address is adjacent to the first bit line; the third bit line is coupled to the adjacent cell.

9. The method according to claim 2, characterized in that, The address set includes: a first address, a second address, a third address, and a fourth address; The first address includes the first word line address and the second bit line address; The second address includes the first word line address and the third bit line address; The third address includes the second word line address and the first bit line address; The fourth address includes the third word line address and the first bit line address.

10. The method according to claim 1, characterized in that, The current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count, including: Increment the current write crosstalk impact count for each of the second target storage units by 1 to obtain the updated write crosstalk impact count.

11. A storage system, characterized in that, include: A phase-change memory includes a memory cell array and multiple transmission lines. The memory cell array includes multiple memory cells arranged in an array, and the multiple memory cells are coupled between the multiple transmission lines. The controller is coupled to the phase-change memory; the controller is configured to: A first target storage cell is determined among the plurality of storage cells, and a first transmission line is determined among the plurality of transmission lines, wherein the first target storage cell is coupled to the first transmission line; the first target storage cell includes a storage cell that has completed one write operation. A plurality of second target storage cells are determined among the plurality of storage cells; the second target storage cell includes at least one of an adjacent cell and a remote cell; the adjacent cell is adjacent to the first target storage cell; the remote cell is coupled to the first transmission line; and the remote cell and the first target storage cell are respectively the first storage cell and the last storage cell on the first transmission line; The current write crosstalk impact count for each of the second target storage units is updated to obtain the updated write crosstalk impact count; From a plurality of second target storage units, storage units whose updated write crosstalk impact count is greater than a preset threshold number are selected to obtain third target storage units; A refresh operation is performed on the third target storage unit.

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