FeFET-based storage and computing unit and read-write decoupled storage and computing integrated system

Abstract

The application discloses a FeFET-based memory and computing unit and a read-write decoupled memory and computing integrated system, the memory and computing unit comprises a 4T structure composed of a first MOS tube, a second MOS tube, a third MOS tube and a FeFET, the first MOS tube is connected to a source line to form a write path, the second MOS tube and the third MOS tube are connected to a bit line to form a read path, and the write path and the read path are independent of each other; the FeFET has a non-volatile threshold voltage state, the non-volatile threshold voltage state is used for storing data and controlling the level change of the bit line, so that at least one of data reading, Boolean logic operation, ternary content addressable memory (TCAM) search and full adder operation is realized; the advantage is that the same hardware architecture can be compatible with and efficiently support multiple working modes of data storage, Boolean logic operation, TCAM search and full adder operation, the performance bottleneck caused by the decoupling of a functional array and the coupling of a read-write path is eliminated from an architecture level, and the practical application of memory and computing integration technology in edge intelligent terminals is promoted.

Description

Technical Field

[0001] This invention relates to digital logic operation technology, and in particular to a FeFET-based in-memory computing unit and a read-write decoupled in-memory computing system. Background Technology

[0002] With the rapid development of artificial intelligence and Internet of Things technologies, edge computing, smart gateways, and other terminal devices are facing increasingly higher real-time processing requirements in application scenarios. These terminal devices typically need to be able to complete real-time storage, high-speed retrieval, and arithmetic operations on massive amounts of data, exhibiting typical "storage + retrieval + computation" three-in-one application characteristics.

[0003] In the actual operation of these terminal devices, massive amounts of network terminal addresses and instruction data need to be written into the storage unit first. Then, the retrieval unit quickly searches and matches the target address. After matching, the processing unit performs arithmetic operations and logical judgments on the corresponding parameters. Storage, retrieval, and processing form a closely related logical loop, and none of them can be omitted. If these functional modules are separated, the storage unit, which only has storage functions, will not be able to handle address matching and logical judgment tasks. On the other hand, the retrieval unit and the processing unit, lacking local storage support, have to frequently call data across arrays, resulting in significant data transfer overhead. This functional separation will lead to frequent data transfer between different functional modules, severely restricting response speed and making it difficult to meet the stringent requirements of instantaneous response in edge computing scenarios.

[0004] Among various non-volatile memories, ferroelectric field-effect transistors (FeFETs) have become ideal candidates for in-memory computing units due to their high on / off ratio and good compatibility with standard CMOS processes. Currently, some research has attempted to integrate storage and computing functions, but for the aforementioned edge computing scenarios, existing implementations have two significant drawbacks: First, existing solutions mostly employ dedicated discrete array designs, meaning that storage, ternary content-addressable memory (TCAM), and logic operations are deployed in physically isolated independent arrays. This architecture heavily relies on complex on-chip networks or additional interface circuits to achieve data interaction and control coordination between arrays, making it difficult to dynamically reconfigure multiple computing modes within a single array. In edge computing scenarios with varying task requirements, application flexibility is significantly limited.

[0005] Secondly, existing solutions generally lack physical isolation design for read and write paths, resulting in serious read-write mutual exclusion problems. In traditional in-memory computing units, whether performing TCAM retrieval or full adder operations, shared bit lines or data paths are usually required, making it impossible to perform data write-back or state update operations during computation. This single-path design makes it difficult to execute read and write operations in parallel, causing pipeline stalls when the processor switches between computation and storage tasks, which is insufficient to meet the core real-time processing requirements of edge computing devices.

[0006] Therefore, there is an urgent need for a new type of in-memory computing unit and system architecture that can solve the above two defects at the same time. Summary of the Invention

[0007] This invention aims to overcome the shortcomings of existing technologies and provide a FeFET-based in-memory computing unit and a read / write decoupled in-memory computing system. This in-memory computing unit and read / write decoupled in-memory computing system enable the same hardware architecture to be compatible with and efficiently support multiple operating modes, including data storage, Boolean logic operations, TCAM retrieval, and full adder operations. It eliminates the performance bottlenecks caused by functional array separation and read / write path coupling at the architectural level, promoting the practical application of multifunctional in-memory computing technology in edge intelligent terminals.

[0008] This invention solves the technical problems in existing FeFET-based in-memory computing schemes, such as the difficulty in dynamic reconfiguration and limited application flexibility due to the discrete functional array, as well as the mutual exclusion of read and write operations caused by read and write path coupling, the inability to perform data write-back or state updates in parallel, and the resulting pipeline stalls.

[0009] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a FeFET-based memory cell, comprising a 4T structure consisting of a first MOS transistor, a second MOS transistor, a third MOS transistor, and a FeFET. The first MOS transistor is connected to a source line to form a write path, and the second MOS transistor and the third MOS transistor are connected to a bit line to form a read path. The write path and the read path are independent of each other. The FeFET has a non-volatile threshold voltage state, which is used to store data and to control the level change of the bit line to realize at least one of data readout, Boolean logic operation, tri-state content addressing, and full adder operation.

[0010] When the above-mentioned memory computing units are used to build a memory computing array structure, in the same working cycle, while performing a read or logical calculation on a certain memory computing unit through the bit line, a write operation can also be performed on other memory computing units through the source line, thereby achieving decoupling of read and write operations.

[0011] In a preferred embodiment, the drain of the FeFET is the horizontal line terminal of the memory cell, connected to the horizontal line and receiving a horizontal line excitation signal. The gate is the word line terminal of the memory cell, and the source is connected to the drain of the first MOS transistor and the gate of the second MOS transistor. The word line terminal of the memory cell is connected to the word line and receiving a word line excitation signal. The gate of the first MOS transistor is the word select line terminal of the memory cell, and the source is the source line terminal of the memory cell. The word select line terminal of the memory cell is connected to the word select line and receiving a word select line excitation signal, and the source line terminal of the memory cell is connected to the source line and receiving a source line excitation signal. The source of the second MOS transistor is grounded, and its drain is connected to the source of the third MOS transistor. The gate of the third MOS transistor is the read select line terminal of the memory cell, and its drain is the bit line terminal of the memory cell. The read select line terminal of the memory cell is connected to the read select line and receiving a read select line excitation signal, and the bit line terminal of the memory cell is connected to the bit line and receiving a bit line excitation signal.

[0012] In the aforementioned memory computing unit, the non-volatile threshold voltage state of the FeFET includes a low threshold voltage state and a high threshold voltage state. The FeFET is an N-type FeFET, and the first MOSFET, the second MOSFET, and the third MOSFET are all NMOS transistors. When a positive voltage is applied to the gate of the FeFET, the FeFET is turned on and is in the low threshold voltage state. When a negative voltage is applied to the gate of the FeFET, the FeFET is turned off and is in the high threshold voltage state. Therefore, the non-volatile threshold voltage state of the FeFET can be controlled by the word line excitation signal connected to the word line WL and the source line excitation signal connected to the source line SL, making it either in the low threshold voltage state or the high threshold voltage state. During data writing, the voltage between the gate and source of the FeFET is controlled through the write path formed by the source line SL-first MOSFET-FeFET-word line WL, thereby controlling the non-volatile threshold voltage state of the FeFET to achieve the writing of logic data 1 or 0. When performing data reading or calculation, the read path consisting of horizontal line HL-FeFET-second MOS transistor-third MOS transistor-read select line RSL is activated, and the discharge of bit line BL is controlled according to the non-volatile threshold voltage state of FeFET, resulting in a level change. Logic data reading or calculation is realized by detecting the level change of bit line BL.

[0013] Secondly, this invention also provides a FeFET-based read / write decoupled in-memory computing system, including a row driving circuit, a column driving circuit, a computing array, and a sensing amplifier circuit. The row driving circuit generates row excitation signals, and the column driving circuit generates column excitation signals. The computing array is formed by arranging multiple computing units in a multi-row, multi-column array. The computing units adopt any of the aforementioned types of computing units. Each column of computing units shares a bit line. By configuring the levels of the row excitation signals and the column excitation signals, the read / write decoupled in-memory computing system can be controlled to selectively enter data storage mode, data readout mode, Boolean logic operation mode, and three-state content addressing mode. The system includes a data storage mode and a full adder operation mode. The data storage mode is implemented by controlling the non-volatile threshold voltage state of the FeFETs in the storage array, and the data readout mode, Boolean logic operation mode, tri-state content addressing mode, and full adder operation mode are implemented by controlling the level changes of the corresponding bit lines. The sensing amplifier circuit is used to detect the level changes and generate corresponding signal outputs. The read / write decoupled storage-computing integrated system also includes logic gate circuits. These logic gate circuits are used in conjunction with the sensing amplifier circuit in the full adder operation mode to obtain the signal output by the sensing amplifier circuit, perform full adder operations, and generate the carry result and summation result of the full adder operation.

[0014] Compared with the prior art, the advantages of the present invention are as follows: (1) Decoupling of read and write paths, supporting parallel operation: The in-memory computing unit of this invention adopts a 4T structure composed of a first MOS transistor, a second MOS transistor, a third MOS transistor, and a FeFET. The write path and the read path are physically independent of each other. In the constructed in-memory computing array, when a certain in-memory computing unit is read or logically calculated through the bit line, other in-memory computing units can be written to simultaneously through the source line. Parallel reading and writing processing is achieved within the same working cycle, avoiding pipeline stalls caused by read-write mutual exclusion in traditional solutions.

[0015] (2) Multi-mode reconfigurable: By configuring the levels of row excitation signals and column excitation signals, the same system can selectively enter data storage mode, data readout mode, Boolean logic operation mode, three-state content addressing mode and full adder operation mode. It does not require separate design of discrete arrays or additional circuits for each function, providing flexible underlying support for terminal devices such as smart gateways and adapting to the combined scenario of "storage + retrieval + operation".

[0016] In a further technical solution, during the working cycle of performing Boolean logic operations or full adder operations, the memory array supports simultaneously writing the result of the previous stage operation or external data into the target memory unit through the source line while using the bit line to sense the current operation result.

[0017] In a further technical solution, the in-memory array is formed by arranging M×N in-memory units in an M-row N-column array, where M and N are even numbers greater than or equal to 2; the sensing amplifier circuit includes N sensing amplifiers, each of which corresponds one-to-one with one of the N columns of in-memory units, and each sensing amplifier shares a bit line with its corresponding column of in-memory units; the read-write decoupled in-memory computing system also includes N control units; the logic gate circuit includes N logic operation units; the N control units are connected one-to-one with the N sensing amplifiers, and the N logic operation units are connected one-to-one with the N control units.

[0018] In a further technical solution, the memory array further includes M horizontal lines, M word lines, M word select lines, M read select lines, N source lines, and N bit lines; the horizontal line end of the m-th row memory unit is connected to the m-th horizontal line; the word line end of the m-th row memory unit is connected to the m-th word line; the word select line end of the m-th row memory unit is connected to the m-th word select line; the read select line end of the m-th row memory unit is connected to the m-th read select line; the source line end of the n-th column memory unit is connected to the n-th source line; the bit line end of the n-th column memory unit is connected to the n-th bit line; the n-th sense amplifier is connected to the n-th bit line; m=1, 2, ..., M, n=1, 2, ..., N.

[0019] In a further technical solution, the row excitation signal includes an M-bit horizontal line excitation signal, an M-bit word line excitation signal, an M-bit word select line excitation signal, and an M-bit read select line excitation signal; the M-bit horizontal line excitation signal, the M-bit word line excitation signal, the M-bit word select line excitation signal, and the M-bit read select line excitation signal are respectively output to M horizontal lines, M word lines, M word select lines, and M read select lines. The column excitation signal includes an N-bit source line excitation signal, an N-bit bit line excitation signal, an N-bit switch excitation signal, and an N-bit latch excitation signal; the N-bit source line excitation signal and the N-bit bit line excitation signal are respectively output to N source lines and N bit lines, the N-bit switch excitation signal is output to N control units to control the N control units to turn on or off, and the N-bit latch excitation signal is output to N control units to control the N control units to sample or latch data.

[0020] In a further technical solution, each sensing amplifier has an input terminal, a reference terminal, a positive output terminal, and a negative output terminal; each logic operation unit has a first input terminal, a second input terminal, a carry input terminal, a summation output terminal, and a carry output terminal; each control unit has a first input terminal, a second input terminal, a switch control terminal, a latch control terminal, a first output terminal, and a second output terminal; the input terminal of the nth sensing amplifier is connected to the nth bit line; the positive output terminal of the nth sensing amplifier is connected to the first input terminal of the nth control unit, and the negative output terminal of the nth sensing amplifier is connected to the nth control unit. The second input terminal of the nth control unit is connected to the first input terminal of the nth logic operation unit, and the second output terminal of the nth control unit is connected to the second input terminal of the nth logic operation unit. The summation output terminal of the nth logic operation unit is used to output the nth bit of the summation result, the carry output terminal of the nth logic operation unit is used to output the nth bit of the carry result, the switch control terminal of the nth control unit is used to receive the nth bit of the N-bit switch excitation signal, and the latch control terminal of the nth control unit is used to receive the nth bit of the N-bit latch excitation signal.

[0021] In a preferred embodiment, each logic operation unit includes a first XOR gate, a first NOT gate, a first AND gate, a second AND gate, and a first OR gate. The first NOT gate has an input terminal and an output terminal. The first XOR gate, the first AND gate, the second AND gate, and the first OR gate each have a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate is the second input terminal of the logic operation unit. The second input terminal of the first AND gate is connected to the input terminal of the first NOT gate, and its connection terminal is the first input terminal of the logic operation unit. The output terminal of the first AND gate is connected to the first input terminal of the first XOR gate and the first input terminal of the second AND gate, respectively. The output terminal of the first NOT gate is connected to the first input terminal of the first OR gate. The second input terminal of the second AND gate is connected to the second input terminal of the first XOR gate, and its connection terminal is the carry input terminal of the logic operation unit. The output terminal of the second AND gate is connected to the second input terminal of the first OR gate. The output terminal of the first XOR gate is the summation output terminal of the logic operation unit, and the output terminal of the first OR gate is the carry output terminal of the logic operation unit.

[0022] In a preferred embodiment, the control unit includes a first latch and a first switch. The first latch has an input terminal, an output terminal, and a latch control terminal. The first switch has a first terminal, a second terminal, and a switch control terminal. The input terminal of the first latch and the first terminal of the first switch are respectively the first input terminal and the second input terminal of the control unit. The output terminal of the first latch and the second terminal of the first switch are respectively the first output terminal and the second output terminal of the control unit. The latch control terminal of the first latch is the latch control terminal of the control unit, and the switch control terminal of the first switch is the switch control terminal of the control unit. Attached Figure Description

[0023] Figure 1 A circuit diagram of a memory computing unit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the signal states during the write and read operations of the storage unit provided in this embodiment of the invention; wherein, (a) is the write logic data 1, (b) is the write logic data 0, (c) is the read logic data 1, and (d) is the read logic data 0. Figure 3 This is a schematic diagram of the structure of the read-write decoupled storage-computing integrated system provided in an embodiment of the present invention; Figure 4 A circuit connection diagram of the sensing amplifier, control unit, and logic operation unit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the implementation of Boolean logic operations in a read-write decoupled storage-computing integrated system provided in an embodiment of the present invention; wherein, (a) represents an N(OR) logic operation; and (b) represents an N(AND) logic operation. Figure 6 A timing diagram illustrating the TCAM matching operation implemented in the read-write decoupled storage-computing integrated system provided in this embodiment of the invention; Figure 7 This is a timing diagram illustrating the decoupled read / write operations implemented in the read / write decoupled storage-computing integrated system provided in this embodiment of the invention. Detailed Implementation

[0024] With the rapid development of artificial intelligence and Internet of Things technologies, terminal devices such as smart gateways are facing increasingly higher requirements for real-time performance and integration in edge computing scenarios. In current typical "storage + retrieval + computing" three-in-one application scenarios, existing FeFET-based in-memory computing solutions are increasingly unable to meet the real-time performance and integration requirements of terminal devices due to the independent arrays and the lack of physical isolation design for read / write paths in the in-memory computing units.

[0025] In view of this, this invention, based on the integration of storage and computing functions, innovatively proposes a storage-computing integrated hardware architecture with decoupled read / write paths and reconfigurable logical functions, to adapt to the typical "storage + retrieval + computing" three-in-one edge computing scenario of terminal devices such as smart gateways, thereby promoting the industrial application of storage-computing integrated technology in edge smart terminals.

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in detail and completely below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can understand and implement them. The embodiments described in this section are only used to illustrate the technical solutions of this invention and are not intended to limit the scope of protection of this invention.

[0027] Example 1: Figure 1 This is a circuit diagram of the memory computing unit according to an embodiment of the present invention. Figure 1 As shown, the memory cell is implemented using a 4T structure, including a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a FeFET F1. FeFET F1 is an N-type FeFET, exhibiting both low and high threshold voltage states. When a positive voltage is applied to the gate of FeFET F1, FeFET F1 is turned on, operating in the low threshold voltage state. When a negative voltage is applied to the gate of FeFET F1, FeFET F1 is turned off, operating in the high threshold voltage state. The first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all NMOS transistors.

[0028] Each memory cell has a horizontal line terminal, a word line terminal, a word select line terminal, a read select line terminal, a source line terminal, and a bit line terminal. The drain of FeFET F1 is the horizontal line terminal of the memory cell, connected to the horizontal line HL, which receives the horizontal line excitation signal. Its gate is the word line terminal of the memory cell, connected to the word line WL, which receives the word line excitation signal. Its source is connected to the drain of the first MOS transistor M1 and the gate of the second MOS transistor M2. The gate of the first MOS transistor M1 is the word select line terminal of the memory cell, connected to the word select line WSL, which receives the word select line excitation signal. Its source is the source line terminal of the memory cell, connected to the source line SL. L is connected to the source line excitation signal; the first MOSFET M1 is connected to the source line to form the write path; the source of the second MOSFET M2 is grounded, and its drain is connected to the source of the third MOSFET M3; the gate of the third MOSFET M3 is the read select line terminal of the memory cell, connected to the read select line RSL, which is connected to the read select line excitation signal; the drain is the bit line terminal of the memory cell, connected to the bit line BL, which is connected to the bit line excitation signal; the second MOSFET M2 controls the discharge path, and together with the third MOSFET M3, they are connected to the bit line to form the read path.

[0029] The specific signal flow of the write path is as follows: source line SL → first MOSFET M1 → FeFET F1 → word line WL. The specific signal flow of the read path is as follows: horizontal line HL → FeFET F1 → second MOSFET M2 → third MOSFET M3 → read select line RSL. The write and read paths are independent in circuit configuration. The write path is controlled by the source line excitation signal, and the read path is controlled by the bit line excitation signal.

[0030] During data writing, the write path is activated. By controlling the voltage difference between the gate and source of the FeFET F1, logic data 1 or 0 is written based on the non-volatile threshold voltage state of the FeFET F1. During data reading or calculation, the read path is activated. By controlling the voltage between the gate and source of the FeFET F1, the non-volatile threshold voltage state of the FeFET F1 is controlled, which in turn controls the discharge state of the bit line BL, causing a level change. Logic data reading or calculation is achieved by detecting the level change of the bit line BL.

[0031] Figure 2 This is a schematic diagram of the signal states during writing and operation of the memory computing unit provided in this embodiment; where (a) represents writing logic data 1, (b) represents writing logic data 0, (c) represents reading logic data 1, and (d) represents reading logic data 0. The following is in conjunction with... Figure 2 The read and write operations of the memory computing unit in this embodiment will be described below: like Figure 2 As shown in (a) and (b), writing logical data 1 or 0 is performed in two stages.

[0032] In the first stage, the word line excitation signal connected to the gate of FeFET F1 is the write level Vwrite (set to 5V in this embodiment, but will be experimentally calibrated according to the specific circuit process parameters in actual use). The horizontal line excitation signal connected to the drain of FeFET F1 is low (0V). The read select line excitation signal connected to the gate of the third MOS transistor M3 is low (0V). At this time, the third MOS transistor M3 is turned off. The bit line excitation signal connected to the drain of the third MOS transistor M3 is low (0V). The word select line excitation signal connected to the gate of the first MOS transistor M1 is the write level Vwrite (5V). At this time, the first MOS transistor M1 is turned on. The source line excitation signal connected to the source of the first MOS transistor M1 is the write data level corresponding to the data to be written. If the source line excitation signal is low (0V), the voltage Vgs (Gate-Source Voltage) between the gate and source of FeFET F1 is 5V, which bears a large positive voltage and is switched to the low threshold voltage state. The corresponding logic data 1 is written. Otherwise, there is no gate-source voltage difference for FeFET F1, and the state remains unchanged.

[0033] In the second stage, the word line excitation signal of the gate of FeFET F1 and the horizontal line excitation signal of the drain are low (0V), the read select line excitation signal connected to the gate of the third MOSFET M3 is low (0V), at this time the third MOSFET M3 is turned off, the bit line excitation signal connected to the drain of the third MOSFET M3 is low (0V), the word select line excitation signal connected to the gate of the first MOSFET M1 is the write level Vwrite (5V), at this time the first MOSFET M1 is turned on, the source line excitation signal connected to the source of the first MOSFET M1 is the write data level corresponding to the data to be written. If the source line excitation signal is low (0V), then FeFET F1 has no gate-source voltage difference and maintains the low threshold voltage state of the first stage of writing. Otherwise, the voltage Vgs between the gate and source of FeFET F1 is -5V, which withstands a large negative voltage and is switched to the high threshold voltage state, and the corresponding logic data 0 is written.

[0034] like Figure 2 As shown in (c) and (d), when reading data, the word line excitation signal of the gate of FeFET F1 is low (0V), the horizontal line excitation signal connected to the drain of FeFET F1 is the read level Vread (set to 1V in this embodiment, but experimentally calibrated according to the specific process parameters of the specific circuit in actual use), the read select line excitation signal connected to the gate of the third MOS transistor M3 is the read level Vread (1V), at this time the third MOS transistor M3 is turned on, the bit line excitation signal connected to the drain of the third MOS transistor M3 is the precharge high level (set to 1V in this embodiment, but experimentally calibrated according to the specific process parameters of the specific circuit in actual use), the word select line excitation signal connected to the gate of the first MOS transistor M1 is low (0V), at this time the first MOS transistor M1 is turned off, and the source line excitation signal connected to the source of the first MOS transistor M1 is low (0V). If FeFET F1 is in a low threshold voltage state (corresponding to logic data 1), the bit line discharges from the pre-charge high level to the low level (0V) through the third MOSFET M3 and the second MOSFET M2. At this time, the level change corresponds to reading logic data 1. Conversely, if the bit line remains at the pre-charge high level, the level change corresponds to reading logic data 0. By detecting the level of the bit line through a sensing amplifier, the corresponding logic data can be read.

[0035] Example 2: Figure 3 This is a schematic diagram of the read-write decoupled in-memory computing system provided in this embodiment. Figure 3 As shown, the system includes row driving circuits, column driving circuits, memory arrays, sensing amplifier circuits, control units, and logic gate circuits.

[0036] Specifically, the in-memory array consists of 64×64 in-memory units of Embodiment 1 arranged in a 64-row × 64-column array. The in-memory array also includes: 64 horizontal lines HL1 to HL64, 64 word lines WL1 to WL64, 64 word select lines WSL1 to WSL64, 64 read select lines RSL1 to RSL64, 64 source lines SL1 to SL64, and 64 bit lines BL1 to BL64.

[0037] In this configuration, the word line terminals of each row of memory units are connected to a corresponding word line, the word select line terminals of each row of memory units are connected to a corresponding word select line, the read select line terminals of each row of memory units are connected to a corresponding read select line, the horizontal line terminals of each row of memory units are connected to a corresponding horizontal line, the bit line terminals of each column of memory units are connected to a corresponding bit line, and the source line terminals of each column of memory units are connected to a corresponding source line.

[0038] In this embodiment, there are 64 control units. Each control unit has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a switch control terminal, and a latch control terminal. The sensing amplifier circuit includes 64 sensing amplifiers, each with an input terminal, a reference terminal, a positive output terminal, and a negative output terminal. The logic gate circuit includes 64 logic operation units, each with a first input terminal, a second input terminal, a carry input terminal, a summation output terminal, and a carry output terminal.

[0039] In this embodiment, the specific connection relationships between the bit lines, sensing amplifiers, control units, and logic operation units are as follows: the i-th bit line is connected one-to-one with the input terminal of the i-th sensing amplifier; the positive output terminal of the i-th sensing amplifier is connected to the first input terminal of the i-th control unit; the negative output terminal of the i-th sensing amplifier is connected to the second input terminal of the i-th control unit; the first output terminal of the i-th control unit is connected to the first input terminal of the i-th logic operation unit; and the second output terminal of the i-th control unit is connected to the second input terminal of the i-th logic operation unit, where i = 1, 2, ..., 64. In this embodiment, the row driving circuit generates row stimulus signals according to external working instructions. The row stimulus signals include 64-bit horizontal line stimulus signals, 64-bit word line stimulus signals, 64-bit word select line stimulus signals, and 64-bit read select line stimulus signals. The column driving circuit generates column stimulus signals according to external working instructions. The column stimulus signals include 64-bit source line stimulus signals, 64-bit bit line stimulus signals, 64-bit switch stimulus signals, and 64-bit latch stimulus signals. The 64-bit horizontal line excitation signal, 64-bit word line excitation signal, 64-bit word select line excitation signal, and 64-bit read select line excitation signal are output to 64 horizontal lines, 64 word lines, 64 word select lines, and 64 read select lines, respectively. The 64-bit source line excitation signal and 64-bit bit line excitation signal are output to 64 source lines and 64 bit lines, respectively. The 64-bit switch excitation signal is output to the switch control terminals of 64 control units to control the 64 switches to be turned on or off. The 64-bit latch excitation signal is output to the latch control terminals of 64 control units to control the 64 latches to sample or latch data. Both the row drive circuit and the column drive circuit adopt mature technologies in this field.

[0040] In this embodiment, each column of storage and computing units shares a bit line; each sensing amplifier circuit is used to collect the level change of its own bit line and generate corresponding logic data; by configuring the levels of the row excitation signal and the column excitation signal, the read-write decoupled storage and computing integrated system is controlled to selectively enter the data storage mode, data readout mode, Boolean logic operation mode, three-state content addressing mode and full adder operation mode.

[0041] In data storage mode, the corresponding function of data storage mode is realized by the non-volatile threshold voltage state of FeFET F1 in the memory array. Specifically, by configuring the row excitation signal and the column excitation signal, the gate-source voltage difference of FeFET F1 changes its non-volatile threshold voltage state, thereby realizing the storage of logic data 0 (corresponding to the high threshold voltage state) or logic data 1 (corresponding to the low threshold voltage state).

[0042] In the data readout mode, Boolean logic operation mode, or tri-state content addressing mode, the non-volatile threshold voltage state of FeFET F1 in the memory array controls the level change of the corresponding bit line to realize the data readout mode, Boolean logic operation mode, or tri-state content addressing mode. At this time, the sensing amplifier circuit connected to the corresponding bit line detects the level change and generates the corresponding readout data, operation data, or addressing data output.

[0043] In the full adder operation mode, the level change of the corresponding bit line is controlled by the non-volatile threshold voltage state of FeFET F1 in the memory array to realize the corresponding function of the full adder operation mode. At this time, the sensing amplifier circuit connected to the corresponding bit line detects the level change and generates the corresponding logic data. The logic operation unit connected to the sensing amplifier circuit obtains the logic data output by the sensing amplifier circuit, performs the full adder operation, and generates the carry result and summation result of the full adder operation.

[0044] Example 3: Based on Example 2, this example further defines the specific circuit structure of the control unit, sensing amplifier and logic operation unit.

[0045] In this embodiment, the sensing amplifier is a differential latching sensing amplifier, and its reference terminal is connected to a reference voltage V. ref When the input voltage is higher than V ref When the input voltage is below V, the positive output terminal outputs a low level and the negative output terminal outputs a high level; when the input voltage is below V... ref When the positive output terminal outputs a high level, the negative output terminal outputs a low level.

[0046] Figure 4 This is a circuit connection diagram of the sensing amplifier, control unit, and logic operation unit provided in this embodiment. Figure 4 As shown, each control unit includes a first latch L1 and a first switch S1. The first latch L1 has an input terminal, an output terminal, and a latch control terminal. The first switch S1 has a first terminal, a second terminal, and a switch control terminal. The input terminal of the first latch L1 and the first terminal of the first switch S1 are respectively the first input terminal and the second input terminal of the control unit. The output terminal of the first latch L1 and the second terminal of the first switch S1 are respectively the first output terminal and the second output terminal of the control unit. The latch control terminal of the first latch L1 is the latch control terminal of the control unit, and the switch control terminal of the first switch S1 is the switch control terminal of the control unit.

[0047] like Figure 4As shown, each logic operation unit includes a first XOR gate (xor1), a first NOT gate (not1), a first AND gate (and1), a second AND gate (and2), and a first OR gate (or1). The first NOT gate (not1) has an input terminal and an output terminal. The first XOR gate (xor1), the first AND gate (and1), the second AND gate (and2), and the first OR gate (or1) all have a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate (and1) is the second input terminal of the logic operation unit. The second input terminal of the first AND gate (and1) is connected to the input terminal of the first NOT gate (not1), and its connection terminal is the first input terminal of the logic operation unit. The output of AND gate AND1 is connected to the first input of XOR gate XOR1 and the first input of AND gate AND2, respectively; the output of NOT gate NOT1 is connected to the first input of OR gate OR1; the second input of AND gate AND2 is connected to the second input of XOR gate XOR1, and its connection point is the carry input of the logic operation unit; the output of AND gate AND2 is connected to the second input of OR gate OR1; the output of XOR gate XOR1 is the summation output of the logic operation unit; and the output of OR gate OR1 is the carry output of the logic operation unit.

[0048] Example 4: Based on Example 2 or 3, this example details the level configuration and operation process of the read-write decoupled storage-computing integrated system under various working modes.

[0049] I. Data storage mode: Data is stored in two stages using a row-by-row writing method.

[0050] In the first stage, the word line excitation signal and word select line excitation signal connected to a specific row of memory units to be written are configured to write level (high level). This row of memory units is selected and enters the working state. The word line excitation signal and word select line excitation signal connected to other rows of memory units are configured to low level, and they are not selected; their original stored data remains unchanged. The 64-bit horizontal line excitation signal, 64-bit read select line excitation signal, and 64-bit bit line excitation signal are all configured to low level, and the 64-bit source line excitation signal is configured to the write data level corresponding to the data to be written. The 64-bit switch excitation signal and 64-bit latch excitation signal are all configured to low level. The first switch S1 of all 64 control units is turned off, and the first latch L1 is in the latched state. Subsequent logic gate circuits do not work.

[0051] At this time, within each memory cell of the selected row, the read select line excitation signal connected to the gate of the third MOS transistor M3 is low, the third MOS transistor M3 is turned off, the bit line excitation signal connected to the drain of the third MOS transistor M3 is low, the word select line excitation signal connected to the gate of the first MOS transistor M1 is at the write level, the first MOS transistor M1 is turned on, and a voltage difference is generated between the gate and source of FeFET F1 caused by the word line excitation signal and the source line excitation signal. If the write data level is equal to the write level, the voltage difference is 0, and the state of FeFET F1 remains unchanged. If the write data level is low, the voltage difference between the gate and source of FeFET F1 is positive, and it is in a low threshold voltage state, realizing the writing of logic data 1.

[0052] In the second stage, the word select line excitation signal connected to a specific row of memory units to be written to is kept at the write level, and the word line excitation signal is configured to be low. The word line excitation signals and word select line excitation signals connected to other rows of memory units are all kept low, indicating they are not selected, and their original stored data remains unchanged. The 64-bit horizontal line excitation signal, the 64-bit read select line excitation signal, and the 64-bit bit line excitation signal are all kept low, and the 64-bit source line excitation signal is configured to the write data level corresponding to the data to be written. The 64-bit switch excitation signal and the 64-bit latch excitation signal are both configured to be low. The first switch S1 of all 64 control units is turned off, and the first latch L1 is in a latched state. Subsequent logic gates do not operate.

[0053] At this time, within each memory cell of the selected row, the read select line excitation signal connected to the gate of the third MOS transistor M3 is low, so the third MOS transistor M3 is turned off. The bit line excitation signal connected to the drain of the third MOS transistor M3 is low, and the word select line excitation signal connected to the gate of the first MOS transistor M1 is at the write level, so the first MOS transistor M1 is turned on. The source line excitation signal connected to the source of the first MOS transistor M1 is at the write data level corresponding to the data to be written. A voltage difference is generated between the gate and source of FeFET F1 caused by the word line excitation signal and the source line excitation signal. If the write data level in the first stage is equal to the write level, then the write data level at this time is also equal to the write level, and the voltage difference between the gate and source of FeFET F1 is negative, in a high threshold voltage state, realizing the writing of logic data 0. If the write data level in the first stage is low, then the write data level at this time is also low, and the voltage difference between the gate and source of FeFET F1 is 0, maintaining the logic data 1 written in the first stage.

[0054] II. Data Reading Mode: Data is read out using a row-by-row reading method.

[0055] When a specific row of data to be read is connected to a memory cell with its read select line and horizontal line excitation signals at read level, that row of memory cell is selected and enters the working state. The read select line and horizontal line excitation signals for other rows of memory cells are configured to low level and are not selected. All 64-bit bit line excitation signals are precharged high, while the 64-bit word line excitation signal, 64-bit word select line excitation signal, and 64-bit source line excitation signal are configured low. The 64-bit switch excitation signal and 64-bit latch excitation signal are configured low. The first switch S1 of all 64 control units is off, and the first latch L1 is in a latched state; subsequent logic gates are not operational.

[0056] At this time, within each memory cell of the selected row of memory cells, the word line excitation signal connected to the gate of FeFET F1 is low, the horizontal line excitation signal connected to the drain of FeFET F1 is read level, the read select line excitation signal connected to the gate of the third MOSFET M3 is read level, the third MOSFET M3 is turned on, the bit line excitation signal connected to the drain of the third MOSFET M3 is precharge high level, the word select line excitation signal connected to the gate of the first MOSFET M1 is low level, the first MOSFET M1 is turned off, and the source line excitation signal connected to the source of the first MOSFET M1 is low level. If FeFET F1 is in a low threshold voltage state, the bit line discharges from the precharge high level to the low level through the third MOSFET M3 and the second MOSFET M2, and the bit line level change corresponds to logic data 1; conversely, if FeFET F1 is in a high threshold voltage state, the bit line remains at the precharge high level, and the bit line level change corresponds to logic data 0.

[0057] By using 64 sensing amplifiers to detect the level changes of 64 bit lines and generate corresponding stored data outputs, the corresponding 64-bit logic data can be read out.

[0058] III. Boolean Logic Operation Mode: Boolean logic operations are performed using logical data stored in two rows of storage units as logical operands. The logical data in each row of storage units constitutes an N-bit logical operand, and the logical data stored in each storage unit is used as a one-bit logical operand.

[0059] The read select line and horizontal line excitation signals connected to the two in-memory units performing Boolean logic operations are both configured to read level, and these two in-memory units are selected and enter the working state. The read select line and horizontal line excitation signals connected to the other in-memory units are both configured to low level, and they are not selected. The 64-bit bit line excitation signal is configured to precharge high level, and the 64-bit word line excitation signal, 64-bit word select line excitation signal, and 64-bit source line excitation signal are all configured to low level. The 64-bit switch excitation signal and 64-bit latch excitation signal are both configured to low level, the first switch S1 of all 64 control units is turned off, the first latch L1 is in latched state, and the subsequent logic gate circuits do not work.

[0060] In the two-row memory cell, within the two memory cells in the same column, the word line excitation signals connected to the gate of FeFET F1 are all low level, the horizontal line excitation signals connected to the drain of FeFET F1 are all read level, and the read select line excitation signals connected to the gate of the third MOS transistor M3 are all read level. The duration of the read select line excitation signal is configured to match the logic operation type. At this time, the third MOS transistor M3 of the two memory cells is turned on, the bit line excitation signal connected to the drain of the third MOS transistor M3 is precharge high level, and the word select line excitation signals connected to the gate of the first MOS transistor M1 are all low level. At this time, the first MOS transistor M1 of the two memory cells is turned off, and the source line excitation signal connected to the source of the first MOS transistor M1 is low level.

[0061] When implementing N(AND) logic operations, the duration of the read select line excitation signal is configured to be a preset short time to ensure that when the bit lines where the two memory units are located discharge slowly, they cannot be completely discharged to a low level within the duration of the read select line excitation signal.

[0062] If both FeFET F1 of the two memory cells are in a low threshold voltage state, that is, both logic operands are logic data 1, then the discharge paths of both memory cells are open. Regardless of the duration of the read select line excitation signal, the bit line containing it will discharge rapidly from the precharge high level to the low level through the third MOS transistor M3 and the second MOS transistor M2 of the two memory cells.

[0063] If both FeFET F1 of the two memory cells are in a high threshold voltage state, that is, both logic operands are logic data 0, then the discharge paths of the two memory cells are closed, and the bit line where the read select line excitation signal is located remains precharged high, regardless of the duration of the read select line excitation signal.

[0064] If the FeFET F1 of two memory cells is in a low threshold voltage state and a high threshold voltage state, meaning the two logic operands are logic data 0 and 1 respectively, and one memory cell has its discharge path open while the other has its discharge path closed, then the bit line of that memory cell can only slowly discharge from the pre-charge high level through the third MOSFET M3 and the second MOSFET M2 of one memory cell. Since the duration of the read select line excitation signal is short, the bit line cannot be completely discharged to a low level within the duration of the read select line excitation signal.

[0065] Therefore, by detecting the level change of the bit line during the duration of the read select line excitation signal (rapid discharge to low level, holding high level, slow discharge but not to low level) by the sensing amplifier, the positive output terminal of the sensing amplifier can output the AND logic operation result of two logic operands, and the negative output terminal can output the NAND logic operation result of two logic operands.

[0066] When implementing N(OR) logic operation, the duration of the read select line excitation signal is configured to be a preset long time to ensure that when the bit lines where the two memory units are located discharge slowly, they can be completely discharged to a low level within the duration of the read select line excitation signal.

[0067] If both FeFET F1 of the two memory cells are in a low threshold voltage state, that is, both logic operands are logic data 1, then the discharge paths of both memory cells are open. Regardless of the duration of the read select line excitation signal, the bit line where it is located discharges rapidly from the precharge high level to the low level through the third MOS transistor M3 and the second MOS transistor M2 of the two memory cells.

[0068] If both FeFET F1 values ​​of the two memory cells are in a high threshold voltage state, meaning both logic operands are logic data 0, then the discharge paths of both memory cells are closed, and the bit lines containing the read select line excitation signal remain precharged high regardless of the duration of the excitation signal.

[0069] If the FeFET F1 of two memory cells is in a low threshold voltage state and a high threshold voltage state, meaning the two logic operands are logic data 1 and 0 respectively, and one memory cell has its discharge path open while the other has its discharge path closed, then the bit line of that memory cell can only slowly discharge from the pre-charge high level through the third MOSFET M3 and the second MOSFET M2 of one memory cell. Since the duration of the read select line excitation signal is relatively long, the bit line can be completely discharged to the low level within the duration of the read select line excitation signal.

[0070] Therefore, by detecting the level change of the bit line during the duration of the read selection line excitation signal by the sensing amplifier (rapid discharge to low level, hold high level, slow discharge to low level), the positive output terminal of the sensing amplifier outputs the OR logic operation result of two logic operands, and the negative output terminal outputs the NOR logic operation result of two logic operands.

[0071] It should be noted that, in actual use, the duration of the read select line excitation signal is determined according to the actual circuit parameters, so that when the N(AND) logic bit line discharges slowly, it cannot be completely discharged to a low level within the duration of the read select line excitation signal, and when the N(OR) logic bit line discharges slowly, it can be completely discharged to a low level within the duration of the read select line excitation signal.

[0072] Figure 5 The diagram illustrates the implementation of Boolean logic operations in the read-write decoupled storage-computing integrated system provided in this embodiment of the invention; wherein, (a) is an N(OR) logic operation; and (b) is an N(AND) logic operation. Figure 5 In this context, A and B represent any two memory cells located in the same column within the two rows of memory cells performing Boolean logic operations; BL represents the bit line level of memory cells A and B; RSL-A and RSL-B represent the read select line excitation signals connected to memory cells A and B, respectively; and V... ref The reference voltage is connected to the reference terminal of the sense amplifier connected to the same bit line as the memory units A and B; t0 represents the time when the logic data write operation is completed; the time period from t0 to t1 represents the duration of the read select line excitation signal during the N(AND) logic operation; the time period from t0 to t2 represents the duration of the read select line excitation signal during the N(OR) logic operation.

[0073] like Figure 5 As shown in (a), when implementing Boolean logic N(OR), the duration of the read select line excitation signal is preset to t0 to t2. Before time t0, logic data is written in the same manner as in Example 1, and the bit line excitation signal of the drain of the third MOS transistor M3 connected to memory units A and B is precharge high level. At time t0, the read select line excitation signal of the gate of the third MOS transistor M3 connected to memory units A and B is read level, and at this time, the third MOS transistor M3 of both memory units is turned on. When both memory units A and B store logic data 0, the level BL of their respective bit lines remains precharge high level, which is greater than V. ref When memory cell A stores logic data 0 and memory cell B stores logic data 1, their respective bit lines begin to discharge from time t0 and are fully discharged by time t2. At this time, the bit line level BL is less than V. refWhen both memory cell A and memory cell B store logic data 1, their respective bit lines rapidly discharge from a pre-charge high level starting at time t0 and are fully discharged at time t1. At this time, the bit line level BL is less than V. ref Therefore, by detecting the level change of the corresponding bit line through the sensing amplifier, the result of the N(OR) logic operation of the two memory units connected to that bit line can be output.

[0074] like Figure 5 As shown in (b), when implementing Boolean logic N (AND), the duration of the read select line excitation signal is preset to t0 to t1. Before time t0, logic data is written in the same manner as in Example 1, and the bit line excitation signal of the drain of the third MOS transistor M3 connected to memory units A and B is precharge high level. At time t0, the read select line excitation signal of the gate of the third MOS transistor M3 connected to memory units A and B is read level, and at this time, the third MOS transistor M3 of both memory units is turned on. When both memory units A and B store logic data 0, the level BL of their respective bit lines remains precharge high level, which is greater than V. ref When memory cell A stores logic data 0 and memory cell B stores logic data 1 respectively, their respective bit lines begin discharging from time t0. At time t1, the read select line excitation signal connected to the gate of the third MOS transistor M3 of memory cells A and B is at a low level, and both third MOS transistors M3 of both memory cells are turned off. Because the duration of the read select line excitation signal is short, the corresponding bit line cannot completely discharge to a low level within the duration of the read select line excitation signal. At this time, the level BL of the corresponding bit line is greater than V. ref When both memory cell A and memory cell B store logic data 1, their respective bit lines rapidly discharge from a pre-charge high level starting at time t0 and are fully discharged at time t1. At this time, the level BL of their respective bit lines is less than V. ref Therefore, by detecting the level change of the corresponding bit line through the sensing amplifier, the result of the N (AND) logic operation of the two memory units connected to that bit line can be output.

[0075] IV. Three-state content addressing mode: In each column of 64 memory cells, two adjacent memory cells are combined into a TCAM cell. The two memory cells in the TCAM cell store complementary data or irrelevant states. In this case, the memory array is formed by 32×64 TCAM cells arranged in a 32-row, 64-column array. Each row of TCAM cells consists of two rows of memory cells.

[0076] Taking the tri-state addressing of any row of TCAM cells as an example, the horizontal line excitation signals of the two in-memory units of that row of TCAM cells are configured to read level, and the read select line excitation signals are configured to a pair of complementary levels to represent the search data level, thus putting that row of TCAM cells into the working state. The horizontal line excitation signals and read select line excitation signals of the in-memory units of other rows of TCAM cells are configured to low level, indicating they are not selected. The 64-bit bit line excitation signal is configured to precharge high level, and the 64-bit word line excitation signal, 64-bit word select line excitation signal, and 64-bit source line excitation signal are all configured to low level. The 64-bit switch excitation signal and 64-bit latch excitation signal are both configured to low level, the first switch S1 of all 64 control units is turned off, the first latch L1 is in the latched state, and subsequent logic gates do not operate.

[0077] For any TCAM unit, in its two memory units, the word line excitation signals connected to the gate of FeFET F1 are all low level, the horizontal line excitation signals connected to the drain of FeFET F1 are all read level, the read select line excitation signals connected to the gate of the third MOS transistor M3 are a pair of complementary levels, the bit line excitation signals connected to the drain of the third MOS transistor M3 are precharge high level, and the word select line excitation signals connected to the gate of the first MOS transistor M1 are all low level. At this time, the first MOS transistor M1 of both memory units is turned off, and the source line excitation signal connected to the source of the first MOS transistor M1 is low level.

[0078] If both FeFET F1 of the two memory cells are in a high threshold voltage state and both store logic data 0, it means that the TCAM cell stores an irrelevant state (X). At this time, regardless of the high or low state of the read select line excitation signal (complementary level) connected to the two memory cells, the bit lines where the two memory cells are located will remain precharged high.

[0079] If, in the two memory-based memory units, the FeFET F1 of the first memory-based unit is in a low threshold voltage state, storing logic data 1, and the second memory-based unit is in a high threshold voltage state, storing logic data 0, then this indicates that the TCAM unit stores logic data 1. If, at this time, the read select line excitation signal connected to the first memory-based unit is high, and the read select line excitation signal connected to the second memory-based unit is low, then the search data level corresponds to logic data 0, which does not match the logic data 1 stored in the TCAM unit. The bit line connected to the TCAM unit discharges from the pre-charge high level to the low level through the third MOS transistor M3 and the second MOS transistor M2 of the first memory-based unit. Conversely, if the search data level corresponds to logic data 1, which matches the logic data 1 stored in the TCAM unit, the bit line connected to the TCAM unit remains at the pre-charge high level.

[0080] If, in the two memory-based memory units, the FeFET F1 of the first memory-based unit is in a high threshold voltage state, storing logic data 0, and the FeFET F1 of the second memory-based unit is in a low threshold voltage state, storing logic data 1, then this indicates that the TCAM unit stores logic data 0. If the read select line excitation signal connected to the first memory-based unit is high, and the read select line excitation signal connected to the second memory-based unit is low, then the search data level corresponds to logic data 0, which matches the logic data 0 stored in the TCAM unit, and the bit line connected to the TCAM unit remains at a pre-charge high level. Conversely, if the search data level corresponds to logic data 1, which does not match the logic data 0 stored in the TCAM unit, the bit line connected to the TCAM unit discharges from the pre-charge high level to the low level through the third MOS transistor M3 and the second MOS transistor M2 of the second memory-based unit.

[0081] Finally, the search matching result is read out by detecting the level change of the corresponding bit line through each sensing amplifier.

[0082] Figure 6 This is a timing diagram illustrating the implementation of three-state content addressing operations in the read-write decoupled storage-computing integrated system provided in this embodiment. (See diagram for details.) Figure 6 As shown, taking the three-state content addressing of a TCAM cell in any column as an example, the two storage units in the TCAM cell are denoted as A and B respectively, and storage units A and B constitute a TCAM cell. Figure 6 In the diagram, WSL-A and WSL-B represent the word select line excitation signals connected to memory units A and B, respectively; WL-A and WL-B represent the word line excitation signals connected to memory units A and B, respectively; BL1 represents the bit line level of memory units A and B; HL-A and HL-B represent the horizontal line excitation signals connected to memory units A and B, respectively; SL1 represents the source line excitation signals connected to memory units A and B; and RSL-A and RSL-B represent the read select line excitation signals connected to memory units A and B, respectively.

[0083] Stage (1) is the logic data writing stage, which uses the same method as in Example 1 to write logic data. In this stage, memory unit A writes logic data 0, and memory unit B writes logic data 1, indicating that the TCAM unit stores logic data 0. During this stage, the bit line excitation signal of the drain of the third MOS transistor M3 connected to memory units A and B is a pre-charge high level. Figure 6 As can be seen from this, in stage (1), the logical data 0 in the TCAM unit was written.

[0084] Phase (2) is the search phase for logic data 1. Specifically, in memory cell A and memory cell B, the word line excitation signals connected to the gate of FeFET F1 are all low, the horizontal line excitation signals connected to the drain of FeFET F1 are all read levels, and the word select line excitation signals connected to the gate of the first MOS transistor M1 are all low. At this time, the first MOS transistors M1 in both memory cells are turned off, the source line excitation signal connected to the source of the first MOS transistor M1 is low, the read select line excitation signal connected to the gate of the third MOS transistor M3 in memory cell A is low, and the read select line excitation signal connected to the gate of the third MOS transistor M3 in memory cell B is high, indicating that the search data level corresponds to logic data 1. Since this TCAM unit stores logic data 0, while the search data level corresponds to logic data 1, the two do not match. At this time, the bit lines connected to memory cell A and memory cell B discharge from the pre-charge high level to the low level. Figure 6 As can be seen from this, in stage (2), the bit lines connected to memory units A and B are discharged to a low level.

[0085] Phase (3) is the search phase for logic data 0. Specifically, in memory cell A and memory cell B, the word line excitation signals connected to the gate of FeFET F1 are all low, the horizontal line excitation signals connected to the drain of FeFET F1 are all read levels, and the word select line excitation signals connected to the gate of the first MOS transistor M1 are all low. At this time, the first MOS transistors M1 in both memory cells are turned off, the source line excitation signal connected to the source of the first MOS transistor M1 is low, the read select line excitation signal connected to the gate of the third MOS transistor M3 in memory cell A is high, and the read select line excitation signal connected to the gate of the third MOS transistor M3 in memory cell B is low, indicating that the search data level corresponds to logic data 0. Since this TCAM unit stores logic data 0, and the search data level corresponds to logic data 0, the two match. At this time, the bit lines connected to memory cell A and memory cell B are kept at a precharge high level. Figure 6 As can be seen from this, in stage (3), the bit lines connected to memory units A and B are kept at a pre-charge high level.

[0086] pass Figure 6 It can be seen that the logic function of the three-state content addressing operation implemented in this embodiment is correct and can realize reliable three-state content addressing operation.

[0087] During the actual search, all 64-bit horizontal line excitation signals are configured to read level. The read select line excitation signals of the two in-memory units in each row of the TCAM cell are configured as a pair of complementary levels to indicate that the search data level of that row of the TCAM cell is logic data 1 or 0. The 32 rows of TCAM cells then enter the working state. The 64-bit bit line excitation signal is configured to precharge high level, while the 64-bit word line excitation signal, 64-bit word select line excitation signal, and 64-bit source line excitation signal are all configured low level. The 64-bit switch excitation signal and 64-bit latch excitation signal are both configured low level. The first switch S1 of all 64 control units is turned off, and the first latch L1 is in a latched state. Subsequent logic gates do not operate. Since TCAM cells in the same column share the same bit line, if any TCAM cell in the same column has a mismatch, its connected bit line will discharge from the precharge high level to the low level through the mismatched TCAM cell, indicating that the column search is mismatched. Only when all TCAM cells in the same column are matched, and their connected bit lines remain at the precharge high level, does it indicate that the column search is matched.

[0088] V. Full Adder Operation Mode: The data stored in two rows of memory units are used as the addend and augend of the full adder. The logic data in each row of memory units constitutes an N-bit logic operand. The carry input terminal of each logic unit is connected to a one-bit carry signal from an external input. The logic data stored in each memory unit is used as a one-bit logic operand.

[0089] The full adder operation mode performs two operations in two phases within one cycle: the first phase performs NAND logic operations, and the second phase performs OR logic operations.

[0090] During the first stage of NAND logic operation, the horizontal line excitation signal and read select line excitation signal of the two rows of memory cells involved in the operation are configured to read level, selecting these two rows of memory cells. The duration of the read select line excitation signal is a preset short time. The read select line excitation signal and horizontal line excitation signal connected to other rows of memory cells are configured to low level, and other rows of memory cells are not selected. The 64-bit bit line excitation signal is configured to precharge high level, the 64-bit switch excitation signal is configured to low level, the first switch S1 of the 64 control units is turned off, the 64-bit latch excitation signal is configured to high level, the first latch L1 of the 64 control units samples the NAND logic operation result output by the sense amplifier, and the carry signal connected to the carry input terminal of the 64 logic operation units is configured to low level, so subsequent logic gate circuits do not work. The 64-bit word line excitation signal, the 64-bit word select line excitation signal, and the 64-bit source line excitation signal are all configured to low level.

[0091] At this time, in the two selected memory cells, the word line excitation signals connected to the gate of FeFET F1 in the two memory cells in the same column are both low level, the horizontal line excitation signals connected to the drain of FeFET F1 are both read level, and the read select line excitation signals connected to the gate of the third MOS transistor M3 are both read level. At this time, the third MOS transistor M3 of both memory cells is turned on, and the bit line excitation signal connected to the drain of the third MOS transistor M3 is precharge high level. The word select line excitation signals connected to the gate of the first MOS transistor M1 are both low level. At this time, the first MOS transistor M1 of both memory cells is turned off, and the source line excitation signal connected to the source of the first MOS transistor M1 is low level. Since the duration of the read select line excitation signal is configured to be a preset short time, when the bit lines of the two memory cells are slowly discharged, they cannot be completely discharged to a low level within the duration of the read select line excitation signal.

[0092] If both FeFET F1 of the two memory cells are in a low threshold voltage state, that is, both logic operands are logic data 1, then the discharge paths of both memory cells are open. Regardless of the duration of the read select line excitation signal, the bit line containing it will discharge rapidly from the precharge high level to the low level through the third MOS transistor M3 and the second MOS transistor M2 of the two memory cells.

[0093] If both FeFET F1 of the two memory cells are in a high threshold voltage state, that is, both logic operands are logic data 0, then the discharge paths of the two memory cells are closed, and the bit line where the read select line excitation signal is located remains precharged high, regardless of the duration of the read select line excitation signal.

[0094] If the FeFET F1 of two memory cells is in a low threshold voltage state and a high threshold voltage state, meaning the two logic operands are logic data 0 and 1 respectively, and one memory cell has its discharge path open while the other has its discharge path closed, then the bit line of that memory cell can only slowly discharge from the pre-charge high level through the third MOSFET M3 and the second MOSFET M2 of one memory cell. Since the duration of the read select line excitation signal is short, the bit line cannot be completely discharged to a low level within the duration of the read select line excitation signal.

[0095] Therefore, by detecting the level change of the bit line during the duration of the read select line excitation signal (rapid discharge to low level, holding high level, slow discharge but not to low level) through the sensing amplifier, the negative output of the sensing amplifier can output the NAND logic operation result of two logic operands, and configure the switch excitation signal connected to the connected control unit to low level and the latch excitation signal to high level, so that the first switch S1 of the control unit is turned off and the first latch L1 is sampled. The first latch L1 of the 64 control units samples the NAND logic operation result. The carry signals connected to the carry input terminals of the 64 logic operation units are all configured to low level, and the subsequent logic gate circuits do not work.

[0096] In the second stage of implementing the OR logic operation, the horizontal line excitation signal and read select line excitation signal of the two rows of memory units involved in the operation are configured to read level, selecting these two rows of memory units. The read select line excitation signal and horizontal line excitation signal connected to other rows of memory units are configured to low level, and the other rows of memory units are not selected. At this time, the level of the bit lines connected to each column of memory units is the remaining level at the end of the first stage. The 64-bit switch excitation signal is configured to high level, the first switch S1 of the 64 control units is turned on, the 64-bit latch excitation signal is configured to low level, the first latch L1 of the 64 control units is latched, and the carry signal connected to the carry input terminal of the 64 logic operation units is configured to the corresponding carry input, and the subsequent logic gate circuits operate. The 64-bit word line excitation signal, the 64-bit word select line excitation signal, and the 64-bit source line excitation signal are all configured to low level.

[0097] At this time, in the two selected memory cells, the word line excitation signals connected to the gate of FeFET F1 in the two memory cells in the same column are all at a low level, the horizontal line excitation signals connected to the drain of FeFET F1 are all at a read level, and the read select line excitation signals connected to the gate of the third MOS transistor M3 are all at a read level. At this time, the third MOS transistor M3 of both memory cells is turned on, and the bit line excitation signal connected to the drain of the third MOS transistor M3 is at the level of the bit line after the first step. The word select line excitation signals connected to the gate of the first MOS transistor M1 are all at a low level. At this time, the first MOS transistor M1 of both memory cells is turned off, and the source line excitation signal connected to the source of the first MOS transistor M1 is at a low level.

[0098] If both FeFET F1 values ​​of the two memory cells are in a low threshold voltage state, meaning both logic operands are logic data 1, then the discharge paths of both memory cells are open, and their corresponding bit lines remain low.

[0099] If both FeFET F1 values ​​of the two memory cells are in a high threshold voltage state, meaning both logic operands are logic data 0, then the discharge paths of both memory cells are closed, and their corresponding bit lines remain precharged high.

[0100] If the FeFET F1 of two memory cells is in a low threshold voltage state and a high threshold voltage state, meaning the two logic operands are logic data 1 and 0 respectively, and one memory cell has its discharge path open while the other has its discharge path closed, then the bit line of that memory cell can only slowly discharge from the level after the end of the first stage through the third MOS transistor M3 and the second MOS transistor M2 of one memory cell until the bit line is completely discharged to a low level.

[0101] Therefore, by detecting the level change of the bit line during the duration of the read selection line excitation signal (holding low level, holding high level, slowly discharging to low level) through the sensing amplifier, the positive output of the sensing amplifier outputs the OR logic operation result of the two logic operands. The switch excitation signal connected to the connected control unit is configured to high level, and the latch excitation signal is configured to low level, causing the first switch S1 of the control unit to open and the first latch L1 to latch. The NAND logic operation result and the OR logic operation result are then output to the first and second input terminals of the corresponding logic operation units, respectively. Each logic operation unit performs a full addition operation on the carry signal connected to its carry input terminal, the NAND logic operation result (i.e., the first logic data) connected to its first input terminal, and the OR logic operation result (i.e., the second logic data) connected to its second input terminal, obtaining the summation result and the carry result output.

[0102] Figure 7 This is a timing diagram illustrating the decoupled read / write operations implemented in the read / write decoupled in-memory computing system provided in this embodiment. Figure 7 As shown, three adjacent memory units located in the same column are designated as follows: the first row of memory units is denoted as A, the second row as B, and the third row as C. WSL-A, WSL-B, and WSL-C represent the word select line excitation signals connected to memory units A, B, and C, respectively; WL-A, WL-B, and WL-V represent the word line excitation signals connected to memory units A, B, and C, respectively; BL1 represents the bit line level of memory units A, B, and C; HL-A, HL-B, and HL-C represent the horizontal line excitation signals connected to memory units A, B, and C, respectively; SL1 represents the source line excitation signal connected to memory units A, B, and C; and RSL-A, RSL-B, and RSL-C represent the read select line excitation signals connected to memory units A, B, and C, respectively.

[0103] The decoupling of read and write operations is carried out in three stages.

[0104] Stage (1) is the logic data writing stage. The logic data is written in the same way as in Example 1. In this stage, the storage unit A writes logic data 1 and the storage unit B writes logic data 1. At this time, the bit line excitation signal of the drain of the third MOS transistor M3 connected to storage units A, B and C is pre-charge high level.

[0105] Phase (2) involves the simultaneous Boolean logic operations between memory units A and B, and the simultaneous writing of logical data to memory unit C. In this phase, the Boolean logic operations between memory units A and B are performed as shown in Example 4, with the bit lines of memory units A, B, and C rapidly discharging from a pre-charge high level to a low level. Memory unit C is written with logical data 0 using the same method as in Example 1. Figure 7 As we can see from this, in stage (2), the bit lines connected to memory units A, B and C are discharged to a low level.

[0106] It should be noted that the write operation to memory cell C is completed through an independent write path (source line - first MOS transistor - FeFET - word line). This operation is physically independent of the Boolean logic operations (involving bit line discharge) performed on memory cells A and B through the read path. Therefore, they can be executed in parallel within the same time period without interfering with each other.

[0107] Stage (3) is the logic data reading stage. In this stage, logic data 0 is read from memory unit C, using the same method as in Example 1. At this time, the bit lines containing memory units A, B, and C are kept at a pre-charge high level. Figure 7 As can be seen from the data, in stage (3), the bit lines connected to memory units A, B and C are kept at a pre-charge high level, which proves that in this embodiment, while performing Boolean logic operations on memory units A and B, logic data can be written to memory unit C, and the logic data stored in memory unit C can be read correctly in subsequent stages, thus realizing the logical correctness and functional reliability of the decoupled read and write operation.

Claims

1. A memory computing unit based on FeFET, characterized in that, The structure comprises a 4T configuration consisting of a first MOSFET, a second MOSFET, a third MOSFET, and a FeFET. The first MOSFET is connected to the source line to form a write path, and the second MOSFET and the third MOSFET are connected to the bit line to form a read path. The write path and the read path are independent of each other. The FeFET has a non-volatile threshold voltage state, which is used to store data and control the level changes of the bit line to achieve at least one of data readout, Boolean logic operation, tri-state content addressing, and full adder operation.

2. The FeFET-based memory computing unit according to claim 1, characterized in that, The drain of the FeFET is the horizontal line terminal of the memory cell, the gate is the word line terminal of the memory cell, and the source is connected to the drain of the first MOS transistor and the gate of the second MOS transistor, respectively. The gate of the first MOS transistor is the word select line terminal of the memory cell, and the source is the source line terminal of the memory cell. The source of the second MOS transistor is grounded, and the drain is connected to the source of the third MOS transistor. The gate of the third MOS transistor is the read select line terminal of the memory cell, and the drain is the bit line terminal of the memory cell.

3. A read / write decoupled in-memory computing system based on FeFET, comprising a row driving circuit, a column driving circuit, a memory computing array, and a sensing amplification circuit, wherein the row driving circuit is used to generate row excitation signals, the column driving circuit is used to generate column excitation signals, and the memory computing array is formed by arranging multiple memory computing units in a multi-row, multi-column array, characterized in that... The in-memory computing unit adopts the in-memory computing unit described in claim 1 or 2; each column of in-memory computing units shares a bit line; the read-write decoupled in-memory computing system is controlled to selectively enter data storage mode, data readout mode, Boolean logic operation mode, tri-state content addressing mode, and full adder operation mode by configuring the levels of the row excitation signal and the column excitation signal; the data storage mode corresponding function is realized by the non-volatile threshold voltage state of the FeFET in the in-memory computing array, and the data readout mode, Boolean logic operation mode, tri-state content addressing mode, and full adder operation mode corresponding function is realized by controlling the level change of the corresponding bit line; the sensing amplification circuit is used to detect the level change and generate a corresponding signal output; the read-write decoupled in-memory computing system also includes a logic gate circuit, which is used to cooperate with the sensing amplification circuit to perform full adder operation in full adder operation mode.

4. The FeFET-based read / write decoupled in-memory computing system according to claim 3, characterized in that, Within the working cycle of performing Boolean logic operations or full adder operations, the memory array supports simultaneously writing the result of the previous stage operation or external data to the target memory unit via the source line while using bit lines to sense the current operation result.

5. The FeFET-based read / write decoupled in-memory computing system according to claim 4, characterized in that, The in-memory array is formed by arranging M×N in-memory units in an M-row N-column array, where M and N are even numbers greater than or equal to 2; the sensing amplifier circuit includes N sensing amplifiers, each of which corresponds one-to-one with one of the N columns of in-memory units, and each sensing amplifier shares a bit line with its corresponding column of in-memory units; the read-write decoupled in-memory computing system also includes N control units; the logic gate circuit includes N logic operation units; the N control units are connected one-to-one with the N sensing amplifiers, and the N logic operation units are connected one-to-one with the N control units.

6. The FeFET-based read / write decoupled in-memory computing system according to claim 5, characterized in that, The memory array further includes M horizontal lines, M word lines, M word select lines, M read select lines, N source lines, and N bit lines; the horizontal line end of the m-th row memory unit is connected to the m-th horizontal line; the word line end of the m-th row memory unit is connected to the m-th word line; the word select line end of the m-th row memory unit is connected to the m-th word select line; the read select line end of the m-th row memory unit is connected to the m-th read select line; the source line end of the n-th column memory unit is connected to the n-th source line; the bit line end of the n-th column memory unit is connected to the n-th bit line; the n-th sense amplifier is connected to the n-th bit line; m = 1, 2, ..., M, n = 1, 2, ..., N.

7. The FeFET-based read / write decoupled in-memory computing system according to claim 6, characterized in that, The row excitation signals include M-bit horizontal line excitation signals, M-bit word line excitation signals, M-bit word select line excitation signals, and M-bit read select line excitation signals; these signals are output to M horizontal lines, M word lines, M word select lines, and M read select lines, respectively. The column excitation signals include N-bit source line excitation signals, N-bit bit line excitation signals, N-bit switch excitation signals, and N-bit latch excitation signals; these signals are output to N source lines and N bit lines, respectively; the N-bit switch excitation signals are output to N control units to control the N control units to be on or off; and the N-bit latch excitation signals are output to N control units to control the N control units to sample or latch data.

8. The FeFET-based read / write decoupled in-memory computing system according to claim 7, characterized in that, Each sense amplifier has an input terminal, a reference terminal, a positive output terminal, and a negative output terminal; each logic operation unit has a first input terminal, a second input terminal, a carry input terminal, a summation output terminal, and a carry output terminal; each control unit has a first input terminal, a second input terminal, a switch control terminal for receiving switch excitation signals, a latch control terminal for receiving latch excitation signals, a first output terminal, and a second output terminal; the input terminal of the nth sense amplifier is connected to the nth bit line; the positive output terminal of the nth sense amplifier is connected to the first input terminal of the nth control unit, the negative output terminal of the nth sense amplifier is connected to the second input terminal of the nth control unit, the first output terminal of the nth control unit is connected to the first input terminal of the nth logic operation unit, and the second output terminal of the nth control unit is connected to the second input terminal of the nth logic operation unit.

9. The FeFET-based read / write decoupled in-memory computing system according to claim 8, characterized in that, Each logic operation unit includes a first XOR gate, a first NOT gate, a first AND gate, a second AND gate, and a first OR gate. The first NOT gate has an input terminal and an output terminal. The first XOR gate, the first AND gate, the second AND gate, and the first OR gate each have a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate is the second input terminal of the logic operation unit. The second input terminal of the first AND gate is connected to the input terminal of the first NOT gate, and its connection terminal is the first input terminal of the logic operation unit. The output terminal of the first AND gate is connected to the first input terminal of the first XOR gate and the first input terminal of the second AND gate, respectively. The output terminal of the first NOT gate is connected to the first input terminal of the first OR gate. The second input terminal of the second AND gate is connected to the second input terminal of the first XOR gate, and its connection terminal is the carry input terminal of the logic operation unit. The output terminal of the second AND gate is connected to the second input terminal of the first OR gate. The output terminal of the first XOR gate is the summation output terminal of the logic operation unit, and the output terminal of the first OR gate is the carry output terminal of the logic operation unit.

10. The FeFET-based read / write decoupled in-memory computing system according to claim 8, characterized in that, The control unit includes a first latch and a first switch. The first latch has an input terminal, an output terminal, and a latch control terminal. The first switch has a first terminal, a second terminal, and a switch control terminal. The input terminal of the first latch and the first terminal of the first switch are respectively the first input terminal and the second input terminal of the control unit. The output terminal of the first latch and the second terminal of the first switch are respectively the first output terminal and the second output terminal of the control unit. The latch control terminal of the first latch is the latch control terminal of the control unit, and the switch control terminal of the first switch is the switch control terminal of the control unit.

Images