A multi-stage wave control system of an active phased array antenna
The active phased array antenna beam control system with a three-level collaborative architecture solves the problems of concentrated computational load, synchronization jitter and fault propagation in large-scale array antennas, realizes high-speed beam switching and fault isolation, and improves beam pointing accuracy and system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-12
Smart Images
Figure CN122204147A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to beam control technology for active phased array antennas, specifically to a three-level collaborative multi-level beam control system suitable for satellite communication phased array antennas, applicable to high-speed beam switching, precise amplitude and phase control, and fault isolation scenarios for large-scale array antennas. Background Technology
[0002] Active phased array antennas, with their inertia-free beam agility, multi-beam parallel operation, high reliability, and strong anti-interference capabilities, have been widely used in low-Earth orbit satellite communications, airborne and shipborne radars, and next-generation mobile communication systems. Among them, high-frequency phased array antennas are the core payload of satellite communications. Their beam control system undertakes core functions such as beam control code decoding, amplitude and phase configuration, timing synchronization, and array surface monitoring, directly determining the antenna's scanning speed, pointing accuracy, and system stability.
[0003] Existing active phased array antenna beam control systems mostly adopt centralized or simple two-level architectures, which have significant drawbacks in large-scale array, broadband multi-band, miniaturized low-power application scenarios: First, centralized architectures suffer from concentrated computational load and bus congestion, failing to meet the requirements of high-speed beam switching; two-level architectures lack hierarchical optimization of timing, synchronization, and fault isolation, introducing phase errors and synchronization jitter during long-distance transmission, and resulting in significant beam distortion during wide-bandwidth angle scanning; Second, fault coupling is strong, with single-node faults easily propagating to the entire array, resulting in insufficient redundancy and maintainability; Third, amplitude and phase errors caused by array surface drift and device aging cannot be compensated in real time at different levels, leading to deterioration of antenna radiation performance; Fourth, inconsistent interface protocols and fixed extension levels result in poor compatibility and high upgrade and modification costs when facing multi-array and common-aperture integrated scenarios.
[0004] As phased array antennas evolve towards large-scale integration, broadband, miniaturization, and low power consumption, traditional wave control architectures are no longer adequate for engineering requirements. Therefore, there is an urgent need for a multi-level wave control system with hierarchical driving, high-speed synchronization, fault isolation, and real-time amplitude and phase compensation. This system, through a three-level architecture, achieves balanced computational load and modular expansion, addressing the bottlenecks of existing architectures in terms of real-time performance, synchronization accuracy, reliability, and scalability. Summary of the Invention
[0005] This invention addresses the technical shortcomings of existing beam control systems by providing a multi-level beam control system for active phased array antennas. It employs a three-level collaborative architecture—a computational management layer, a data distribution layer, and a protocol conversion layer—to achieve high-speed beam control, precise amplitude and phase compensation, and fault domain isolation for large-scale phased array antennas. A multi-level beam control system for an active phased array antenna, characterized in that it comprises: a computation management layer, a data distribution layer, and a protocol conversion layer connected in sequence; The operation and management layer is used to send control parameters of the active phased array antenna to the data distribution layer and receive status data transmitted back from the array surface. The data distribution layer is used to parse the control parameters of the active phased array antenna issued by the operation management layer, generate channel phase shift codes, attenuation codes and working timing, and distribute them serially to the protocol conversion layer. The protocol conversion layer converts the serial channel phase shift code, attenuation code, and operating timing into parallel drive signals.
[0006] The control parameters of the active phased array antenna include: operating status, beam pointing, operating frequency, bandwidth, repetition rate, and timing requirements.
[0007] The computational management layer is located on the system's main control board.
[0008] The system's main control board is equipped with a dual-channel switching module for external clock input and built-in clock source.
[0009] The data distribution layer is arranged on the FPGA and FLASH memory, and the FPGA and FLASH memory are connected to the system main control board.
[0010] The system analyzes the control parameters of the active phased array antenna issued by the operational management layer to generate channel phase shift codes, attenuation codes, and operating timing sequences, specifically including: Based on the control parameters of the active phased array antenna, amplitude and phase calculations are performed on the transmitting and receiving channels of the active phased array. The initial amplitude and phase calibration data of the working frequency point are called up to compensate for the amplitude and phase errors of the channels in real time, and the channel phase shift code and attenuation code are obtained. At the same time, the frequency conversion control signal and the frequency source control signal are output to form the working timing.
[0011] The protocol conversion layer is arranged on multiple T / R (Transmitter and Receiver) components, and each T / R (Transmitter and Receiver) component is connected to the FPGA field-programmable gate array and FLASH memory.
[0012] Further optimization yielded the following specific technical solution: The multi-level wave control system consists of a computation management layer, a data distribution layer, and a protocol conversion layer. The three levels of units are interconnected in sequence to realize the hierarchical distribution of control commands and the transmission of data.
[0013] The operation and management layer, implemented by the system main control board, serves as the top-level control core. Based on the beam scheduling instructions from the satellite communication processor, it issues control parameters such as working status, beam pointing, working frequency, bandwidth, repetition rate, and timing synchronization. Simultaneously, it receives array working status, fault information, and amplitude and phase calibration data transmitted back from the data distribution layer. It supports dual-channel switching between external and internal clocks and has functions for transmit and receive control, multiple working mode configuration, and array self-test instruction issuance.
[0014] Data distribution layer: Implemented by the array beam control module, serving as the intermediate data distribution core, it receives control parameters from the computational management layer, completes beam pointing calculation, and generates phase shift codes, attenuation codes, and operating timing signals for each channel; it calls the initial amplitude and phase calibration data for the corresponding frequency point according to the operating frequency to compensate for amplitude and phase errors caused by environmental drift and device aging; it distributes control codes to each channel of the transmitter and receiver arrays via a high-speed serial bus, and simultaneously outputs synchronization control signals for the frequency conversion module and frequency source to achieve full array timing synchronization.
[0015] Protocol conversion layer: Integrated inside the T / R component, it is implemented using a dedicated serial-to-parallel conversion chip, which converts the synchronous serial wave control signal transmitted by the data distribution layer into parallel data, driving devices such as phase shifters, attenuators, and RF switches to complete amplitude and phase configuration; it adopts a multi-level buffer register structure to ensure the stability of data transmission and configuration accuracy.
[0016] The technical advantages of this invention are as follows: High-speed beam switching: The three-level architecture offloads the computing load, enabling microsecond-level beam agility and meeting the requirements of high-speed beam scheduling; Precise amplitude and phase control: Enables graded real-time amplitude and phase compensation, improving antenna amplitude and phase consistency and beam pointing accuracy; Fault isolation and controllability: Supports independent on / off control of a single channel, has multiple working modes and self-test function, and fault domain isolation can prevent the entire array from failing; Modular expansion: Unified interface protocol, adaptable to multi-array and common-aperture integration, compatible with broadband multi-waveform applications; High synchronization accuracy: It adopts a high-speed synchronization bus and an external clock priority mechanism to eliminate synchronization jitter and phase error in long-distance transmission. Attached Figure Description
[0017] Figure 1 is a diagram of the multi-stage beam control system architecture of the active phased array antenna of the present invention. Figure 2 is a schematic diagram of the internal serial-to-parallel conversion wave control principle of the T / R component; Figure 3 is a block diagram of the protocol conversion layer register unit; Figure 4 shows the timing diagram of the wave controller serial interface. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to embodiments. This embodiment is based on a Ka-band satellite communication phased array antenna, and the specific implementation of the multi-level beam control system is fully described: The present invention will be further described in detail below with reference to an embodiment. This embodiment is based on a Ka-band satellite communication phased array antenna (320 transmit channels and 256 receive channels), and fully describes the specific implementation of the multi-level beam control system: This embodiment of the multi-level beam control system adopts a three-level architecture: a computational management layer, a data distribution layer, and a protocol conversion layer. It works in conjunction with the transmitting array, receiving array, frequency conversion module, frequency source, and power supply module of the Ka-band phased array antenna. The overall dimensions are 249mm × 200mm × 41mm. Power is supplied via a 28V primary power conversion, and the beam control system's power consumption is ≤2W. Figure 1 The following details the three-layer implementation method: 1. Specific implementation of the computational management layer The computational management layer uses the system's main control board to achieve top-level control and data interaction. Command reception and transmission: Implement 2.5V LVDS asynchronous serial communication with the host computer to receive operating status, beam pointing, operating frequency, bandwidth, repetition rate, timing requirements, and transmit them to the data distribution layer; Clock synchronization management: Configure the built-in clock source and the external 100MHz clock input interface. The clock switching logic prioritizes the external clock to ensure the timing synchronization accuracy of the entire array. Operating mode control: Supports switching between high power mode, low power mode, and silent mode (default power-on mode), and controls the on / off state of the transceiver array channel by sending channel enable commands; Status monitoring and self-test: Receives real-time data on array temperature, channel faults, and amplitude and phase errors from the data distribution layer, and transmits the self-test results back to the host computer.
[0019] 2. Specific Implementation of the Data Distribution Layer The data distribution layer employs a dedicated array wave control module, equipped with an FPGA main control chip and a FLASH storage chip, to achieve intermediate-level data processing and high-speed distribution. Phase and amplitude code calculation: For the Ka band uplink 29.4GHz~31GHz and downlink 19.6GHz~21.2GHz operating frequency bands, the phase shift code and attenuation code of 320 transmit channels and 256 receive channels are calculated based on the beam pointing parameters. The phase shift code is 6 bits (step 5.625°) and the attenuation code is 5 bits (step 0.5dB). Amplitude and phase error compensation: Call the pre-stored initial state amplitude and phase calibration data of the frequency point to compensate for the amplitude and phase errors caused by array temperature drift, device aging and mechanical deformation in real time, so as to ensure the consistency of the amplitude and phase of the entire array; High-speed data distribution: A 2.5V LVDS asynchronous serial bus is used to distribute amplitude and phase control codes and timing signals to the T / R components of the transmitter array and receiver array. The bus transmission rate matches the microsecond-level configuration requirements. Collaborative control: Output frequency converter module up / down frequency conversion timing and frequency source phase-locked control signals to achieve timing synchronization between the RF link and the beam control system.
[0020] 3. Specific Implementation of the Protocol Conversion Layer The protocol conversion layer is integrated inside the SIP-packaged T / R component, using a silicon-based ASIC serial-to-parallel conversion chip to implement underlying protocol conversion and device driving. Serial-to-parallel conversion function: Figure 2 The diagram shows the internal serial-to-parallel conversion wave control principle of TR, which consists of a serial-to-parallel conversion shift register and NAND circuits, realizing the functions of serial-to-parallel conversion, registering, power modulation and logic protection of data.
[0021] Register configuration: such as Figure 3 As shown, a two-level cache register structure is adopted, with reg_data1 as the data input register, reg_data2 as the latch register, and reg_data3 as the output register. The SEL signal is the first-level cache latch signal, and the DARY signal is the second-level cache latch signal, ensuring that the data configuration is error-free. Work sequence: such as Figure 3 and Figure 4 As shown, when SEL is low, data will be written from the SDI port to reg_data1[0] sequentially on the rising edge of CLK, and the original data in reg_data1 will be moved from reg_data1[0] to reg_data1
[31] . The OUT of the previous channel in the chip is connected to the IN of the next channel. When the data in the first channel is written to reg_data1
[31] , the data will be written to reg_data1[0] of the second channel in the next clock cycle, until the last bit of data is output from the SDO port on the falling edge of CLK. There are 8 sets of registers in reg_data2, and each set of registers is also 32 bits. When SEL generates a rising edge, all 8×32 sets of data in reg_data1 will be latched into the specified reg_data2. There are 8 sets of registers in reg_data3, and each set of registers is also 32 bits. When DARY generates a rising edge, all 8×32 data sets in reg_data2 will be latched into the specified reg_data3.
[0022] 4. Implementation of wave control response time This embodiment achieves beam setup time ≤25μs, beam pointing error better than 1 / 10 of beamwidth, receive channel isolation ≥50dB, and transmit clutter suppression ≥60dBc through a three-level architecture with hierarchical parallel processing, meeting the engineering application requirements of Ka-band communication phased array antennas.
[0023] The description and application of this invention are exemplary and not intended to limit the scope of the invention. Any modifications, substitutions and improvements made within the spirit and principles of this invention should be included within the protection scope of this invention.
Claims
1. A multi-stage beam control system for an active phased array antenna, characterized in that, include: The computation management layer, data distribution layer, and protocol conversion layer are connected sequentially. The operation and management layer is used to send control parameters of the active phased array antenna to the data distribution layer and receive status data transmitted back from the array surface. The data distribution layer is used to parse the control parameters of the active phased array antenna issued by the operation management layer, generate channel phase shift codes, attenuation codes and working timing, and distribute them serially to the protocol conversion layer. The protocol conversion layer converts the serial channel phase shift code, attenuation code, and operating timing into parallel drive signals.
2. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The control parameters of the active phased array antenna include: operating status, beam pointing, operating frequency, bandwidth, repetition rate, and timing requirements.
3. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The computational management layer is located on the system's main control board.
4. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The system's main control board is equipped with a dual-channel switching module for external clock input and built-in clock source.
5. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The data distribution layer is arranged on the FPGA and FLASH memory, and the FPGA and FLASH memory are connected to the system main control board.
6. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The system analyzes the control parameters of the active phased array antenna issued by the operational management layer to generate channel phase shift codes, attenuation codes, and operating timing sequences, specifically including: Based on the control parameters of the active phased array antenna, amplitude and phase calculations are performed on the transmitting and receiving channels of the active phased array. The initial amplitude and phase calibration data of the working frequency point are called up to compensate for the amplitude and phase errors of the channels in real time, and the channel phase shift code and attenuation code are obtained. At the same time, the frequency conversion control signal and the frequency source control signal are output to form the working timing.
7. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The protocol conversion layer is arranged on multiple T / R components, and each T / R component is connected to the FPGA field-programmable gate array and FLASH memory.
8. The multi-stage beam control system for an active phased array antenna according to claim 1, characterized in that, The T / R component adopts a two-level cache register structure.