A radio frequency integrated chip digital part data sending pre-processing module

Abstract

The application relates to a radio frequency integrated chip digital part data sending pre-processing module, which comprises a first DAC module for generating a standard data waveform signal; at least one compensation DAC module for generating a corresponding compensation waveform signal at a jump edge of the standard data waveform signal; and a convolution module for summing the compensation waveform signal and the standard data waveform signal to obtain a convolution waveform signal and outputting the convolution waveform signal. In the transmission process of a high-speed signal, the attenuation of a high-frequency component is much larger than that of a low-frequency signal, the performance is a low-pass filter, the waveform of a receiving end is seriously tailing, which can cause serious inter-symbol interference and increase the bit error rate. The scheme solves the tailing phenomenon to reduce the bit error rate.

Description

Technical Field

[0001] This invention relates to the field of communications, and more specifically to a data transmission preprocessing module for the digital portion of a radio frequency integrated chip. Background Technology

[0002] In modern high-speed digital communication systems, signal integrity has become the ultimate bottleneck restricting transmission rate and distance. Whether it's the interconnection between chips on a board, data exchange between device backplanes, or photoelectric transmission via cables, system designers face a common physical challenge: signal attenuation and distortion caused by the channel. Among these, inter-symbol interference caused by the low-pass filtering effect of the channel is the core factor leading to increased system bit error rate, directly determining the performance and reliability of the communication link. Ideally, a digital square wave signal contains a rich array of frequency components, ranging from the fundamental frequency to very high harmonics. However, when this signal is transmitted through physical channels (such as PCB microstrip lines, coaxial cables, or optical fibers), its different frequency components experience varying degrees of attenuation. A generally accepted physical law is that the attenuation of high-frequency components is much greater than that of low-frequency components. This frequency-selective attenuation is mainly caused by the following effects: Conductor loss: According to the skin effect, as the frequency increases, the current tends to flow on the surface of the conductor, which leads to a decrease in the effective conductive cross-sectional area of ​​the conductor and an increase in resistance, thus making the ohmic loss of high-frequency components more significant. Dielectric loss: The dielectric material constituting the insulating layer of the channel is not an ideal dielectric. Its molecules undergo polarization and relaxation under the influence of an alternating electric field, converting some electromagnetic energy into heat energy. This loss is positively correlated with frequency and is another major factor leading to high-frequency attenuation. Radiation loss: Discontinuities in the signal path (such as vias and connectors) radiate electromagnetic energy like small antennas, and this radiation effect is more pronounced at higher frequency bands. The aforementioned loss mechanisms work together to give the entire transmission channel the characteristics of a "low-pass filter." This means that high-frequency components carrying rapidly changing information are severely suppressed, while slowly changing low-frequency components are relatively preserved. This low-pass effect has a disastrous impact on digital waveforms in the time domain. An ideal rectangular pulse (representing a bit 0 or 1), after passing through this channel, will have its steep rising and falling edges become smooth and delayed, and the pulse itself will widen to both sides, producing a long trail. This trail will intrude into and cover the decision time window of subsequent bits. Intersymbol interference (ISI) is the direct consequence of this trailing phenomenon. When the trail of a bit extends to the decision time of the next one or more bits, it will act as interference noise, superimposed on the signal amplitude of subsequent bits. The problem is that, assuming the previous bit was 1 (high level), its strong positive tail might persist until the current bit's sampling time. If the current bit should be 0 (low level), this positive tail will raise the voltage value at the sampling point, potentially exceeding the decision threshold and being misinterpreted as 1. This makes it difficult for the receiving end's sampling circuitry to determine the correct voltage level at the correct time. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a data transmission preprocessing module for the digital part of an RF integrated chip, which solves the data trailing phenomenon by fine-tuning the signal compensation. The objective of this invention is achieved through the following technical solution: A data transmission preprocessing module for the digital section of an RF integrated chip includes: The first DAC module is used to generate standard data waveform signals; And at least one compensation DAC module, the compensation DAC module being used to generate a corresponding compensation waveform signal at the transition edge of the standard data waveform signal; The convolution module is used to sum the compensated waveform signal and the standard data waveform signal to obtain the convolved waveform signal and output it. Traditional solutions often perform equalization at the receiver, a passive approach. This innovative solution utilizes multiple DACs at the transmitter for active, programmable pre-compensation, directly offsetting distortions such as positive tailing caused by transmission lines. This optimizes the signal before it enters the channel, significantly reducing inter-symbol interference and fundamentally improving signal quality. Through convolution and synthesis in the analog / mixed signal domain, this solution effectively avoids the high computational latency and high power consumption issues associated with purely digital FIR filter schemes. The parallel processing mechanism of the DAC array and synthesis module maintains extremely high processing efficiency and extremely low path latency while achieving complex waveform shaping, making it particularly suitable for latency-sensitive real-time communication systems. Furthermore, the transition edge refers to the rising edge and / or falling edge of the standard data waveform signal. Furthermore, the compensation DAC module is used to perform compensation before and / or before and after the rising edge of the standard data waveform signal. and or; The compensation DAC module is used to perform compensation before the falling edge of the standard data waveform signal. Furthermore, the compensation weights of the compensation waveform signals output by the compensation DAC module can all be configured through the chip's built-in registers. By modifying the internal registers, the DAC's compensation weights can be adjusted, giving the system unprecedented online configurability. When the operating frequency changes, or channel characteristics change due to temperature or device aging, the system can quickly adapt by updating the register configuration without hardware modifications, always maintaining optimal performance. This flexibility greatly expands the product's application scenarios. Furthermore, the compensation DAC module is a single module, including a second DAC module, which is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal. Furthermore, the compensation DAC module consists of two modules, including a second DAC module and a fourth DAC module; The second DAC module is used to generate a first compensation waveform signal during the t1 time period before the rising edge of the standard data waveform signal, and the fourth DAC module is used to generate a third compensation waveform signal during the t3 time period before the falling edge of the standard data waveform signal. Furthermore, the compensation DAC module comprises three modules: a second DAC module, a third DAC module, and a fourth DAC module. The second DAC module is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal, the third DAC module is used to generate a second compensation waveform signal during a time period t2 after the rising edge of the standard data waveform signal, and the fourth DAC module is used to generate a third compensation waveform signal during a time period t3 before the falling edge of the standard data waveform signal. Using a dedicated DAC channel for edge acceleration and tail cancellation provides higher precision waveform shaping. Compared to fixed FIR filters, this multi-channel parallel approach with finely adjustable weights can more precisely match the non-ideal characteristics of the channel, achieving better compensation results and thus supporting higher data transmission rates or longer transmission distances. Furthermore, t1, t2, and t3 may be equal or unequal. Furthermore, it also includes a driver, through which the convolutional waveform signal is processed and output. Furthermore, the driver generates a non-return-to-zero encoded differential signal output based on the convolutional waveform signal. The beneficial effects of this invention are: during the transmission of high-speed signals, the attenuation of high-frequency components is much greater than that of low-frequency signals, exhibiting the characteristics of a low-pass filter, which causes severe tailing of the waveform at the receiving end. This can lead to serious inter-symbol interference and increase the bit error rate. This solution reduces the bit error rate by addressing the tailing phenomenon. Attached Figure Description

[0004] Figure 1 This is a circuit block diagram of the present invention; Figure 2 This is a schematic diagram of waveform compensation according to the present invention. Detailed Implementation

[0005] The technical solution of the present invention will be further described in detail below with reference to specific embodiments, but the scope of protection of the present invention is not limited to the following description. refer to Figure 1 As shown, a data transmission preprocessing module for the digital section of an RF integrated chip includes a first DAC module and at least one compensation DAC module. The first DAC module generates a standard data waveform signal; the compensation DAC module generates a corresponding compensation waveform signal at the transition edge of the standard data waveform signal; and a convolution module sums the compensation waveform signal with the standard data waveform signal to obtain a convolved waveform signal, which is then output. Unless otherwise specified, the transition edge in this application refers to the rising edge and / or falling edge of the standard data waveform signal. In other words, this application can compensate for either the rising edge or the falling edge of the standard data waveform signal, or it can compensate for both the rising and falling edges. That is, the compensation DAC module can compensate before and / or before the rising edge of the standard data waveform signal; and / or the compensation DAC module can compensate before the falling edge of the standard data waveform signal. The specific compensation methods will be described in detail later. Optionally, in some preferred embodiments, the data transmission preprocessing module for the digital portion of an RF integrated chip further includes a driver, through which the convolved waveform signal is processed and output. The driver generates a non-return-to-zero encoded differential signal output based on the convolved waveform signal. Traditional solutions often perform equalization at the receiver, a passive approach. This innovative solution utilizes multiple DACs at the transmitter for active, programmable pre-compensation, directly offsetting distortions such as positive tailing caused by transmission lines. This optimizes the signal before it enters the channel, significantly reducing inter-symbol interference and fundamentally improving signal quality. Through convolution and synthesis in the analog / mixed signal domain, this solution effectively avoids the high computational latency and high power consumption issues associated with purely digital FIR filter schemes. The parallel processing mechanism of the DAC array and synthesis module maintains extremely high processing efficiency and extremely low path latency while achieving complex waveform shaping, making it particularly suitable for latency-sensitive real-time communication systems. Furthermore, the compensation weights of the compensation waveform signals output by the compensation DAC module can all be configured through the chip's built-in registers. By modifying the internal registers, the DAC's compensation weights can be adjusted, giving the system unprecedented online configurability. When the operating frequency changes, or channel characteristics change due to temperature or device aging, the system can quickly adapt by updating the register configuration without hardware modifications, always maintaining optimal performance. This flexibility greatly expands the product's application scenarios. Optionally, in one embodiment, a data transmission preprocessing module for the digital part of an RF integrated chip includes a first DAC module and a compensation DAC module, namely a second DAC module. The second DAC module is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal. In addition, the second DAC module can also generate the first compensation waveform signal during a time period t1 after the rising edge or before the falling edge of the standard data waveform signal. Optionally, in one embodiment, a data transmission preprocessing module for the digital part of an RF integrated chip includes a first DAC module and two compensation DAC modules, namely a second DAC module and a fourth DAC module; wherein, the second DAC module is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal, and the fourth DAC module is used to generate a third compensation waveform signal during a time period t3 before the falling edge of the standard data waveform signal. refer to Figure 1 As shown in the illustration, a preferred embodiment provides a data transmission preprocessing module for the digital section of an RF integrated chip, comprising a first DAC module (DAC1) and three compensation DAC modules (DAC2-DAC4), namely a second DAC module, a third DAC module, and a fourth DAC module. The second DAC module generates a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal; the third DAC module generates a second compensation waveform signal during a time period t2 after the rising edge of the standard data waveform signal; and the fourth DAC module generates a third compensation waveform signal during a time period t3 before the falling edge of the standard data waveform signal. Employing independent DAC channels specifically for edge acceleration and tail cancellation provides higher precision waveform shaping. Compared to fixed FIR filters, this multi-path parallel approach with finely adjustable weights can more precisely match the non-ideal characteristics of the channel, achieving superior compensation effects and thus supporting higher data transmission rates or longer transmission distances. refer to Figure 2 As shown in the figure, the original signal waveform and the actual received signal waveform are as follows. The first DAC module (DAC1) is used to generate a standard data waveform signal corresponding to the original waveform, that is, the DAC1 waveform. Figure 2 It can be seen that the DAC1 waveform is consistent with the original signal waveform, which is the standard waveform signal without trailing that we need. For ease of description, let's assume that the rising edge of the DAC1 waveform corresponds to time T0 and the falling edge corresponds to time T1. Then, the time periods corresponding to the supplemented waveforms of the three compensation DAC modules (DAC2-DAC4) are as follows: DAC2 waveform supplemented by time period T01-T0 (t1 time period), DAC2 waveform supplemented by time period T0-T01 (t2 time period), and DAC2 waveform supplemented by time period T11-T1 (t3 time period). That is, a waveform segment is compensated before and after the rising edge of the DAC1 waveform, and a waveform segment is compensated before the falling edge of the DAC1 waveform. Among them, t1, t2, and t3 may be equal or unequal, and the maximum should not exceed 1 / 4 clock cycle of the DAC1 waveform. In this embodiment, it is preferably designed to be 1 / 8 clock cycle. The compensation amplitude should be modulated according to the actual received signal waveform fed back in time, that is, the compensation weight is configured through registers. refer to Figure 2 As shown, after convolution of the DAC1, DAC2, DAC3, and DAC4 waveforms (i.e., after summation), the convolved waveform is shown in the figure. It can be seen that at the transmitting end, the waveform signal is positively compensated for by the rising edge peak, which means the level is raised, while the low level is further reduced, thereby canceling the trailing phenomenon of the received signal. refer to Figure 1The illustrated application includes a chip core and four DAC modules (DAC1-DAC4) corresponding to the first, second, third, and fourth DAC modules, respectively, as well as a convolution module and a driver. The chip core is connected to the first, second, third, and fourth DAC modules to transmit the data to be sent. The first DAC module generates a standard data waveform (DAC1 waveform), while the second, third, and fourth DAC modules generate corresponding compensation waveform signals (DAC2 waveform - DAC4 waveform). The standard data waveform and the compensation waveform signals are transmitted together to the convolution module for summation. This scheme sends parallel data to the first, second, third, and fourth DAC modules through the core. The signals generated by the first, second, third, and fourth DAC modules are convolved and then sent to the driver, which generates NRZ-encoded differential signals. DAC1 generates the standard data waveform signal. DAC2-4 can adjust the preprocessing compensation weights for signal rise and fall based on the measured signal waveform and operating frequency by modifying the internal register configuration of the RF integrated chip. This counteracts the positive tail of the transmission line, resulting in an optimal waveform at the receiving end. The register configuration information specifies the hold time and amplitude of the compensation waveform before and after each rise and fall. Each clock cycle variation must conform to the operating frequency, which is determined during the design phase. The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A data transmission preprocessing module for the digital section of a radio frequency integrated chip, characterized in that, include: The first DAC module is used to generate standard data waveform signals; And at least one compensation DAC module, the compensation DAC module being used to generate a corresponding compensation waveform signal at the transition edge of the standard data waveform signal; The convolution module is used to sum the compensated waveform signal and the standard data waveform signal to obtain the convolved waveform signal and output it.

2. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The transition edge refers to the rising edge and / or falling edge of the standard data waveform signal.

3. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 2, characterized in that, The compensation DAC module is used to perform compensation before and / or before and after the rising edge of the standard data waveform signal. and or; The compensation DAC module is used to perform compensation before the falling edge of the standard data waveform signal.

4. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The compensation weights of the compensation waveform signals output by the compensation DAC module can be configured through the chip's built-in registers.

5. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The compensation DAC module is one, including a second DAC module, which is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal.

6. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The compensation DAC module consists of two modules: a second DAC module and a fourth DAC module. The second DAC module is used to generate a first compensation waveform signal during the t1 time period before the rising edge of the standard data waveform signal, and the fourth DAC module is used to generate a third compensation waveform signal during the t3 time period before the falling edge of the standard data waveform signal.

7. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The compensation DAC module consists of three modules: a second DAC module, a third DAC module, and a fourth DAC module. The second DAC module is used to generate a first compensation waveform signal during a time period t1 before the rising edge of the standard data waveform signal, the third DAC module is used to generate a second compensation waveform signal during a time period t2 after the rising edge of the standard data waveform signal, and the fourth DAC module is used to generate a third compensation waveform signal during a time period t3 before the falling edge of the standard data waveform signal.

8. The data transmission preprocessing module for the digital part of an RF integrated chip according to claim 1, characterized in that, The values ​​t1, t2, and t3 may be equal or unequal.

9. A data transmission preprocessing module for the digital section of a radio frequency integrated chip according to any one of claims 1-8, characterized in that, It also includes a driver, through which the convolutional waveform signal is processed and output.

10. A data transmission preprocessing module for the digital part of an RF integrated chip according to claim 9, characterized in that, The driver generates a non-return-to-zero encoded differential signal output based on the convolutional waveform signal.

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