Single reference level decoding transceiver system based on ovm encoding and time comparison

Abstract

A single-reference-level decoding and transceiver system based on OVM coding and time comparison includes: a low-speed serializer, a four-channel 2:1 serializer, four parallel edge modulation modules and their corresponding enable drivers at the transmitting end, and a single-ended input to differential output circuit (S2D), a continuous-time linear equalizer (CTLE), an odd-even dual-branch decision module, and a decoding and deserializing unit connected in sequence at the receiving end. This invention specifically solves the trade-offs faced by existing single-ended channel transmitters in terms of bandwidth, energy efficiency, and equalization capability, as well as the limitations of the time comparator architecture in the receiver that requires multiple reference levels, resulting in additional power consumption and area overhead. It only requires a single decision level to achieve high anti-inter-symbol interference capability while having low power consumption and high transmission speed.

Description

Technical Field

[0001] This invention relates to a technology in the field of communication systems, specifically a single-reference level decoding and transceiver system based on an overlapped multiplexing architecture (OVM) and time comparison. Background Technology

[0002] Transceivers that transmit data via single-ended channels are core modules of memory interfaces in applications such as mobile devices and big data applications. Current transceivers involve trade-offs at both ends and cannot physically support overlapping multiplexing, failing to meet current key requirements for energy efficiency, interference resistance, and bandwidth. Summary of the Invention

[0003] This invention addresses the trade-offs faced by existing single-ended channel transmitters in terms of bandwidth, energy efficiency, and equalization capabilities, as well as the limitations of receiver time comparator architecture requiring the generation of multiple reference levels, resulting in additional power consumption and area overhead. It proposes a single-reference-level decoding transceiver system based on OVM coding and time comparison, which requires only one decision level to achieve high anti-inter-symbol interference capability while maintaining low power consumption and high transmission speed.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a single-reference level decoding and transceiver system based on OVM encoding and time comparison, comprising: a low-speed serializer, a four-channel 2:1 serializer, four parallel edge modulation modules and their corresponding enable drivers at the transmitting end; and a single-ended input to differential output circuit (S2D), a continuous-time linear equalizer (CTLE), an odd-even dual-branch decision module, and a decoding / deserializing unit connected in sequence at the receiving end. The low-speed serializer serializes the digital signal to be transmitted into a single-bit high-speed analog signal, obtaining four channels of data; the four-channel 2:1 serializer serializes the four channels of data to obtain four channels of half-rate encoded data, which are then edge-modulated and output to their respective enable drivers. Each enable driver, according to... Each clock signal with its corresponding phase is enabled or disabled, ensuring that there are two enabled drivers outputting the required encoded data in any time slot. The single-ended input to differential output circuit extracts the relative swing magnitude from the single-ended input signal after passing through the channel, converting it into a dual-ended differential signal. The continuous linear time equalizer compensates for the frequency domain response attenuation caused by the channel to cancel signal distortion, resulting in a pair of high-integrity signals. The parity dual-branch decision module performs dual-branch parity decision on the high-integrity signals based on the reference level to obtain the corresponding time sequence decision results. The decoding and deserialization unit deserializes the single-bit high-speed signal into a multi-bit low-speed signal based on the two decision results, obtaining the low-speed bus signal.

[0006] The reference level is obtained by, but is not limited to, selecting the corresponding voltage output according to the control word.

[0007] The digital signal to be transmitted adopts, but is not limited to, a pseudo-random sequence, which is obtained by shifting the enable information every clock cycle; correspondingly, at the receiving end, the cumulative bit error rate is obtained by verifying the low-speed bus signal.

[0008] The parity-even dual-branch decision module includes: two pairs of parallel dual-tailed comparators, two pairs of delay modulation equalizers, one pair of time comparators, and a reference level generation module. The first and third dual-tailed comparators receive the high integrity signal Vafe_m, and the second and fourth dual-tailed comparators receive the high integrity signal Vafe_p. Based on the input signal and the reference level, the four dual-tailed comparators determine their relative magnitude and voltage difference, and after a period of metastable state, provide a decision result, obtaining information about the level position of the input signal, and outputting it to the corresponding delay modulation equalizer. The differential output of the first time comparator is connected to the third and fourth delay modulation equalizers and the decoding / deserialization unit, respectively. The differential output of the second time comparator is connected to the first and second delay modulation equalizers and the decoding / deserialization unit, respectively. This allows each delay modulation equalizer to modulate the edge of the current cycle signal based on the decision of the previous cycle circuit, obtaining a signal to compensate for jitter caused by inter-symbol interference. The time comparators detect different time differences in the metastable state to obtain the time sequence decision result.

[0009] Technical effect

[0010] This invention is based on an overlapped multiplexing architecture at the transmitter end. By inputting four sets of half-rate coded sequences into parallel drivers, an overlapped interval for data output is created between the drivers. This allows for doubling the driving capability by simultaneously activating two enabled drivers, and the selection of the drivers can use a standard four-phase clock signal. By modulating the position of the edge change of one of the data paths using time-domain modulation technology, one of the active drivers at each moment can dynamically assume the pre-emphasis function. This allows the driver to alternate and multiplex between the main tap and the equalization tap roles, further improving the transmission efficiency and signal integrity of the circuit.

[0011] This invention utilizes a time comparator architecture at the receiving end to compare the differential input signal with a single reference level, initially obtaining state information of high, low, or intermediate levels. Through a secondary comparison of the decision signal, when the input is at an intermediate level, the convergence speed characteristic of the signal is used to decode its relationship with the common-mode level, thus completing the full decoding of the signal. Simultaneously, the comparison signal is fed back to the delay modulation module in the next cycle to equalize inter-symbol interference generated by the previous symbol and improve sampling margin.

[0012] Compared with the prior art, the present invention saves a reference voltage generation circuit, optimizes chip area and power consumption, and makes full use of the level relationship obtained when further decoding is required, effectively reducing the load capacitance of the subsequent circuit, thereby improving the overall energy efficiency of the receiver. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the transceiver structure and its timing diagram according to the present invention;

[0014] Figure 2 Timing diagram for the transmitter front-end data input, serialization and edge modulation modules;

[0015] Figure 3 This is a schematic diagram of the decoding logic for PAM4 under various conditions with a single reference level.

[0016] Figure 4 This is a schematic diagram illustrating the impact of inter-symbol interference (ISI) on decoding logic. Detailed Implementation

[0017] like Figure 1 As shown in the illustration, this embodiment relates to a single-reference level decoding transceiver system based on OVM encoding and time comparison. It includes: a low-speed serializer at the transmitter, a four-channel 2:1 serializer, four parallel edge modulation modules and their corresponding enable drivers, and at the receiver, a single-ended input to differential output circuit (S2D), a continuous-time linear equalizer (CTLE), an odd-even dual-branch decision module, and a decoding / deserializing unit connected in sequence. The edge modulation module modulates the edges of the input signals D0-D1 received by the second enable driver through a variable delay chain controlled by a gating signal based on an inverter architecture, causing them to transition to the next data bit D1 earlier. The two enable drivers combine to drive the output to the transition level. This allows the signal to switch to the target level more quickly when outputting the next data bit, thereby balancing the negative impact of channel interference and parasites on the edge transition skew. By using either enable driver as an emphasis tap, the transmitter exhibits better anti-interference capability.

[0018] like Figure 2As shown, in the operating state when driving D0 data, half-rate encoded data serves as the input to each enabled driver (for example, the D0D1 signal in the figure represents the serialization of D0 and D1 signals). All signal data is maintained for 2UI, and because adjacent signals overlap in the same state, the clock signals controlled by adjacent drivers also go high simultaneously for 1UI. Therefore, within each 1UI period, two enabled drivers are simultaneously enabled and driving the same data, achieving double the driving capability through overlapping multiplexing. Due to the increased driving capability, the size of each enabled driver can be reduced accordingly for the same requirements, thereby reducing parasitics at the output and improving circuit power consumption.

[0019] like Figure 1 As shown, the four-channel 2:1 serializer includes four pairs of registers, four latches, and four multiplexers. One register's D terminal is connected to the output data of the low-speed serializer, and its Q terminal is connected to the input of the multiplexer. Another register's D terminal is connected to the data, and its Q terminal is connected to the input of a latch controlled by an opposite clock. The latch's output is connected to the other input of the multiplexer. The multiplexer's output is the serialized data, which is connected to the enable driver.

[0020] The enable driver described herein is implemented using, but is not limited to, the technology described in "13.6 A 16Gb 37Gb / s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration".

[0021] In any given time slot, there are two enable drivers. One enable driver will stop working after 1 UI, while the other enable driver will switch data midway after 1 UI and then enable the second UI.

[0022] like Figure 1As shown, the odd / even dual-branch decision module includes: two pairs of parallel dual-tailed comparators, two pairs of delay modulation equalizers, one pair of time comparators, and a reference level generation module. The first and third dual-tailed comparators receive the high integrity signal Vafe_m, and the second and fourth dual-tailed comparators receive the high integrity signal Vafe_p. Based on the input signal and the reference level, the four dual-tailed comparators determine their relative magnitude and voltage difference, and after a period of metastable state, provide a decision result, obtaining information about the level position of the input signal, and outputting it to the corresponding delay modulation equalizer. The output of the first time comparator is connected to the third and fourth delay modulation equalizers and the decoding / deserialization unit, respectively. The output of the second time comparator is connected to the first and second delay modulation equalizers and the decoding / deserialization unit, respectively. This allows each delay modulation equalizer to modulate the edge of the current cycle signal based on the decision of the previous cycle circuit, obtaining a signal to compensate for inter-symbol interference. The time comparators detect different time differences in the metastable state to obtain the time sequence decision result.

[0023] The voltage difference between the decision signals at both ends of the dual-tailed comparator When the decision is made, i.e., the voltage difference is sufficient to trigger the threshold for subsequent module bit toggling, ,get Where t is the time variable, The regeneration time constant depends on parameters such as the transistor size used in the specific implementation of the circuit module. The voltage difference across the output terminals of the dual-tailed comparator is where... The voltage difference in the initial state. The threshold that triggers bit flipping in subsequent modules, The output of the double-tailed comparator is sufficient to trigger a bit flip, which is the time required to complete the comparison.

[0024] Since the two dual-tailed comparators share a single decision level The higher end will have a shorter convergence time, meaning a faster decision will be made.

[0025] The aforementioned delay modulation equalizer is implemented using a current-starved inverter. It modulates the delay time based on the input level, i.e., the previous reference level, thereby equalizing the delay difference introduced by inter-symbol interference and optimizing signal jitter.

[0026] The time comparator preferably employs a cross-coupled transconductance unit. When the clock is low, the reset period occurs, and the output node is reset to VDD. In subsequent comparison periods, the different convergence speeds of the signals result in differences in the pull-down capabilities at both ends. This difference is further amplified by the cross-coupled transistors until one end is pulled to ground and the other to VDD. When the previous time comparator is operating, its input signal is fed back to the output path of the current comparator, forming a feedback loop to control the delay of the two time comparison modules.

[0027] like Figure 3 The diagram illustrates the specific decoding logic for each PAM4 level under a single reference level in the receiver module. The reference level is set to the low decision level in traditional PAM4 comparison, between 00 and 01. When the input signal corresponds to 00 (low level) or 11 (high level), one of the levels after single-ended to differential conversion will be lower than the reference level. When both differential signals are higher than the decision level, the voltage difference between these two signals and the decision level will differ. Since a larger voltage difference at the comparator input results in a faster decision convergence time, comparing the decision signals output by the two comparators, the signal that converges faster will indicate that the differential terminal is closer to the decision level. The common mode of the differential terminals is the common mode of the PAM4 encoded signal; therefore, the signal closer to the decision level, i.e., lower than the common mode level, corresponds to the intermediate decision level in traditional comparison. This allows us to determine which intermediate level it belongs to.

[0028] like Figure 4 As shown, considering the impact of intersymbol interference (ISI), taking a negative ISI effect as an example, this effect reduces the voltage difference between the p-terminal voltage and the reference level, while increasing the voltage difference between the n-terminal voltage and the reference level. Therefore, the decision convergence time at the p-terminal increases, while the decision convergence time at the n-terminal decreases. By introducing a delay modulation module into the input path of the time comparator and connecting the two delay modules to the output of the time comparator during the previous decoding, the result of the previous decoding can compensate for the time difference caused by ISI in the current path. Thus, the input signal finally reaches the time comparator without the influence of ISI.

[0029] Through practical application scenario experiments, circuits were built and simulated in Cadence Virtuoso, and experiments were conducted at various process corners. The reference level and delay module parameters were scanned, and the experimental data obtained were as follows: under phase modulation at the transmitter, the output eye diagram can improve the mid-eye by 0.06 UI; when the equalization parameters at the receiver are set in the scanning range of 200 fs to 1 ps, the time difference can be improved by up to 0.3 ps.

[0030] The single-reference level decoding transceiver system based on OVM coding and time comparison was simulated to achieve a transceiver operating at a rate of 32Gbps. It can balance the 8.6dB attenuation at the Nyquist frequency of the channel and open the eye. The eye height of the three eyes accounts for 50% of the overall swing, and the power consumption can be controlled at 1.809 pJ / b.

[0031] Compared with existing technologies, this system utilizes four sets of half-rate sequences to control four enable drivers at the transmitting end, achieving double the driving force through output overlap. It can replace complex pulse generation circuits under 47%-53% duty cycle clock conditions. Combined with time-domain modulation technology, the enable drivers alternately perform the pre-emphasis function, thereby improving working efficiency. The receiving end adopts a single reference level scheme, using comparison decision and convergence feature analysis to resolve high, low, and intermediate levels. This design not only saves additional reference level generation overhead but also simplifies subsequent decoding logic by utilizing the inherent information of the comparator output, optimizing circuit area utilization and overall energy efficiency.

[0032] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. An OVM encoding and time comparison based single reference level decoding transceiver system, characterized by, include: The transmitter consists of a low-speed serializer, a four-channel 2:1 serializer, four parallel edge modulation modules and their corresponding enable drivers, while the receiver consists of a single-ended input to differential output circuit (S2D), a continuous-time linear equalizer (CTLE), an odd-even dual-branch decision module, and a decoding / deserializing unit, connected in sequence. Specifically: the low-speed serializer serializes the digital signal to be transmitted into a single-bit high-speed analog signal, obtaining four channels of data; the four-channel 2:1 serializer serializes the four channels of data to obtain four channels of half-rate encoded data, which are then edge-modulated and output to their respective enable drivers. Each enable driver is enabled or disabled according to its corresponding clock signal of a different phase. The circuit is shut down, ensuring that there are two enable drivers outputting the required encoded data in any time slot. The single-ended input to differential output circuit extracts the relative swing size based on the single-ended input signal after passing through the channel, converting it into a double-ended differential signal. The continuous linear time equalizer compensates for the response attenuation caused by the channel in the frequency domain to cancel signal distortion and obtain a pair of high integrity signals based on the differential analog signal. The parity dual-branch decision module performs dual-branch parity decision on the high integrity signal based on the reference level to obtain the corresponding time sequence decision results. The decoding and deserialization unit deserializes the single-bit high-speed signal into a multi-bit low-speed signal based on the two decision results to obtain the low-speed bus signal.

2. The OVM encoding and time comparison based single reference level decoding transceiver system according to claim 1, characterized in that, The parity-even dual-branch decision module includes: two pairs of parallel dual-tailed comparators, two pairs of delay modulation equalizers, one pair of time comparators, and a reference level generation module. The first and third dual-tailed comparators receive the high integrity signal Vafe_m, and the second and fourth dual-tailed comparators receive the high integrity signal Vafe_p. Based on the input signal and the reference level, the four dual-tailed comparators determine their relative magnitude and voltage difference, and after a period of metastable state, provide a decision result, obtaining information about the input signal's level position, and outputting it to the corresponding delay modulation equalizer. The output of the first time comparator is connected to the third and fourth delay modulation equalizers and the decoding / deserialization unit, respectively. The output of the second time comparator is connected to the first and second delay modulation equalizers and the decoding / deserialization unit, respectively. This allows each delay modulation equalizer to modulate the edge of the current cycle signal based on the decision of the previous cycle circuit, obtaining a signal to compensate for inter-symbol interference. The time comparators detect different time differences in the metastable state to obtain the time sequence decision result.

3. The single-reference level decoding and transceiver system based on OVM encoding and time comparison according to claim 2, characterized in that, The voltage difference of the two ends of the double-tail comparator When the decision is completed, that is, the voltage difference is enough to trigger the threshold value of the bit flip of the subsequent module, , get , wherein: t is the time independent variable, is the regeneration time constant, which depends on the transistor size and other parameters selected by the specific implementation of the circuit module, is the voltage difference between the two ends of the double-tail comparator output, wherein is the initial state voltage difference, is the threshold value of triggering the bit flip of the subsequent module, is the time when the output of the double-tail comparator is enough to trigger the bit flip, that is, the comparison is completed.

4. The single-reference level decoding and transceiver system based on OVM encoding and time comparison according to claim 2, characterized in that, The aforementioned delay modulation equalizer is implemented using a current-deficient inverter. It modulates the delay time based on the input level, i.e., the previous reference level, thereby equalizing the delay differences introduced by inter-symbol interference and optimizing the clock sampling margin. The outputs of the dual-tail comparator and the time comparator are deserialized, and the comparison result is decoded into data using digital logic according to the above principle, thus comparing it with the original sequence.

5. The single-reference level decoding and transceiver system based on OVM encoding and time comparison according to claim 2, characterized in that, The time comparator employs a cross-coupled transconductance unit. When the clock is low, it serves as a reset cycle, resetting the output node to VDD. In subsequent comparison cycles, the different convergence speeds of the signals result in differences in the pull-down capabilities at both ends. This difference is further amplified by the cross-coupled transistors until one end is pulled to ground and the other to VDD. When the previous time comparator is operating, its input signal is fed back to the output path of the current comparator, forming a feedback loop to control the delay of the two time comparison modules.

6. The single-reference level decoding transceiver system based on OVM encoding and time comparison according to claim 1, characterized in that, The edge modulation module modulates the edges of the input signals D0-D1 received by the second enable driver through a variable delay chain controlled by a gating signal based on an inverter architecture, causing them to transition to the next data bit D1 earlier. The two enable drivers then combine to drive the output to the transition level. This allows the signal to switch to the target level more quickly when outputting the next data bit, thereby balancing the negative impact of channel interference and parasites on the edge transition skew. By using either enable driver as an emphasis tap, the transmitter exhibits better anti-interference capability.

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