equalizer circuit

Abstract

This application discloses an equalizer circuit. The equalizer circuit includes a current source module, an RC network, and a differential transistor pair. The current source module is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair. The equalizer circuit also includes: an adjustable active inductor module, electrically connected to the first and second transistors in the differential transistor pair; and a control module, electrically connected to the current source module, the RC network, and the adjustable active inductor module, used to change the frequencies of the dominant and secondary poles of the equalizer circuit by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module. The above equalizer circuit can obtain compensation curves for peak values ​​at different frequency points, effectively solving channel compensation problems under different protocols and data rates. It solves the problem in related technologies where the equalizer needs to compensate for different channel attenuations under different protocols and data rates, making it impossible to achieve adjustable gain enhancement within 0-15dB for each frequency peak.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and more specifically, to an equalizer circuit. Background Technology

[0002] An equalizer (EQ) is a crucial component of a chip's receiver, used to compensate for signal attenuation in the channel. The amount of channel attenuation the EQ needs to compensate for varies depending on the interface protocol and data rate. To address the different attenuation levels in long and short channels, the EQ's gain boost is typically made adjustable, for example, within 0-15dB in 1dB increments.

[0003] Related technologies compensate for the maximum bandwidth during data transmission, ensuring that the EQ provides the maximum gain boost at its maximum bandwidth. For example, in a re-driver chip (a signal retiming chip), the EQ is the primary module for compensating for channel attenuation. If this chip supports both USB 4.0 and USB 3.2, and the EQ circuit is designed for USB 4.0 speeds, with a frequency peaking of 10GHz and a maximum gain boost of 15dB, while also considering long and short channels and being adjustable within 0-15dB, then at the USB 3.2 Nyquist frequency (5GHz), the gain boost will be much less than 15dB, limiting its application in USB 3.2 channel re-attenuation. Conversely, if the frequency peaking is designed to be 5GHz, and the maximum gain boost is also designed to be 15dB, then the gain boost at 10GHz will be much greater than 15dB, resulting in significant power waste and making it difficult to ensure the gain boost is adjustable within 0-15dB, especially struggling to cover the lowest gain boost.

[0004] There is currently no effective solution to the problem that the channel attenuation that EQ needs to compensate for varies under different protocols and rates, making it difficult to achieve adjustable gain boost within 0-15dB for each frequency peaking. Summary of the Invention

[0005] This application provides an equalizer circuit to solve the problem in related technologies where equalizers need to compensate for different channel attenuation under different protocols and different rates.

[0006] This application provides an equalizer circuit including a current source module, an RC network, and a differential transistor pair. The current source module is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair. The equalizer circuit further includes: an adjustable active inductor module, which is electrically connected to the first transistor and the second transistor in the differential transistor pair; and a control module, which is electrically connected to the current source module, the RC network, and the adjustable active inductor module, for changing the frequency of the dominant and secondary poles of the equalizer circuit by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module.

[0007] Optionally, the adjustable active inductor module includes a first adjustable current source, a first adjustable resistor, a first adjustable capacitor, and a first transistor, wherein: an RC network is electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor respectively; a first end of the first adjustable resistor is electrically connected to the RC network; and a second end of the first adjustable resistor is electrically connected to the gate of the first transistor and the first adjustable capacitor respectively.

[0008] Optionally, the current source module includes a second current source and a third current source, the differential transistor pair includes a second transistor and a third transistor, and the RC network includes a second adjustable resistor, a second adjustable capacitor module, and a third adjustable capacitor module, wherein: the second adjustable resistor and the second adjustable capacitor module are connected in parallel, the second current source and the first parallel node of the second adjustable resistor and the second adjustable capacitor module are electrically connected, the third current source and the second parallel node of the second adjustable resistor and the second adjustable capacitor module are electrically connected, the first parallel node is electrically connected to the first terminal of the third adjustable capacitor module through the second transistor, and the second parallel node is electrically connected to the second terminal of the third adjustable capacitor module through the third transistor.

[0009] Optionally, the control module includes: a decoder for receiving the encoded signal and decoding the encoded signal according to the decoder's truth table to obtain a logic control signal; and a controller electrically connected to the decoder, the current source module, the RC network, and the adjustable active inductor module, respectively, for adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module according to the logic control signal.

[0010] Optionally, the decoder is used to receive the first encoded signal and decode the first encoded signal according to the truth table of the first decoder to obtain a first logic control signal, wherein the first logic control signal is used to instruct the controller to the following control information: increase the current value of the second current source and the third current source, decrease the capacitance value of the first adjustable capacitor, and decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a first preset range; the controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the first logic control signal to reduce the frequency of the dominant pole and the secondary pole of the equalizer circuit.

[0011] Optionally, the decoder receives the second encoded signal and decodes it according to the truth table of the second decoder to obtain a second logic control signal. The second logic control signal is used to instruct the controller to perform the following control information: decrease the current values ​​of the second current source and the third current source, increase the capacitance value of the first adjustable capacitor, and increase the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the second logic control signal to increase the frequency of the dominant and secondary poles of the equalizer circuit.

[0012] Optionally, the decoder receives the second encoded signal and the third encoded signal, decodes the second encoded signal according to the truth table of the second decoder to obtain the second logic control signal, and decodes the third encoded signal according to the truth table of the third decoder to obtain the third logic control signal. The third logic control signal is used to instruct the controller to perform the following control information: reduce the current values ​​of the second current source and the third current source, reduce the capacitance value of the first adjustable capacitor, and reduce the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets the second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source in sequence according to the second logic control signal and the third logic control signal.

[0013] Optionally, the second adjustable capacitor module includes multiple first capacitor branches connected in parallel, each first capacitor branch including a first capacitor and a first switch connected in series; the third adjustable capacitor module includes multiple second capacitor branches connected in parallel, each first capacitor branch including a second capacitor and a second switch connected in series.

[0014] Optionally, the controller is also used to control the opening and closing of the first switch and the second switch according to the logic control signal.

[0015] According to this application, the equalizer circuit also includes an adjustable active inductor module and a control module. Since the control module is electrically connected to the current source module, the RC network and the adjustable active inductor module respectively, it can change the frequency of the dominant and secondary poles of the equalizer circuit by adjusting the performance parameters of the current source module, the RC network and the adjustable active inductor module. This allows for the acquisition of compensation curves for different frequency peaks, effectively solving the channel compensation problem under different protocols and data rates. It can achieve adjustable gain boost for multiple frequency peaks within 0-15dB, solving the problem in related technologies where the channel attenuation that the equalizer (EQ) needs to compensate for differs under different protocols and data rates, making it impossible to achieve adjustable gain boost for each frequency peak within 0-15dB. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 This is a schematic diagram of an equalizer circuit provided according to an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a dynamically adjustable active inductor in an equalizer circuit provided according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of the zero-point distribution of a dynamically adjustable active inductor according to an embodiment of this application;

[0020] Figure 4 This is a schematic representation of the true value of a decoder that adjusts the frequency peak of an equalizer circuit to shift to a higher frequency, according to an embodiment of this application.

[0021] Figure 5 This is a schematic diagram of the relationship between the frequency at which the peak value of an equalizer circuit shifts to a higher frequency and the gain increase, according to an embodiment of this application.

[0022] Figure 6 This is a schematic representation of the true value of a decoder that adjusts the frequency peak of an equalizer circuit to shift to a lower frequency, according to an embodiment of this application.

[0023] Figure 7 This is a schematic diagram of the relationship between the frequency at which the peak value of an equalizer circuit shifts to a lower frequency and the gain increase, according to an embodiment of this application.

[0024] Figure 8 This is a schematic representation of the decoder truth value of another equalizer circuit that shifts the frequency peak value to a lower frequency, according to an embodiment of this application.

[0025] Figure 9 This is a schematic diagram showing the relationship between the frequency at which the peak value of an equalizer circuit shifts to a lower frequency and the gain increase, according to an embodiment of this application. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0030] Equalizer: Abbreviated as EQ, full English name is Equalizer.

[0031] Decoder: Abbreviated as Dec, full English name is Decoder.

[0032] Gain boost: The full English name is gain boost.

[0033] Frequency peaking: The full English name is frequency peaking.

[0034] According to an embodiment of this application, an equalizer circuit is provided, such as... Figure 1 As shown, the equalizer circuit includes: a current source module 10, an RC network, and a differential transistor pair 20. The current source module is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair. The equalizer circuit also includes:

[0035] The adjustable active inductor module 30 is electrically connected to the first and second transistors in the differential transistor pair 20, respectively;

[0036] The control module 40 is electrically connected to the current source module 10, the RC network and the adjustable active inductor module 30 respectively (not shown in the connection diagram), and is used to change the frequency of the main pole and the secondary pole of the equalizer circuit by adjusting the performance parameters of the current source module 10, the RC network and the adjustable active inductor module 30.

[0037] In this embodiment, since the control module is electrically connected to the current source module, the RC network, and the adjustable active inductor module respectively, it can change the frequency of the dominant and secondary poles of the equalizer circuit by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module. This allows for the generation of compensation curves for different frequency peaks, effectively addressing channel compensation issues under different protocols and speeds. It enables adjustable gain boost for multiple frequency peaks within 0-15dB, solving the problem in related technologies where different channel attenuation needs to be compensated by the equalizer (EQ) under different protocols and speeds, making it impossible to achieve adjustable gain boost for each frequency peak within 0-15dB.

[0038] In some optional implementations, the equalizer circuit provided in this embodiment includes an adjustable active inductor module comprising a first adjustable current source, a first adjustable resistor, a first adjustable capacitor, and a first transistor, wherein: an RC network is electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor respectively; a first end of the first adjustable resistor is electrically connected to the RC network; and a second end of the first adjustable resistor is electrically connected to the gate of the first transistor and the first adjustable capacitor respectively.

[0039] In the above optional implementation, the adjustable active inductor module is used to contribute the zeros and poles of the equalizer circuit, wherein the function of the first adjustable current source is to shunt the current of the first transistor and adjust the transconductance of the first transistor.

[0040] For example, such as Figure 1 and Figure 2 As shown, the adjustable active inductor module 30 consists of a first adjustable current source I1, a first adjustable resistor R1, a first adjustable capacitor C1, and a first transistor M1. The zeros and poles contributed by this adjustable active inductor module are as follows: Figure 3 As shown, specifically, R f Let C be the resistance value of the first adjustable resistor R1. f Let g be the capacitance value of the first adjustable capacitor C1. md For the transconductance of the first transistor M1, from Figure 3 As can be seen directly, the amplitude of the high frequency is larger than that of the low frequency, so it is equivalent to zero.

[0041] In some optional implementations, the equalizer circuit provided in this embodiment includes a current source module comprising a second current source and a third current source, a differential transistor pair comprising a second transistor and a third transistor, and an RC network comprising a second adjustable resistor, a second adjustable capacitor module, and a third adjustable capacitor module, wherein: the second adjustable resistor and the second adjustable capacitor module are connected in parallel; the second current source and the second adjustable resistor and the second adjustable capacitor module are electrically connected to a first parallel node; the third current source and the second adjustable resistor and the second adjustable capacitor module are electrically connected to a second parallel node; the first parallel node is electrically connected to a first terminal of the third adjustable capacitor module through a second transistor; and the second parallel node is electrically connected to a second terminal of the third adjustable capacitor module through a third transistor.

[0042] For example, such as Figure 1 As shown, the current source module 10 includes a second current source I2 and a third current source I3, and the two current sources provide the same static current. The differential transistor pair 20 includes a second transistor M2 and a third transistor M3. The RC network includes a second adjustable resistor R2, a second adjustable capacitor module C2, and a third adjustable capacitor module C3 connected in parallel.

[0043] Specifically, in order to address the issue that the equalizer (EQ) needs to compensate for different channel attenuation under different protocols and data rates, and to achieve an adjustable gain boost of 0-15dB for each frequency peak, the primary and secondary poles of the equalizer can be made dynamically adjustable to achieve adjustable frequency peak.

[0044] by Figure 1 Taking the equalizer circuit shown as an example, the positions of the zeros, dominant poles, and secondary poles can be changed by adjusting the adjustable resistors, adjustable capacitors, and adjustable resistors, thereby altering the frequency response of the equalizer and compensating for signal attenuation in the channel. Specifically, the expression for the transfer function of the above equalizer circuit is: Among them, g m For the transconductance of the second transistor M2, C d R is the capacitance value of the third adjustable capacitor module C3. s C is the resistance value of the second adjustable resistor R2. s R is the capacitance value of the second adjustable capacitor module C2. d This is the resistance value of the adjustable active inductor module.

[0045] Based on the above transfer function, the expression for the zero point of the equalizer circuit is obtained as follows: The expression for the principal pole is: The expression for the second pole: Wherein, the resistance value R dThe first adjustable current source I1, the first adjustable resistor R1, the first adjustable capacitor C1, and the first transistor M1 in the adjustable active inductor module determine the adjustment of the primary and secondary poles of the equalizer by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module.

[0046] In the equalizer circuit provided in this embodiment, the control module may include a decoder and a controller. The decoder is used to receive the encoded signal and decode the encoded signal according to the decoder truth table to obtain a logic control signal. The controller is electrically connected to the decoder, the current source module, the RC network, and the adjustable active inductor module respectively, and is used to adjust the performance parameters of the current source module, the RC network, and the adjustable active inductor module according to the logic control signal.

[0047] Specifically, by configuring the performance parameters of the current source module, RC network, and adjustable active inductor module through a decoder, the dominant pole ω is determined when designing higher frequency peak values. p1 and sub-polarity ω p2 Pushing all frequencies upwards, when designing for lower frequency peak values, will ω p1 and ω p2 By pushing the frequency down to achieve frequency changes at the two extremes, the problem of compensation for different rates and channels can be solved. At the same time, for low-rate data transmission, power consumption can also be reduced.

[0048] For example, the first adjustable current source I1 is configured to have a current value I. f The second adjustable current source I2 and the third adjustable current source I3 have a current value I s The first adjustable resistor R1 has a resistance value R f The first adjustable capacitor C1 has a capacitance value C f The second adjustable capacitor C2 has a capacitance value C s The third adjustable capacitor C3 has a capacitance value C d Configure I through the decoder s C d C s R f C f I f The value of ω is used to achieve the dominant pole of the equalizer. p1 and sub-polarity ω p2 The controller's control logic can be implemented through a decoder, and it is adjustable.

[0049] Furthermore, in order to achieve the capacitance value C s and C dThe adjustable capacitor module C2 can include multiple first capacitor branches connected in parallel. Each first capacitor branch includes a first capacitor and a first switch connected in series. The truth table of the decoder determines whether the first capacitors in the multiple first capacitor branches are in an active state, thereby determining whether the corresponding capacitors are connected to the internal nodes of the equalizer circuit through the first switch. This allows the controller to control the opening and closing of the first switch according to the logic control signal, thereby adjusting the capacitance value C of the second adjustable capacitor module C2. s The third adjustable capacitor module C3 may also include multiple parallel second capacitor branches. Each second capacitor branch includes a second capacitor and a second switch connected in series. The truth table of the decoder determines whether the second capacitors on the multiple second capacitor branches are in an active state, thereby determining whether the corresponding capacitors are connected to the internal nodes of the equalizer circuit through the second switches. This allows the controller to control the opening and closing of the second switches according to the logic control signals, thereby adjusting the capacitance value C of the third adjustable capacitor module C3. d In the truth table, whether the first capacitor and the second capacitor are in a working state is represented by 0 and 1, respectively.

[0050] To achieve a higher peak frequency, in some optional implementations, a decoder is used to receive a first encoded signal and decode the first encoded signal according to a truth table of the first decoder to obtain a first logic control signal. The first logic control signal is used to instruct the controller to perform the following control information: increase the current values ​​of the second and third current sources, decrease the capacitance value of the first adjustable capacitor, and decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a first preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the first logic control signal to reduce the frequency of the dominant and secondary poles of the equalizer circuit.

[0051] For example, the truth table of the first decoder described above is as follows: Figure 4 As shown, the first capacitor C s1 ~C s7 When the value is 1 (representing true), it means that the corresponding capacitor is connected to the internal node of the equalizer circuit through the first switch that is turned on. The first capacitor C s1 ~C s7 When the value is 0 (indicating false), it means that the corresponding capacitor is not connected to the internal node of the equalizer circuit because the first switch is off, and the second capacitor C... d1 ~C d8 When the value equals 1, it indicates that the corresponding second capacitor is connected to the internal node of the equalizer circuit through the activated second switch. The second capacitor C d1 ~C d8 When the value is 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit because the second switch is turned off.s R is the current source value used to provide the equalizer (EQ) current. s The decoder is used to adjust the DC gain of the circuit. Its inputs are A<5:0> and its outputs are B<16:0>. The first capacitor C... s1 ~C s7 The true / false values ​​in the table are binary operators for A<3:0>, and the binary number in A<3:0> follows the first capacitor C. s1 ~C s7 Regardless of the true or false values ​​in the table, A<5:4> always retains an input value of 00.

[0052] Specifically, when designing high-frequency peak values, such as Figure 4 As shown, I can be s Set C to a larger value x1. f Let y1 be the smaller value, and let R... f Let z1 be a smaller value, so that I s Increase and R f and C f Reduce them all, and I f The gain of the equalizer can be increased by adjusting C, assuming a reasonable value X. s and C d This is achieved by obtaining a set of 16 adjustable gain boost bands, such as... Figure 5 As shown, the peak frequency is 10GHz, and the gain of the peak frequency is adjustable within 0-15dB.

[0053] To achieve a lower frequency peak, in some optional implementations, a decoder is used to receive a second encoded signal and decode the second encoded signal according to a second decoder truth table to obtain a second logic control signal. This second logic control signal is used to instruct the controller to: decrease the current values ​​of the second and third current sources, increase the capacitance value of the first adjustable capacitor, and increase the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the second logic control signal to increase the frequency of the dominant and secondary poles of the equalizer circuit.

[0054] For example, the truth table of the second decoder described above is as follows: Figure 6 As shown, the first capacitor C s1 ~C s7 When the value is 1 (representing true), it means that the corresponding capacitor is connected to the internal node of the equalizer circuit through the first switch that is turned on. The first capacitor C s1 ~C s7When the value is 0 (indicating false), it means that the corresponding capacitor is not connected to the internal node of the equalizer circuit because the first switch is off, and the second capacitor C... d1 ~C d8 When the value equals 1, it indicates that the corresponding second capacitor is connected to the internal node of the equalizer circuit through the activated second switch. The second capacitor C d1 ~C d8 When the value is 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit because the second switch is turned off. s R is the current source value used to provide the equalizer (EQ) current. s The decoder is used to adjust the DC gain of the circuit. Its inputs are A<5:0> and its outputs are B<16:0>. The first capacitor C... s1 ~C s7 The true / false values ​​in the table are binary operators for A<3:0>, and the binary number in A<3:0> follows the first capacitor C. s1 ~C s7 Regardless of the true or false values ​​in the table, A<5:4> always retains an input value of 01.

[0055] Specifically, in order to shift the frequency peak to lower frequencies, such as Figure 6 As shown, I can be s Set it to a smaller value x2, so that I is first... s The current decreases, causing the dominant pole ω to... p1 It will move to lower frequencies, and at the same time, C f Let y2 be a larger value, and set R... f Let z2 be a larger value, so that R f and C f Increase them all so that the secondary pole ω p2 It also shifts to lower frequencies and... f Let Y be a reasonable value. Similarly, the gain of the equalizer can be increased by adjusting C. s and C d This is achieved by obtaining a set of 16 adjustable gain boost bands, such as... Figure 7 As shown, the peak frequency is 5GHz, and the gain of the peak frequency is adjustable within 0-15dB.

[0056] Because of C f and R fAn increase in frequency might cause the frequency-gain relationship curve to rise overall. To address this, and in order to achieve a lower frequency peak, in some alternative implementations, the decoder receives the second and third encoded signals, decodes the second encoded signal according to the truth table of the second decoder to obtain a second logic control signal, and decodes the third encoded signal according to the truth table of the third decoder to obtain a third logic control signal. The third logic control signal is used to instruct the controller to: reduce the current values ​​of the second and third current sources, reduce the capacitance value of the first adjustable capacitor, and reduce the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source sequentially according to the second encoded signal and the third logic control signal.

[0057] For example, the truth table of the third decoder described above is as follows: Figure 8 As shown, the first capacitor C s1 ~C s7 When the value is 1 (representing true), it means that the corresponding capacitor is connected to the internal node of the equalizer circuit through the first switch that is turned on. The first capacitor C s1 ~C s7 When the value is 0 (indicating false), it means that the corresponding capacitor is not connected to the internal node of the equalizer circuit because the first switch is off, and the second capacitor C... d1 ~C d8 When the value equals 1, it indicates that the corresponding second capacitor is connected to the internal node of the equalizer circuit through the activated second switch. The second capacitor C d1 ~C d8 When the value is 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit because the second switch is turned off. s R is the current source value used to provide the equalizer (EQ) current. s The decoder is used to adjust the DC gain of the circuit. Its inputs are A<5:0> and its outputs are B<16:0>. The first capacitor C... s1 ~C s7 The true / false values ​​in the table are binary operators for A<3:0>, and the binary number in A<3:0> follows the first capacitor C. s1 ~C s7 Regardless of the true or false values ​​in the table, A<5:4> always retains an input value of 10.

[0058] Specifically, the above implementation method may include two steps: First, as Figure 8 As shown, I can be adjusted. f To a reasonable value Y, and I s Set it to a smaller value x2, thus setting Is Make it smaller, and at the same time reduce C f Let y2 be a larger value, and set R... f Let z2 be a larger value, so that R f and C f Increase each one, then adjust C. s and C d This yields a set of 16 gain-boost curves for each band; then, C... f Let y1 be the smaller value, and let R... f Let z1 be a smaller value, so that R f and C f Reduce each one by a small amount, then adjust C. s and C d This yields another set of 16 gain enhancement curves. The two sets of curves are then superimposed, and the 16 desired gain enhancement curves are selected, such as... Figure 9 As shown, the peak frequency is 5GHz, and the gain of the peak frequency is adjustable within 0-15dB. Its control logic is implemented through a decoder, which can achieve an adjustable gain of 0-15dB for each peak frequency.

[0059] According to an embodiment of this application, a method for adjusting the pole frequency of an equalizer circuit is also provided. The method for adjusting the pole frequency of an equalizer circuit according to the embodiment of this application can be applied to the equalizer circuit provided in the above embodiment. The method for adjusting the pole frequency of an equalizer circuit provided in the embodiment of this application will be described below.

[0060] The pole frequency method provided in this embodiment includes the following steps:

[0061] The control module in the equalizer circuit receives control signals;

[0062] The aforementioned control module adjusts the performance parameters of the current source module, RC network, and adjustable active inductor module in the equalizer circuit according to the control signal. Specifically, the controller adjusts the performance parameters of the current source module, RC network, and adjustable active inductor module according to the logic control signal to change the frequency of the dominant and secondary poles of the equalizer circuit.

[0063] In this embodiment, since the control module in the equalizer circuit is electrically connected to the current source module, RC network, and adjustable active inductor module respectively, it can adjust the performance parameters of the current source module, RC network, and adjustable active inductor module according to the received control signal, thereby changing the frequency of the dominant and secondary poles of the equalizer circuit. This allows for the generation of compensation curves for different frequency peaks, effectively addressing channel compensation issues under different protocols and data rates. The gain boost of multiple frequency peaks can be adjusted within 0-15dB, solving the problem in related technologies where the equalizer (EQ) needs to compensate for different channel attenuations under different protocols and data rates, making it impossible to achieve adjustable gain boost of each frequency peak within 0-15dB.

[0064] In some optional implementations, the control module in the equalizer circuit includes a decoder and a controller, with the controller electrically connected to the decoder, current source module, RC network, and adjustable active inductor module, respectively. Receiving the control signal includes: the decoder receiving the encoded signal and decoding the encoded signal according to the decoder's truth table to obtain a logic control signal.

[0065] In the above optional implementation, since the decoder can decode the encoded signal according to the decoder truth table to obtain the logic control signal, the controller can adjust the performance parameters of the current source module, RC network and adjustable active inductor module according to the logic control signal after receiving the logic control signal.

[0066] Specifically, by configuring the performance parameters of the current source module, RC network, and adjustable active inductor module through a decoder, the dominant pole ω is determined when designing higher frequency peak values. p1 and sub-polarity ω p2 Pushing all frequencies upwards, when designing for lower frequency peak values, will ω p1 and ω p2 By pushing the frequency down to achieve frequency changes at the two extremes, the problem of compensation for different rates and channels can be solved. At the same time, for low-rate data transmission, power consumption can also be reduced.

[0067] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0068] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An equalizer circuit, characterized in that, The equalizer circuit includes a current source module, an RC network, and a differential transistor pair, wherein the current source module is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair. The equalizer circuit further includes: An adjustable active inductor module is electrically connected to the first and second transistors in the differential transistor pair, respectively; The control module is electrically connected to the current source module, the RC network, and the adjustable active inductor module, respectively, and is used to change the frequency of the main pole and the secondary pole of the equalizer circuit by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module. The adjustable active inductor module includes a first adjustable current source, a first adjustable resistor, a first adjustable capacitor, and a first transistor, wherein: the RC network is electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor respectively; the first end of the first adjustable resistor is electrically connected to the RC network; and the second end of the first adjustable resistor is electrically connected to the gate of the first transistor and the first adjustable capacitor respectively.

2. The equalizer circuit according to claim 1, characterized in that, The current source module includes a second current source and a third current source; the differential transistor pair includes a second transistor and a third transistor; the RC network includes a second adjustable resistor, a second adjustable capacitor module, and a third adjustable capacitor module, wherein: The second adjustable resistor is connected in parallel with the second adjustable capacitor module. The second current source is electrically connected to the first parallel node of the second adjustable resistor and the second adjustable capacitor module. The third current source is electrically connected to the second parallel node of the second adjustable resistor and the second adjustable capacitor module. The first parallel node is electrically connected to the first terminal of the third adjustable capacitor module through the second transistor. The second parallel node is electrically connected to the second terminal of the third adjustable capacitor module through the third transistor.

3. The equalizer circuit according to claim 2, characterized in that, The control module includes: A decoder is used to receive an encoded signal and decode the encoded signal according to the decoder truth table to obtain a logic control signal; The controller is electrically connected to the decoder, the current source module, the RC network, and the adjustable active inductor module, respectively, and is used to adjust the performance parameters of the current source module, the RC network, and the adjustable active inductor module according to the logic control signal.

4. The equalizer circuit according to claim 3, characterized in that, The decoder is used to receive the first encoded signal and decode the first encoded signal according to the truth table of the first decoder to obtain the first logic control signal. The first logic control signal is used to indicate the following control information to the controller: increase the current value of the second current source and the third current source, decrease the capacitance value of the first adjustable capacitor, decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets the first preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the first logic control signal, so as to reduce the frequency of the major pole and the minor pole of the equalizer circuit.

5. The equalizer circuit according to claim 3, characterized in that, The decoder is used to receive the second encoded signal and decode the second encoded signal according to the truth table of the second decoder to obtain the second logic control signal. The second logic control signal is used to indicate the following control information to the controller: reduce the current value of the second current source and the third current source, increase the capacitance value of the first adjustable capacitor, increase the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets the second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source according to the second logic control signal, so as to increase the frequency of the major pole and the minor pole of the equalizer circuit.

6. The equalizer circuit according to claim 5, characterized in that, The decoder is used to receive the second encoded signal and the third encoded signal, and decode the second encoded signal according to the truth table of the second decoder to obtain the second logic control signal, and decode the third encoded signal according to the truth table of the third decoder to obtain the third logic control signal. The third logic control signal is used to indicate the following control information to the controller: reduce the current value of the second current source and the third current source, reduce the capacitance value of the first adjustable capacitor, and reduce the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets the second preset range. The controller is used to adjust the second current source, the third current source, the first adjustable capacitor, the first adjustable resistor, and the first adjustable current source in sequence according to the second logic control signal and the third logic control signal.

7. The equalizer circuit according to claim 3, characterized in that, The second adjustable capacitor module includes multiple first capacitor branches connected in parallel, and each first capacitor branch includes a first capacitor and a first switch connected in series. The third adjustable capacitor module includes multiple second capacitor branches connected in parallel, and each first capacitor branch includes a second capacitor and a second switch connected in series.

8. The equalizer circuit according to claim 7, characterized in that, The controller is also used to control the opening and closing of the first switch and the second switch according to the logic control signal.

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