Frame rate determination method and apparatus

Abstract

The application discloses a frame rate determination method and device, and relates to the technical field of image processing. The specific technical scheme is as follows: a timestamp is acquired through a master control chip, the timestamp comprises a rendering timestamp of a rendering frame and a generation timestamp of a generated frame, and the generated frame is generated based on the rendering frame; the acquired timestamp is stored in a cache unit of a timestamp cache area through the master control chip; all the timestamps stored in the timestamp cache area are read through the master control chip under the condition that all the cache units of the timestamp cache area have cached the timestamps, a timestamp set is obtained, and every interval of a first time length, all the timestamps stored in the timestamp cache area are read, and a timestamp set is obtained; and the display frame rate of the screen of the electronic device is determined through the master control chip based on two timestamp sets read through adjacent twice reading operations.

Description

Technical Field

[0001] This application belongs to the field of image processing, and specifically relates to a frame rate determination method and apparatus. Background Technology

[0002] Currently, with the development of electronic devices, more and more users are using them for entertainment. For example, users can play games and watch videos on electronic devices. To make the game or video displayed on the screen of an electronic device smoother, the device typically renders the game or video using its GPU, then uses a dedicated graphics chip to perform super-resolution frame interpolation on the rendered game or video, increasing the frame rate. Finally, the super-resolution interpolated game or video is transmitted to the screen, resulting in a smoother gaming or video experience.

[0003] However, how electronic devices can display the game's frame rate after obtaining the frame rate from the discrete graphics chip's super-resolution interpolation is a problem that urgently needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a frame rate determination method and apparatus that can determine the frame rate of the game screen displayed on the screen of an electronic device after the discrete graphics chip performs super-resolution frame interpolation.

[0005] In a first aspect, embodiments of this application provide a frame rate determination method applied to an electronic device, the electronic device including a main control chip, the method comprising:

[0006] The timestamp is obtained through the main control chip. The timestamp includes the rendering timestamp of the rendering frame and the generation timestamp of the generated frame. The generated frame is generated based on the rendering frame.

[0007] The main control chip stores the acquired timestamps into the cache unit of the timestamp cache area;

[0008] With all cache units in the timestamp buffer cache containing timestamps, the main control chip reads all timestamps stored in the timestamp buffer cache to obtain a timestamp set. Then, at each first time interval, it reads all timestamps stored in the timestamp buffer cache to obtain a timestamp set.

[0009] The display frame rate of the electronic device's screen is determined by the main control chip based on two sets of timestamps read from two adjacent read operations.

[0010] Secondly, embodiments of this application provide a frame rate determination device, which includes a main control chip. The main control chip is used for:

[0011] Get the timestamps, which include the rendering timestamp of the rendering frame and the generation timestamp of the generated frame. The generated frame is generated based on the rendering frame.

[0012] The acquired timestamp is stored in the cache unit of the timestamp cache area;

[0013] If all cache units in the timestamp cache contain timestamps, read all timestamps stored in the timestamp cache to obtain a timestamp set, and at each first interval, read all timestamps stored in the timestamp cache to obtain a timestamp set.

[0014] The display frame rate of the electronic device's screen is determined based on two sets of timestamps read in two consecutive read operations.

[0015] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0016] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0017] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0018] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0019] In this embodiment, the main control chip acquires timestamps, including the rendering timestamp of the rendered frame and the generation timestamp of the generated frame, where the generated frame is generated based on the rendered frame. The main control chip stores the acquired timestamps into cache units of the timestamp cache. With all cache units in the timestamp cache containing timestamps, the main control chip reads all timestamps stored in the timestamp cache to obtain a timestamp set. This process is repeated every first time interval. The main control chip determines the display frame rate of the electronic device's screen based on the two timestamp sets read in two adjacent read operations. Thus, since the timestamps stored in the timestamp cache by the main control chip include not only the rendering timestamp of the rendered frame but also the generation timestamp of the generated frame, the two timestamp sets read by the main control chip in two adjacent read operations necessarily include both the rendering timestamp of the rendered frame and the generation timestamp of the generated frame. Therefore, when displaying rendered frames and generated frames, the display frame rate determined by the main control chip based on two sets of timestamps read in two adjacent read operations can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a frame rate determination method provided in an embodiment of this application;

[0021] Figure 2 This is a flowchart illustrating a frame rate determination method provided in an embodiment of this application;

[0022] Figure 3 This is a flowchart illustrating a frame rate determination method provided in an embodiment of this application;

[0023] Figure 4 This is a flowchart illustrating a frame rate determination method provided in an embodiment of this application;

[0024] Figure 5 This is a flowchart illustrating a frame rate determination method provided in an embodiment of this application;

[0025] Figure 6A This is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0026] Figure 6B This is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0027] Figure 6C This is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0028] Figure 6DThis is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0029] Figure 6E This is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0030] Figure 6F This is a schematic diagram of a frame interpolation method provided in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of a frame rate determination device provided in an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of a frame rate determination device provided in an embodiment of this application;

[0033] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0034] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0036] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0037] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0038] The following will explain the terminology used in the embodiments of this application.

[0039] A System on Chip (SoC), also known as a system-on-a-chip or main control chip, is a system composed of multiple integrated circuits with specific functions. It typically includes modules such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Display Processing Unit (DPU), a Digital Signal Processor (DSP), Random Access Memory (RAM), and a Modem.

[0040] Motion estimation and motion compensation (MEMC) can insert intermediate frames into low frame rate videos to make the video smoother, based on the continuity of dynamic images.

[0041] Artificial Intelligence Super Resolution (AISR) uses neural networks to restore low-resolution images to high-resolution images.

[0042] Image quality (PQ) refers to color adjustments made to achieve a desired visual effect.

[0043] The frame rate determination method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0044] The frame rate determination method provided in this application embodiment can be applied to scenarios where the frame rate of the screen display of an electronic device is determined. The screen can be a video screen, a game screen, or other screens. This embodiment does not impose specific limitations here.

[0045] The following explanation uses the example of how to determine the frame rate of a game screen.

[0046] Currently, all mobile phone manufacturers are developing games. To improve game frame rates, dedicated graphics chips are typically used to increase the frame rate and improve the smoothness of the game displayed on the electronic device's screen. However, in addition to experiencing the increased frame rate brought by dedicated graphics chips, users also want to view the frame rate curve in real time to understand the current game status. Users can view game frame rates through "game apps" and "benchmarking tools."

[0047] Game apps typically have a built-in real-time frame rate display switch. For example, after enabling frame rate display in the settings of a certain game like Honor of Kings, the real-time rendered frame rate will be displayed in the upper right corner of the game screen. Game frame rate measurement tools, such as Perfdog, can acquire the game frame rate in real time and plot the game frame rate curve, thereby indicating the performance throughout the game. The real-time frame rate information displayed by the game app is obtained during the rendering stage, where the CPU in the main control chip obtains the game screen data from the game's backend server, transmits the acquired game screen data to the GPU, and the main control chip then uses the GPU to render the game screen based on the game screen data. The frame rate information displayed by the benchmarking tool is obtained during the process where the main control chip transmits the game screen to the DPU for further processing after the GPU renders the game screen.

[0048] Perfdog and other frame rate measurement tools calculate game frame rates by reading the timestamp information of the game rendering. Each time the GPU renders a frame, it generates three timestamps: the estimated on-screen timestamp, the actual on-screen timestamp, and the rendering completion timestamp. The main control chip stores these timestamps as a group in a circular buffer with 128 cache units, with each cache unit holding one group of timestamps. Perfdog reads all the timestamps in the circular buffer every 0.5 seconds and determines the number of timestamp groups that differ between two consecutive reads. This number represents the actual number of game frames within that 0.5-second timeframe. Assuming the number of frames is N (within 0.5 seconds), the game's frame rate is 2N / s.

[0049] For example, suppose that 0.5 seconds ago, the circular buffer contained 128 timestamps representing frames 1 through 128 of the game. 0.5 seconds later, the GPU continued rendering 60 frames (frames 129 through 188). The main control chip would then store the timestamps from frames 129 to 188 in the circular buffer, overwriting the timestamps from frames 1 through 60. Therefore, the Perfdog tool read the timestamps from the circular buffer 0.5 seconds ago from frames 1 through 128, and 0.5 seconds later from frames 61 through 188. Perfdog performs a deduplication operation on the two timestamp reads, removing the timestamps from frames 61 through 128, and obtaining the timestamps from frames 129 through 188. At this point, perfdog knows that the game frames from frame 129 to frame 188 are newly added game frames within this 0.5 seconds, and the total number of newly added game frames is 188-129+1=60 frames, that is, the frame rate per second is 60*2=120 FPS.

[0050] Since discrete graphics chips are externally connected to the DPU for frame interpolation in games, neither of these two methods can obtain the actual frame rate displayed on the electronic device's screen after the discrete graphics chip's frame interpolation; they can only obtain the rendered frame rate. For example, if the game's rendered frame rate is 60 FPS, and the discrete graphics chip uses a frame interpolation algorithm to increase the frame rate to 120 FPS, the user will see a frame rate of 60 FPS through these two methods, but will not obtain the frame rate information of the discrete graphics chip increasing the frame rate to 120 FPS. Therefore, the user will not know whether the discrete graphics chip's frame interpolation function is effective based on the perceived frame rate.

[0051] To address this, this application provides a frame rate determination method. The method involves acquiring timestamps via a main control chip. These timestamps include the rendering timestamp of the rendered frame and the generation timestamp of the generated frame, where the generated frame is generated based on the rendered frame. The main control chip stores the acquired timestamps in a cache unit of a timestamp cache. With all cache units in the timestamp cache containing timestamps, the main control chip reads all timestamps stored in the timestamp cache to obtain a timestamp set. This process is repeated every first time interval to obtain another timestamp set. Based on the two timestamp sets read in two consecutive read operations, the main control chip determines the display frame rate of the electronic device's screen. Since the timestamps stored in the timestamp cache by the main control chip include not only the rendering timestamp of the rendered frame but also the generation timestamp of the generated frame, the two timestamp sets read by the main control chip in two consecutive read operations necessarily include both the rendering timestamp of the rendered frame and the generation timestamp of the generated frame. Therefore, when displaying rendered frames and generated frames, the display frame rate determined by the main control chip based on two sets of timestamps read in two adjacent read operations can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen.

[0052] The frame rate determination method provided in this application can be executed by an electronic device, or at least one of the functional modules and physical modules within the electronic device capable of implementing the frame rate determination method. The specific implementation can be determined according to actual usage requirements, and this invention does not impose any limitations. The following explanation uses the execution of the frame rate determination method by an electronic device as an example to illustrate the frame rate determination method provided in this application.

[0053] This application provides an image processing method applied to an electronic device containing a main control chip. Figure 1 This is a schematic flowchart of the image processing method provided in the embodiments of this application, as shown below. Figure 1 As shown, the image processing method provided in this application embodiment may include the following steps 101 to 104:

[0054] Step 101: The electronic device obtains the timestamp through the main control chip.

[0055] In some embodiments of this application, the timestamp may include the rendering timestamp of the rendering frame and the generation timestamp of the generated frame, wherein the generated frame is generated based on the rendering frame.

[0056] In some embodiments of this application, the above-mentioned rendering frame may be obtained by the electronic device through the GPU in the main control chip.

[0057] In some embodiments of this application, the electronic device generates a rendering timestamp of the rendering frame at the same time as the rendering frame is obtained by the GPU in the main control chip.

[0058] In some embodiments of this application, the above-mentioned rendering frame can be a game screen, video screen, or live broadcast screen rendered by the GPU. The specific frame can be determined according to actual needs, and no specific limitation is made here.

[0059] In some embodiments of this application, before the GPU renders the above-mentioned rendering frame, the electronic device can obtain screen data from the background server of the first application through the CPU in the main control chip, and pass the obtained screen data to the GPU, and then the GPU renders the above-mentioned screen data to obtain the above-mentioned rendering frame.

[0060] In some embodiments of this application, the first application mentioned above can be a game application, a video application, or other applications. The specific application can be determined according to actual needs, and no specific limitation is made here.

[0061] For example, if the aforementioned screen data is game screen data, the electronic device can obtain the aforementioned screen data from the background server of the game application through the CPU.

[0062] In some embodiments of this application, after the electronic device obtains the above-mentioned rendering frame through GPU rendering, it can perform super-interpolation processing on the above-mentioned rendering frame through an image processing chip to generate the above-mentioned generated frame.

[0063] In some embodiments of this application, the electronic device can use the main control chip to perform frame interpolation processing on the above-mentioned rendering frame using the MEMC algorithm, and then use the AISR algorithm to perform super-resolution processing on the interpolated rendering frame to generate the above-mentioned generated frame.

[0064] In some embodiments of this application, after the electronic device generates the above-mentioned generated frame through the discrete graphics chip, the above-mentioned rendered frame and the above-mentioned generated frame can be transmitted to the screen for display in chronological order through the discrete graphics chip.

[0065] Step 102: The electronic device stores the acquired timestamp into the cache unit of the timestamp cache area through the main control chip.

[0066] In some embodiments of this application, each time an electronic device obtains a timestamp through the main control chip, it can store the obtained timestamp into a cache unit of the aforementioned timestamp cache area.

[0067] Step 103: When all the cache units in the timestamp cache area have cached timestamps, the electronic device reads all the timestamps stored in the timestamp cache area through the main control chip to obtain a timestamp set, and reads all the timestamps stored in the timestamp cache area at intervals of the first time period to obtain a timestamp set.

[0068] In some embodiments of this application, the timestamp buffer can be a ring buffer, a first-in-first-out buffer, or other buffers. The specific type can be determined according to actual needs, and no specific limitation is made here.

[0069] In some embodiments of this application, a cache unit of the timestamp cache is used to store a timestamp.

[0070] Step 104: The electronic device determines the display frame rate of the screen by using the main control chip to read two sets of timestamps from two adjacent read operations.

[0071] In some embodiments of this application, the electronic device can obtain the number of timestamps that differ between two sets of timestamps read in two adjacent read operations, and determine the display frame rate of the screen of the electronic device based on the number.

[0072] In some embodiments of this application, since the timestamps obtained by the electronic device include the rendering timestamp of the rendering frame and the generation timestamp of the generated frame, all timestamps cached in the timestamp buffer must include at least one rendering timestamp of the rendering frame and at least one generation timestamp of the generated frame. Consequently, the set of timestamps read by the electronic device through the main control chip based on the read operation also includes at least one rendering timestamp of the rendering frame and at least one generation timestamp of the generated frame. Therefore, the display frame rate determined by the electronic device through the main control chip based on the two sets of timestamps read in two adjacent read operations must be determined based on reading at least one rendering timestamp of the rendering frame and at least one generation timestamp of the generated frame in two adjacent read operations.

[0073] In some embodiments of this application, since the electronic device displays not only rendered frames but also generated frames, the display frame rate determined by the main control chip based on the two sets of timestamps read in two adjacent read operations, compared to the frame rate determined by the number of timestamps that differ between the two sets of rendered timestamps read in two adjacent read operations in related technologies, can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen.

[0074] In the frame rate determination method provided in this application embodiment, the main control chip stores the acquired timestamps into the cache units of the timestamp cache area. The timestamps include the rendering timestamp of the rendered frame and the generation timestamp of the generated frame, where the generated frame is generated based on the rendered frame. When all cache units in the timestamp cache area have timestamps cached, the main control chip reads all the timestamps stored in the timestamp cache area to obtain a timestamp set. Then, at each first time interval, it reads all the timestamps stored in the timestamp cache area to obtain another timestamp set. Based on the two timestamp sets read in two adjacent read operations, the main control chip determines the display frame rate of the electronic device's screen. Thus, since the timestamps stored in the timestamp cache area by the main control chip include not only the rendering timestamp of the rendered frame but also the generation timestamp of the generated frame based on the rendered frame, the two timestamp sets read by the main control chip in two adjacent read operations necessarily include both the rendering timestamp of the rendered frame and the generation timestamp of the generated frame based on the rendered frame. Therefore, when displaying rendered frames and generated frames, the display frame rate determined by the main control chip based on two sets of timestamps read in two adjacent read operations can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen.

[0075] In some embodiments of this application, combined with Figure 1 ,like Figure 2 As shown, the step 102 above, "the main control chip stores the acquired timestamp into the cache unit of the timestamp cache area," can be achieved through the following step 102a:

[0076] Step 102a: When all cache units in the timestamp cache area have cached timestamps, the electronic device, upon obtaining a timestamp through the main control chip, caches the obtained timestamp in the first cache unit among the multiple cache units in the timestamp cache area, and overwrites the original timestamp cached in the first cache unit.

[0077] In some embodiments of this application, the first cache unit may be the cache unit with the earliest timestamp among the plurality of cache units.

[0078] In some embodiments of this application, when all cache units in the aforementioned timestamp cache area cache timestamps, the electronic device can cache the acquired timestamp to the aforementioned first cache unit each time it obtains a timestamp through the main control chip. This effectively avoids the same cache unit being repeatedly overwritten, thereby preventing errors in the number of timestamps that differ between the two timestamp sets read by the electronic device in two adjacent read operations through the main control chip. This makes the number of timestamps that differ between the two timestamp sets read by the read operation more accurate, thereby improving the accuracy of the screen's display frame rate.

[0079] For example, the aforementioned timestamp cache contains 10 cache units, from cache unit 1 to cache unit 10, and all 10 cache units cache timestamps. The timestamp cached in cache unit 1 is the oldest, followed by the timestamp cached in cache unit 2, and so on, with the timestamp cached in cache unit 10 being the latest. Suppose an electronic device obtains a timestamp 'a' through the main control chip. Since timestamp 'a' is newly obtained, it is later than the timestamp cached in cache unit 10. If the electronic device caches the timestamp in cache unit 1, overwriting the original timestamp cached in cache unit 1, then the timestamp cached in cache unit 2 will be the oldest, followed by the timestamp cached in cache unit 3, and so on, with the timestamp cached in cache unit 1 being the latest. The next time the electronic device obtains a timestamp 'b' through the main control chip, again, since timestamp 'b' is newly obtained, it will be later than the timestamp 'a' cached in cache unit 1. If the electronic device continues to cache timestamps in cache unit 1, then when the electronic device obtains one timestamp set for every two timestamps cached in the aforementioned timestamp cache area by the main control chip, the only difference between the two timestamp sets read by the electronic device in two consecutive read operations is the timestamps cached in cache unit 1. That is, the number of timestamps differing between the two timestamp sets read in two consecutive read operations is 1. However, the electronic device caches two timestamps, timestamp a and timestamp b, in the aforementioned timestamp cache area by the main control chip, meaning the actual number of newly added timestamps is 2. Therefore, the actual number of timestamps differing between the two timestamp sets should be 2. Thus, there is an error in the number of timestamps differing between the two timestamp sets obtained by the electronic device in two consecutive read operations by the main control chip. Therefore, to avoid this error, after obtaining timestamp b through the main control chip, the electronic device can cache timestamp b in cache unit 2, which has the earliest cached timestamp. In this way, the timestamps cached in cache unit 1 and cache unit 2 will differ in the two timestamp sets read by the electronic device in two consecutive read operations of the main control chip. That is, the number of timestamps that differ in the two timestamp sets read in the two read operations is 2, which is the same as the actual number of timestamps that differ in the two timestamp sets.

[0080] It should be noted that when some cache units in the timestamp cache area have cached timestamps, each time the main control chip of the electronic device obtains a timestamp, it will cache the obtained timestamp in the first cache unit of the timestamp cache area that does not have a cached timestamp.

[0081] Thus, when all cache units in the timestamp buffer have timestamps cached, each time the main control chip of the electronic device obtains a timestamp, it caches the obtained timestamp in the first cache unit of the timestamp buffer and overwrites the timestamps originally cached in the first cache unit. This effectively avoids the same cache unit being overwritten repeatedly, and thus avoids errors in the number of timestamps that differ between the two timestamp sets read by the electronic device in two adjacent read operations by the main control chip. This makes the number of timestamps that differ between the two timestamp sets read in the read operation more accurate, thereby improving the accuracy of the screen's display frame rate.

[0082] In some embodiments of this application, combined with Figure 1 ,like Figure 3 As shown, step 104 above can be achieved through the following steps 104a and 104b:

[0083] Step 104a: The electronic device determines the number of timestamps that differ between two adjacent timestamp sets read by the main control chip.

[0084] In some embodiments of this application, the electronic device can compare a third timestamp in the first timestamp set of the main control chip with all timestamps in the second timestamp set to determine whether there is a timestamp in the second timestamp set that is the same as the third timestamp. If not, the third timestamp is taken as a timestamp that differs from the first timestamp set and the second timestamp set. Here, the first timestamp set is any one of the two timestamp sets, the second timestamp set is any timestamp in the two timestamp sets excluding the first timestamp set, and the third timestamp is any timestamp in the first timestamp set.

[0085] Step 104b: The electronic device determines the display frame rate based on the quantity and the first duration through the main control chip.

[0086] In some embodiments of this application, the electronic device may calculate the ratio of the above quantity to the above first duration and determine the above ratio as the above display frame rate.

[0087] For example, an electronic device can calculate the above display frame rate using the following formula:

[0088] F=N / t1;(1)

[0089] Where F represents the aforementioned display frame rate, N represents the aforementioned quantity, and t1 represents the aforementioned first duration.

[0090] In this way, the electronic device uses the main control chip to determine the number of timestamps that differ between two adjacent timestamp sets; and the main control chip determines the display frame rate based on the number and the first duration, thus enabling the electronic device screen to quickly and accurately determine the display frame rate.

[0091] In some embodiments of this application, combined with Figure 1 ,like Figure 4 As shown, the frame rate determination method provided in this application embodiment may further include the following steps 105 to 107:

[0092] Step 105: Each time the electronic device renders a rendering frame through the main control chip, it transmits the current rendering frame to the image processing chip.

[0093] In some embodiments of this application, the electronic device transmits the current rendering frame to the image processing chip every time the GPU in the main control chip renders a rendering frame.

[0094] In some embodiments of this application, the electronic device can transmit the currently rendered frame to the image processing chip through the MIPI interface of the main control chip.

[0095] Step 106: The electronic device generates M generated frames and a first bit sequence based on the current rendering frame transmitted by the main control chip and the previous rendering frame adjacent to the current rendering frame.

[0096] In some embodiments of this application, the first bit sequence may include L bits, which may correspond to L time points within the rendering interval between the current rendering frame and the previous rendering frame. The number of bits in the first bit sequence whose bit value is the first bit value is M. The M bits in the first bit sequence whose bit value is the first bit value correspond to the generation time of the M generated frames, where M is a positive integer or 0, and L is a positive integer greater than or equal to M.

[0097] In some embodiments of this application, the bit value of a bit in the first bit sequence described above can be either a first bit value or a second bit value.

[0098] In some embodiments of this application, the first bit value can be 1 and the second bit value can be 0, or the first bit value can be 0 and the second bit value can be 1. The first bit value and the second bit value can be determined according to actual needs, and this embodiment does not impose specific limitations here.

[0099] In some embodiments of this application, the rendering interval can be the interval between the end time of the rendering of the previous rendering frame and the end time of the rendering of the current rendering frame.

[0100] In some embodiments of this application, the "generating the first bit sequence" in step 106 above can be achieved through the following steps 106a and 106b:

[0101] Step 106a: The electronic device generates a bit every second time interval between the first and second time intervals via the image processing chip.

[0102] The first moment can be the rendering timestamp of the previous rendering frame, and the second moment can be the moment indicated by the rendering timestamp of the current rendering frame.

[0103] In some embodiments of this application, the rendering timestamp of the previous rendering frame can be understood as the rendering end time of the previous rendering frame. In other words, the first moment can be the rendering end time of the previous rendering frame.

[0104] In some embodiments of this application, the time indicated by the rendering timestamp of the current rendering frame can be understood as the rendering end time of the previous rendering frame. In other words, the second time can be the rendering end time of the current rendering frame.

[0105] In some embodiments of this application, the time interval between the first time moment and the second time moment is the rendering interval.

[0106] In some embodiments of this application, the second duration can be the refresh interval of the screen of the electronic device.

[0107] Step 106b: The electronic device uses the image processing chip to take the bit sequence consisting of all the bits generated between the first and second time moments as the first bit sequence.

[0108] In some embodiments of this application, an electronic device can use an image processing chip to arrange all the bits generated between the first and second moments in chronological order of their generation times to form the first bit sequence described above.

[0109] In this way, the electronic device generates a bit every second time interval between the first and second time intervals through the image processing chip; the image processing chip uses the bit sequence composed of all the bits generated between the first and second time intervals as the first bit sequence, thus quickly and accurately obtaining the first bit sequence.

[0110] In some embodiments of this application, prior to step 106 above, the frame rate determination method provided in this application may further include the following steps 108 or 109:

[0111] Step 108: If the electronic device generates a generation frame at the generation time of the first bit bit through the image processing chip, then the bit value of the first bit bit is determined as the first bit value.

[0112] In some embodiments of this application, the first bit can be any bit in the first bit sequence.

[0113] Step 109: If the electronic device does not generate a frame at the time of generating the first bit, the bit value of the first bit is determined as the second bit value.

[0114] In some embodiments of this application, to ensure the frame rate displayed on the electronic device screen meets the screen refresh rate, thereby improving the smoothness of the displayed image, the electronic device can theoretically generate one generated frame every refresh interval using the image processing chip. However, if frame drops occur during rendering, or if the viewing angle rotates significantly, the electronic device may not be able to generate one generated frame every refresh interval. For example, the interval between the first and second moments is 16.6 ms, and the screen refresh interval is 8.3 ms. Therefore, if no frame drops occur during rendering, and the viewing angle rotation is small, the electronic device can generate two generated frames between the first and second moments using the image processing chip. However, if frame drops occur during rendering, or if the viewing angle rotates significantly, the electronic device may only generate one generated frame, or none at all, between the first and second moments using the image processing chip. However, regardless of the situation, the electronic device can accurately record the number and generation time of the generated frames generated by the electronic device based on the previous rendering frame and the current rendering frame between the first time and the second time by using the bits in the first bit sequence that have the value of the first bit. Then, after the electronic device reads the first bit sequence through the main control chip, it can accurately determine the generation timestamps of the M generated frames based on the bits in the first bit sequence that have the value of the first bit.

[0115] Thus, if the electronic device generates a frame at the time when the first bit is generated, the bit value of the first bit is determined as the first bit value; if the image processing chip does not generate a frame at the time when the first bit is generated, the bit value of the first bit is determined as the second bit value, so that the electronic device can accurately generate the number of frames and the generation time through the first bit sequence.

[0116] Step 107: The electronic device obtains the first bit sequence from the image processing chip through the main control chip, and determines the generation timestamps of M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame.

[0117] In some embodiments of this application, the step 107 above, "determining the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame," can be implemented through the following steps 107a and 107b:

[0118] Step 107a: The electronic device calculates i multiplied by the second duration through the main control chip to obtain the first product, and uses the sum of the first product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence.

[0119] Where i is used to indicate the i-th bit in the first bit sequence, and i∈[1,L].

[0120] In some embodiments of this application, the electronic device can calculate the timestamp corresponding to the i-th bit using the following formula via the main control chip:

[0121] Ti = T + t2*i; (1)

[0122] Where Ti represents the timestamp corresponding to the i-th bit, t2 represents the second duration, and T represents the rendering timestamp of the previous rendering frame.

[0123] Step 107b: The electronic device uses the main control chip to take the M timestamps corresponding to the M bits with the first bit value in the first bit sequence as the generation timestamps of the M generated frames.

[0124] In some embodiments of this application, the electronic device can use the main control chip to take the earliest timestamp among the M timestamps as the timestamp of the first generated frame among the M generated frames, take the next timestamp adjacent to the earliest timestamp among the M timestamps as the timestamp of the second generated frame among the M generated frames, and so on, and take the latest timestamp among the M timestamps as the timestamp of the last generated frame among the M generated frames.

[0125] In this way, the electronic device calculates the product of i and the second duration through the main control chip, and uses the sum of the product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence; the main control chip uses the M timestamps corresponding to the M bits with the first bit value in the first bit sequence as the generation timestamps of the M generated frames, thus accurately determining the generation timestamps of the M generated frames.

[0126] The following describes the frame rate determination method provided in this application embodiment, using a game scenario as an example and in conjunction with specific implementation methods.

[0127] In this embodiment, the electronic device can obtain the timestamp of the generated frame from the discrete graphics chip through the main control chip, and send the timestamp of the generated frame back to the timestamp cache in the DDR of the main control chip. This allows perfdog to read a timestamp set from the timestamp cache in a single read operation, including not only the timestamp of the rendering frame but also the timestamp of the generated frame. Therefore, perfdog can accurately measure the display frame rate of the electronic device screen based on the two timestamp sets read in two adjacent read operations. For example, combined with... Figure 5 As shown, the image processing method may include steps 51 to 503.

[0128] Step 501: After the GPU finishes drawing each frame, the main control chip writes the screen timestamp (Timestamp0) of that frame into the circular buffer.

[0129] For example, a frame drawn by the GPU is called a rendering frame.

[0130] For example, the on-screen timestamp is the rendering timestamp mentioned above.

[0131] For example, while the main control chip writes the on-screen timestamp (Timestamp 0) of this frame into the circular buffer, it can read a bit sequence from the discrete graphics chip. In this bit sequence, bits with a value of 0 represent that the current timestamp corresponding to that bit has no inserted frame, and bits with a value of 10 represent that the current timestamp corresponding to that bit has one inserted frame. For example, the timestamps corresponding to adjacent bits in the bit sequence are aligned to form a screen tearing effect (TE) signal, which is used to characterize the screen refresh rate. For example, for a 120Hz screen refresh rate, the electronic device triggers a TE signal every 8.3ms.

[0132] The length of this 0 / 1 bit sequence depends on how many discrete graphics interpolate frames are inserted between two adjacent rendered frames. For example, if there's a 16.6ms interval between two adjacent rendered frames and the screen refresh rate is 8.3ms, then there will be a frame generated by the discrete graphics chip's super-resolution interpolation at the 8.3ms position. Normally, the main control chip would read a 1 bit from the discrete graphics chip. However, considering that frame drops may occur during GPU rendering and discrete graphics chip frame generation, and that the two frames rendered by the GPU might be in a scene with rapid rotation in the game view, the discrete graphics chip might be unable to use the super-resolution interpolation algorithm to generate a new frame based on the rendered frame, potentially leading to interpolation failure. In this case, the CPU will read a 0 bit from the discrete graphics chip. For example... Figure 6AAs shown, when the discrete graphics chip interpolates frames twice the size of the rendered frames, if neither the rendered nor generated frames are dropped, the discrete graphics chip will insert a generated frame between every two adjacent rendered frames. That is, there is a 16.6ms interval between two adjacent rendered frames, and the screen refresh rate is 8.3ms. Therefore, at the 8.3ms interval, there will be a generated frame from the discrete graphics chip's super-resolution interpolation. For example... Figure 6B As shown, when the discrete graphics chip interpolates frames based on twice the rendering frame, if a rendering frame is dropped but the generated frame is not, the discrete graphics chip will generate a duplicate frame between the time position of the rendered frame with dropped frames and the preceding rendered frame adjacent to the rendered frame with dropped frames. For rendered frames without dropped frames, a generated frame is inserted between every two adjacent rendered frames. That is, the interval between two adjacent rendered frames without dropped frames is 16.6ms, and the screen refresh rate is 8.3ms. At the 8.3ms position between two rendered frames without dropped frames, there will be a generated frame image generated by the discrete graphics chip's super-resolution interpolation. For example... Figure 6C As shown, when the discrete graphics chip interpolates frames based on twice the rendering frame, if the rendering frame is delayed but the generated frame is not dropped, the discrete graphics chip will generate a duplicate frame between the delayed rendering frame and its adjacent previous rendering frame. A generated frame is inserted at the time position of the delayed rendering frame, and a generated frame is inserted between every two adjacent rendering frames in the non-delayed rendering frames. That is, the interval between two adjacent non-delayed rendering frames is 16.6ms, and the screen refresh rate is 8.3ms. At the 8.3ms position between two non-delayed rendering frames, there will be a generated frame image generated by the discrete graphics chip's super-resolution interpolation. For example... Figure 6D As shown, when the discrete graphics chip interpolates frames at twice the rendering frame rate, if the game screen undergoes a significant rotation, the discrete graphics chip may generate duplicate frames. Specifically, there's a 16.6ms interval between two adjacent rendering frames, and the screen refresh rate is 8.3ms. In the 8.3ms interval between two rendering frames where the game screen hasn't rotated, there will be a frame generated by the discrete graphics chip's super-resolution interpolation. Conversely, in the 8.3ms interval between two rendering frames where the game screen has rotated, the discrete graphics chip will generate a duplicate frame. For example... Figure 6E As shown, when the discrete graphics chip interpolates frames at twice the rendering frame rate, if the game screen undergoes significant rotation and rendering frames are dropped, the discrete graphics chip will also generate duplicate frames. Specifically, there is a 16.6ms interval between two adjacent rendering frames, and the screen refresh rate is 8.3ms. In the 8.3ms interval between two rendering frames without game screen rotation or frame drops, a frame generated by the discrete graphics chip's super-resolution interpolation will appear. Similarly, in the 8.3ms interval between two rendering frames with game screen rotation or frame drops, a duplicate frame will be generated by the discrete graphics chip. For example... Figure 6FAs shown, when the discrete graphics chip interpolates frames based on twice the number of rendered frames, if a rendered frame exceeds the frame limit, the discrete graphics chip will insert a generated frame between two adjacent rendered frames that do not exceed the frame limit. That is, if there is a 16.6ms interval between two adjacent rendered frames that do not exceed the frame limit, and the screen refresh rate is 8.3ms, the discrete graphics chip can generate a generated frame at the 8.3ms position between the two adjacent rendered frames that do not exceed the frame limit.

[0133] But from Figure 6A Of Figure 6F Based on various scenario reasoning, regardless of the scenario, the discrete graphics chip only needs to return a bit sequence to indicate the timestamp of the actual frame generation inserted by the discrete graphics chip.

[0134] Similarly, if the time interval between two adjacent rendering frames is 33.3ms and the screen refresh interval is 8.3ms, then the bits read by the main control chip from the discrete graphics chip may be 00 / 01 / 11 / 10. Then the timestamp sequence of the circular buffer filled with the screen timestamp is T0 (rendering frame) T1 (rendering frame) / T0 (rendering frame) T0+16.6ms (discrete graphics frame) T1 (rendering frame) / T0 (rendering frame) T0+8.3ms (discrete graphics frame) T0+16.6ms (discrete graphics frame) T1 (rendering frame) / T0 (rendering frame) T0+8.3ms (discrete graphics frame) T1 (rendering frame).

[0135] Step 502: After the main control chip obtains the bit sequence, it determines the generation timestamp of the generated frame based on the bit value of each bit in the bit sequence.

[0136] For example, the main control chip first iterates through the bit sequence. For bits with a value of 0, the current timestamp is calculated as `currentTimestamp = Timestamp0 + TE_interval(8.3ms)`. This timestamp is not used as the timestamp for generating the frame, nor does it need to be stored in the circular buffer. For bits with a value of 1, the current timestamp is calculated as `currentTimestamp = currentTimestamp(timestamp of the previous bit) + TE_interval(8.3ms)`. This timestamp is used as the timestamp for generating the frame and needs to be added to the circular buffer. This process is repeated until all bits have been iterated through and the circular buffer is full.

[0137] Step 503: The main control chip uses the perfdog tool to determine the display frame rate of the electronic device's screen based on the number of timestamps that differ between the two sets of timestamps read from the circular buffer in two adjacent read operations.

[0138] For example, the perfdog tool reads a set of timestamps from the circular buffer each time, which includes not only the timestamp information of the rendered frames but also the timestamp information of the generated frames produced by the discrete graphics chip. Therefore, the actual frame rate information can be easily calculated using this timestamp information.

[0139] For example, the main control chip can use the perfdog tool to take the ratio of the number of timestamps that differ between two sets of timestamps read from the circular buffer to the interval between two adjacent read operations as the display frame rate of the electronic device screen.

[0140] The frame rate determination method provided in this embodiment reads a very small number of bits of information from the discrete graphics card and calculates the timestamp information of each frame inserted by the discrete graphics card based on the timestamp information of each rendered frame. This allows users to obtain the true display frame rate information of the screen through evaluation tools, improving user perception and user experience, enhancing mobile phone evaluation results, and ultimately encouraging users to purchase the device.

[0141] It should be noted that each of the above method embodiments, or various possible implementations of each method embodiment, can be executed individually or in combination of any two or more. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0142] or,

[0143] It should be noted that the above-described method embodiments, or the various possible implementations of the method embodiments, can be executed individually, or, provided there are no contradictions, they can be combined with each other. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0144] The frame rate determination method provided in this application can be executed by a frame rate determination device. This application uses an example of a frame rate determination device executing the frame rate determination method to illustrate the frame rate determination device provided in this application.

[0145] Figure 7 This is a schematic diagram of a frame rate determination device 700 provided in an embodiment of this application. Figure 7 As shown, the frame rate determination device includes: a main control chip 701, which is used for:

[0146] Obtain the timestamp, which includes the rendering timestamp of the rendering frame and the generation timestamp of the generated frame, wherein the generated frame is generated based on the rendering frame;

[0147] The acquired timestamp is stored in the cache unit of the timestamp cache area;

[0148] If all cache units in the timestamp cache have cached timestamps, read all timestamps stored in the timestamp cache to obtain a timestamp set, and at each first time interval, read all timestamps stored in the timestamp cache to obtain a timestamp set.

[0149] The display frame rate of the electronic device's screen is determined based on two sets of timestamps read in two consecutive read operations.

[0150] In some embodiments of this application, the main control chip 701 is specifically used for:

[0151] Determine the number of timestamps that differ between two adjacent timestamp sets read;

[0152] The display frame rate is determined based on the quantity and the first duration.

[0153] In some embodiments of this application, the main control chip 701 is specifically used for:

[0154] When all cache units in the timestamp cache area have cached timestamps, each time the main control chip obtains a timestamp, it caches the obtained timestamp in the first cache unit among the multiple cache units in the timestamp cache area, and overwrites the timestamp originally cached in the first cache unit. The first cache unit is the cache unit with the earliest cached timestamp among the multiple cache units.

[0155] In some embodiments of this application, combined with Figure 7 ,like Figure 8 As shown, the device 700 further includes an image processing chip 702 connected to the main control chip 701, and the main control chip 701 is further used for:

[0156] Each time a rendering frame is rendered by the GPU, the current rendering frame is transmitted to the image processing chip.

[0157] The image processing chip 702 is used to generate M generated frames and a first bit sequence based on the current rendering frame transmitted by the main control chip and the previous rendering frame adjacent to the current rendering frame; the first bit sequence includes L bits, the L bits correspond to L time points within the rendering interval between the current rendering frame and the previous rendering frame, the number of bits in the first bit sequence with a bit value of the first bit value is M, and the M bits in the first bit sequence with a bit value of the first bit value correspond to the generation time of the M generated frames, where M is a positive integer or 0, and L is a positive integer greater than or equal to M;

[0158] The main control chip 701 is further configured to obtain the first bit sequence from the image processing chip 702, and determine the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame.

[0159] In some embodiments of this application, the main control chip 701 is specifically used for:

[0160] Calculate i multiplied by the second duration to obtain the first product, and use the sum of the first product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence, where i is used to indicate the i-th bit in the first bit sequence;

[0161] The M timestamps corresponding to the M bits in the first bit sequence that have the first bit value are used as the generation timestamps of the M generated frames.

[0162] Where i∈[1,L].

[0163] In some embodiments of this application, the image processing chip 702 is specifically used for:

[0164] Between the first and second time points, one bit is generated every second time interval;

[0165] The bit sequence consisting of all bits generated between the first and second time points is taken as the first bit sequence.

[0166] Wherein, the first moment is the moment indicated by the rendering timestamp of the previous rendering frame, and the second moment is the moment indicated by the rendering timestamp of the current rendering frame.

[0167] In some embodiments of this application, the image processing chip 702 is further configured to:

[0168] Based on the first bit sequence and the rendering timestamp of the previous rendering frame, before determining the generation timestamp of the M generated frames, if a generated frame is generated at the generation time of the first bit, then the bit value of the first bit is determined as the first bit value.

[0169] If a generation frame is not generated at the generation time of the first bit, then the bit value of the first bit is determined as the second bit value;

[0170] Wherein, the first bit is any bit in the first bit sequence.

[0171] In the frame rate determination device provided in this application embodiment, the main control chip acquires timestamps, including the rendering timestamp of the rendered frame and the generation timestamp of the generated frame, where the generated frame is generated based on the rendered frame. The main control chip stores the acquired timestamps in the cache unit of the timestamp cache area. When all cache units in the timestamp cache area have cached timestamps, the main control chip reads all the timestamps stored in the timestamp cache area to obtain a timestamp set, and at each first time interval, reads all the timestamps stored in the timestamp cache area to obtain a timestamp set. Based on the two timestamp sets read in two adjacent read operations, the main control chip determines the display frame rate of the electronic device's screen. Thus, since the timestamps stored in the timestamp cache area by the frame rate determination device through the main control chip include not only the rendering timestamp of the rendered frame but also the generation timestamp of the generated frame based on the rendered frame, the two timestamp sets read by the electronic device through the main control chip in two adjacent read operations necessarily include both the rendering timestamp of the rendered frame and the generation timestamp of the generated frame based on the rendered frame. Therefore, when electronic devices display rendering frames and generating frames, the display frame rate determined by the frame rate determination device based on the two timestamp sets read by the main control chip in two adjacent reading operations can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen.

[0172] The frame rate determination device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0173] The frame rate determination device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0174] The frame rate determination device provided in this application embodiment can achieve... Figure 1 To avoid repetition, the various processes implemented in the method embodiment shown in Figure 6 will not be described again here.

[0175] Optionally, such as Figure 9 As shown, this application embodiment also provides an electronic device 1000, including a processor 1001 and a memory 1002. The memory 1002 stores a program or instructions that can run on the processor 1001. When the program or instructions are executed by the processor 1001, they implement the various steps of the above-described frame rate determination method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0176] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0177] Figure 10 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0178] The electronic device 1000 includes, but is not limited to, the following components: radio frequency unit 1001, network module 1002, audio output unit 1003, input unit 1004, sensor 1005, display unit 1006, user input unit 1007, interface unit 1008, memory 1009, and processor 1010.

[0179] Those skilled in the art will understand that the electronic device 1000 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1010 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 10 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0180] The processor 1010 is used for:

[0181] The timestamp is obtained through the main control chip. The timestamp includes the rendering timestamp of the rendering frame and the generation timestamp of the generation frame. The generation frame is generated based on the rendering frame.

[0182] The main control chip stores the acquired timestamps into the cache unit of the timestamp cache area;

[0183] When all cache units in the timestamp cache area have cached timestamps, the main control chip reads all the timestamps stored in the timestamp cache area to obtain a timestamp set, and at each first time interval, reads all the timestamps stored in the timestamp cache area to obtain a timestamp set.

[0184] The display frame rate of the electronic device's screen is determined by the main control chip based on two sets of timestamps read from two adjacent read operations.

[0185] In some embodiments of this application, the processor 1010 is specifically used for:

[0186] The main control chip determines the number of timestamps that differ between two adjacent timestamp sets read.

[0187] The main control chip determines the display frame rate based on the quantity and the first duration.

[0188] In some embodiments of this application, the processor 1010 is specifically used for:

[0189] When all cache units in the timestamp cache area have cached timestamps, each time a timestamp is obtained by the main control chip, the obtained timestamp is cached in the first cache unit among the multiple cache units in the timestamp cache area, and the timestamp originally cached in the first cache unit is overwritten. The first cache unit is the cache unit with the earliest cached timestamp among the multiple cache units.

[0190] In some embodiments of this application, the processor 1010 is further configured to:

[0191] Each time a rendering frame is rendered by the GPU in the main control chip, the current rendering frame is transmitted to the image processing chip.

[0192] The image processing chip generates M generated frames and a first bit sequence based on the current rendering frame transmitted by the main control chip and the previous rendering frame adjacent to the current rendering frame. The first bit sequence includes L bits, which correspond to L time points within the rendering interval between the current rendering frame and the previous rendering frame. The number of bits in the first bit sequence with a bit value of the first bit value is M. The M bits in the first bit sequence with a bit value of the first bit value correspond to the generation time of the M generated frames. M is a positive integer or 0, and L is a positive integer greater than or equal to M.

[0193] The main control chip obtains the first bit sequence from the image processing chip, and determines the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame.

[0194] In some embodiments of this application, the processor 1010 is specifically used for:

[0195] The main control chip calculates i multiplied by the second duration to obtain the first product, and uses the sum of the first product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence, where i is used to indicate the i-th bit in the first bit sequence.

[0196] The main control chip uses the M timestamps corresponding to the M bits in the first bit sequence that have the first bit value as the generation timestamps of the M generated frames.

[0197] Where i∈[1,L].

[0198] In some embodiments of this application, the processor 1010 is specifically used for:

[0199] The image processing chip generates one bit every second time interval between the first and second time moments;

[0200] The image processing chip will use a bit sequence consisting of all bits generated between the first and second time points as the first bit sequence.

[0201] Wherein, the first moment is the moment indicated by the rendering timestamp of the previous rendering frame, and the second moment is the moment indicated by the rendering timestamp of the current rendering frame.

[0202] In some embodiments of this application, the processor 1010 is further configured to:

[0203] Based on the first bit sequence and the rendering timestamp of the previous rendering frame, before determining the generation timestamp of the M generated frames, if a generated frame is generated at the generation time of the first bit, then the bit value of the first bit is determined as the first bit value.

[0204] If a generation frame is not generated at the generation time of the first bit, then the bit value of the first bit is determined as the second bit value;

[0205] Wherein, the first bit is any bit in the first bit sequence.

[0206] In the electronic device provided in this application embodiment, a timestamp is obtained through a main control chip. The timestamp includes the rendering timestamp of the rendered frame and the generation timestamp of the generated frame, where the generated frame is generated based on the rendered frame. The main control chip stores the obtained timestamps into a cache unit of the timestamp cache area. When all cache units in the timestamp cache area have timestamps cached, the main control chip reads all timestamps stored in the timestamp cache area to obtain a timestamp set. This process is repeated every first time interval to obtain another timestamp set. The main control chip determines the display frame rate of the electronic device's screen based on the two timestamp sets read in two adjacent read operations. Thus, since the timestamps stored in the timestamp cache area by the main control chip include not only the rendering timestamp of the rendered frame but also the generation timestamp of the generated frame based on the rendered frame, the two timestamp sets read by the main control chip in two adjacent read operations necessarily include both the rendering timestamp of the rendered frame and the generation timestamp of the generated frame based on the rendered frame. Therefore, when displaying rendered frames and generated frames, the display frame rate determined by the main control chip based on two sets of timestamps read in two adjacent read operations can more accurately reflect the display frame rate of the electronic device's screen, thereby improving the accuracy of the display frame rate of the electronic device's screen.

[0207] It should be understood that, in this embodiment, the input unit 1004 may include a graphics processing unit (GPU) 10041 and a microphone 10042. The GPU 10041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1006 may include a display panel 10061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 1007 includes at least one of a touch panel 10071 and other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here.

[0208] The memory 1009 can be used to store software programs and various data. The memory 1009 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1009 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1009 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0209] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor 1010.

[0210] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described frame rate determination method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0211] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0212] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described frame rate determination method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0213] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0214] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the frame rate determination method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0215] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0216] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0217] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A frame rate determination method, characterized in that, Applied to an electronic device, the electronic device including a main control chip, the method includes: The timestamp is obtained through the main control chip. The timestamp includes the rendering timestamp of the rendering frame and the generation timestamp of the generated frame. The generated frame is generated based on the rendering frame. The main control chip stores the acquired timestamp into the cache unit of the timestamp cache area; When all cache units in the timestamp cache have cached timestamps, the main control chip reads all the timestamps stored in the timestamp cache to obtain a timestamp set, and at each first time interval, reads all the timestamps stored in the timestamp cache to obtain a timestamp set. The main control chip determines the display frame rate of the electronic device's screen based on two sets of timestamps read from two adjacent read operations.

2. The method according to claim 1, characterized in that, Determining the display frame rate of the electronic device's screen based on two sets of timestamps read consecutively includes: The main control chip determines the number of timestamps that differ between two adjacent timestamp sets read. The main control chip determines the display frame rate based on the quantity and the first duration.

3. The method according to claim 1, characterized in that, The cache unit that stores the timestamp obtained by the main control chip into the timestamp cache area includes: When all cache units in the timestamp cache area have cached timestamps, each time a timestamp is obtained by the main control chip, the obtained timestamp is cached in the first cache unit among the multiple cache units in the timestamp cache area, and the timestamp originally cached in the first cache unit is overwritten. The first cache unit is the cache unit with the earliest cached timestamp among the multiple cache units in the timestamp cache area.

4. The method according to claim 1, characterized in that, The electronic device further includes an image processing chip connected to the main control chip, and the method further includes: Each time the main control chip renders a rendering frame, the current rendering frame is transmitted to the image processing chip. The image processing chip generates M generated frames and a first bit sequence based on the current rendering frame transmitted by the main control chip and the previous rendering frame adjacent to the current rendering frame. The first bit sequence includes L bits, which correspond to L time points within the rendering interval between the current rendering frame and the previous rendering frame. The number of bits in the first bit sequence with the first bit value is M. The M bits in the first bit sequence with the first bit value correspond to the generation time of the M generated frames. M is a positive integer or 0, and L is a positive integer greater than or equal to M. The main control chip obtains the first bit sequence from the image processing chip, and determines the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame.

5. The method according to claim 4, characterized in that, Determining the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendered frame includes: Calculate i multiplied by the second duration to obtain the first product, and use the sum of the first product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence, where i is used to indicate the i-th bit in the first bit sequence; The M timestamps corresponding to the M bits in the first bit sequence that have the first bit value are used as the generation timestamps of the M generated frames. Where i∈[1,L].

6. The method according to claim 4, characterized in that, The generation of the first bit sequence includes: Between the first and second time points, one bit is generated every second time interval; The bit sequence consisting of all bits generated between the first and second time points is taken as the first bit sequence. Wherein, the first moment is the moment indicated by the rendering timestamp of the previous rendering frame, and the second moment is the moment indicated by the rendering timestamp of the current rendering frame.

7. A frame rate determination device, characterized in that, The frame rate determination device includes a main control chip, which is used for: Obtain the timestamp, which includes the rendering timestamp of the rendering frame and the generation timestamp of the generated frame, wherein the generated frame is generated based on the rendering frame; The obtained timestamp is stored in the cache unit of the timestamp cache area; If all cache units in the timestamp cache have cached timestamps, read all timestamps stored in the timestamp cache to obtain a timestamp set, and at each first time interval, read all timestamps stored in the timestamp cache to obtain a timestamp set. The display frame rate of the electronic device's screen is determined based on two sets of timestamps read in two consecutive read operations.

8. The apparatus according to claim 7, characterized in that, The main control chip is specifically used for: Determine the number of timestamps that differ between two consecutive timestamp sets read; The display frame rate is determined based on the quantity and the first duration.

9. The apparatus according to claim 7, characterized in that, The main control chip is specifically used for: When all cache units in the timestamp cache area have cached timestamps, each time a timestamp is obtained, the obtained timestamp is cached in the first cache unit among the multiple cache units in the timestamp cache area, and the timestamp originally cached in the first cache unit is overwritten. The first cache unit is the cache unit with the earliest cached timestamp among the multiple cache units.

10. The apparatus according to claim 7, characterized in that, The device further includes an image processing chip connected to the main control chip, the main control chip being further used for: Each time a rendering frame is rendered by the GPU, the current rendering frame is transmitted to the image processing chip. The image processing chip is used to generate M generated frames and a first bit sequence based on the current rendering frame transmitted by the main control chip and the previous rendering frame adjacent to the current rendering frame; the first bit sequence includes L bits, the L bits correspond to L time points within the rendering interval between the current rendering frame and the previous rendering frame, the number of bits in the first bit sequence with a bit value of the first bit value is M, and the M bits in the first bit sequence with a bit value of the first bit value correspond to the generation time of the M generated frames, where M is a positive integer or 0, and L is a positive integer greater than or equal to M; The main control chip is further configured to obtain the first bit sequence from the image processing chip, and determine the generation timestamps of the M generated frames based on the first bit sequence and the rendering timestamp of the previous rendering frame.

11. The apparatus according to claim 10, characterized in that, The main control chip is specifically used for: Calculate i multiplied by the second duration to obtain the first product, and use the sum of the first product and the rendering timestamp of the previous rendering frame as the timestamp corresponding to the i-th bit in the first bit sequence, where i is used to indicate the i-th bit in the first bit sequence; The M timestamps corresponding to the M bits in the first bit sequence that have the first bit value are used as the generation timestamps of the M generated frames. Where i∈[1,L].

12. The apparatus according to claim 10, characterized in that, The image processing chip is specifically used for: Between the first and second time points, one bit is generated every second time interval; The bit sequence consisting of all bits generated between the first and second time points is taken as the first bit sequence. Wherein, the first moment is the moment indicated by the rendering timestamp of the previous rendering frame, and the second moment is the moment indicated by the rendering timestamp of the current rendering frame.

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