Semiconductor device

Abstract

According to an embodiment, a semiconductor device includes a substrate and a chip stack including a plurality of chips stacked on the substrate. The plurality of chips includes a first memory chip, a second memory chip different in kind from the first memory chip, and a first bridge chip electrically connecting the first memory chip and the second memory chip.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a semiconductor device. Background Technology

[0002] When multiple memory chips are mounted on a packaging substrate, the question arises as to what form these memory chips should be mounted. Summary of the Invention

[0003] According to one embodiment, a semiconductor device includes a substrate and a chip stack comprising a plurality of chips stacked on the substrate. The plurality of chips includes a first memory chip, a second memory chip of a different type from the first memory chip, and a first bridge chip electrically connecting the first memory chip and the second memory chip. Attached Figure Description

[0004] Figure 1 This is a block diagram illustrating the configuration of the information processing apparatus according to the first embodiment.

[0005] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0006] Figure 3 (a) and (b) are cross-sectional views showing two examples of the structure of the semiconductor device according to the first embodiment.

[0007] Figure 4 (a), (b), (c) and (d) are cross-sectional views showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0008] Figure 5 (a), (b), (c) and (d) are cross-sectional views showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0009] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a cross-sectional view showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0010] Figure 11 (a), (b), and (c) are cross-sectional views illustrating a second example of the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 12 (a), (b), and (c) are cross-sectional views illustrating a second example of the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a cross-sectional view showing a second example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 19 This is a block diagram illustrating the configuration of the information processing apparatus according to the second embodiment.

[0014] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0015] Figure 21 This is a block diagram illustrating the configuration of the information processing apparatus according to the third embodiment.

[0016] Figure 22 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. Detailed Implementation

[0017] The embodiments of this disclosure are described below with reference to the accompanying drawings. Figures 1 to 22 In Chinese, the same symbol is used to mark the same components, and repeated descriptions are omitted.

[0018] (First Embodiment)

[0019] Figure 1 This is a block diagram illustrating the configuration of the information processing apparatus according to the first embodiment.

[0020] The information processing device of this embodiment includes a processor 1, a memory 2, a storage device 3, a bus 4, and a bus 5. The information processing device of this embodiment is, for example, a computer such as a smartphone.

[0021] Processor 1 performs various information processing tasks. Processor 1 is, for example, a CPU (Central Processing Unit). Memory 2 temporarily stores various data. Memory 2 is, for example, RAM (Random Access Memory). Storage device 3 stores various data. Details of storage device 3 will be described later.

[0022] Bus 4 is used for communication between processor 1 and memory 2. Bus 5 is used for communication between processor 1 and memory device 3. Bus 4 and bus 5 can be the same bus or different buses.

[0023] Storage device 3 includes memory chip 11, memory chip 12, bridge chip 13, and IF (interface) chip 14. Memory chip 11 is an example of a first memory chip. Memory chip 12 is an example of a second memory chip. Bridge chip 13 is an example of a first bridge chip.

[0024] Memory chip 11 and memory chip 12 are different types. For example, memory chip 11 and memory chip 12 differ in at least one of their data storage method, memory capacity, and access speed. Memory chip 11 is, for example, a non-volatile memory such as flash memory. Memory chip 12 is, for example, a non-volatile memory such as a storage device memory. In this case, since memory chips 11 and 12 both store data non-volatilely, their data storage methods are the same. Furthermore, since memory chip 11 has a large capacity and memory chip 12 has a small capacity, their memory capacities are different. Additionally, since memory chip 11 has a low access speed and memory chip 12 has a high access speed, their access speeds are different. For example, memory chips 11 and 12 each have a memory cell array containing multiple memory cells and a circuit (e.g., CMOS (Complementary Metal Oxide Semiconductor) circuit containing multiple transistors controlling the multiple memory cells).

[0025] A bridge chip 13 is disposed between memory chips 11 and 12 to electrically connect memory chips 11 and 12. The bridge chip 13 has the function of transferring data between memory chips of different types. In this embodiment, because memory chips 11 and 12 are of different types, the bridge chip 13 is disposed between them. The bridge chip 13 transfers data from one of memory chips 11 and 12 to the other.

[0026] The IF chip 14 is electrically connected to memory chips 11 and 12, bridge chip 13, and bus 5 (processor 1). The IF chip 14 functions as an interface between memory chips 11, 12, and 13 and bus 5 (processor 1). For example, the IF chip 14 receives signals from processor 1 and accesses memory chips 11, 12, or 13 based on these signals. As an example, the IF chip 14 sends an instruction to bridge chip 13, which then transfers data from memory chip 12 to memory chip 11 based on the instruction. Thus, the data can be transferred from memory chip 12 to memory chip 11 without temporarily storing it in memory 2. An example of such an instruction is a write instruction that writes data to memory chip 11.

[0027] For example, when processor 1 performs information processing related to AI (Artificial Intelligence), the storage device 3 of this embodiment is used. According to this embodiment, information processing can be performed at high speed by transferring data between memory chips 11 and 12 without passing through memory 2. As an example of such information processing, information processing related to AI reasoning is given.

[0028] In this embodiment, the storage device 3 is a semiconductor device having a semiconductor package P. The memory chip 11, memory chip 12, bridge chip 13, and IF chip 14 of this embodiment are mounted on a packaging substrate described later, and become part of the semiconductor package P.

[0029] The storage device 3 also includes, for example, a first electrode (through electrode 21), a second electrode (through electrode 22), a third electrode (through electrode 23), a fourth electrode (through electrode 24), and a fifth electrode (through electrode 25). Furthermore, the IF chip 14 includes, for example, a first pad (metal pad 31), a second pad (metal pad 32), a third pad (metal pad 33), and a fourth pad (metal pad 34). Through electrodes 21-25 or metal pads 31-34 also become part of the semiconductor package P.

[0030] Through electrode 21 is configured to electrically connect memory chip 11 and IF chip 14. Through electrode 22 is configured to electrically connect memory chip 12 and IF chip 14. Through electrode 23 is configured to electrically connect bridge chip 13 and IF chip 14. IF chip 14 can access memory chip 11 using through electrode 21, access memory chip 12 using through electrode 22, and access bridge chip 13 using through electrode 23.

[0031] Through electrode 24 is configured to electrically connect memory chip 11 to bridge chip 13. Through electrode 25 is configured to electrically connect memory chip 12 to bridge chip 13. Bridge chip 13 can use through electrodes 24 and 25 to transfer data from one of memory chips 11 and 12 to the other of memory chips 11 and 12.

[0032] Metal pad 31 is electrically connected to through electrode 21. Metal pad 32 is electrically connected to through electrode 22. Metal pad 33 is electrically connected to through electrode 23. IF chip 14 can access memory chip 11 using metal pad 31, access memory chip 12 using metal pad 32, and access bridge chip 13 using metal pad 33.

[0033] Metal pad 34 is electrically connected to bus 5. IF chip 14 can use metal pad 34 to communicate with processor 1 or memory 2.

[0034] According to this embodiment, by employing a bridge chip 13 or an IF chip 14, memory chips 11 and 12 of different types can be housed within the same semiconductor package P. This reduces the total area of ​​the storage device 3 on the motherboard of the information processing device of this embodiment, enabling miniaturization of the information processing device. Therefore, the storage device 3 of this embodiment is suitable, for example, for mobile devices such as smartphones.

[0035] The following describes further details of the storage device 3 according to this embodiment. In the following description, the storage device 3 according to this embodiment will also be referred to as "semiconductor device 3".

[0036] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device 3 according to the first embodiment.

[0037] like Figure 2 As shown, the semiconductor device 3 includes multiple memory chips 11 and multiple memory chips 12. Figure 2 Each memory chip 11 shown corresponds to Figure 1 The memory chip 11 shown has the same characteristics as... Figure 1 The memory chip 11 shown has the same structure or function. Similarly, Figure 2 The memory chips 12 shown correspond to Figure 1 The memory chip 12 shown has the same characteristics as... Figure 1 The memory chip 12 shown has the same structure or function.

[0038] As described above, the semiconductor device 3 further includes a bridge chip 13, an IF chip 14, through electrodes 21-25, and metal pads 31-34. The semiconductor device 3 also includes multiple through electrodes 26, a substrate 41, multiple bumps 42, multiple bumps 43, multiple external connection terminals 44, multiple wirings 51, a resin layer 52, and a resin layer 53. Each through electrode 26 is an example of a sixth electrode.

[0039] Substrate 41 is, for example, a packaging substrate (wiring substrate). Figure 2 The X and Y directions, which are parallel to and perpendicular to the upper and lower surfaces of the substrate 41, and the Z direction, which is perpendicular to the upper and lower surfaces of the substrate 41, are shown. The X, Y, and Z directions intersect each other.

[0040] The substrate 41 includes an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c. Figure 2 The upper surface S1 and lower surface S2 of the insulating substrate 41a are shown. A wiring layer 41b and a resin layer 41c are sequentially formed on the upper surface S1 and lower surface S2 of the insulating substrate 41a, and are also sequentially formed within through-holes disposed in the insulating substrate 41a. The wiring layer 41b includes a plurality of wirings.

[0041] The semiconductor device 3 also includes a chip stack C mounted on a substrate 41. The chip stack C includes a plurality of memory chips 11, a plurality of memory chips 12, and a bridge chip 13 stacked in the Z direction. More specifically, the chip stack C includes a plurality of memory chips 12 stacked on the substrate 41, a bridge chip 13 stacked on the plurality of memory chips 12, and a plurality of memory chips 11 stacked on the bridge chip 13. Therefore, the bridge chip 13 is disposed between the plurality of memory chips 11 and the plurality of memory chips 12. On the other hand, the IF chip 14 is disposed between the substrate 41 and the chip stack C and mounted on the chip stack C.

[0042] Each bump 42 is disposed on the upper surface of the IF chip 14 and electrically connected to the IF chip 14. Each bump 43 is disposed on the upper surface of the substrate 41 and electrically connected to the wiring layer 41b. Each external connection terminal 44 is disposed on the lower surface of the substrate 41 and electrically connected to the wiring layer 41b. The IF chip 14 is electrically connected to the bus 5 through multiple external connection terminals 44. Figure 1 It functions as an interface between multiple chips within the chip stack C and multiple external connection terminals 44 under the substrate 41.

[0043] In addition, each external connection terminal 44 in this embodiment is Figure 2 The cross-section shown is not connected to wiring layer 41b, but is connected to... Figure 2The different cross-sections shown are connected to the wiring layer 41b. As a result, each external connection terminal 44 in this embodiment is electrically connected to the wiring layer 41b. Each external connection terminal 44 is, for example, a solder ball.

[0044] Each wiring 51 is located under the chip stack C, between the substrate 41 and the chip stack C. Figure 2 The shape of each wiring 51 is shown in thick lines. Each wiring 51 is disposed on a corresponding bump 43 and electrically connected to a corresponding external connection terminal 44 via the bump 43 and wiring layer 41b. Each wiring 51 is electrically connected to the chip stack C, the IF chip 14, and the corresponding external connection terminal 44. Figure 2 In the chip stack C, multiple bumps 43 and multiple wirings 51 are disposed above the substrate 41.

[0045] Alternatively, each wiring 51 can be disposed on the outside of the chip stack C or inside the chip stack C. In the former case, each wiring 51 can also be mounted on the lower surface of the bottommost memory chip 12 of the chip stack C. In the latter case, each wiring 51 can also be part of a multilayer wiring structure within the bottommost memory chip 12 of the chip stack C.

[0046] Resin layer 52 is formed to cover the surface of the chip stack C. Resin layer 53 is formed to cover the surface of resin layer 52. A portion of resin layers 52 and 53 is formed between the substrate 41 and the chip stack C. In addition, a portion of resin layer 53 is formed around the IF chip 14 or the bumps 42 and 43.

[0047] The chip stack C includes through electrodes 21 to 26. Each of the through electrodes 21 to 26 penetrates one or more chips within the chip stack C in the Z direction. Through electrode 21 is configured to electrically connect multiple memory chips 11 to an IF chip 14. Through electrode 22 is configured to electrically connect multiple memory chips 12 to an IF chip 14. Through electrode 23 is configured to electrically connect a bridge chip 13 to an IF chip 14. Through electrode 24 is configured to electrically connect multiple memory chips 11 to a bridge chip 13. Through electrode 25 is configured to electrically connect multiple memory chips 12 to a bridge chip 13. Each through electrode 26 is configured to electrically connect a corresponding external connection terminal 44 to multiple memory chips 11, multiple memory chips 12, and a bridge chip 13. Each through electrode 26 is disposed on a corresponding wiring 51 and electrically connected to an IF chip 14 or an external connection terminal 44 via the wiring 51.

[0048] The IF chip 14 has metal pads 31-34 on its upper surface. Metal pad 31 is electrically connected to the through electrode 21 via bump 42. Metal pad 32 is electrically connected to the through electrode 22 via bump 42. Metal pad 33 is electrically connected to the through electrode 23 via bump 42. Figure 2 The IF chip 14 shown includes multiple metal pads 34. Each metal pad 34 is electrically connected to a corresponding wiring 51 via a bump 42, thereby being electrically connected to a corresponding through electrode 26 or a corresponding external connection terminal 44.

[0049] As described above, in this embodiment, memory chips 11 and 12 are mounted on substrate 41 in the form of a chip stack C. This reduces the area of ​​the semiconductor device 3 when viewed from above, enabling miniaturization of the semiconductor device 3.

[0050] Furthermore, in this embodiment, the bridging chip 13 is disposed between multiple memory chips 11 and multiple memory chips 12 as part of the chip stack C. Therefore, data transfer between memory chips 11 and 12 of different types can be performed within the semiconductor package P via the bridging chip 13, and the increase in area of ​​the semiconductor device 3 due to the bridging chip 13 can be suppressed.

[0051] Figure 3 These are cross-sectional views showing two examples of the structure of the semiconductor device 3 according to the first embodiment.

[0052] Figure 3 (a) shows a first example of the semiconductor device 3 according to this embodiment. In the first example, the through electrode 21 includes a plurality of electrodes 61, a plurality of pads 62, and a plurality of bumps 63. Each electrode 61 penetrates one chip within the chip stack C (in Figure 3 (a) shows the memory chip 11. Each pad 62 is disposed on the upper or lower surface of one electrode 61. Each bump 63 is disposed between the pad 62 disposed on the upper surface of one electrode 61 and the pad 62 disposed on the lower surface of another electrode 61, electrically connecting the preceding pad 62 to the following pad 62. The plurality of electrodes 61 and the plurality of bumps 63 are alternately disposed in the Z direction. In addition, in the first example, the through electrodes 22 to 26 also have the same structure as the through electrode 21.

[0053] Figure 3 (b) shows a second example of the semiconductor device 3 of this embodiment. In the second example, the through electrode 21 includes a plurality of electrodes 61 and a plurality of pads 62. Each electrode 61 penetrates one chip within the chip stack C (in Figure 3(b) shows the memory chip 11. Each pad 62 is disposed between the upper surface of one electrode 61 and the lower surface of another electrode 61, electrically connecting the former electrode 61 to the latter electrode 61. In addition, in the second example, the through electrodes 22 to 26 also have the same structure as the through electrode 21.

[0054] in addition, Figure 2 The through electrodes 21 to 26 shown have the same structure as the through electrode 21 in the second example, but they can also be replaced by having the same structure as the through electrode 21 in the first example.

[0055] [Example 1]

[0056] Figures 4 to 10 This is a cross-sectional view showing a first example of a method for manufacturing the semiconductor device 3 according to the first embodiment. Figures 4 to 10 In China, the following is adopted Figure 3 The construction of example 1 is shown in (a) in the figure.

[0057] Figure 4 (a) in Figure 4 (d) shows the process of forming the uppermost memory chip 11 of the chip stack C.

[0058] First, a portion of pads 62 and bumps 63 with through electrodes 21-26 are formed on the memory chip 11. Figure 4 (a) in the middle. Figure 4 In (a), pads 62 and bumps 63 that pass through electrodes 21, 24, and 26 are formed on memory chip 11.

[0059] Next, the memory chip 11 is temporarily attached to the support substrate 71. Figure 4 (b)). At this time, the memory chip 11 is placed on the support substrate 71 with a dielectric resin layer 72. Additionally, Figure 4 The lower surface of the memory chip 11 shown in (b) corresponds to Figure 4 The upper surface of memory chip 11 shown in (a) is shown in the figure.

[0060] Next, the memory chip 11 is thin-film coated. Figure 4 (c) in the middle. As a result, Figure 4 The thickness of the memory chip 11 shown in (c) is less than Figure 4 The thickness of memory chip 11 shown in (b) is shown.

[0061] Next, the memory chip 11 is peeled off from the support substrate 71 and placed on another support substrate 73. Figure 4 (d) in the middle. Additionally, Figure 4 The upper surface of the memory chip 11 shown in (d) corresponds to Figure 4 The lower surface of memory chip 11 shown in (c) is shown.

[0062] Figure 5 (a) in Figure 5 (d) in the diagram shows the process of forming the second memory chip 11 from the top layer of the chip stack C.

[0063] First, a portion of pads 62 and bumps 63 with through electrodes 21-26 are formed on the memory chip 11. Figure 5 (a) in the middle. Figure 5 In (a), pads 62 and bumps 63 that pass through electrodes 21, 24, and 26 are formed on memory chip 11.

[0064] Next, the memory chip 11 is temporarily attached to the support substrate 74. Figure 5 (b)). At this time, the memory chip 11 is placed on the support substrate 74 with a dielectric resin layer 75. Additionally, Figure 5 The lower surface of the memory chip 11 shown in (b) corresponds to Figure 5 The upper surface of memory chip 11 shown in (a) is shown in the figure.

[0065] Next, the memory chip 11 is thin-film coated. Figure 5 (c) in the middle. As a result, Figure 5 The thickness of the memory chip 11 shown in (c) is less than Figure 5 The thickness of memory chip 11 shown in (b) is shown.

[0066] Next, electrodes 61 and pads 62 with through electrodes 21-26 are formed within and on the memory chip 11. Figure 5 (c) in the middle. Figure 5 In (c), electrode 61 and pad 62, which pass through electrodes 21, 24, and 26, are formed within and on memory chip 11. Figure 5 In (c) of the figure, each electrode 61 is further formed on a corresponding pad 62. Additionally, in this embodiment, in... Figure 5 In process (a), a portion of each electrode 61 is formed. Figure 5 The remaining portion of each electrode 61 is formed in process (c) of the process.

[0067] Next, the memory chip 11 is peeled off from the support substrate 74, and the peeled memory chip 11 is stacked onto the memory chip 11 placed on the support substrate 73. Figure 5 (d)). As a result, two memory chips 11 are stacked on the support substrate 73. Additionally, Figure 5The upper surface of the memory chip 11 shown in (d) corresponds to Figure 5 The lower surface of memory chip 11 is shown in (c). Figure 5 In (d), the pad 62 of the upper memory chip 11 is placed on the pad 63 of the lower memory chip 11.

[0068] In this embodiment, the other chips in the chip stack C (memory chip 11, memory chip 12, and bridge chip 13) are also connected via... Figure 5 (a) in Figure 5 The process in step (d) is performed. As a result, a chip stack C is formed on the support substrate 74, and through electrodes 21-26 are formed within the chip stack C. Figure 6 ). Figure 6 The through electrodes 21-26 shown have Figure 3 The construction of example 1 is shown in (a) in the figure.

[0069] Next, multiple wirings 51 are formed on the chip stack C. Figure 7 Each wiring 51 is configured on the pad 62 of the corresponding through electrode 26.

[0070] Next, multiple bumps 42 are formed on the metal pads 31-34 of the IF chip 14, and then the IF chip 14 is placed on the chip stack C. Figure 7 The bumps 42 of the metal pad 31 are disposed on the pad 62 of the through electrode 21. The bumps 42 of the metal pad 32 are disposed on the pad 62 of the through electrode 22. The bumps 42 of the metal pad 33 are disposed on the pad 62 of the through electrode 23. The bumps 42 of each metal pad 34 are disposed on the corresponding wiring 51.

[0071] Next, a substrate 41 comprising an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c is prepared, and a plurality of bumps 43 are formed on the wiring layer 41b of the substrate 41. Figure 8 Next, the chip stack C is peeled off from the support substrate 73 and placed on the multiple bumps 43. Figure 8 ).in addition, Figure 8 The upper surface of the chip stack C shown corresponds to Figure 7 The lower surface of the chip stack C shown. Figure 8 In the middle, each wiring 51 is placed on the corresponding bump 43.

[0072] Next, a resin layer 54 is formed on the surface of the chip stack C. Figure 9 A portion of the resin layer 54 is embedded between the substrate 41 and the chip stack C. Figure 9 In this process, a resin layer 54 is formed to replace the resin layers 52 and 53.

[0073] Next, a plurality of external connection terminals 44 are formed on the lower surface of the substrate 41. Figure 10 Each external connection terminal 44 is electrically connected to the wiring layer 41b of the substrate 41.

[0074] Thus, the semiconductor device 3 of this embodiment, having a semiconductor package P, is manufactured.

[0075] [Example 2]

[0076] Figures 11-18 This is a cross-sectional view showing a second example of a method for manufacturing the semiconductor device 3 according to the first embodiment. Figures 11-18 In China, the following is adopted Figure 3 The construction of example 2 shown in (b) is shown in the figure.

[0077] Figure 11 (a) in Figure 11 (c) shows the process of forming the memory chip 12, the bottom layer of the chip stack C.

[0078] First, electrodes 61 and pads 62 with through electrodes 21-26 are formed within and on the memory chip 12. Figure 11 (a) in the middle. Figure 11 In (a), electrode 61, which connects electrodes 21, 22, 23, and 26, is formed within memory chip 12, and pad 62, which connects electrodes 21, 22, and 23, is formed on memory chip 12. Furthermore, Figure 11 The electrodes 61 shown in (a) are formed in a manner that do not penetrate the memory chip 12.

[0079] Next, the memory chip 12 is placed on the support substrate 81. Figure 11 (b) in the text. Additionally, Figure 11 The lower surface of the memory chip 12 shown in (b) corresponds to Figure 11 The upper surface of memory chip 12 shown in (a) is shown in the figure.

[0080] Figure 11 (b) shows a plurality of wirings 51 disposed under memory chip 12. Figure 11 In (b) of the diagram, the electrode 61 of each through electrode 26 is disposed on the corresponding wiring 51. Each wiring 51 can be Figure 11 In process (a), it is disposed on the upper surface of memory chip 12, or it can be disposed on the upper surface of memory chip 12. Figure 11 In process (b), it is disposed on the lower surface of memory chip 12.

[0081] Next, a portion of a resin layer 52 is formed on the surface of the memory chip 12, thereby thinning the resin layer 52 and the memory chip 12. Figure 11(c)). As a result, the upper surface of the memory chip 12 is exposed from the resin layer 52. Figure 11 The thickness of the memory chip 11 shown in (c) is less than Figure 11 The thickness of the memory chip 11 is shown in (b). Furthermore, the upper surface of each electrode 61 protrudes from the memory chip 12, and each electrode 61 penetrates the memory chip 12.

[0082] Figure 12 (a) in Figure 12 (c) shows the process of forming the second memory chip 12 from the bottom layer of the chip stack C.

[0083] First, electrodes 61 and pads 62 with through electrodes 21-26 are formed within and on the memory chip 12. Figure 12 (a) in the middle. Figure 12 In (a), electrode 61, which passes through electrodes 21, 22, 23, 25, and 26, is formed within the memory chip 12, and pad 62, which passes through electrodes 21, 22, 23, 25, and 26, is formed on the memory chip 12. Furthermore, Figure 12 The electrodes 61 shown in (a) are formed in a manner that do not penetrate the memory chip 12.

[0084] Next, Figure 12 In step (a), the memory chip 12 prepared in the process is laminated onto the memory chip 12 placed on the support substrate 81. Figure 12 (b) in the text. Additionally, Figure 12 The lower surface of the upper memory chip 12 shown in (b) corresponds to Figure 12 The upper surface of memory chip 12 is shown in (a) of the diagram. Figure 12 In (b), the pads 62 of the through electrodes 21, 22, 23, 26 of the memory chip 11 on the electrodes 61 of the through electrodes 21, 22, 23, 26 on the lower side are mounted.

[0085] Next, a portion of a resin layer 52 is formed on the surface of the upper memory chip 12, and the resin layer 52 and the upper memory chip 12 are thinned. Figure 12 (c)). As a result, the upper surface of the memory chip 12 on the upper side is exposed from the resin layer 52. Figure 12 The thickness of the memory chip 11 on the upper side shown in (c) is less than Figure 12 The thickness of the upper memory chip 11 is shown in (b). Furthermore, the upper surfaces of each electrode 61 of the upper memory chip 12 are exposed from the upper memory chip 12, and each electrode 61 of the upper memory chip 12 penetrates the upper memory chip 12.

[0086] In this embodiment, the other chips in the chip stack C (memory chip 11, memory chip 12, and bridge chip 13) are also connected via... Figure 12 (a) in Figure 12 The process in step (c) is performed. As a result, a chip stack C is formed on the support substrate 81, and through electrodes 21-26 are formed within the chip stack C. Figure 13 ). Figure 13 The through electrodes 21-26 shown have Figure 3 The construction of example 2 shown in (b) is also mentioned. Figure 13 In the process, a portion of the resin layer 52 is also formed on the upper surface of the memory chip 11, the uppermost layer of the chip stack C.

[0087] Next, the chip stack C, together with the wiring 51 or the resin layer 52, is peeled off from the support substrate 81, and the chip stack C, etc., is placed on another support substrate 82. Figure 14 ).in addition, Figure 14 The upper surface of the chip stack C shown corresponds to Figure 13 The lower surface of the chip stack C shown.

[0088] Next, multiple bumps 42 are formed on the metal pads 31-34 of the IF chip 14, and then the IF chip 14 is placed on the chip stack C. Figure 15 The bumps 42 of the metal pad 31 are disposed on the pad 62 of the through electrode 21. The bumps 42 of the metal pad 32 are disposed on the pad 62 of the through electrode 22. The bumps 42 of the metal pad 33 are disposed on the pad 62 of the through electrode 23. The bumps 42 of each metal pad 34 are disposed on the corresponding wiring 51.

[0089] Next, a substrate 41 comprising an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c is prepared, and a plurality of bumps 43 are formed on the wiring layer 41b of the substrate 41. Figure 16 Next, the chip stack C is peeled off from the support substrate 82 and placed on the multiple bumps 43. Figure 16 ).in addition, Figure 16 The upper surface of the chip stack C shown corresponds to Figure 15 The lower surface of the chip stack C shown. Figure 16 In the middle, each wiring 51 is placed on the corresponding bump 43.

[0090] Next, a resin layer 53 is formed on the surface of the resin layer 52. Figure 17 A portion of the resin layer 53 is embedded between the substrate 41 and the resin layer 52.

[0091] Next, a plurality of external connection terminals 44 are formed on the lower surface of the substrate 41. Figure 18 Each external connection terminal 44 is electrically connected to the wiring layer 41b of the substrate 41.

[0092] Thus, the semiconductor device 3 of this embodiment, having a semiconductor package P, is manufactured.

[0093] As described above, the semiconductor device 3 of this embodiment includes memory chips 11 and 12 of different types, and a bridge chip 13 that electrically connects the memory chips 11 and 12. In addition, the semiconductor device 3 of this embodiment includes a chip stack C comprising the memory chips 11 and 12 and the bridge chip 13 stacked on a substrate 41.

[0094] Therefore, according to this embodiment, various memory chips 11 and 12 can be mounted on the substrate 41 in a preferred configuration. For example, the area of ​​the semiconductor device 3 when viewed from above can be reduced, and the semiconductor device 3 can be miniaturized. Furthermore, data transfer between different types of memory chips 11 and 12 can be performed via the bridging chip 13, and the increase in the area of ​​the semiconductor device 3 due to the bridging chip 13 can be suppressed.

[0095] (Second Implementation)

[0096] Figure 19 This is a block diagram illustrating the configuration of the information processing apparatus according to the second embodiment.

[0097] The information processing device of this embodiment ( Figure 19 ) possesses the information processing device of the first embodiment ( Figure 1 The storage device 3 of this embodiment has the same constituent elements. However, it also includes a memory chip 11' and a bridge chip 13'. The memory chip 11' is an example of a third memory chip. The bridge chip 13' is an example of a second bridge chip.

[0098] Memory chips 11', 11, and 12 are of different types. For example, memory chips 11', 11, and 12 differ in at least one of their data storage method, memory capacity, and access speed. Memory chip 11' is, for example, a non-volatile memory such as flash memory. Memory chip 11 is, for example, a non-volatile memory such as a storage device memory. Memory chip 12 is, for example, a volatile memory such as DRAM (Dynamic Random Access Memory). In this case, memory chips 11' and 11 have the same data storage method (non-volatile), while memory chip 12 has a different data storage method (volatile) than memory chips 11' and 11. Furthermore, because memory chip 11' has a large capacity, memory chip 11 has a small capacity, and memory chip 12 has an even smaller capacity, the memory capacities of memory chips 11', 11, and 12 are different. Furthermore, because memory chip 11' has a low access speed, while memory chip 11 has a high access speed, and memory chip 12 has an even higher access speed, the access speeds of memory chips 11', 11, and 12 are different. For example, memory chips 11', 11, and 12 each have a memory cell array containing multiple memory cells and a circuit (e.g., a CMOS circuit) containing multiple transistors controlling the multiple memory cells.

[0099] A bridge chip 13' is configured between memory chips 11' and 11 to electrically connect them. The bridge chip 13' has the function of transferring data between memory chips of different types. In this embodiment, because memory chips 11' and 11 are of different types, the bridge chip 13' is configured between them. The bridge chip 13' transfers data from one of the memory chips 11' and 11 to the other.

[0100] In this embodiment, the IF chip 14 is electrically connected to memory chips 11', 11', 12, bridge chips 13', 13, and bus 5 (processor 1). The IF chip 14 functions as an interface between memory chips 11', 11', 12, bridge chips 13', 13, and bus 5 (processor 1). For example, the IF chip 14 receives signals from processor 1 and accesses any one of memory chips 11', 11', 12, and bridge chips 13', 13 based on these signals. As an example, the IF chip 14 sends an instruction to bridge chip 13', and bridge chip 13' transfers data from memory chip 11 to memory chip 11' based on the instruction. Thus, the data can be transferred from memory chip 11 to memory chip 11' without temporarily storing it in memory 2. An example of such an instruction is a write instruction that writes data to memory chip 11'.

[0101] Similar to the first embodiment, for example, when the processor 1 performs AI-related information processing, the storage device 3 of this embodiment is used. According to this embodiment, information processing can be performed at high speed by transferring data between memory chips 11', 11, and 12 without passing through memory 2. As an example of such information processing, information processing related to AI reasoning is given.

[0102] Similar to the first embodiment, the storage device 3 in this embodiment is a semiconductor device in the form of a semiconductor package P. The memory chips 11', 11, 12, bridge chips 13', 13 and IF chip 14 of this embodiment are mounted on the substrate 41 and become part of the semiconductor package P.

[0103] In addition to the through electrodes 21-25, the storage device 3 of this embodiment also includes through electrodes 21', 23', 24', and 25'. Furthermore, in addition to the metal pads 31-34, the IF chip 14 of this embodiment also includes metal pads 31' and 33'. The through electrodes 21', 23', 24', 25' or the metal pads 31', 33' also become part of the semiconductor package P.

[0104] Through electrode 21' is configured to electrically connect memory chip 11' and IF chip 14. Through electrode 23' is configured to electrically connect bridge chip 13' and IF chip 14. IF chip 14 can access memory chip 11' using through electrode 21' and access bridge chip 13' using through electrode 23'.

[0105] Through electrode 24' is provided to electrically connect memory chip 11' and bridge chip 13'. Through electrode 25' is provided to electrically connect memory chip 11 and bridge chip 13'. Bridge chip 13' can use through electrodes 24' and 25' to transfer data from one of memory chips 11' to the other.

[0106] Metal pad 31' is electrically connected to through electrode 21'. Metal pad 33' is electrically connected to through electrode 23'. IF chip 14 can access memory chip 11' using metal pad 31' and access bridge chip 13' using metal pad 33'.

[0107] According to this embodiment, by employing bridge chips 13', 13 or IF chip 14, memory chips 11', 11, 12 of different types can be housed within the same semiconductor package P. This reduces the total area of ​​the storage device 3 on the motherboard of the information processing device of this embodiment, enabling miniaturization of the information processing device. Therefore, the storage device 3 of this embodiment is suitable, for example, for mobile devices such as smartphones.

[0108] The following describes further details of the storage device 3 according to this embodiment. In the following description, the storage device 3 according to this embodiment will also be referred to as "semiconductor device 3".

[0109] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device 3 according to the second embodiment.

[0110] Semiconductor device 3 in this embodiment ( Figure 20 ) includes the semiconductor device 3 of the first embodiment ( Figure 2 The same constituent elements. However, as Figure 20 As shown, the semiconductor device 3 of this embodiment also includes a plurality of memory chips 11'. Figure 20 Each memory chip 11' shown corresponds to Figure 19 The memory chip 11' shown has the same characteristics as... Figure 19 The memory chip 11' shown has the same structure or function. Figure 19 As described above, the semiconductor device 3 of this embodiment also includes a bridging chip 13', through electrodes 21', 23', 24', 25', and metal pads 31', 33'.

[0111] The chip stack C of this embodiment includes a plurality of memory chips 11', a plurality of memory chips 11, a plurality of memory chips 12, a bridge chip 13', and a bridge chip 13 stacked in the Z direction. More specifically, the chip stack C of this embodiment includes a plurality of memory chips 12 stacked on a substrate 41, a bridge chip 13 stacked on the plurality of memory chips 12, a plurality of memory chips 11 stacked on the bridge chip 13, a bridge chip 13' stacked on the plurality of memory chips 11, and a plurality of memory chips 11' stacked on the bridge chip 13'. Therefore, the bridge chip 13' is disposed between the plurality of memory chips 11' and the plurality of memory chips 11, and the bridge chip 13 is disposed between the plurality of memory chips 11 and the plurality of memory chips 12.

[0112] The chip stack C of this embodiment includes through electrodes 21', 23', 24', and 25'. Each of the through electrodes 21', 23', 24', and 25' penetrates one or more chips within the chip stack C in the Z direction. Through electrode 21' is configured to electrically connect multiple memory chips 11' to an IF chip 14. Through electrode 23' is configured to electrically connect a bridge chip 13' to an IF chip 14. Through electrode 24' is configured to electrically connect multiple memory chips 11' to a bridge chip 13'. Through electrode 25' is configured to electrically connect multiple memory chips 11' to a bridge chip 13'.

[0113] In this embodiment, the IF chip 14 includes metal pads 31' and 33' on its upper surface. The metal pad 31' is electrically connected to the through electrode 21' via a bump 42. The metal pad 33' is electrically connected to the through electrode 23' via a bump 42.

[0114] As described above, the memory chips 11', 11, and 12 of this embodiment are mounted on the substrate 41 in the form of a chip stack C. This reduces the area of ​​the semiconductor device 3 when viewed from above, and enables miniaturization of the semiconductor device 3.

[0115] Furthermore, in this embodiment, the bridging chips 13' and 13 are disposed as part of the chip stack C between multiple memory chips 11' and multiple memory chips 11, or between multiple memory chips 11 and multiple memory chips 12. Therefore, data transmission between memory chips 11', 11, and 12 of different types can be performed via the bridging chips 13' and 13, and the increase in area of ​​the semiconductor device 3 due to the bridging chips 13' and 13 can be suppressed.

[0116] in addition, Figure 20 The through electrodes 21', 23', 24', and 25' shown have the same characteristics as... Figure 3The through electrode 21 shown in example (b) has the same structure as the second example, but it can also be replaced with the same... Figure 3 The through electrode 21 in example (a) has the same construction as the first example. Figures 4 to 10 In the case of manufacturing the semiconductor device 3 of this embodiment as shown in the first example, each memory chip 11' or bridge chip 13' is also applied. Figure 6 The process shown. On the other hand, in the process shown... Figures 11-18 In the case of manufacturing the semiconductor device 3 of this embodiment as shown in the second example, the memory chip 11' or bridge chip 13' is also applied. Figure 13 The process shown.

[0117] As described above, the semiconductor device 3 of this embodiment includes memory chips 11', 11, 12 of different types and bridge chips 13', 13 that electrically connect these memory chips 11', 11, 12. Furthermore, the semiconductor device 3 of this embodiment includes a chip stack C comprising the memory chips 11', 11, 12 and the bridge chips 13', 13 stacked on the substrate 41.

[0118] Therefore, according to this embodiment, similar to the first embodiment, various types of memory chips 11', 11, 12 can be mounted on the substrate 41 in a preferred configuration.

[0119] In addition, Figure 1 or Figure 19 In the first or second embodiment, the semiconductor device 3 may also include N+1 memory chips of different types and N bridge chips (N being an integer of 3 or more) electrically connecting these N+1 memory chips. When this configuration is applied... Figure 2 or Figure 20 In this case, the semiconductor device 3 of the first or second embodiment may also include multiple memory chips of the same type. In other words, in Figure 2 or Figure 20 In the first or second embodiment, the semiconductor device 3 may also include N+1 types of memory chips and N bridge chips electrically connecting these N+1 types of memory chips. In this case, each bridge chip is arranged between one or more memory chips of one type and one or more memory chips of another type. If the number of memory chips in the semiconductor device 3 in this case is set to K, then the relationship K ≥ N+1 holds true between N and K.

[0120] Furthermore, the semiconductor device 3 of the first embodiment may also be similar to the semiconductor device 3 of the second embodiment, possessing both a non-volatile memory chip and a volatile memory chip. Conversely, the semiconductor device 3 of the second embodiment may also be similar to the semiconductor device 3 of the first embodiment, possessing only a non-volatile memory chip.

[0121] (Third Implementation)

[0122] Figure 21 This is a block diagram illustrating the configuration of the information processing apparatus according to the third embodiment.

[0123] The information processing device of this embodiment ( Figure 21 ) possesses the information processing device of the first embodiment ( Figure 1 The same components. However, the storage device 3 of this embodiment also includes a capacitor 15. Figure 21 In this configuration, capacitor 15 is electrically connected to the metal pad 34 of IF chip 14. Capacitor 15 is, for example, a thin capacitor such as a silicon capacitor.

[0124] The following describes further details of the storage device 3 according to this embodiment. In the following description, the storage device 3 according to this embodiment will also be referred to as "semiconductor device 3".

[0125] Figure 22 This is a cross-sectional view showing the structure of the semiconductor device 3 according to the third embodiment.

[0126] Semiconductor device 3 in this embodiment ( Figure 22 ) includes the semiconductor device 3 of the first embodiment ( Figure 2 The same constituent elements. However, as Figure 22 As shown, the semiconductor device 3 of this embodiment also includes a plurality of capacitors 15. Figure 22 Each capacitor 15 shown corresponds to Figure 21 The capacitor 15 shown has the same characteristics as... Figure 21 The capacitor 15 shown has the same construction or function.

[0127] The semiconductor device 3 of this embodiment further includes a plurality of through electrodes 27, a plurality of through electrodes 28, and a plurality of bumps 45. Each through electrode 27 is an example of a seventh electrode. Each through electrode 28 is an example of an eighth electrode. Furthermore, Figure 22 The diagram of through electrode 26 is omitted. Through electrodes 27 and 28 are disposed within the chip stack C in the same manner as through electrodes 21-26. Through electrode 26 is disposed, for example, within the stack C. Figure 22 The XZ sections shown are different within the XZ sections.

[0128] Each through electrode 27 is electrically connected to a plurality of memory chips 11, a plurality of memory chips 12, a bridge chip 13, and an IF chip 14. Each through electrode 27 is also electrically connected to a corresponding capacitor 15. In this embodiment, each through electrode 27 is, for example, a power supply line (VDD line).

[0129] Each through electrode 28 is electrically connected to a plurality of memory chips 11, a plurality of memory chips 12, and a bridge chip 13. Each through electrode 28 is also electrically connected to a corresponding capacitor 15. In this embodiment, each through electrode 28 is, for example, a grounding wiring (GND wiring).

[0130] Each protrusion 45 is disposed on the upper surface of the corresponding capacitor 15. Figure 22 In this configuration, a plurality of protrusions 45 are provided on the upper surface of each capacitor 15. Specifically, each capacitor 15 has a protrusion 45 that electrically connects the capacitor 15 to the through electrode 27 and a protrusion 45 that electrically connects the capacitor 15 to the through electrode 28.

[0131] Each capacitor 15 is electrically connected to a corresponding through electrode 27 via a bump 45, and also electrically connected to a corresponding through electrode 28 via a bump 45. Each capacitor 15 has two capacitor electrodes (not shown), one capacitor electrode is electrically connected to the through electrode 27 and the IF chip 14, and the other capacitor electrode is electrically connected to the through electrode 28. According to this embodiment, each capacitor 15 can suppress noise between the through electrode 27 (power supply wiring) and the through electrode 28 (ground wiring).

[0132] Figure 22 and Figure 2 Multiple wirings 51 are also shown. Figure 22 The plurality of wirings 51 shown include electrical connections to Figure 22 The wiring 51 of the through electrode 27 of the capacitor 15 on the left side is electrically connected to... Figure 22 The through electrode 27 of the capacitor 15 on the right side is connected to the IF chip 14 via the preceding wiring 51, and the through electrode 27 of the capacitor 15 on the right side is connected to the IF chip 14 via the following wiring 51. Additionally, Figure 22 The diagrams of the through electrode 26 and the wiring 51 used with the through electrode 26 are omitted. The wiring 51 used with the through electrode 26 is, for example, installed in connection with... Figure 22 The XZ sections shown are different within the XZ sections.

[0133] exist Figure 22 In this configuration, each wiring 51 is disposed under the chip stack C, positioned between the substrate 41 and the chip stack C. Each wiring 51 is disposed on a corresponding bump 43 and electrically connected to a corresponding external connection terminal 44 via the bump 43 and wiring layer 41b. Each wiring 51 is electrically connected to the chip stack C, the IF chip 14, and the corresponding external connection terminal 44. Figure 22 Details of each wiring 51 shown are as follows Figure 2 The details of each wiring 51 shown are roughly the same.

[0134] exist Figure 22 In this configuration, each capacitor 15 is disposed under the chip stack C, positioned between the substrate 41 and the chip stack C. Each capacitor 15 has a barrier bump 45 mounted on the lower surface of the through electrodes 27 and 28.

[0135] in addition, Figure 22 The through electrodes 27 and 28 shown have the same characteristics as... Figure 3 The through electrode 21 shown in example (b) has the same structure as the second example, but it can also be replaced with the same... Figure 3 The through electrode 21 in example (a) has the same construction as the first example. Figures 4 to 10 In the case of manufacturing the semiconductor device 3 of this embodiment as shown in the first example, in Figure 7 In the process shown, each capacitor 15 is mounted on the chip stack C. On the other hand, in the process shown... Figures 11-18 In the case of manufacturing the semiconductor device 3 of this embodiment as shown in the second example, in Figure 15 In the process shown, each capacitor 15 is placed on the chip stack C.

[0136] As described above, the semiconductor device 3 of this embodiment includes memory chips 11 and 12 of different types, and a bridge chip 13 electrically connecting the memory chips 11 and 12. Furthermore, the semiconductor device 3 of this embodiment includes a chip stack C comprising the memory chips 11 and 12 and the bridge chip 13 stacked on a substrate 41. Additionally, the semiconductor device 3 of this embodiment includes a capacitor 15 between the through electrode 27 and the through electrode 28.

[0137] Therefore, according to this embodiment, similar to the first embodiment, various types of memory chips 11 and 12 can be mounted on the substrate 41 in a preferred configuration. Furthermore, according to this embodiment, noise between the through electrode 27 and the through electrode 28 can be suppressed by the capacitor 15.

[0138] Furthermore, the capacitor 15 of this embodiment can also be applied to the semiconductor device 3 of the second embodiment, instead of the semiconductor device 3 applied to the first embodiment. Additionally, the capacitor 15 of this embodiment can also be configured in... Figure 22 Locations other than those shown.

[0139] Several embodiments have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. The novel apparatus described in this specification can be implemented in various other forms. Furthermore, various omissions, substitutions, and modifications can be made to the form of the apparatus described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass the forms or variations included within the scope or spirit of the invention.

[0140] [Explanation of Symbols]

[0141] 1 processor

[0142] 2. Memory

[0143] 3. Storage devices (semiconductor devices)

[0144] 4-bus

[0145] 5-bus

[0146] 11. Memory Chip

[0147] 11' memory chip

[0148] 12 Memory Chips

[0149] 13 Bridge chips

[0150] 13' Bridge Chip

[0151] 14 IF Chip

[0152] 15 Capacitors

[0153] 21 Through-electrode

[0154] 21' Through electrode

[0155] 22 Through-electrode

[0156] 23 Through-electrode

[0157] 23' Through electrode

[0158] 24 Through-electrode

[0159] 24' Through electrode

[0160] 25 Through-electrode

[0161] 25' Through Electrode

[0162] 26 Through-electrode

[0163] 27 Through-electrode

[0164] 28 Through-electrode

[0165] 31 Metal pads

[0166] 31' metal pad

[0167] 32 metal pads

[0168] 33 Metal pads

[0169] 33' metal pad

[0170] 34 Metal pads

[0171] 41 Substrate

[0172] 41a Insulating substrate

[0173] 41b wiring layer

[0174] 41c resin layer

[0175] 42 bumps

[0176] 43 bumps

[0177] 44 External connection terminals

[0178] 45 bumps

[0179] 51 Wiring

[0180] 52 Resin Layer

[0181] 53 Resin layer

[0182] 54 Resin Layer

[0183] 61 Electrode

[0184] 62 pads

[0185] 63 bumps

[0186] 71 Supporting substrate

[0187] 72 Resin Layer

[0188] 73 Supporting substrate

[0189] 74 Supporting substrate

[0190] 75 Resin Layer

[0191] 81 Supporting substrate

[0192] 82 Supporting substrate.

Claims

1. A semiconductor device comprising: Substrate; and A chip stack comprises a plurality of chips stacked on the substrate; and The plurality of chips include: First memory chip; The second memory chip is of a different type than the first memory chip; and The first bridge chip electrically connects the first memory chip to the second memory chip.

2. The semiconductor device according to claim 1, wherein The first memory chip is disposed above the substrate; The second memory chip is disposed between the substrate and the first memory chip; and The first bridge chip is configured between the first memory chip and the second memory chip to transmit data between the first memory chip and the second memory chip.

3. The semiconductor device according to claim 1, wherein the first memory chip differs from the second memory chip in at least one of the data storage method, memory capacity, and access speed.

4. The semiconductor device of claim 1, wherein the memory capacity of the first memory chip is greater than the memory capacity of the second memory chip, and the access speed of the first memory chip is slower than the access speed of the second memory chip.

5. The semiconductor device according to claim 1, further comprising: External connection terminals are disposed under the substrate; and An IF (interface) chip is disposed between the substrate and the chip stack, and is electrically connected to the first memory chip, the second memory chip, the first bridge chip and the external connection terminal, serving as an interface between the first memory chip, the second memory chip and the first bridge chip and the external connection terminal.

6. The semiconductor device according to claim 5, wherein The chip stack comprises: The first electrode electrically connects the first memory chip to the IF chip; The second electrode electrically connects the second memory chip to the IF chip; The third electrode electrically connects the first bridging chip to the IF chip. The fourth electrode electrically connects the first memory chip to the first bridge chip; The fifth electrode electrically connects the second memory chip to the first bridge chip; and The sixth electrode electrically connects the first memory chip, the second memory chip, and the first bridge chip to the external connection terminal.

7. The semiconductor device of claim 6, wherein one of the first to sixth electrodes comprises a plurality of electrodes respectively disposed within the plurality of chips, and a plurality of bumps alternately disposed with the plurality of electrodes; and One of the plurality of electrodes is electrically connected to one of the plurality of bumps via a pad.

8. The semiconductor device of claim 6, wherein one of the first to sixth electrodes comprises a plurality of electrodes respectively disposed within the plurality of chips; and One of the plurality of electrodes is electrically connected to another of the plurality of electrodes via a pad.

9. The semiconductor device according to claim 6, further comprising: wiring disposed under the chip stack and electrically connected to the sixth electrode, the IF chip and the external connection terminal.

10. The semiconductor device of claim 9, further comprising: a bump disposed on the wiring wire, electrically connecting the wiring wire to the external connection terminal; and The bump is electrically connected to the external connection terminal via a wiring layer within the substrate.

11. The semiconductor device according to claim 6, wherein The IF chip includes: The first pad is electrically connected to the first electrode; The second pad is electrically connected to the second electrode; The third pad is electrically connected to the third electrode; and The fourth pad is electrically connected to the external connection terminal.

12. The semiconductor device according to claim 11, further comprising: wiring disposed under the chip stack and electrically connected to the sixth electrode, the fourth pad and the external connection terminal.

13. The semiconductor device according to claim 1, wherein The plurality of chips also include: The third memory chip is of a different type than the first memory chip and also different type from the second memory chip; and The second bridge chip electrically connects the first memory chip to the third memory chip.

14. The semiconductor device of claim 13, wherein The third memory chip is disposed above the substrate; The first memory chip is disposed between the substrate and the third memory chip; The second memory chip is disposed between the substrate and the first memory chip; The first bridge chip is configured between the first memory chip and the second memory chip, and transmits data between the first memory chip and the second memory chip; and The second bridge chip is configured between the first memory chip and the third memory chip to transmit data between the first memory chip and the third memory chip.

15. The semiconductor device of claim 13, wherein at least one of the data storage method, memory capacity and access speed of the first memory chip, the second memory chip and the third memory chip is different.

16. The semiconductor device of claim 5, wherein the chip stack comprises: The seventh electrode is electrically connected to the first memory chip, the second memory chip, the first bridge chip, and the IF chip; and The eighth electrode is electrically connected to the first memory chip, the second memory chip, and the first bridge chip; and the semiconductor device further comprises: A capacitor is electrically connected to the 7th electrode and the 8th electrode.

17. The semiconductor device according to claim 16, further comprising: wiring disposed under the chip stack and electrically connected to the 7th electrode, the IF chip and the external connection terminal.

18. The semiconductor device of claim 16, wherein the seventh electrode is a power supply wiring and the eighth electrode is a ground wiring.

19. A semiconductor device comprising: First memory chip; The second memory chip is of a different type than the first memory chip; and The first bridge chip electrically connects the first memory chip and the second memory chip, and transmits data between the first memory chip and the second memory chip.

20. The semiconductor device according to claim 19, further comprising: The third memory chip is of a different type than the first memory chip and also different type from the second memory chip; and The second bridge chip electrically connects the first memory chip and the third memory chip, and transmits data between the first memory chip and the third memory chip.

Images