Internal error checking circuit and memory

Abstract

An internal error checking circuit, comprising a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit, wherein the clock generation circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit counts the self-refresh clock signal when an error checking enable signal indicates that an internal error checking function is enabled, and generates and outputs an internal error checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit counts the internal error checking command signal to generate and output an internal error checking address; the control logic circuit controls, in response to the internal error checking command signal, the error correction circuit to sequentially perform an internal read-modify-write operation on target memory cells corresponding to the internal error checking address in a plurality of memory arrays.

Description

An internal error checking circuit and memory

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411754887.3, filed on December 3, 2024, entitled “An Internal Error Checking Circuit and Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and more particularly to an internal error checking circuit and a memory. Background Technology

[0004] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using equipment such as computers. In order to obtain faster data transmission speeds, a series of dynamic random access memory devices (DRAMs) capable of transmitting data at double data rate (DDR) have emerged.

[0005] However, with the increasing speed of memory transfers, the shrinking of memory cell sizes, and row hammering, problems such as charge leakage in DRAM memory are becoming more severe, potentially increasing data instability and the potential error rate in the storage system. Therefore, an appropriate internal error checking mechanism is needed to periodically check the memory for errors and promptly correct any detected errors to ensure data integrity and system reliability. Summary of the Invention

[0006] This disclosure provides an internal error checking circuit and a memory.

[0007] In a first aspect, embodiments of this disclosure provide an internal error checking circuit, including: a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit; the clock generation circuit is configured to generate and output a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit is configured to receive the self-refresh clock signal and the error checking enable signal, count the self-refresh clock signal when the error checking enable signal indicates that the internal error checking function is enabled, and generate and output an internal error checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit is configured to receive the internal error checking command signal and count the internal error checking command signal to generate and output an internal error checking address; the control logic circuit is configured to receive the internal error checking command signal and the internal error checking address, and in response to the internal error checking command signal, control the error correction circuit to sequentially perform an internal read-modify-write operation on the target memory cell corresponding to the internal error checking address in multiple memory arrays; wherein the multiple memory arrays share the error correction circuit.

[0008] In some embodiments, the control logic circuit includes multiple memory array control circuits, each corresponding to one of the multiple memory arrays. Each memory array control circuit is configured to receive the internal error checking command signal and the internal error checking address, generate multiple sets of internal signals in response to the internal error checking command signal, and, when the corresponding memory array is enabled, control the error correction circuit to perform an internal read-modify-write operation on the target memory cell in the corresponding memory array according to the corresponding set of internal signals. Each set of internal signals includes an internal read signal and an internal write signal.

[0009] In some embodiments, the error correction circuit is configured to read stored data from the target storage unit according to the internal read signal, and to perform error detection and correction on the stored data to generate corrected data; the error correction circuit is further configured to write the corrected data into the target storage unit according to the internal write signal.

[0010] In some embodiments, the internal command generation circuit is further configured to generate and output an internal self-refresh command signal in response to each pulse on the self-refresh clock signal when the error check enable signal indicates that the internal error check function is not enabled; and to generate and output an internal self-refresh command signal when the error check enable signal indicates that the internal error check function is enabled and the count value of the self-refresh clock signal is not a first preset value.

[0011] In some embodiments, the control logic circuit is further configured to, after controlling the error correction circuit to perform an internal read-modify-write operation on the target storage cell corresponding to the internal error check address in the plurality of storage arrays in sequence, control to perform a self-refresh operation on all storage arrays.

[0012] In some embodiments, the address generation circuit includes a column address generation circuit, a first decoding circuit, and a row address generation circuit; the column address generation circuit is configured to receive the internal error checking command signal, count columns of the current storage row according to the internal error checking command signal, and generate and output a target column address; the first decoding circuit is configured to decode the target column address, and generate and output a column end signal when the target column address indicates that the column counting of the current storage row is complete; the row address generation circuit is configured to receive the column end signal and the internal error checking command signal, and count rows of the storage array according to the column end signal, and generate and output a target row address signal.

[0013] In some embodiments, the row address generation circuit includes: a row counting circuit configured to receive the column end signal, and count rows of the storage array according to the column end signal, generating and outputting a row count value; and a row address sampling circuit configured to receive the internal error checking command signal and the row count value, and sample the row count value in response to the internal error checking command signal, generating and outputting the target row address signal.

[0014] In some embodiments, the address generation circuit further includes a refresh address generation circuit, configured to receive the internal self-refresh command signal, and perform row counting on the storage array according to the internal self-refresh command signal to generate and output a self-refresh address; the control logic circuit is further configured to control the execution of a refresh operation on all storage arrays based on the self-refresh address.

[0015] In some embodiments, the column address generation circuit includes N cascaded first flip-flops, where N is an integer greater than or equal to 1; the clock control terminal of the first stage of the first flip-flops serves as the input terminal of the column address generation circuit, receiving the internal error checking command signal; the inverted output terminal of each stage of the first flip-flops is connected to its own data input terminal; the clock control terminals of the other first flip-flops besides the first stage are all connected to the inverted output terminal of the previous stage of the first flip-flops; the non-inverted output terminals of the N first flip-flops jointly output the target column address; the first decoding circuit includes a first NAND gate, the N input terminals of the first NAND gate are respectively connected to the non-inverted output terminals of the N first flip-flops, and the output terminal of the first NAND gate is used to output the column end signal.

[0016] In some embodiments, the row counting circuit includes M cascaded second flip-flops, where M is an integer greater than or equal to 1; the clock control terminal of the first-stage second flip-flop serves as the input terminal of the row counting circuit, receiving the column end signal; the inverted output terminal of each stage of the second flip-flop is connected to its own data input terminal; the clock control terminals of the other second flip-flops besides the first-stage second flip-flops are all connected to the inverted output terminal of the previous stage of the second flip-flops; the non-inverted output terminals of the M second flip-flops jointly output the row count value; the row address sampling circuit includes M third flip-flops; the clock control terminal of each third flip-flop receives the internal error check command signal; the data input terminals of the M third flip-flops are connected one-to-one with the non-inverted output terminals of the M second flip-flops, receiving the row count value; the non-inverted output terminals of the M third flip-flops jointly output the target row address.

[0017] In some embodiments, the storage array control circuit includes: an identification signal generation circuit configured to receive the internal error check command signal and, in response to the internal error check command signal, generate and output an operation identification signal at a valid level; a read / write command generation circuit configured to receive the operation identification signal and the internal error check command signal, and, in response to the internal error check command signal, sequentially generate multiple sets of internal signals while the operation identification signal is at a valid level; the identification signal generation circuit is further configured to receive the internal write signal and, when the count value of the internal write signal reaches a second preset value, set the operation identification signal to an invalid level.

[0018] In some embodiments, the identification signal generation circuit includes: a command counting circuit configured to count the inverted signal of the internal write signal to generate and output a count value of the internal write signal; a second decoding circuit configured to receive the count value of the internal write signal and generate and output an operation end signal when the count value of the internal write signal is a second preset value; and an SR flip-flop configured to receive the internal error checking command signal and the operation end signal, and in response to the internal error checking command signal, set the operation identification signal to an active level, and set the operation identification signal to an inactive level when the count value of the internal write signal reaches the second preset value.

[0019] In some embodiments, the read / write command generation circuit includes: a second NAND gate, the first input of which receives the operation identifier signal, and the second input of which receives the internal error check command signal; a first NOR gate, the first input of which is electrically connected to the output of which is used to output the internal read signal; a second NOR gate, the first input of which is electrically connected to the output of which is electrically connected, and the output of which is electrically connected to the second input of which is electrically connected; a delay unit, the input of which is electrically connected to the output of which is electrically connected; a first NOT gate, the input of which is electrically connected to the output of which is electrically connected, and the output of which is electrically connected to the second input of which is electrically connected; a second NOT gate, the input of which receives the operation identifier signal; and a third NOR gate, the first input of which is electrically connected to the output of which is electrically connected, and the second input of which is electrically connected to the output of which is electrically connected, and the output of which is used to output the internal write signal.

[0020] In some embodiments, the storage array control circuit further includes a self-refresh control circuit, configured to receive the operation identifier signal and the self-refresh address, and when the operation identifier signal flips to an invalid level, control the corresponding storage array to perform a refresh operation according to the self-refresh address.

[0021] In some embodiments, the error correction circuit is further configured to generate and output an error identification signal when an error exists in the stored data of the target storage unit during an internal read-modify-write operation on the target storage unit; the internal error checking circuit further includes an error register configured to receive the internal error checking address and the error identification signal, and to store the internal error checking address in response to the error identification signal.

[0022] In a second aspect, embodiments of this disclosure provide a memory that includes the internal error checking circuitry described in the first aspect.

[0023] This disclosure provides an internal error checking circuit and a memory. The internal command generation circuit in the internal error checking circuit can "steal" the current pulse on the self-refresh clock signal to generate an internal error checking command signal whenever the error checking enable signal indicates that the internal error checking function is enabled and whenever the count value of the self-refresh clock signal reaches a first preset value. The control logic circuit can reuse the original operation circuit and path for executing external read-modify-write commands based on the internal error checking command signal, and control the error correction circuit to sequentially perform an internal read-modify-write operation on the target memory cell in the multiple memory arrays that share it. Since the internal read-modify-write operation performed by the error correction circuit has the function of data error detection / correction. In this way, the memory error checking circuit can reuse the original clock generation circuit (for self-refresh operation), the operation circuit and path for executing external read-modify-write commands, without affecting the timing of the original self-refresh operation and external read-modify-write operation. Moreover, only simple improvements are needed to the original internal command generation circuit, address generation circuit and control logic circuit to realize periodic data error detection / correction operations on multiple memory arrays. While implementing the internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area is saved. Attached Figure Description

[0024] Figure 1 is a schematic diagram of the composition structure of an internal error checking circuit provided in an embodiment of this disclosure;

[0025] Figure 2 is a schematic diagram of the composition structure of a control logic circuit provided in an embodiment of this disclosure;

[0026] Figure 3 is a schematic diagram of the composition structure of a storage region provided in an embodiment of this disclosure;

[0027] Figure 4 is a signal timing diagram of an internal error checking circuit provided in an embodiment of this disclosure.

[0028] Figure 5 is a schematic diagram of the composition structure of an address generation circuit provided in an embodiment of this disclosure;

[0029] Figure 6 is a signal timing diagram of an internal error checking circuit provided in an embodiment of this disclosure.

[0030] Figure 7 is a schematic diagram of the composition structure of a row address generation circuit provided in an embodiment of this disclosure;

[0031] Figure 8 is a schematic diagram of the composition structure of a column address generation circuit provided in an embodiment of this disclosure;

[0032] Figure 9 is a schematic diagram of the composition structure of a first decoding circuit provided in an embodiment of this disclosure;

[0033] Figure 10 is a schematic diagram of the composition structure of a row counting circuit and a row address sampling circuit provided in an embodiment of this disclosure;

[0034] Figure 11 is a schematic diagram of the composition structure of a storage array control circuit provided in an embodiment of this disclosure;

[0035] Figure 12 is a schematic diagram of the composition structure of an identification signal generation circuit provided in an embodiment of this disclosure;

[0036] Figure 13 is a schematic diagram of the composition structure of another storage array control circuit provided in an embodiment of this disclosure;

[0037] Figure 14 is a schematic diagram of the composition structure of a read / write command generation circuit provided in an embodiment of this disclosure;

[0038] Figure 15 is a schematic diagram of the composition structure of another internal error checking circuit provided in an embodiment of this disclosure;

[0039] Figure 16 is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0042] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] To establish an appropriate internal error checking mechanism for periodically performing error detection / correction operations on multiple memory arrays (within the memory), this disclosure provides an internal error checking circuit including a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit. The clock generation circuit is configured to generate and output a self-refresh clock signal in response to a self-refresh enable signal. The internal command generation circuit is configured to receive the self-refresh clock signal and the error checking enable signal, count the pulses on the self-refresh clock signal when the error checking enable signal is at an active level, and generate and output an internal error checking command signal when the count value of the self-refresh clock signal is a first preset value. The address generation circuit is configured to receive the internal error checking command signal and count the internal error checking command signal to generate and output an internal error checking address. The control logic circuit is configured to receive the internal error checking command signal and the internal error checking address, and in response to the internal error checking command signal, control the error correction circuit to sequentially perform an internal read-modify-write operation on the target memory cell corresponding to the internal error checking address in the multiple memory arrays. The error correction circuit is shared by multiple memory arrays. Thus, when the error checking enable signal indicates that the internal error checking function is enabled, and whenever the count value of the self-refresh clock signal reaches the first preset value, the internal command generation circuit can "steal" the current pulse on the self-refresh clock signal to generate an internal error checking command signal. The control logic circuit can also reuse the original operation circuit and path for executing external read-modify-write commands, and control the error correction circuit to perform an (internal) read-modify-write operation on the target memory cells in the multiple memory arrays that share it in sequence based on the internal error checking command signal. Since the internal read-modify-write operation performed by the error correction circuit has the function of data error detection / correction. In this way, the memory error checking circuit can reuse the original clock generation circuit (for self-refresh operation), the operation circuit and path for executing external read-modify-write commands, without affecting the timing of the original self-refresh operation and external read-modify-write operation. Moreover, only simple improvements are needed to the original internal command generation circuit, address generation circuit and control logic circuit to realize periodic data error detection / correction operations on multiple memory arrays. While implementing the internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area is saved.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] In one embodiment of this disclosure, referring to FIG1, a schematic diagram of the composition structure of an internal error checking circuit 10 provided in this embodiment is shown. As shown in FIG1, the internal error checking circuit 10 includes: a clock generation circuit 11, an internal command generation circuit 12, an address generation circuit 13, a control logic circuit 14, and an error correction circuit 16, wherein,

[0047] The clock generation circuit 11 is configured to generate and output a self-refresh clock signal SR_CLK in response to the self-refresh enable signal SR_EN; wherein the self-refresh clock signal SR_CLK has a first preset period.

[0048] The internal command generation circuit 12 is configured to receive the self-refresh clock signal SR_CLK and the error check enable signal, count the pulses on the self-refresh clock signal SR_CLK when the error check enable signal indicates that the internal error check function is enabled, and generate and output an internal error check command signal IMWRAB when the count value of the self-refresh clock signal SR_CLK is a first preset value.

[0049] Address generation circuit 13 is configured to receive internal error check command signal IMWRAB and count the internal error check command signal IMWRAB to generate and output internal error check address IMWR_AD;

[0050] The control logic circuit 14 is configured to receive the internal error checking command signal IMWRAB and the internal error checking address IMWR_AD, and in response to the internal error checking command signal IMWRAB, control the error correction circuit 16 to perform an internal read-modify-write operation on the target memory cell corresponding to the internal error checking address IMWR_AD in the multiple memory arrays 15 in sequence.

[0051] Multiple storage arrays 15 share an error correction circuit 16.

[0052] It should be noted that the embodiments disclosed herein involve the overall circuit framework design of an internal error checking and correction mechanism, particularly in DRAM LPDDR series chips and DRAM DDR4 chips. Since the ECS function is only specified in the SPEC of DRAM DDR4 chips, while the SEPC of LPDDR series chips and DDR4 chips does not specify the ECS function or related requirements, it is impossible to use the ECS function to periodically (perhaps every 12 hours / 24 hours / 48 hours, etc.) perform complete error checking and clearing on such DRAM chips. Therefore, to implement an internal error checking and correction mechanism similar to ECS in such chips, it is necessary to complete the overall framework design of the internal error checking circuit without affecting the original functions and timing requirements of the DRAM chip. This internal error checking circuit reuses the original clock generation circuit, self-refresh command path, and operation circuit and path for executing external read-modify-write commands. It does not affect the original functions and timing of the DRAM chip's self-refresh operation and external read-modify-write operation. Only simple improvements are needed to the original internal command generation circuit, address generation circuit, and control logic circuit to achieve a periodic internal error checking and correction mechanism. This internal error checking circuit can be applied to DDR4 chips and LPDDR series chips, but it is not limited to this scope. Other memory chips, as well as other internal command generation and timing control, can also adopt this design.

[0053] It should also be noted that in related technologies, when the external write command received by the DRAM chip is a masked write (MWR) command, an external read-modify-write (RMW) operation will be performed. The external read-modify-write operation can be decomposed into three operation steps: read, modify, and write back. Specifically, read: the error correction circuit first reads the stored data from the memory array; modify: the error correction circuit modifies the read stored data according to the partial data to be written to generate the write data, and can generate new verification data based on the write data; write back: the error correction circuit stores the write data and the verification data. The internal error checking circuit 10 of this embodiment reuses the relevant circuits and paths of the original external read-modify-write operation of the DRAM chip to perform internal read-modify-write operation on the stored data in the storage array to realize the internal error detection / correction function. The internal read-modify-write operation can be decomposed into two operation steps: read-modify and write-back. Specifically, read-modify: the error correction circuit 16 reads the stored data from the storage array 15 based on the internal read signal IRD, and performs error detection and correction on the stored data based on the verification data to generate correction data. Write: the correction data is written into the storage array based on the internal write signal IWR. The read and modification operations are both completed during the valid period of the write command signal and should belong to the same operation step. Therefore, it can be seen that although the internal read-modify-write operation in this embodiment reuses the relevant circuits (error correction circuit 16) and paths (interaction path between control logic circuit 14, error correction circuit 16 and storage array 15) of the external read-modify-write operation, the internal read-modify-write operation is different from the external read-modify-write operation. The modification in the external read-modify-write operation refers to modifying the read storage data according to the part of data to be written, while there is no external input data to be written in the internal read-modify-write operation. Its modification is actually to perform error detection and error correction operations on the read storage data. Furthermore, performing an internal read-modify-write operation can be considered as completing an internal error checking operation. Since the error correction circuit 16 reads the memory array based on the internal error checking command, it can only read a few bits of stored data from one memory address (internal error checking address) each time, which can be 64 bits, 128 bits, 256 bits, etc. Therefore, it is necessary to count the columns and rows of the memory array based on each internal error checking command to traverse each memory address in the memory array. In this way, each internal error checking command can generate an internal error checking address, thereby ensuring that internal read-modify-write operations can be performed on the stored data in all memory cells of the memory array. Performing an internal read-modify-write operation on all memory cells of the memory array can be considered as completing one round of internal error checking operations.

[0054] As shown in Figure 1, the clock generation circuit 11 generates a self-refresh clock signal SR_CLK when the self-refresh enable signal SR_EN indicates that the memory has entered the self-refresh state. Without an internal error checking function, the internal command generation circuit 12 can generate a self-refresh command signal IREFAB based on each pulse on the self-refresh clock signal SR_CLK to control a self-refresh operation. With the introduction of an internal error checking function, the clock generation circuit 11 and the internal command generation circuit 12 can be reused, and the internal command generation circuit 12 can be simply improved. Specifically, the internal command generation circuit 12 can receive the error checking enable signal IMWR_EN. When the error checking enable signal IMWR_EN is at a valid level, it indicates that the internal error checking function is enabled. The internal command generation circuit 12 needs to periodically "steal" one pulse from the self-refresh clock signal SR_CLK to generate the internal error checking command signal IMWRAB, that is, whenever the count value of the self-refresh clock signal SR_CLK reaches the first preset value... An internal error check command signal IMWRAB is generated and output, and simultaneously sent to the address generation circuit 13 and the control logic circuit 14 to control the execution of the internal read-modify-write operation. At this time, the internal self-refresh command signal IREFAB is no longer generated based on the pulse on the self-refresh clock signal SR_CLK that has been "stolen". When the error check enable signal IMWR_EN is at an invalid level, it indicates that the internal error check function is not enabled. The internal command generation circuit 12 then generates the internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK and executes the relevant functions of the original self-refresh operation.

[0055] It should be noted that the count value of the self-refresh clock signal SR_CLK refers to the count value generated by counting the pulses on the self-refresh clock signal SR_CLK; and after generating the internal error check command signal IMWRAB, the internal command generation circuit 12 needs to reset the count value of the self-refresh clock signal SR_CLK to 0 to ensure that the time interval for generating the internal error check command signal IMWRAB is the same.

[0056] In some embodiments, the first preset value can be any integer greater than 1, that is, the internal command generation circuit 12 generates an internal error check command signal IMWRAB based on the self-refresh clock signal SR_CLK every first preset value of pulses; in other embodiments, the first preset value is 1, that is, each pulse on the self-refresh clock signal SR_CLK corresponds to the generation of an internal error check command signal IMWRAB. In this case, since the internal command generation circuit 12 does not generate a self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK, in order to ensure the normal execution of the self-refresh operation, a self-refresh operation needs to be performed immediately after each internal read-modify-write operation is completed.

[0057] In this embodiment of the disclosure, the valid level is a high level (logic "1") and the invalid level is a low level (logic "0"); in some other embodiments, the invalid level may also be a high level (logic "1") and the valid level may be a low level (logic "0"), and there is no limitation on this.

[0058] In some embodiments, the clock generation circuit 11 can be an oscillator with a control terminal. When an external Self-Refresh Entry (SRE) command instructs the memory to enter a self-refresh state, it activates the self-refresh enable signal SR_EN. The control terminal of the oscillator starts oscillating upon receiving the activated self-refresh enable signal SR_EN, generating and outputting a self-refresh clock signal SR_CLK. The period of the self-refresh clock signal can be set according to the interval of the self-refresh command signal or the self-refresh period, and typically, the duty cycle of the self-refresh clock signal SR_CLK is less than 50%. In this embodiment, the self-refresh enable signal SR_EN is in an active state when it is high (logic "1") and in an inactive state when it is low (logic "0"); in other embodiments, the self-refresh enable signal SR_EN is in an inactive state when it is high (logic "1") and in an active state when it is low (logic "0"), and this is not limited in any way.

[0059] Referring again to Figure 1, the address generation circuit 13 generates a corresponding internal error check address IMWR_AD based on the internal error check command signal IMWRAB output by the internal command generation circuit 12. This address indicates the target memory cell for performing the current internal error check operation (internal read-modify-write operation), so that the control logic circuit 14 can control the error correction circuit 16 to sequentially perform an internal read-modify-write operation on the target memory cells in the multiple memory arrays 15 based on the internal error check command signal IMWRAB. The internal error check address IMWR_AD includes the target row address and the target column address. This internal error check address IMWR_AD is shared by multiple memory arrays 15, meaning that each memory array 15 contains the target memory cell indicated by the internal error check address IMWR_AD. Moreover, the error correction circuit 16 is shared by multiple memory arrays 15, and the error correction circuit 16 can only perform an internal read-modify-write operation on the target memory cell in one memory array 15 at a time. Therefore, based on each internal error check command signal IMWRAB and the corresponding internal error check address IMWR_AD, the error correction circuit 16 needs to perform an internal read-modify-write operation on the target memory cell in each memory array 15 in sequence. That is, the error correction circuit 16 actually performs multiple internal read-modify-write operations (corresponding to multiple sets of internal signals IRD / IWR) in sequence before it can complete the internal error check operation (internal read-modify-write operation) corresponding to the current internal error check command signal IMWRAB.

[0060] In some embodiments, the error correction circuit 16 can be an on-die ECC circuit. The error correction circuit 16 can generate verification data for the write data written to the storage array 15, and can also use the stored data and verification data read from the storage array 15 to check and correct errors in the stored data. The internal read-modify-write operation in this disclosure utilizes the function of the error correction circuit 16 to check and correct errors in the stored data. Furthermore, the error correction circuit 16 can use encoding methods such as Hamming code, RS code, and convolutional code, which are not specifically limited here.

[0061] Further, regarding the composition of the control logic circuit 14, as shown in Figure 2, the control logic circuit 14 includes multiple memory array control circuits 141, which correspond one-to-one with multiple memory arrays 15. Each memory array control circuit 141 is configured to receive an internal error checking command signal IMWRAB and an internal error checking address IMWR_AD, generate multiple sets of internal signals IRD / IWR in response to the internal error checking command signal IMWRAB, and control the error correction circuit 16 to perform an internal read-modify-write operation on the target memory cell in the corresponding memory array 15 according to the corresponding set of internal signals IRD / IWR when the corresponding memory array 15 is in the enabled state. Each set of internal signals includes an internal read signal IRD and an internal write signal IWR.

[0062] It should be noted that in the DRAM chip, each memory array 15 can correspond to a memory array control circuit 141. The memory array control circuit 141 can not only control the error correction circuit 16 to perform internal read-modify-write operations on the corresponding memory array 15, but also control the error correction circuit 16 to perform external read-modify-write operations on the corresponding memory array 15. That is, the internal error checking circuit 10 of this embodiment realizes the related circuits (memory array control circuit 141 and error correction circuit 16) and paths (interaction paths between memory array control circuit 141, error correction circuit 16 and memory array 15) of the original external read-modify-write operations. Only by making simple improvements to the memory array control circuit 141, internal read-modify-write operations can be performed on the stored data in the memory array 15 to realize the internal error detection / correction function.

[0063] In addition, the storage array control circuit 141 can also control the corresponding storage array 15 to perform external read-modify-write operations and normal read-write operations. Specifically, the storage array control circuit 141 can control the corresponding storage cells in the storage array to perform word line enable, charge sharing, data amplification, data reading, data writing, pre-charging and other operations in sequence according to information such as activation command signal, read / write command signal, pre-charge signal, row address, and column address, so as to realize the correct reading or writing of stored data.

[0064] For example, if four memory arrays 15 (BA0, BA1, BA2, BA3) share one error correction circuit 16, the logic control circuit 14 includes four memory array control circuits 141 (BA Logic0, BA Logic1, BA Logic2, BA Logic3), corresponding one-to-one with the four memory arrays 15. Each memory array control circuit 141 generates four sets of internal signals IRD / IWR (IRD0 / IWR0, IRD1 / IWR1, IRD2 / IWR2, IRD3 / IWR3), enabling the four memory arrays BA0, BA1, BA2, and BA3 in sequence. This ensures that the error correction circuit 16 performs internal read-modify-write operations on only one memory array 15 at a time. In the first time period T0, each memory array control circuit sends the first set of internal signals IRD0 / IWR0. At this time, memory array BA0 is enabled, while other memory arrays BA1, BA2, and BA3 are not enabled. The error correction circuit 16 only receives the signals from the corresponding memory array control circuit BA0. The first set of internal signals IRD0 / IWR0 sent by Logic0 controls an internal read-modify-write operation on the target memory cell in memory array BA0. In the second time period T1, each memory array control circuit sends the second set of internal signals IRD1 / IWR1. At this time, memory array BA1 is enabled, while other memory arrays BA0, BA2, and BA3 are disabled. Error correction circuit 16 only receives the second set of internal signals IRD1 / IWR1 sent by the corresponding memory array control circuit BA1, controlling an internal read-modify-write operation on the target memory cell in memory array BA1. Similarly, in the third time period T2, error correction circuit 16 only receives the third set of internal signals IRD2 / IWR2 sent by the corresponding memory array control circuit BA2, controlling an internal read-modify-write operation on the target memory cell in memory array BA2. In the third time period T3, error correction circuit 16 only receives the third set of internal signals IRD2 / IWR2 sent by the corresponding memory array control circuit BA2. The fourth set of internal signals IRD3 / IWR3 sent by Logic3 controls the execution of an internal read-modify-write operation on the target memory cell in memory array BA3. Thus, based on the set of internal signals sent by the corresponding memory array control circuit, the error correction circuit 16 sequentially performs an internal read-modify-write operation on the target memory cells in the four memory arrays BA0, BA1, BA2, and BA3.

[0065] Referring to Figure 3, it shows a schematic diagram of the layout of a storage array 15, a storage array control circuit 141, and an error correction circuit 16 provided in an embodiment of this disclosure. In the example shown in Figure 3, the storage region (also called the core region) includes 8 storage groups (Bank Groups, BG): BG0-BG7. Different storage groups can operate synchronously. Each storage group corresponds to an error correction circuit 16: ECC0-ECC7. Each storage group includes 4 storage arrays 15 (also called storage banks, BA): BA0, BA1, BA2, and BA3. The 4 storage arrays BA0, BA1, BA2, and BA3 in each storage group share one error correction circuit 16. Each storage bank in each storage group corresponds to a storage array control circuit 151 (also called storage bank logic circuit). Taking BA3 in BG1 as an example, storage array BA3 includes m rows: ROW0-ROWm, and storage array BA3 includes n columns: Col0-Coln. In Figure 3, a circle represents multiple storage units corresponding to a storage address. Specifically, in storage array BA3, multiple storage units can be located based on a storage address (including row address ROW0 and row address Col0). Each internal read-modify-write operation is for multiple storage units corresponding to a storage address in storage array 15.

[0066] In some embodiments, the internal command generation circuit 12 and the address generation circuit 13 are shared by all memory arrays 15 within the memory. That is, the internal error check command signal IMWRAB generated by the internal command generation circuit 12 and the internal error check address IMWR_AD (including the target row address Row_ad and the target column address Col_ad) generated by the address generation circuit 13 are sent to each memory array 15. Since different memory groups BG0-BG7 can operate synchronously, each memory group BG needs to be equipped with one control logic circuit 14 and one error correction circuit 16. Multiple memory arrays 15 within each memory group BG can share one control logic circuit 14 and one error correction circuit 16. Specifically, as shown in Figure 3, the storage area includes a total of 4*8=32 memory arrays 15, and the 32 memory arrays 15 in the 8 memory groups share one internal command generation circuit 12 and one address generation circuit 13. Each memory group (BG) corresponds to one control logic circuit 14 (including four memory array control circuits 141) and one error correction circuit 16. The eight memory groups correspond to eight control logic circuits 14 (32 memory array control circuits) and eight error correction circuits 16. The four memory arrays 15 in each memory group (BG) share one error correction circuit 16, and each memory array control circuit 141 controls one memory array.

[0067] It should be noted that a storage array can be a storage unit (BA), a storage group (BG), or a storage block. Here, we use a storage array as a storage unit (BA) as an example, but this does not constitute a limitation on the disclosure.

[0068] In some embodiments, as shown in Figures 1-2, the error correction circuit 16 is configured to read stored data RD_Data from the target storage cell according to the internal read signal IRD, and perform error detection and correction on the stored data RD_Data to generate corrected data WR_Data; the error correction circuit 16 is also configured to write the corrected data WR_Data into the target storage cell according to the internal write signal IWR.

[0069] It should be noted that, as shown in Figure 2, the error correction circuit 16 needs to perform an internal read-modify-write operation on multiple memory arrays 15 sequentially based on multiple sets of internal signals IRD / IWR. When performing the internal read-modify-write operation on each memory array 15, the error correction circuit 16 needs to perform the above-mentioned read-modify function (i.e., read the stored data RD_Data from the target memory cell according to the internal read signal IRD, and perform error detection and correction on the stored data RD_Data to generate correction data WR_Data) and write function (i.e., write the correction data WR_Data into the target memory cell according to the internal write signal IWR).

[0070] In some embodiments, as shown in FIG1, the internal command generation circuit 12 is further configured to generate and output an internal self-refresh command signal IMWRAB in response to each pulse on the self-refresh clock signal SR_CLK when the error check enable signal IMWR_EN indicates that the internal error check function is not enabled; and to generate and output an internal self-refresh command signal IMWRAB when the error check enable signal IMWR_EN indicates that the internal error check function is enabled and the count value of the self-refresh clock signal SR_CLK is not a first preset value.

[0071] It should be noted that, as mentioned earlier, when the error checking enable signal IMWR_EN is at an active level, it indicates that the internal error checking function is enabled. The internal command generation circuit 12 needs to periodically "steal" a pulse from the self-refresh clock signal SR_CLK to generate the internal error checking command signal IMWRAB. However, when the count value of the self-refresh clock signal SR_CLK is not the first preset value, or when the error checking enable signal IMWR_EN is at an inactive level, indicating that the internal error checking function is not enabled, it is not necessary to "steal" a pulse from the self-refresh clock signal SR_CLK to generate the internal error checking command signal IMWRAB. The internal command generation circuit 12 continues to generate and output an internal self-refresh command signal IREFAB based on the pulse from the self-refresh clock signal SR_CLK, and performs the original self-refresh operation related functions.

[0072] Referring to the signal timing diagram shown in Figure 4, the working principle of the internal error checking circuit 10 provided in this embodiment of the present disclosure will be explained in detail as follows:

[0073] At time t0, when the external self-refresh entry command SRE instructs the memory to enter the self-refresh state, the self-refresh enable signal SR_EN will be activated, that is, the self-refresh enable signal SR_EN will be flipped from low level to high level; the clock generation circuit 11 responds to the self-refresh enable signal SR_EN and starts to generate and output the self-refresh clock signal SR_CLK.

[0074] During the t0-t1 phase, the error checking enable signal IMWR_EN is at an invalid level (low level). At this time, the internal error checking function is not enabled. The internal command generation circuit 12 generates the internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK to control the memory array 15 to perform the original self-refresh operation.

[0075] At time t1, the error checking enable signal IMWR_EN flips to an active level (high level), at which point the internal error checking function is enabled, and the internal command generation circuit 12 begins to count the pulses on the self-refresh clock signal SR_CLK.

[0076] At time t2, when the count value of the pulse on the self-refresh clock signal SR_CLK reaches the first preset value for the first time, the first internal error check command signal IMWRAB is generated and the count value is reset.

[0077] During the t2-t3 phase, the address generation circuit 13 counts the row / column addresses of the memory array based on the received first internal error check command signal IMWRAB, and generates and outputs the target row address Row_ad = RA and the target column address Col_ad = CA+1 = 000000 (taking the column address as a 6-bit signal and the column address CA as the initial value 111111 as an example), which is the internal error check address IMWR_AD; the control logic circuit 14 (or the memory array control circuit 141) sets the operation flag signal IMWR_FLAG to an active level (high level) at time t3 based on the received internal error check command signal IMWRAB; here, the internal error check command signal IMWRAB actually refers to the pulse on the internal error check command signal;

[0078] It should be noted that the timing diagram shown in Figure 4 has taken into account the transmission delay between circuits and the delay inherent in the circuit devices themselves. Therefore, the change times of some associated signals are not completely aligned. Specifically, the internal error check command signal IMWRAB is generated at time t2, and the associated operation flag signal IMWR_FLAG is flipped from an invalid level to an active level at time t3, which is after time t2.

[0079] During the t3-t7 phase, the operation flag signal IMWR_FLAG is at an active level. The control logic circuit 14 (or the memory array control circuit 141) generates four sets of internal signals in sequence, that is, it alternately generates four internal read signals IRD and four internal write signals IWR to control the error correction circuit 16 to perform an internal read-modify-write operation on the four memory arrays 15 in sequence. Here, the example of four memory arrays 15 (BA0-BA3) sharing one error correction circuit 16 is given and is not intended to be limiting.

[0080] Specifically, during the t3-t4 phase, the count value IWR_cnt of the internal write signal is initially 00. At this time, the memory array BA0 is enabled, while the memory arrays BA1-BA3 are not enabled. The error correction circuit 16 receives the first set of internal signals sent by the control logic circuit 14 (or only receives the corresponding memory array control circuit 141), namely, the internal read signal IRD and the internal write signal IWR sent during the t3-t4 phase. Based on this first set of internal signals, the error correction circuit 16 performs an internal read-modify-write operation on the memory array BA0. At time t4, based on the first rising edge of the inverted signal IWRB of the internal write signal, the count value IWR_cnt of the internal write signal is... The signal changes from 00 to 01, at which point storage array BA1 is enabled, while other storage arrays are disabled. During t4-t5, error correction circuit 16 receives the second set of internal signals sent by control logic circuit 14 (or only receives the corresponding storage array control circuit 141). Error correction circuit 16 performs an internal read-modify-write operation on storage array BA1 based on the second set of internal signals. Similarly, during t5-t6, error correction circuit 16 performs an internal read-modify-write operation on storage array BA2 based on the third set of internal signals. During t6-t7, error correction circuit 16 performs an internal read-modify-write operation on storage array BA3 based on the fourth set of internal signals.

[0081] Until time t8, based on the last rising edge of the inverted signal IWRB of the internal write signal, the count value IWR_cnt of the internal write signal changes from 11 to 00, and the operation end signal IMWR_END generates a rising edge, that is, it toggles from invalid level (low level, logic "0") to valid level (high level, logic "1"); based on the rising edge of the operation end signal IMWR_END, the operation flag signal IMWR_FLAG toggles from valid level to invalid level. At this point, the entire internal read-modify-write operation is completed.

[0082] At time t9, when the count value of the pulse on the self-refresh clock signal SR_CLK reaches the first preset value again, the second internal error check command signal IMWRAB is generated and the count value is reset; the address generation circuit 13 counts the row / column addresses of the storage array according to the second internal error check command signal IMWRAB. Specifically, the column address is "+1" to generate and output the target column address Col_ad = CA+2 = 000001, while the target row address Row_ad = RA remains unchanged.

[0083] Until time t10, when the count value of the pulse on the self-refresh clock signal SR_CLK reaches the first preset value for the nth time, the nth internal error check command signal IMWRAB is generated. Assuming n is 64, the address generation circuit 13 performs the 64th "+1" operation on the column address, generates and outputs the target column address Col_ad = 111111, and the target row address Row_ad = RA remains unchanged. At this time, it indicates that the address generation circuit 13 has traversed all column addresses (Col_ad = 000000 to Col_ad = 111111) in the RA row of the memory array 15. The error correction circuit 16 will perform an internal read-modify-write operation on the memory cell corresponding to the last column address CA = 111111 in the RA row.

[0084] It should be noted that the address generation circuit 13 needs to synchronously sample and output the target row address Row_ad and target column address Col_ad based on the internal error checking command signal IMWRAB each time. The row count value Row_cnt changes based on the currently generated target column address Col_ad. That is, the target row address Row_ad output by the address generation circuit 13 each time corresponds to the previous target column address Col_ad. Since the next internal error checking command signal IMWRAB will instruct the error correction circuit 16 to perform an internal read-modify-write operation on the memory cell corresponding to the first column address Col_ad = 000000 in the next row RA+1 of the memory array 15, when the currently generated target column address Col_ad = 111111, the row count value Row_cnt needs to be set to RA+1 so that when the next internal error checking command signal IMWRAB is received, the address generation circuit 13 can synchronously sample and output the correct target row address Row_ad = RA+1 and target column address Col_ad = 000000.

[0085] In some embodiments, as shown in FIG1, the control logic circuit 14 is further configured to control the execution of a self-refresh operation on all memory arrays 15 after the control error correction circuit 16 sequentially performs an internal read-modify-write operation on the target memory cell corresponding to the internal error check address IMWR_AD in the plurality of memory arrays 15.

[0086] It should be noted that when the error checking enable signal IMWR_EN indicates that the internal error checking function is enabled, the internal command generation circuit 12 needs to periodically "steal" a pulse from the self-refresh clock signal SR_CLK to generate the internal error checking command signal IMWRAB. At this time, the internal self-refresh command signal IREFAB is no longer generated based on the pulse from the "stolen" self-refresh clock signal SR_CLK. At this time, the control logic circuit 14 can no longer perform the self-refresh operation based on the internal self-refresh command signal IREFAB, which is equivalent to performing one less self-refresh operation. In order to ensure that the introduction of the internal error checking function does not affect the original self-refresh function, after the control logic circuit 14 completes the internal read-modify-write operation based on the internal error checking command signal IMWRAB, it can immediately perform a self-refresh operation on all memory arrays 141 (without waiting for the next pulse of the self-refresh clock signal SR_CLK), which is equivalent to making up for the impact of the internal error checking operation on the original self-refresh function.

[0087] In some embodiments, as shown in FIG5, the address generation circuit 13 includes a column address generation circuit 131, a first decoding circuit 132, and a row address generation circuit 133.

[0088] The column address generation circuit 131 is configured to receive the internal error check command signal IMWRAB, count the columns of the current storage row according to the internal error check command signal IMWRAB, and generate and output the target column address Col_ad.

[0089] The first decoding circuit 132 is configured to decode the target column address Col_ad, and generate and output a column end signal Col_End when the target column address Col_ad indicates that the column count of the current storage row has been completed.

[0090] The row address generation circuit 133 is configured to receive the column end signal Col_End and the internal error check command signal IMWRAB, and to perform row counting on the memory array according to the column end signal Col_End, thereby generating and outputting the target row address signal Row_ad.

[0091] Taking the storage area shown in Figure 3 as an example, the working principle of the address generation circuit 13 will be explained in conjunction with Figures 4 and 5. The column address generation circuit 131 can sequentially traverse all column addresses (Col_ad = 000000 to Col_ad = 111111) of each row in the memory array 15. Each time, it performs a "+1" count on the current column address based on the internal error checking command signal IMWRAB to generate and output the target column address Col_ad. This continues until the currently generated target row address Row_ad = RA and the target column address Col_ad = 111111, as shown at time t10 in Figure 4. This indicates that the column address generation circuit 131 has completed the traversal and counting of all column addresses (Col_ad = 000000 to Col_ad = 111111) of the current row RA in the memory array 15. At this time, the first decoding circuit 132 decodes the current target column address Col_ad = 111111 and outputs the column end signal Col_End to instruct the row address generation circuit 133 to perform a "+1" count on the current row address to generate and output the new target row address RA+1. Meanwhile, the column address generation circuit 131 will still increment the target column address Col_ad = 111111 by "+1" to obtain a new target column address Col_ad = 000000, so as to indicate that a read-modify-write operation will be performed on the memory cell corresponding to the first column address of the next row RA+1.

[0092] Referring to Figures 1, 5, and 6, the working principle of the internal error checking circuit 10 in this embodiment of the present disclosure, which performs a self-refresh operation after the internal read-modify-write operation is completed, is explained as follows:

[0093] At time t11, similar to Figure 4, when the external self-refresh entry command SRE indicates that the memory enters the self-refresh state, the self-refresh enable signal SR_EN is activated, and the clock generation circuit 11 starts to generate and output the self-refresh clock signal SR_CLK.

[0094] During the t11-t13 phase, the error checking enable signal IMWR_EN is at an invalid level, and the internal error checking function is not enabled. The internal command generation circuit 12 generates an internal self-refresh command signal IREFAB based on each pulse on the self-refresh clock signal SR_CLK to control the memory array 15 to perform a self-refresh operation. Specifically, at time t13, the internal command generation circuit 12 generates an internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK. At the same time, the address generation circuit 13 (or refresh address generation circuit 136) also counts rows of the memory array based on the internal self-refresh command signal IREFAB, generates and outputs the self-refresh address S_RA, and the control logic circuit 14 (or memory array control circuit 141) controls the self-refresh operation to be performed on the memory rows corresponding to the self-refresh address S_RA in all memory arrays 15.

[0095] At time t13, the error check enable signal IMWR_EN flips to the active level, at which point the internal error check function is enabled, and the internal command generation circuit 12 begins to count the pulses on the self-refresh clock signal SR_CLK.

[0096] During the t14-t16 phase, when the count value of the pulse on the self-refresh clock signal SR_CLK reaches the first preset value for the first time (taking the first preset value as m as an example), after the internal command generation circuit 12 generates the internal error check command signal IMWRAB, the address generation circuit 13 and the control logic circuit 14 (or the memory array control circuit 141) control the error correction circuit 16 to perform an internal read-modify-write operation on multiple memory arrays 15 in sequence. The timing is the same as shown in Figure 4, and can be referred to the above content, which will not be repeated here.

[0097] It should be noted that during the t13-t14 phase, before the internal read-modify-write operation is performed (i.e., before the pulse count on the self-refresh clock signal SR_CLK first reaches the first preset value m), the internal command generation circuit 12 has already generated m-1 self-refresh command signals IREFAB. Correspondingly, the address generation circuit 13 (or refresh address generation circuit 136) also performs m-1 "+1" counts on the self-refresh address SREF_Row based on the m-1 self-refresh command signals IREFAB, and the self-refresh address SREF_Row becomes S_RA+m-1. When performing another self-refresh operation after the internal read-modify-write operation is completed, to avoid this self-refresh... The operation repeats the self-refresh operation on the previous self-refresh address S_RA+m-1. The address generation circuit 13 (or refresh address generation circuit 136) also needs to increment the self-refresh address SREF_Row by "1" to output the self-refresh address SREF_Row corresponding to this self-refresh operation. However, since the internal command generation circuit 12 does not generate the self-refresh command signal IREFAB, at time t14, the address generation circuit 13 (or refresh address generation circuit 136) can increment the self-refresh address SREF_Row by "1" based on the internal error checking command signal IMWRAB and output the new self-refresh address SREF_Row = S_RA+m.

[0098] At time t16, the operation flag signal IMWR_FLAG flips from an active level to an inactive level, indicating that all memory arrays 15 have completed this internal read-modify-write operation. At this time, in response to the falling edge of the operation flag signal IMWR_FLAG, the control logic circuit 14 (specifically, the self-refresh control circuit 147 in the memory array control circuit 141) flips the self-refresh window signal SREF_WIN from an inactive level (low level, logic "0") to an active level (high level, logic "1"). Based on the active self-refresh window signal SREF_WIN and the received self-refresh address S_RA+m, the control logic circuit 14 (specifically, the self-refresh control circuit 147 in the memory array control circuit 141) controls the memory array 15 to perform a self-refresh operation.

[0099] In some embodiments, as shown in FIG7, the row address generation circuit 133 includes: a row counting circuit 134 configured to receive a column end signal Col_End, and count rows in the storage array 15 according to the column end signal Col_End, generating and outputting a row count value Row_cnt; and a row address sampling circuit 135 configured to receive an internal error checking command signal IMWRAB and the row count value Row_cnt, and sample the row count value Row_cnt in response to the internal error checking command signal IMWRAB, generating and outputting a target row address signal Row_ad.

[0100] It should be noted that after the control logic circuit 14 (or the memory array control circuit 141) receives the internal error checking command signal IMWRAB, it still needs to wait for the corresponding internal error checking address (i.e., the target row address Row_ad and the target column address Col_ad) before it can control the error correction circuit 16 to perform the internal read-modify-write operation. In order not to affect the original external read-modify-write operation timing requirements of the memory, the column address generation circuit 131 and the row address generation circuit 133 need to synchronously sample and output the target row address Row_ad and the target column address Col_ad based on the internal error checking command signal IMWRAB each time. This can ensure that the time of outputting the target row address Row_ad and the target column address Col_ad is less delayed than that of the internal error checking command signal IMWRAB.

[0101] It should also be noted that the row counting circuit 134 performs row counting on the column end signal Col_End to generate a row count value Row_cnt. The row count value Row_cnt changes based on the currently generated target column address Col_ad, and the target column address Col_ad changes based on the internal error check command signal IMWRAB. Therefore, before the row count value Row_cnt changes, the row address sampling circuit 135 has already sampled the row count value Row_cnt based on the internal error check command signal IMWRAB and output the target row address Row_ad. That is, the target row address Row_ad output by the row address sampling circuit 135 each time corresponds to the previous target column address Col_ad output by the row address generation circuit 131.

[0102] In some embodiments, as shown in FIG5, the address generation circuit 13 further includes a refresh address generation circuit 136, configured to receive an internal self-refresh command signal IREFAB, and perform row counting on the memory array 15 according to the internal self-refresh command signal IREFAB, generate and output a self-refresh address SREF_Row; the control logic circuit 14 is further configured to control the execution of a refresh operation on all memory arrays based on the self-refresh address SREF_Row.

[0103] It should be noted that the refresh operation is performed on one or more rows of the storage array 15. Therefore, the refresh address generation circuit 136 does not need to traverse and count the column addresses, but only needs to complete the traversal and count of the row addresses. The self-refresh address SREF_Row only includes the row address information.

[0104] In some embodiments, referring to FIG5, the address generation circuit 13 further includes a refresh address generation circuit 136, configured to receive an internal self-refresh command signal IREFAB or an internal error check command signal IMWRAB, and perform row counting on the storage array 15 according to the internal self-refresh command signal IREFAB or the internal error check command signal IMWRAB, and generate and output a self-refresh address SREF_Row.

[0105] Referring to Figure 6, at time t16, when the control logic circuit 14 performs a self-refresh operation after completing the internal read-modify-write operation, the refresh address generation circuit 136, which includes the address generation circuit 13, also needs to synchronously output the self-refresh address SREF_Row corresponding to the self-refresh operation to the control logic circuit 14. If the refresh address generation circuit 136 only counts rows of the memory array based on the internal self-refresh command signal IREFAB, but because the current pulse of the self-refresh clock signal SR_CLK is "stolen" to generate the internal error check command signal IMWRAB instead of generating the internal self-refresh command signal IREFAB, the refresh address generation circuit 136 cannot generate a new self-refresh address based on the internal self-refresh command signal IREFAB. It will still output the self-refresh address S_RA corresponding to the previous self-refresh operation (the refresh operation before time t10), resulting in the memory cell at the same row address being refreshed twice. Therefore, in this case, the refresh address generation circuit 136 can be configured to simultaneously receive the internal error check command signal IMWRAB and the internal self-refresh command signal IREFAB, and perform row counting on the memory array according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, generating and outputting the self-refresh address SREF_Row. That is, regardless of whether the internal command address generation circuit 12 generates the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, the refresh address generation circuit 136 can perform a row counting on the memory array once. For example, at time t10, the refresh address generation circuit 136 can generate a new self-refresh address S_RA+m based on the internal error check command signal IMWRAB, so as to ensure that at time t16, after the internal read-modify-write operation, a self-refresh operation can be performed on the new self-refresh address S_RA+m, avoiding performing two self-refresh operations on the same row address at time t15.

[0106] In some embodiments, the memory array control circuit 141 can control multiple memory rows of the memory array 15 to perform a refresh operation simultaneously. In this case, the refresh address generation circuit 136 can output multiple self-refresh addresses simultaneously. Each time, the memory array is counted according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, and it may not be a +1 count. For example, based on the parameter configuration in the mode register, the memory array control circuit 141 can perform a refresh operation on 4 memory rows simultaneously. Each time, the refresh address generation circuit 136 counts the memory array by +4 according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB. If the 4 self-refresh addresses corresponding to the previous self-refresh operation are S_RA, S_RA+1, S_RA+2, and S_RA+3, the 4 self-refresh addresses output this time are S_RA+4, S_RA+5, S_RA+6, and S_RA+7. Of course, if the storage rows of the storage array are divided into 4 groups, with P storage rows in each group, the refresh address generation circuit 136 can also increment the row count by 1 each time. When the 4 self-refresh addresses corresponding to the previous self-refresh operation are S_RA, S_RA+P, S_RA+2P, and S_RA+3P, the 4 self-refresh addresses output this time are S_RA+1, S_RA+P+1, S_RA+2P+1, and S_RA+3P+1.

[0107] In some embodiments, as shown in Figures 8-9, the column address generation circuit 131 includes N cascaded first flip-flops DFF1, where N is an integer greater than or equal to 1; the clock control terminal of the first-stage first flip-flop DFF1 serves as the input terminal of the column address generation circuit 131, receiving the internal error check command signal IMWRAB; the inverted output terminal of each stage of the first flip-flop DFF1 is connected to its own data input terminal; the clock control terminals of the other first flip-flops DFF1 besides the first-stage first flip-flop DFF1 are all connected to the inverted output terminal of the previous stage's first flip-flop DFF1; the non-inverted output terminals of the N first flip-flops DFF1 jointly output the target column address Col_ad; the first decoding circuit includes a first NAND gate 137, the N input terminals of the first NAND gate 137 are respectively connected to the non-inverted output terminals of the N first flip-flops DFF1, and the output terminal of the first NAND gate 137 is used to output the column end signal.

[0108] Figures 8 and 9 illustrate this with N=6 as an example, meaning the target column address Col_ad<5:0> includes 6 bits of information, but this does not constitute a limitation of this disclosure.

[0109] It should be noted that the column address generation circuit 131 shown in Figure 8 is a synchronous binary counter. In some other embodiments, the column address generation circuit 131 can also be implemented by an asynchronous binary counter, which is not specifically limited here. The first decoding circuit 132 shown in Figure 9 outputs the column count signal Col_End when Col_ad<5:0> is 111111, that is, it traverses and counts the target column address Col_ad<5:0> in the order of CA=000000 to CA=111111. In some other embodiments, it can also traverse and count in other orders. Specifically, it can traverse and count the target column address Col_ad<5:0> in the order of CA=100000 to CA=011111. In this case, the first decoding circuit 132 outputs the column count signal Col_End when Col_ad<5:0> is 011111.

[0110] In some embodiments, as shown in FIG10, the row counting circuit 134 includes M cascaded second flip-flops DFF2, where M is an integer greater than or equal to 1; the clock control terminal of the first-stage second flip-flop DFF2 serves as the input terminal of the row counting circuit 134, receiving the column end signal Col_End; the inverted output terminal of each stage of the second flip-flop DFF2 is connected to its own data input terminal; the clock control terminals of the other second flip-flops DFF2 besides the first-stage second flip-flop DFF2 are all connected to the inverted output terminal of the previous stage of the second flip-flop DFF2; the non-inverted output terminals of the M second flip-flops DFF2 jointly output the row count value Row_cnt; the row address sampling circuit 135 includes M third flip-flops DFF3; the clock control terminal of each third flip-flop DFF3 receives the internal error check command signal IMWRAB; the data input terminals of the M third flip-flops DFF3 are connected one-to-one with the non-inverted output terminals of the M second flip-flops DFF2, receiving the row count value Row_cnt; the non-inverted output terminals of the M third flip-flops DFF3 jointly output the target row address Row_ad.

[0111] It should be noted that Figure 10 uses M=15 as an example, meaning that both the row count value Row_cnt<14:0> and the target row address Row_ad<14:0> include 15 bits of information, but this does not constitute a limitation of this disclosure; the row counting circuit 134 shown in Figure 10 is a synchronous binary counter. In some other embodiments, the row counting circuit 134 can also be implemented by an asynchronous binary counter, which is not specifically limited here.

[0112] In some embodiments, as shown in FIG11, the storage array control circuit 141 includes: an identification signal generation circuit 142 configured to receive an internal error check command signal IMWRAB, and in response to the internal error check command signal IMWRAB, generate and output an operation identification signal IMWR_FLAG at an active level; a read / write command generation circuit 143 configured to receive the operation identification signal IMWR_FLAG and the internal error check command signal IMWRAB, and in response to the internal error check command signal IMWRAB, sequentially generate multiple sets of internal signals while the operation identification signal IMWR_FLAG is at an active level; the identification signal generation circuit 142 is further configured to receive an internal write signal IWR, and when the count value of the internal write signal IWR reaches a second preset value, set the operation identification signal IMWR_FLAG to an inactive level.

[0113] It should be noted that the second preset value is related to the number of multiple memory arrays 15 that share the error correction circuit 16 in each memory group BG. That is, it ensures that the multiple sets of internal signals (internal read signal IRD and internal write signal IWR) generated and output by the read / write command generation circuit 143 can control the error correction circuit 16 to perform an internal read-modify-write operation on each of the multiple memory arrays 15 in sequence.

[0114] In some embodiments, as shown in FIG12, the identifier signal generation circuit 142 includes: a command counting circuit 144 configured to count the inverted signal of the internal write signal IWR to generate and output the count value of the internal write signal IWR; a second decoding circuit 145 configured to receive the count value of the internal write signal IWR and generate and output an operation end signal IMWR_END when the count value of the internal write signal IWR is a second preset value; and an SR flip-flop 146 configured to receive an internal error check command signal IMWRAB and an operation end signal IMWR_END, and in response to the internal error check command signal IMWRAB, set the operation identifier signal IMWR_FLAG to an active level, and set the operation identifier signal IMWR_FLAG to an inactive level when the count value of the internal write signal IWR reaches the second preset value.

[0115] For example, as shown in Figures 3 and 4, if each memory group BG includes one error correction circuit 16 and four memory arrays 15 (BA0, BA1, BA2, BA3), then the second preset value is 4 (represented by binary "00"). That is, the read / write command generation circuit 143 needs to generate four sets of internal signals during the period when the operation flag signal IMWR_FLAG is at the active level. At time t3, the SR flip-flop 146 in the flag signal generation circuit 142 sets the operation flag signal IMWR_FLAG to the active level (high level) according to the received internal error check command signal IMWRAB. Subsequently, during the period when the operation flag signal IMWR_FLAG is at the active level, i.e., the t3-t7 stage, four internal read signals IRD and four internal write signals IWR are alternately generated, respectively denoted as a set of internal signals IRD1 and IWR1 corresponding to BA0 (in the t3-t4 stage), and a set of internal signals IRD2 and IWR2 corresponding to BA1 (in the t4-t5 stage). A set of internal signals IRD3 and IWR3 corresponding to BA2 (in the t5-t6 stage), and a set of internal signals IRD4 and IWR4 corresponding to BA3 (in the t6-t7 stage), are used to control the error correction circuit 16 to perform one internal read-modify-write operation on the stored data corresponding to the internal error check address in the four storage arrays 15 in sequence. Each internal read-modify-write operation first reads the stored data RD_Data according to the internal read signal IRD, and performs error detection and correction operations. Then, according to the internal write signal IWR, the corrected data WR_Data after error detection and correction is written into the storage array. To ensure that all memory arrays complete the internal read-modify-write operation normally, the command counting circuit 144 needs to count the internal write signal IWR or its inverted signal IWRB. At time t7, the counting is based on the last rising edge of the inverted signal IWRB. When the count value IWR_cnt of the internal write signal output by the command counting circuit 144 is the second preset value 4 (represented by binary "00"), the error correction circuit 16 has written the corresponding correction data into the corresponding memory array BA3 according to the last internal write signal IWR4. The second decoding circuit 145 will output IMWR_END to indicate that all memory arrays 15 have completed the internal read-modify-write operation. At this time, the operation flag signal IMWR_FLAG can be set to an invalid level to stop the generation of the internal signal IRD / IWR.

[0116] It should be noted that, in order to ensure that the last write operation performed by the error correction circuit 16 according to the internal write signal IWR4 is completed normally, the inverted signal IWRB of the internal write signal can be counted to generate the count value IWR_cnt of the internal write signal. This scheme can ensure that when the count value of the internal write signal reaches the second preset value 4 (that is, at time t7 in Figure 4, the fourth rising edge of IWRB corresponds to the fourth falling edge of IWR), the error correction circuit 16 has completed the last write operation according to the internal write signal IWR (valid level, high level "1"). At this time, even if the operation flag signal IMWR_FLAG is set to an invalid level, and the control read / write command generation circuit 143 no longer generates the internal signal IRD / IWR, it will not affect the last internal read-modify-write operation performed by the error correction circuit 16.

[0117] It should also be noted that the internal write signal count value IWR_cnt shown in Figure 4 is represented by a 2-bit signal. The second preset value = 4 corresponds to the signal "00", which is exactly the initial value of the internal write signal count value IWR_cnt. Therefore, after setting the operation flag signal IMWR_FLAG to an invalid level, it is not necessary to reset the internal write signal count value IWR_cnt. However, in some other embodiments, the internal write signal count value IWR_cnt is represented by a 3-bit signal. The second preset value = 4 corresponds to the signal "100". In this case, after the operation flag signal IMWR_FLAG is set to an invalid level, it is necessary to reset the internal write signal count value IWR_cnt to the initial value 000.

[0118] In some embodiments, as shown in FIG14, the read / write command generation circuit 143 includes: a second NAND gate 1431, the first input of which receives an operation flag signal IMWR_FLAG, and the second input of which receives an internal error check command signal IMWRAB; a first NOR gate 1432, the first input of which is electrically connected to the output of the second NAND gate 1431, and the output of the first NOR gate 1432 is used to output an internal read signal IRD; and a second NOR gate 1433, the first input of which is electrically connected to the output of the first NOR gate 1432, and the output of the second NOR gate 1433 is electrically connected to the second input of the first NOR gate 1432. The circuit includes: a delay unit 1434, whose input is electrically connected to the output of a first NOR gate 1432; a first NOT gate 1435, whose input is electrically connected to the output of the delay unit 1434, and whose output is electrically connected to the second input of a second NOR gate 1433; a second NOT gate 1436, whose input receives the operation flag signal IMWR_FLAG; and a third NOR gate 1437, whose first input is electrically connected to the output of the second NOT gate 1436, whose second input is electrically connected to the output of the first NOR gate 1432, and whose output is used to output the internal write signal IWR.

[0119] It should be noted that the delay time of the delay unit 1434 for the input signal is equal to the pulse width of the internal read signal IRD and the internal write signal IWR. Here, it is illustrated by assuming that the delay time, the pulse width of the internal write signal IWR, and the pulse width of the internal read signal IRD are all 2ns. In some embodiments, the delay time of the delay unit 1434 can also be adjusted. Specifically, the delay time of the delay unit 1434 can be adjusted according to the timing requirements of the internal read-modify-write operation, that is, ensuring that within the pulse width of the internal read signal IRD, the error correction circuit 16 can complete the reading, error detection, and error correction operations of the stored data of the target storage cell of the storage array 15, and within the pulse width of the internal write signal IWR, the error correction circuit 16 can write the corrected data after error detection and correction into the target storage cell of the storage array 15. In some embodiments, the pulse width of the internal write signal IWR and the pulse width of the internal read signal IRD can also be different, which is not limited here.

[0120] In some embodiments, as shown in FIG13, the storage array control circuit 141 further includes a self-refresh control circuit 147, configured to receive an operation identifier signal IMWR_FLAG and a self-refresh address SREF_Row, and control the corresponding storage array 15 to perform a refresh operation according to the self-refresh address SREF_Row when the operation identifier signal IMWR_FLAG flips to an invalid level.

[0121] In some embodiments, as shown in FIG15, the error correction circuit 16 is further configured to generate and output an error flag signal Error flag when an error exists in the stored data RD_Data in the target storage unit during an internal read-modify-write operation on the target storage unit; the internal error checking circuit 10 further includes an error register 17, configured to receive the internal error checking address IMWR_AD and the error flag signal Error flag, and to store the internal error checking address IMWR_AD in response to the error flag signal Error flag.

[0122] It should be noted that the error register 17 can be a reserved mode register in the memory. It stores the internal error check address IMWR_AD according to the error flag signal. The memory can perform various repair operations based on the stored error information, or it can periodically provide the stored error information to the memory controller. The memory controller can perform redundant repair processing based on the error signal, or it can skip the storage address where the data error occurred during the next read / write operation, thereby protecting the accuracy of the data and providing stability to the storage system.

[0123] In another embodiment of this disclosure, referring to FIG16, a schematic diagram of the composition structure of a memory 20 provided in an embodiment of this disclosure is shown. As shown in FIG16, the memory 20 may include the internal error checking circuit 10 of any of the foregoing embodiments.

[0124] In some embodiments, the memory 20 may include DRAM.

[0125] It should be noted that the embodiments disclosed herein introduce an internal error checking circuit design into DRAM LPDDR series chips and DRAM DDR4 chips, realizing a new function similar to ECS operation in DDR5. Furthermore, the memory error checking circuit 10 reuses the original clock generation circuit, operation circuit and path for executing external read-modify-write commands for self-refresh operations, without affecting the timing of the original self-refresh operations and external read-modify-write operations. Moreover, only simple improvements are needed to the original internal command generation circuit, address generation circuit and control logic circuit to realize periodic data error detection / correction operations for multiple memory arrays. Under the premise of implementing an internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area of ​​the DRAM chip is saved.

[0126] In this embodiment of the disclosure, the DRAM can conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, without any limitation.

[0127] In this embodiment of the disclosure, the memory 20 includes the internal error checking circuit 10 of any of the foregoing embodiments, thereby enabling internal error checking operations on the memory and improving the performance of the memory.

[0128] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0129] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0130] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0131] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0132] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An internal error checking circuit (10), comprising: Clock generation circuit (11), internal command generation circuit (12), address generation circuit (13), control logic circuit (14) and error correction circuit (16); The clock generation circuit (11) is configured to generate and output a self-refresh clock signal (SR_CLK) in response to the self-refresh enable signal (SR_EN). The internal command generation circuit (12) is configured to receive the self-refresh clock signal (SR_CLK) and the error checking enable signal (IMWR_EN), count the self-refresh clock signal (SR_CLK) when the error checking enable signal (IMWR_EN) indicates that the internal error checking function is enabled, and generate and output an internal error checking command signal (IMWRAB) when the count value (IWR_cnt) of the self-refresh clock signal (SR_CLK) is a first preset value. The address generation circuit (13) is configured to receive the internal error check command signal (IMWRAB) and count the internal error check command signal (IMWRAB) to generate and output the internal error check address (IMWR_AD). The control logic circuit (14) is configured to receive the internal error checking command signal (IMWRAB) and the internal error checking address (IMWR_AD), and in response to the internal error checking command signal (IMWRAB), control the error correction circuit (16) to perform an internal read-modify-write operation on the target storage cell corresponding to the internal error checking address (IMWR_AD) in the multiple storage arrays (15) in sequence; The plurality of storage arrays (15) share the error correction circuit (16).

2. The internal error checking circuit (10) as described in claim 1, wherein, The control logic circuit (14) includes multiple memory array control circuits (141), and the multiple memory array control circuits (141) correspond one-to-one with the multiple memory arrays (15); Each of the memory array control circuits (141) is configured to receive the internal error checking command signal (IMWRAB) and the internal error checking address (IMWR_AD), generate multiple sets of internal signals (IRD / IWR) in sequence in response to the internal error checking command signal (IMWRAB), and control the error correction circuit (16) to perform an internal read-modify-write operation on the target memory cell in the corresponding memory array (15) according to the corresponding set of internal signals (IRD / IWR) when the corresponding memory array (15) is in the enabled state. Each set of internal signals (IRD / IWR) includes an internal read signal (IRD) and an internal write signal (IWR).

3. The internal error checking circuit (10) as described in claim 2, wherein, The error correction circuit (16) is configured to read stored data from the target storage cell according to the internal read signal (IRD), and perform error detection and correction on the stored data to generate correction data; The error correction circuit (16) is further configured to write the correction data into the target storage unit according to the internal write signal (IWR).

4. The internal error checking circuit (10) as described in any one of claims 1-3, wherein, The internal command generation circuit (12) is further configured to generate and output an internal self-refresh command signal (IREFAB) in response to each pulse on the self-refresh clock signal (SR_CLK) when the error check enable signal (IMWR_EN) indicates that the internal error check function is not enabled; and to generate and output an internal self-refresh command signal (IREFAB) when the error check enable signal (IMWR_EN) indicates that the internal error check function is enabled and the count value (IWR_cnt) of the self-refresh clock signal (SR_CLK) is not a first preset value.

5. The internal error checking circuit (10) as described in any one of claims 1-4, wherein, The control logic circuit (14) is further configured to control the error correction circuit (16) to perform an internal read-modify-write operation on the target storage cell corresponding to the internal error check address (IMWR_AD) in the multiple storage arrays (15) in sequence, and then control the self-refresh operation to be performed on all storage arrays (15).

6. The internal error checking circuit (10) as described in claim 2, wherein, The address generation circuit (13) includes a column address generation circuit (131), a first decoding circuit (132), and a row address generation circuit (133); The column address generation circuit (131) is configured to receive the internal error checking command signal (IMWRAB), count the columns of the current storage row according to the internal error checking command signal (IMWRAB), and generate and output the target column address (Col_ad); The first decoding circuit (132) is configured to decode the target column address (Col_ad) and generate and output a column end signal (Col_End) when the target column address (Col_ad) indicates that the column count of the current storage row is complete. The row address generation circuit (133) is configured to receive the column end signal (Col_End) and the internal error check command signal (IMWRAB), and to perform row counting on the storage array (15) according to the column end signal (Col_End) to generate and output the target row address (Row_ad) signal.

7. The internal error checking circuit (10) as described in claim 6, wherein, The row address generation circuit (133) includes: The row counting circuit (134) is configured to receive the column end signal (Col_End), count rows in the storage array (15) according to the column end signal (Col_End), and generate and output the row count value (Row_cnt); The row address sampling circuit (135) is configured to receive the internal error checking command signal (IMWRAB) and the row count value (Row_cnt), and to sample the row count value (Row_cnt) in response to the internal error checking command signal (IMWRAB) to generate and output the target row address (Row_ad) signal.

8. The internal error checking circuit (10) as described in claim 6, wherein, The address generation circuit (13) further includes a refresh address generation circuit (136), configured to receive the internal self-refresh command signal (IREFAB), and perform row counting on the storage array (15) according to the internal self-refresh command signal (IREFAB), generate and output a self-refresh address (SREF_Row). The control logic circuit (14) is further configured to control all memory arrays (15) to perform a refresh operation based on the self-refresh address (SREF_Row).

9. The internal error checking circuit (10) as described in claim 6, wherein, The column address generation circuit (131) includes N cascaded first flip-flops (DFF1), where N is an integer greater than or equal to 1; the clock control terminal of the first stage first flip-flop (DFF1) serves as the input terminal of the column address generation circuit (131) and receives the internal error check command signal (IMWRAB); the inverted output terminal of each stage first flip-flop (DFF1) is connected to its own data input terminal; the clock control terminals of the other first flip-flops (DFF1) besides the first stage first flip-flop (DFF1) are all connected to the inverted output terminal of the previous stage first flip-flop (DFF1); the non-inverted output terminals of the N first flip-flops (DFF1) jointly output the target column address (Col_ad); The first decoding circuit (132) includes a first NAND gate (137), the N input terminals of the first NAND gate (137) are respectively connected to the positive output terminals of the N first flip-flops (DFF1), and the output terminal of the first NAND gate (137) is used to output the column end signal (Col_End).

10. The internal error checking circuit (10) as claimed in claim 7, wherein, The row counting circuit (134) includes M cascaded second flip-flops (DFF2), where M is an integer greater than or equal to 1; the clock control terminal of the first-stage second flip-flop (DFF2) serves as the input terminal of the row counting circuit (134) and receives the column end signal (Col_End); the inverted output terminal of each stage of the second flip-flop (DFF2) is connected to its own data input terminal; the clock control terminals of the other second flip-flops (DFF2) besides the first-stage second flip-flop (DFF2) are all connected to the inverted output terminal of the previous stage of the second flip-flop (DFF2); the non-inverted output terminals of the M second flip-flops (DFF2) jointly output the row count value (Row_cnt); The row address sampling circuit (135) includes M third flip-flops (DFF3); the clock control terminal of each third flip-flop (DFF3) receives the internal error check command signal (IMWRAB); the data input terminals of the M third flip-flops (DFF3) are connected one-to-one with the non-inverting output terminals of the M second flip-flops (DFF2) to receive the row count value (Row_cnt); the non-inverting output terminals of the M third flip-flops (DFF3) jointly output the target row address (Row_ad).

11. The internal error checking circuit (10) as described in claim 2, wherein, The storage array control circuit (141) includes: The identification signal generation circuit (142) is configured to receive the internal error check command signal (IMWRAB) and, in response to the internal error check command signal (IMWRAB), generate and output an operation identification signal (IMWR_FLAG) at an active level. The read / write command generation circuit (143) is configured to receive the operation identifier signal (IMWR_FLAG) and the internal error check command signal (IMWRAB), and in response to the internal error check command signal (IMWRAB), sequentially generate multiple sets of internal signals (IRD / IWR) during the period when the operation identifier signal (IMWR_FLAG) is at an active level. The identification signal generation circuit (142) is further configured to receive the internal write signal (IWR) and set the operation identification signal (IMWR_FLAG) to an invalid level when the count value (IWR_cnt) of the internal write signal (IWR) reaches a second preset value.

12. The internal error checking circuit (10) as claimed in claim 11, wherein, The identification signal generation circuit (142) includes: The command counting circuit (144) is configured to count the inverted signal of the internal write signal (IWR) to generate and output the count value (IWR_cnt) of the internal write signal (IWR); The second decoding circuit (145) is configured to receive the count value (IWR_cnt) of the internal write signal (IWR), and generate and output an operation end signal (IMWR_END) when the count value (IWR_cnt) of the internal write signal (IWR) is a second preset value. The SR trigger (146) is configured to receive the internal error check command signal (IMWRAB) and the operation end signal (IMWR_END), and in response to the internal error check command signal (IMWRAB), set the operation identifier signal (IMWR_FLAG) to an active level, and set the operation identifier signal (IMWR_FLAG) to an inactive level when the count value (IWR_cnt) of the internal write signal (IWR) reaches a second preset value.

13. The internal error checking circuit (10) as described in any one of claims 11-12, wherein, The read / write command generation circuit (143) includes: The second NAND gate (1431) receives the operation flag signal (IMWR_FLAG) at its first input and the internal error check command signal (IMWRAB) at its second input. The first NOR gate (1432) is electrically connected to the output of the second NAND gate (1431), and the output of the first NOR gate (1432) is used to output the internal read signal (IRD). The second NOR gate (1433) has its first input terminal electrically connected to the output terminal of the first NOR gate (1432), and its output terminal electrically connected to the second input terminal of the first NOR gate (1432). A delay unit (1434) is provided, wherein the input terminal of the delay unit (1434) is electrically connected to the output terminal of the first NOR gate (1432); The first NOT gate (1435) is electrically connected to the output of the delay unit (1434), and the output of the first NOT gate (1435) is electrically connected to the second input of the second NOR gate (1433). The second NOT gate (1436) receives the operation flag signal (IMWR_FLAG) at its input. The third NOR gate (1437) has its first input terminal electrically connected to the output terminal of the second NOT gate (1436), its second input terminal electrically connected to the output terminal of the first NOR gate (1432), and its output terminal used to output the internal write signal (IWR).

14. The internal error checking circuit (10) as described in any one of claims 11-13, wherein, The storage array control circuit (141) further includes: The self-refresh control circuit (147) is configured to receive the operation identifier signal (IMWR_FLAG) and the self-refresh address (SREF_Row), and when the operation identifier signal (IMWR_FLAG) flips to an invalid level, control the corresponding memory array (15) to perform a refresh operation according to the self-refresh address (SREF_Row).

15. The internal error checking circuit (10) as described in any one of claims 1-14, wherein, The error correction circuit (16) is further configured to generate and output an error identification signal when an error exists in the stored data in the target storage unit during an internal read-modify-write operation on the target storage unit. The internal error checking circuit (10) further includes an error register (17) configured to receive the internal error checking address (IMWR_AD) and the error identification signal, and to store the internal error checking address (IMWR_AD) in response to the error identification signal.

16. A memory (20), characterized in that, The memory (20) includes an internal error checking circuit (10) as described in any one of claims 1 to 15.

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