A flash decoding method, device and computer storage medium

Abstract

The application provides a flash decoding method, device and computer storage medium. The flash decoding method comprises the following steps: in response to a hard decision failure, updating a correction factor according to a current hard decision result; updating the a posteriori information of a variable node by using the updated correction factor; and re-performing a hard decision according to the updated a posteriori information of the variable node. Through the flash decoding method, a dynamic correction factor is introduced, the error correction performance of soft decoding is improved, and the convergence of soft decoding is accelerated.

Description

Technical Field

[0001] This application relates to the field of solid-state storage technology, and in particular to a flash memory decoding method, apparatus, and computer storage medium. Background Technology

[0002] As flash memory density increases, the raw bit error rate (RBER) becomes increasingly higher. LDPC (Low-density Parity-check) codes offer powerful soft decoding error correction capabilities and are widely used in flash memory systems. To maintain data reliability, flash memory systems employ various measures for read recovery. Traditionally, when decoding failure occurs, a retry process is first performed, adjusting the read voltage offset according to the retry table (hard read), followed by hard decoding. If retry still fails to correct errors, a soft reading process is used to obtain soft information, which is then mapped to an LLR (Log-Likelihood Ratio) value and input into the soft decoder (soft decoding).

[0003] The error correction performance of LDPC codes determines the reliability of NAND data, while the error correction performance of LDPC soft decoding determines the upper limit of data reliability. The soft decoding algorithm corrects erroneous codewords by iteratively updating the LLR value of codeword bits between variable nodes and check nodes.

[0004] In the CN update function of existing soft decoders, the NMS (Normalized Min-Sum) algorithm uses only a single fixed normalization factor alpha to optimize performance during the decoding process, and the OMS (Offset Min-Sum) algorithm also uses only a fixed offset factor beta to optimize performance. This approach has limited improvement on the error correction performance of soft decoding. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a flash memory decoding method, apparatus, and computer storage medium.

[0006] To address the aforementioned technical problems, this application proposes a flash memory decoding method, which includes: In response to a failed hard decision, update the correction factor based on the current hard decision result; The posterior information of the variable nodes is updated using the updated correction factor; Hard decision is re-performed based on the updated posterior information of the variable nodes.

[0007] The step of updating the correction factor based on the current hard decision result includes: Update the correction factor based on the checksum weight value in the current hard decision result; The weight value of the checksum is positively or negatively correlated with the correction factor.

[0008] The correction factor includes a first correction factor for the first soft decoding algorithm and a second correction factor for the second soft decoding algorithm, wherein the first correction factor and the second correction factor are updated in opposite directions.

[0009] The step of updating the correction factor based on the checksum weight value includes: Determine the check weight range in which the check weight value falls; The current correction factor is replaced by finding the correction factor corresponding to the weight range of the checksum according to the mapping table.

[0010] The step of updating the correction factor based on the checksum weight value includes: Determine whether the weight value of the verification sub-item is greater than a preset weight value; If so, update the current correction factor to the preset correction factor; If not, substitute the checksum weight value into the update function, calculate the correction factor corresponding to the checksum weight value, and replace the current correction factor.

[0011] The step of updating the correction factor based on the current hard decision result includes: Based on the current hard decision result, a verification node that does not meet the decoding success condition is identified; The correction factor used for the verification node that does not meet the decoding success condition is updated.

[0012] In this process, the verification nodes connected to the target variable node use the updated correction factor to calculate the information passed to the target variable node; the verification nodes connected to other variable nodes use the unupdated correction factor to calculate the information passed to the other variable nodes. The target variable node is a variable node that does not meet the decoding success condition.

[0013] The flash decoding method further includes the following steps after performing a hard decision based on the updated posterior information of the variable node: Determine the outcome of the next hard decision after a re-evaluation; Compare the differences in hard decision results between adjacent iterations; When the difference value in multiple consecutive iterations is less than the preset range, the current flash decoding stage is terminated.

[0014] To address the aforementioned technical problems, this application also proposes a flash memory decoding device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the flash memory decoding method described above.

[0015] To address the aforementioned technical problems, this application also proposes a computer storage medium for storing program data, which, when executed by a computer, is used to implement the aforementioned flash memory decoding method.

[0016] Compared with the prior art, the beneficial effects of this application are: the correction factor changes iteratively according to the hard decision result, so that when the verification node transmits the message to the variable node at each stage, it performs normalization processing or offset processing according to different correction factors, thereby improving the error correction performance of soft decoding; by iteratively changing the correction factor through the hard decision result of each iteration stage, it is also beneficial to accelerate the convergence speed of the soft decoder, thereby enhancing the reliability of the NAND system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating an embodiment of the software decoding algorithm provided in this application; Figure 2 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application; Figure 3 This is a flowchart illustrating another embodiment of the software decoding algorithm provided in this application; Figure 4 yes Figure 2 The flowchart of step S11 of the flash memory decoding method shown is a schematic diagram of an embodiment. Figure 5 yes Figure 2 A flowchart illustrating another embodiment of step S11 of the flash memory decoding method is shown. Figure 6 This is a flowchart illustrating another embodiment of the flash memory decoding method provided in this application; Figure 7 This is a schematic diagram of the structure of an embodiment of the flash memory decoding device provided in this application; Figure 8 This is a schematic diagram of the structure of an embodiment of the computer storage medium provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Solid-state storage, such as solid-state drives (SSDs) and USB cards, is currently in high demand. It stores data using non-volatile flash memory chips, preserving data even when power is lost. However, in SSDs, the optimal read voltage of the flash memory shifts with storage time and the number of erase / write cycles, leading to reduced data reliability.

[0021] As storage density increases, from SLC (Single-Level Cell) to MLC (Multi-Level Cell), TLC (Triple-Level Cell), and even QLC (Quad-Level Cell), the number of bits of data stored per flash memory cell increases, and data reliability gradually decreases. To maintain data reliability, LDPC soft decoding technology is typically used. Soft decoding requires performing multiple read operations (i.e., soft reading) on ​​both sides of the hard read voltage to obtain soft information, which is then mapped to an LLR (log-likelihood ratio) value and input into the soft decoder for decoding.

[0022] This application addresses read data recovery in solid-state storage by optimizing the node update steps in the LDPC software decoder, thereby increasing the software decoding error correction capability and enhancing system reliability.

[0023] Please refer to details. Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the software decoding algorithm provided in this application.

[0024] In storage media such as NAND flash memory, hard decision uses only a single threshold voltage to distinguish states (such as 0 / 1). Soft read, on the other hand, requires applying multiple reference voltages on both sides of the hard decision voltage and obtaining probabilistic information about the voltage distribution through multiple reads.

[0025] For each memory cell, at the hard decision voltage Set on both sides An additional reference voltage (e.g.) , A total of 2m+1 reads are performed. Each read result generates a binary bit, which is combined into a bit tag (e.g., 3 reads generate a 3-bit tag "101"), reflecting the range of the unit voltage.

[0026] By statistically analyzing a large number of cells, a conditional probability density function (PDF) for the voltage distribution is constructed. ,in, The voltage to be read is the stored bit state (0 or 1). In practice, PDFs are often modeled as Gaussian distributions or Gaussian mixture models, with parameters calibrated experimentally.

[0027] Where vector v represents the hard decoding result, H is the LDPC parity check matrix, and t represents the number of iterations. Soft decoding mainly consists of three computational modules: the V2C (VN to CN) information update module for the CN (verification node), the C2V (CN to VN) information update module for the VN (variable node), and the posterior information P update module for the VN.

[0028] based on Figure 1 To address the issue that NMS and OMS algorithms cannot efficiently improve soft decoding error correction performance, this application proposes a novel soft decoding algorithm where the soft decoding factors alpha and beta vary with the codeword checksum. This algorithm can reduce the bit error rate, accelerate soft decoding convergence, and improve soft decoding error correction performance. The core idea of ​​the novel soft decoding algorithm proposed in this application is that alpha and beta are directly related to the codeword checksum. The checksum is calculated in each iteration, and different alpha and beta are set according to the checksum level to improve the soft decoding error correction performance.

[0029] Please continue reading for details. Figure 2 and Figure 3 , Figure 2 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application. Figure 3 This is a flowchart illustrating another embodiment of the software decoding algorithm provided in this application.

[0030] The flash memory decoding method of this application is applied to a flash memory decoding device, which can be a server, a terminal device, or a system in which the server and the terminal device cooperate with each other. Accordingly, the various parts of the flash memory decoding device, such as each unit, subunit, module, and submodule, can all be set in the server, all in the terminal device, or separately in the server and the terminal device.

[0031] Furthermore, the aforementioned server can be either hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it can be implemented as multiple software programs or software modules, such as software or software modules used to provide distributed server functionality, or as a single software program or software module; no specific limitations are made here.

[0032] like Figure 2 As shown, the specific steps are as follows: Step S11: In response to a hard decision failure, update the correction factor based on the current hard decision result.

[0033] In the embodiments of this application, such as Figure 1 As shown, in the case of hard-decision decoding failure, i.e. If the condition is not met, the flash memory decoding device can further determine the hard decision result for the current stage, that is... The operation yields the parity submatrix. It should be noted that if all parameters in the parity submatrix are 0, then... If true, it means the hard decision for the current node was successful. If there is a parameter of 1 in the verification submatrix, then... If the condition is not met, it indicates that the hard decision for the current node has failed. In this case, the flash decoding device can determine the parity weight value (SW value) through parameter 1 in the parity matrix, and / or locate the target variable node that caused parameter 1 to appear. The parity weight value is... The number of parameter 1s in the middle.

[0034] In this application embodiment, in order to improve the soft decoding error correction performance of the soft decoding algorithm, this application proposes a novel soft decoding algorithm in which the soft decoding factor is updated according to the hard decision result.

[0035] The factor update schemes for various implementation methods are described below: First, the embodiments of this application use the checker weight value to update the correction factor.

[0036] Specifically, the flash memory decoding device updates the correction factor based on the checksum weight value in the current hard decision result. The update direction and update step size can be determined based on the checksum weight value. For example, for the alpha correction factor of the NMS algorithm, the larger the checksum weight value, the larger the update step size the flash memory decoding device uses to increase the alpha correction factor; for the beta correction factor of the OMS algorithm, the larger the checksum weight value, the larger the update step size the flash memory decoding device uses to decrease the alpha correction factor.

[0037] Therefore, it can be seen that for the alpha correction factor of the NMS algorithm, the checksum weight value is positively correlated with the correction factor; for the beta correction factor of the OMS algorithm, the checksum weight value is negatively correlated with the correction factor.

[0038] Furthermore, the flash decoding method of this application can also simultaneously use the alpha correction factor of the NMS algorithm and the beta correction factor of the OMS algorithm to update the LLR value of the variable node. In this case, the update directions of the alpha correction factor of the NMS algorithm and the beta correction factor of the OMS algorithm are related, that is, the alpha correction factor increases and the beta correction factor decreases.

[0039] Based on the first factor update scheme described above, this application provides a specific modified factor update scheme, please refer to [link / reference needed]. Figure 4 , Figure 4 yes Figure 2 The flowchart of step S11 of the flash memory decoding method shown is a schematic diagram of an embodiment.

[0040] like Figure 4 As shown, the specific steps are as follows: Step S21: Determine the check weight range in which the check weight value is located.

[0041] In this embodiment, the flash memory decoding device pre-stores a mapping table between the checksum weight value and the correction factor, as shown in the table below:

[0042] The flash memory decoding device determines the range of the current node's checksum weight value. For example, if the checksum weight value is 300, the range is 200-400.

[0043] Step S22: Find the correction factor corresponding to the checker weight range according to the mapping table and replace the current correction factor.

[0044] In this embodiment, the flash memory decoding device replaces the correction factor according to the mapping relationship in the mapping table in step S21. For example, in step S21 above, when the flash memory decoding device determines that the SW range is 200-400, it sets the alpha correction factor for the next stage to 0.6, or sets the beta correction factor for the next stage to 3.

[0045] In addition, the mapping table above can also record the mapping relationship between the SW interval and the update step size, as shown in the table below:

[0046] In this embodiment, the flash memory decoding device updates the correction factor according to the mapping relationship of the above mapping table. For example, in step S21 above, when the flash memory decoding device determines that the SW interval is 200-400, it updates the alpha correction factor of the next stage to the alpha correction factor of the current stage + 0.2, or updates the beta correction factor of the next stage to the beta correction factor of the current stage - 2.

[0047] Based on the first factor update scheme described above, this application provides another specific modified factor update scheme, please refer to [link / reference needed]. Figure 5 , Figure 5 yes Figure 2 The flowchart of another embodiment of the flash memory decoding method step S11 is shown.

[0048] like Figure 5 As shown, the specific steps are as follows: Step S31: Determine whether the weight value of the checker is greater than the preset weight value.

[0049] In this embodiment of the application, the flash memory decoding device determines whether the current stage's check subweight value is greater than a preset weight value. If yes, it proceeds to step S32; otherwise, it proceeds to step S33.

[0050] Step S32: Update the current correction factor to the preset correction factor.

[0051] In this embodiment of the application, when the flash memory decoding device determines that the current check weight value is greater than the preset weight value, it can directly replace the current correction factor with a preset correction factor. The specific value of the preset correction factor can be set in advance by the staff.

[0052] Step S33: Substitute the checksum weight value into the update function, calculate the correction factor corresponding to the checksum weight value, and replace the current correction factor.

[0053] In this embodiment of the application, when the flash memory decoding device determines that the check weight value of the current stage is less than the preset weight value, it can substitute the check weight value of the current stage into the update function to calculate a new correction factor and replace the correction factor of the current stage.

[0054] It should be noted that the flash memory decoding device can also calculate the update step size using the update function, which is used to update the correction factor at the current stage, but this will not be elaborated on here.

[0055] The processes of steps S31 to S33 above are expressed by the following formula: For the alpha correction factor of the NMS algorithm:

[0056] For the beta correction factor of the OMS algorithm:

[0057] It should be noted that in other embodiments, other forms of update functions or update parameters with other values ​​may be used, which will not be listed here.

[0058] It should be noted that, in the above description, the NMS and OMS algorithms in this application are based on the dynamic adjustment of correction factors (alpha and beta) values ​​by SW. Furthermore, this application is not only applicable to the standard NMS algorithm and the table OMS algorithm, but also to their variant algorithms, such as: quantized NMS / OMS, column-level NMS / OMS algorithms, etc.

[0059] Second, in the embodiments of this application, the target variable node is located by verifying the subweight value, and the correction factor is updated for the target variable node.

[0060] Specifically, the flash memory decoding device determines the target variable node corresponding to the checksum that does not meet the decoding success condition based on the current hard decision result. The posterior information of this part of the target variable node is calculated with the check matrix to generate parameter 1. Therefore, the posterior information of this part of the target variable node needs to be flipped to generate parameter 0 in conjunction with the check matrix, so as to achieve the hard decision success condition.

[0061] The flash decoding device can choose to update only the correction factors used by the check nodes connected to the target variable node, and not update the correction factors of check nodes that are not connected to any target variable node, or update them according to a predetermined strategy.

[0062] The flash decoding device can also control the check nodes connected to the target variable node to calculate the C2V information passed to the target variable node using the updated correction factor, while the C2V information of other variable nodes can still be calculated using the correction factor before the update.

[0063] The flash decoding device can update the correction factor used by the check node connected to the target variable node using the first factor update scheme described above, which will not be elaborated here; or it can update the correction factor used by the check node connected to the target variable node according to the number of iterations, that is, this part of the correction factor will be continuously updated with the number of soft decoding iterations, instead of simply using a fixed value for soft decoding.

[0064] Step S12: Update the posterior information of the variable nodes using the updated correction factor.

[0065] In this embodiment of the application, the flash memory decoding device uses the updated correction factor to calculate the C2V message passed from the verification node to the variable node, and uses the C2V message to update the posterior information of the variable node.

[0066] Step S13: Re-perform hard decision based on the updated posterior information of the variable nodes.

[0067] In this embodiment, the flash memory decoding device can continue to perform hard decision after obtaining the updated posterior information of the variable nodes. If the hard decision is successful, decoding ends; if the hard decision fails, the correction factor continues to be updated according to the flash memory decoding method provided in this application.

[0068] based on Figure 2 The flash memory decoding method shown in the previous application also provides another flash memory decoding method, please refer to the following for details. Figure 6 , Figure 6 This is a flowchart illustrating another embodiment of the flash memory decoding method provided in this application.

[0069] like Figure 6 As shown, the specific steps are as follows: Step S41: Determine the next hard decision result for re-making the hard decision.

[0070] Step S42: Compare the differences in hard decision results between adjacent iterations.

[0071] In this embodiment of the application, the flash memory decoding device compares the hard decision results of the two stages, such as comparing the two SW values ​​and calculating their difference value.

[0072] In other embodiments, the flash memory decoding device may also compare the hard decision results of multiple adjacent stages, which will not be elaborated here.

[0073] Step S43: When the difference value of multiple consecutive iterations is less than the preset range, terminate the current flash memory decoding stage.

[0074] In this embodiment, when the difference between the hard decision results of the two preceding and following stages, or the difference between stages in multiple consecutive iterations, is less than a preset range, the flash memory decoding device determines that the update correction factor has no effect on soft decoding and hard decision-making, and the current flash memory decoding stage has a high risk of failure. In this case, the flash memory decoding device can terminate the flash memory decoding stage early without waiting for the maximum number of iterations to be reached, thereby effectively reducing resource waste.

[0075] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0076] To implement the above flash memory decoding method, this application also proposes a flash memory decoding apparatus, for details please refer to [link to details]. Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the flash memory decoding device provided in this application.

[0077] The flash memory decoding device 500 of this embodiment includes a processor 51, a memory 52, an input / output device 53, and a bus 54.

[0078] The processor 51, memory 52, and input / output device 53 are respectively connected to the bus 54. The memory 52 stores program data, and the processor 51 is used to execute the program data to implement the flash memory decoding method described in the above embodiments.

[0079] In this embodiment, processor 51 can also be referred to as a CPU (Central Processing Unit). Processor 51 may be an integrated circuit chip with signal processing capabilities. Processor 51 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 51 can be any conventional processor.

[0080] This application also provides a computer storage medium; please refer to the following: Figure 8 , Figure 8This is a schematic diagram of a computer storage medium according to an embodiment of the present application. The computer storage medium 600 stores a computer program 61, which, when executed by a processor, is used to implement the flash memory decoding method of the above embodiment.

[0081] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0082] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A flash memory decoding method, characterized in that, The flash memory decoding method includes: In response to a failed hard decision, update the correction factor based on the current hard decision result; The posterior information of the variable nodes is updated using the updated correction factor; Hard decision is re-performed based on the updated posterior information of the variable nodes.

2. The flash memory decoding method according to claim 1, characterized in that, The step of updating the correction factor based on the current hard decision result includes: Update the correction factor based on the checksum weight value in the current hard decision result; The weight value of the checksum is positively or negatively correlated with the correction factor.

3. The flash memory decoding method according to claim 2, characterized in that, The correction factor includes a first correction factor for the first soft decoding algorithm and a second correction factor for the second soft decoding algorithm, with the first correction factor and the second correction factor being updated in opposite directions.

4. The flash memory decoding method according to claim 2, characterized in that, The step of updating the correction factor based on the checksum weight value includes: Determine the check weight range in which the check weight value falls; The current correction factor is replaced by finding the correction factor corresponding to the weight range of the checksum according to the mapping table.

5. The flash memory decoding method according to claim 2, characterized in that, The step of updating the correction factor based on the checksum weight value includes: Determine whether the weight value of the verification sub-item is greater than a preset weight value; If so, update the current correction factor to the preset correction factor; If not, substitute the checksum weight value into the update function, calculate the correction factor corresponding to the checksum weight value, and replace the current correction factor.

6. The flash memory decoding method according to claim 1, characterized in that, The step of updating the correction factor based on the current hard decision result includes: Based on the current hard decision result, a verification node that does not meet the decoding success condition is identified; The correction factor used for the verification node that does not meet the decoding success condition is updated.

7. The flash memory decoding method according to claim 1, characterized in that, The verification node connected to the target variable node uses the updated correction factor to calculate the information passed to the target variable node; The verification nodes connected to other variable nodes use the correction factor before the update to calculate the information passed to the other variable nodes; The target variable node is a variable node that does not meet the decoding success condition.

8. The flash memory decoding method according to claim 1, characterized in that, After re-performing the hard decision based on the updated posterior information of the variable node, the flash decoding method further includes: Determine the outcome of the next hard decision after a re-evaluation; Compare the differences in hard decision results between adjacent iterations; When the difference value in multiple consecutive iterations is less than the preset range, the current flash decoding stage is terminated.

9. A flash memory decoding device, characterized in that, The flash memory decoding device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the flash memory decoding method as described in any one of claims 1 to 8.

10. A computer storage medium, characterized in that, The computer storage medium is used to store program data, which, when executed by the computer, is used to implement the flash memory decoding method as described in any one of claims 1 to 8.

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