FPGA-based LDPC encoding and decoding method, system, and device medium
The LDPC encoding and decoding method is implemented by FPGA. It adopts an iterative decoding algorithm that combines buffer XOR calculation and parallel serial calculation, which solves the problem of limited parameter configuration in the existing technology and realizes flexible encoding parameter configuration and efficient decoding process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN SIDANDE INFORMATION TECH CO LTD
- Filing Date
- 2023-02-28
- Publication Date
- 2026-06-19
AI Technical Summary
Existing FPGA-based LDPC encoding and decoding technologies suffer from limitations in polynomial configuration and insufficient parameter flexibility, making it difficult to meet the needs of modern communication systems.
The FPGA-based LDPC encoding and decoding method generates encoded verification data through XOR calculation in the buffer area. It utilizes an iterative decoding algorithm that combines RAM storage and parallel serial computation to achieve flexible configuration of encoding and decoding parameters and efficient encoding.
It enables flexible configuration of LDPC encoding parameters, reduces resource utilization and latency, improves decoding gain, and meets the needs of modern communication systems.
Smart Images
Figure CN116192159B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of encoding and decoding, and relates to an FPGA-based LDPC encoding and decoding method and system device medium. Background Technology
[0002] In the era of prevalent digital communication technology, the reliability of data transmission has become a necessary research direction. In the process of wireless communication, it is necessary to ensure the correctness of data transmission. Channel coding has become an indispensable technology in wireless communication. At the same time, in order to reduce the utilization of bandwidth resources in the communication process, it is necessary to select the optimal channel coding technology to improve the data transmission efficiency. LDPC (Low-Density Parity Check) channel coding has good error correction capability and transmission efficiency, and is used in many wireless communication systems.
[0003] The implementation of FPGA-based LDPC encoding and decoding algorithms requires low decoding latency, configurable encoding and decoding polynomial parameters, ease of implementation, good decoding gain, and less FPGA resources. However, the existing FPGA-implemented LDPC encoding and decoding technology has limited polynomial configuration and is not flexible enough, with only a few optional parameter configurations. Now, the requirements for communication systems are becoming increasingly demanding, and the existing FPGA implementation technology is insufficient to meet the needs of subsequent communication systems. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an FPGA-based LDPC encoding and decoding method and system device medium that can support configurable encoding and decoding parameters and unlimited submatrix size and polynomial.
[0005] To achieve the above objectives, the present invention employs the following technical solution:
[0006] An FPGA-based LDPC encoding and decoding method includes the following steps:
[0007] S1: Receive externally input bit information as raw data, store the raw data into local buffers, there are 12 buffers, the size of the buffers is Z; perform shift and XOR calculation on the data in each buffer according to the coding polynomial to generate 12 encoded buffer data; perform XOR operation on the 12 encoded buffer data according to the coding algorithm to generate 12 encoded check data.
[0008] S2, store the 12 original data and 12 encoded check data into 24 RAM0_0 in sequence, and at the same time store the 12 original data and 12 encoded check data into 76 node update RAM1 according to the loaded decoding polynomial and offset polynomial address. The data in each RAM is a sub-matrix.
[0009] S3 updates the check nodes of the 76 data in RAM1. Parallel computation is performed between each submatrix, and serial computation is performed on the data within each submatrix. The updated data is then written into RAM1.
[0010] S4, combine the updated data of the check node in RAM1 with the original information of RAM0 to update the variable node. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is written into RAM1.
[0011] S5 iterates through processes S3 and S4 until the set number of iterations is reached, then outputs the decoded data.
[0012] Preferably, in S1, the length of the input raw data is 12*Z, the encoding delay is 13*Z clock cycles, and the length of the generated encoded verification data is 24*Z.
[0013] Preferably, in S3, the number of parallel calculations for updating the verification node is 12, which is the number of row submatrices, and the number of serial calculations is the size of the submatrices.
[0014] Preferably, in S3, the process of updating the check node is as follows: the number of input data is the number of non-zero submatrices in each row of the polynomial; the absolute value of the input data and the sign bits of the data excluding itself are accumulated; the minimum value of each data excluding itself is obtained; the sign of the minimum value information is converted according to the accumulated sign bits; and the updated check node information is output.
[0015] Preferably, in S4, the number of parallel computations for updating variable nodes is 24, which is the number of column submatrices, and the number of serial computations is the size of the submatrices.
[0016] Preferably, in S4, the process of updating the variable node is as follows: the number of input data is the number of non-zero submatrices in each column of the polynomial; all input data are accumulated; the accumulated data minus the current data value is the updated value of the current node; the sign bit of the accumulated sum is the decoded data information.
[0017] Preferably, after the decoded data is output, the check node update and the variable node update share RAM1.
[0018] An FPGA-based LDPC encoding and decoding system includes:
[0019] The encoding module receives externally input bit information as raw data, stores the raw data into local buffers (12 buffers, each with a size of Z), performs shift-and-XOR operations on the data in each buffer according to the encoding polynomial to generate 12 encoded buffer data, and performs XOR operations on the 12 encoded buffer data according to the encoding algorithm to generate 12 encoded check data.
[0020] The data storage module is used to store 12 original data and 12 encoded check data into 24 RAM0_0 in sequence. At the same time, it stores the 12 original data and 12 encoded check data into 76 node update RAM1 according to the loaded decoding polynomial and the offset polynomial address. The data in each RAM is a sub-matrix.
[0021] The verification node update module is used to update the verification nodes of the 76 data in RAM1. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is then written into RAM1.
[0022] The variable node update module is used to combine the updated data of the check node in RAM1 with the original information of RAM0 to update the variable node. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is written into RAM1.
[0023] The iteration module is used to iterate the processes S3 and S4 until the set number of iterations is reached, and then output the decoded data.
[0024] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the FPGA-based LDPC encoding and decoding method described above.
[0025] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the FPGA-based LDPC encoding and decoding method described above.
[0026] Compared with the prior art, the present invention has the following beneficial effects:
[0027] This invention enables flexible configuration of the submatrix size and polynomial of the LDPC encoding / decoding algorithm. Encoding employs a submatrix cyclic shift and accumulation method, resulting in high encoding efficiency, low latency, and low resource utilization. In LDPC decoding, an easily implemented posterior probability logarithmic domain confidence propagation decoding algorithm is used, which is easy to implement with FPGA logic and has low resource utilization. During node verification, a combination of serial and parallel computation is used to achieve an optimal solution for resources and latency. Data storage during the decoding process utilizes a shared dual-port RAM, making data updates and storage more flexible. Data computation uses 24-bit operations, reducing data precision loss and providing good decoding gain. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the FPGA-based LDPC encoding and decoding algorithm of this invention;
[0029] Figure 2 This is a flowchart of the LDPC encoding implementation on FPGA in this invention;
[0030] Figure 3 This is a flowchart of the LDPC decoding implementation on FPGA in this invention. Detailed Implementation
[0031] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0032] It should be noted that the terms “front,” “back,” “left,” “right,” “up,” and “down” used in the following description refer to the directions shown in the attached diagram, while the terms “inside” and “outside” refer to the directions toward or away from the geometric center of a specific component, respectively.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0034] like Figure 1 The diagram shows the structure of the FPGA-based LDPC encoding and decoding algorithm described in this invention.
[0035] The FPGA-based LDPC encoding and decoding algorithm is used to encode and decode wireless communication transmission data, realize the error correction function of the system, and improve the correctness of the transmitted data. The FPGA-based LDPC encoding and decoding algorithm mainly includes a parameter configuration module, an encoding module, a decoding module, a data storage module, a check node update module, and a variable node update module.
[0036] The parameter configuration module mainly includes the submatrix size (Z) parameter, the decoding iteration number parameter, and the encoding / decoding polynomial parameter. It is worth noting that the polynomial parameter value must be less than the submatrix size value. If it is greater than the submatrix size value, the submatrix size value needs to be subtracted until it is less than the submatrix size value.
[0037] The encoding module encodes data by cyclic shifting and accumulating. The input data length is 12*Z, the encoding delay is 13*Z clock cycles, and the output data length is 24*Z.
[0038] The decoding algorithm of the decoding module is the posterior probability logarithmic field confidence propagation algorithm. The data storage module, the check node update module, and the variable node update module constitute the entire decoding module. The decoding adopts soft information input and iterative decoding. The operation process is a combination of serial and parallel processing. Each calculation is performed on a row or column of each submatrix. The number of parallel calculations is 12 / 24, and the number of serial calculations is Z, so that the resources and speed reach the optimal solution.
[0039] The process implemented using FPGA is as follows:
[0040] The FPGA implementation of the encoding flowchart is as follows: Figure 2 As shown, the encoding module receives externally input bit information as raw data, stores the bit information into 12 local buffers of size Z, and performs a shift-and-XOR operation on the data in each buffer according to the encoding polynomial to generate 12 encoded buffer data. Then, it performs an XOR operation on the 12 encoded buffer data according to the encoding algorithm to generate 12 encoded check data. Finally, it packages and merges the raw data and the encoded check data, and outputs them to the external interface.
[0041] The FPGA decoding flowchart is as follows: Figure 3 As shown, the decoding module receives externally input soft demodulation information and inputs 12 raw data and 12 encoded check data into the data storage module. The raw data and node update data are stored separately in the data storage module to facilitate node updates during the decoding process. The RAM0 of the data storage module, which stores the raw data, has 24 bytes, a depth of Z, and a bit width of 24 bits. The node update RAM1 has 76 bytes, a depth of Z, and a bit width of 24 bits.
[0042] Twelve raw data points and twelve encoded verification data points are input into the data storage module and stored sequentially in RAM0_0-RAM0_23 for later use in variable node updates. Simultaneously, the twelve raw data points and twelve encoded verification data points are stored in node update RAM1_0-RAM1_75 according to the loaded decoding polynomial and offset polynomial address. When RAM1 is Z, the address is reset to zero, and data information is written to verify the initial value of the node update.
[0043] During the decoding process, the verification node reads the initial value information from RAM1_0 to RAM1_75, updates the verification node, and writes the updated data into RAM1_0 to RAM1_75; the variable node reads the updated data from the verification node in RAM1_0 to RAM1_75 and the original information from RAM0_0 to RAM0_23, updates the variable node, and writes the updated data into RAM1_0 to RAM1_75 for use as the initial value for the next iteration.
[0044] After the decoding iteration is completed, the decoded data information is output. The verification node update and the variable node update share RAM1 to achieve optimal resource utilization. In this embodiment, the number of iterations is 6-8.
[0045] The decoding process employs iterative decoding, with the number of iterations configurable via parameters. The decoding process combines serial and parallel decoding, performing parallel computation between each submatrix and serial computation on the data within each submatrix. The decoding process first updates the check nodes and then updates the variable nodes; one update of the check node and one update of the variable node constitute one iteration. This approach reduces the complexity of the algorithm, enabling iterative decoding to be completed with minimal decoding delay and optimal resources.
[0046] In the decoding process, the number of parallel calculations of the verification nodes is 12, which is the number of row submatrices, and the number of serial calculations is the size of the submatrices; the number of parallel calculations of the variable nodes is 24, which is the number of column submatrices, and the number of serial calculations is the size of the submatrices.
[0047] The check node update process involves inputting data in the form of the number of non-zero submatrices in each row of a polynomial. The absolute value of the input data is taken, and the sign bits of the data (excluding the data itself) are accumulated. The minimum value of each data (excluding the data itself) is then calculated. Based on the accumulated sign bits, the minimum value information is sign-transformed, and the updated check node information is output.
[0048] In the variable node update process, the number of input data is the number of non-zero submatrices in each column of the polynomial. All input data are accumulated, and the current data value is subtracted from the accumulated data to obtain the updated value of the current node. The sign bit of the accumulated sum is the decoded data information.
[0049] This invention implements the LDPC 1 / 2 code encoding and decoding algorithm using FPGA, with configurable submatrix size parameters. Encoding and decoding parameters are configured using external input constants, including the parity polynomial, submatrix size, and decoding iteration count. LDPC encoding employs a shift-accumulation encoding method, which is simple to implement and has low resource utilization. The encoding process loads parameter constants, such as the encoding polynomial and submatrix size. The LDPC decoding algorithm uses a simple posterior probability-based confidence propagation algorithm for decoding operations, exhibiting good decoding gain. The FPGA implementation of this decoding algorithm is simple, reducing logic complexity and a large amount of complex computation. During decoding, data storage is achieved using a shared dual-port RAM, significantly reducing logic resource usage. The node update process in decoding is implemented using a serial-parallel combination, greatly improving resource utilization and decoding speed. Both parity node and variable node updates are implemented using an accumulation and comparison decoding algorithm, which is simple to implement and has low computational load.
[0050] This invention supports configurable encoding and decoding parameters, with no restrictions on submatrix size and polynomial; it supports configurable decoding iterations, allowing for increases or decreases in decoding iterations as needed; it can achieve higher decoding gain; and it can implement decoding operations with fewer resources and lower decoding latency.
[0051] When implementing LDPC decoding, an easy-to-implement posterior probability logarithmic domain confidence propagation decoding algorithm is adopted, which is easy to implement with FPGA logic and low resource utilization. When performing node verification, a combination of serial and parallel computing is used to achieve an optimal solution for resources and latency. Data storage during the decoding process adopts the form of shared dual-port RAM, which makes data updates and storage more flexible. Data calculation is performed using 24 bits, which reduces the loss of data precision and has good decoding gain.
[0052] The following are embodiments of the apparatus of the present invention, which can be used to execute embodiments of the method of the present invention. For details not omitted in the apparatus embodiments, please refer to the embodiments of the method of the present invention.
[0053] In another embodiment of the present invention, an FPGA-based LDPC encoding and decoding system is provided. This FPGA-based LDPC encoding and decoding system can be used to implement the above-mentioned FPGA-based LDPC encoding and decoding method. Specifically, the FPGA-based LDPC encoding and decoding system includes an encoding module, a data storage module, a verification node update module, a variable node update module, and an iteration module.
[0054] The encoding module receives externally input bit information as raw data, stores the raw data into local buffers (12 buffers, each with a size of Z), performs shift-and-XOR operations on the data in each buffer according to the encoding polynomial to generate 12 encoded buffer data, and performs XOR operations on the 12 encoded buffer data according to the encoding algorithm to generate 12 encoded check data.
[0055] The data storage module is used to store 12 original data and 12 encoded check data into 24 RAM0_0 in sequence. At the same time, it stores the 12 original data and 12 encoded check data into 76 node update RAM1 according to the loaded decoding polynomial and offset polynomial address. The data in each RAM is a sub-matrix.
[0056] The check node update module is used to update the check nodes of the 76 data in RAM1. Parallel calculations are performed between each submatrix, and serial calculations are performed on the data within each submatrix. The updated data is then written into RAM1.
[0057] The variable node update module is used to combine the updated data of the check node in RAM1 with the original information of RAM0 to update the variable node. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is then written into RAM1.
[0058] The iteration module is used to iterate the processes S3 and S4 until the set number of iterations is reached, and then output the decoded data.
[0059] In another embodiment of the present invention, a terminal device is provided, comprising a processor and a memory. The memory stores a computer program, the computer program including program instructions, and the processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., are the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to realize the corresponding method flow or corresponding function; the processor described in this embodiment of the invention can be used for the operation of the LDPC encoding and decoding method based on FPGA, including: S1, receiving externally input bit information as raw data, storing the raw data into local buffers, the number of buffers is 12, the size of the buffers is Z; performing shift XOR calculation on the data in each buffer according to the encoding polynomial to generate 12 encoded buffer data; performing XOR operation on the 12 encoded buffer data according to the encoding algorithm to generate 12 encoded check data; S2, storing the 12 raw data into local buffers; The initial data and 12 encoded check data are stored sequentially into 24 RAM0_0 locations. Simultaneously, the 12 original data and 12 encoded check data are stored in 76 node update RAM1 according to the loaded decoding polynomial and its offset address. Each RAM contains a submatrix. In step S3, the check nodes in the 76 RAM1 locations are updated. Parallel computation is performed between submatrices, while serial computation is performed on the data within each submatrix. The updated data is then written into RAM1. In step S4, the updated check node data in RAM1 is combined with the original information from RAM0 to update the variable nodes. Parallel computation is performed between submatrices, while serial computation is performed on the data within each submatrix. The updated data is then written into RAM1. In step S5, steps S3 and S4 are iterated until the set number of iterations is reached, at which point the decoded data is output.
[0060] In another embodiment, the present invention also provides a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It is understood that the computer-readable storage medium here may include both the built-in storage medium in the terminal device and extended storage media supported by the terminal device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which may be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here may be high-speed RAM or non-volatile memory, such as at least one disk storage device.
[0061] One or more instructions stored in the computer-readable storage medium can be loaded and executed by the processor to implement the corresponding steps of the FPGA-based LDPC encoding and decoding method in the above embodiments; one or more instructions in the computer-readable storage medium are loaded and executed by the processor in the following steps: S1, receive externally input bit information as raw data, store the raw data into local caches respectively, the number of caches is 12, the size of the cache is Z; perform shift XOR calculation on the data in each cache according to the encoding polynomial to generate 12 encoded cache data; perform XOR operation on the 12 encoded cache data according to the encoding algorithm to generate 12 encoded check data; S2, store the 12 raw data and the 12 encoded check data into 24 RA in sequence respectively. In M0_0, 12 original data and 12 encoded check data are simultaneously stored in 76-node update RAM1 according to the loaded decoding polynomial and offset polynomial address. The data in each RAM is a sub-matrix. In S3, the check nodes in the 76 RAM1 are updated. Parallel calculations are performed between each sub-matrix, and serial calculations are performed on the data within each sub-matrix. The updated data is then written into RAM1. In S4, the updated data of the check nodes in RAM1 is combined with the original information in RAM0 to update the variable nodes. Parallel calculations are performed between each sub-matrix, and serial calculations are performed on the data within each sub-matrix. The updated data is then written into RAM1. In S5, processes S3 and S4 are iterated until the set number of iterations is reached, and the decoded data is output.
[0062] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0063] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0064] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0065] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0067] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.
Claims
1. An FPGA-based LDPC encoding and decoding method, characterized in that, The process includes the following: S1: Receive externally input bit information as raw data, store the raw data into local buffers, there are 12 buffers, the size of the buffers is Z; perform shift and XOR calculation on the data in each buffer according to the coding polynomial to generate 12 encoded buffer data; perform XOR operation on the 12 encoded buffer data according to the coding algorithm to generate 12 encoded check data. The length of the input raw data is 12*Z, the encoding delay is 13*Z clock cycles, and the length of the generated encoded check data is 24*Z. S2, store the 12 original data and 12 encoded check data into 24 RAM0 in sequence, and at the same time store the 12 original data and 12 encoded check data into 76 node update RAM1 according to the loaded decoding polynomial and offset polynomial address. The data in each RAM0 and each RAM1 is a sub-matrix. S3 updates the check nodes of the 76 data in RAM1. Parallel computation is performed between each submatrix, and serial computation is performed on the data within each submatrix. The updated data is then written into RAM1. The number of parallel computations for updating the verification node is 12, which is the number of row submatrices, and the number of serial computations is the size of the submatrices; The process of updating the check node is as follows: The number of input data is the number of non-zero submatrices in each row of the polynomial. The absolute value of the input data and the sign bits of the data excluding itself are accumulated. The minimum value of each data excluding itself is found. The sign of the minimum value is converted according to the accumulated sign bits. The updated check node information is then output. S4, combine the updated data of the check node in RAM1 with the original information of RAM0 to update the variable node. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is written into RAM1. The number of parallel computations for variable node updates is 24, which is the number of column submatrices, and the number of serial computations is the size of the submatrices; S5 iterates through processes S3 and S4 until the set number of iterations is reached, then outputs the decoded data.
2. The FPGA-based LDPC encoding and decoding method according to claim 1, characterized in that, In S4, the process of updating the variable node is as follows: the number of input data is the number of non-zero submatrices in each column of the polynomial. All input data are accumulated, and the current data value is subtracted from the accumulated data to obtain the updated value of the current node. The sign bit of the accumulated sum is the decoded data information.
3. The FPGA-based LDPC encoding and decoding method according to claim 1, characterized in that, After the decoded data is output, the check node update and the variable node update share RAM1.
4. An FPGA-based LDPC encoding and decoding system, characterized in that, include: The encoding module is used to receive externally input bit information as raw data and store the raw data into local buffers. There are 12 buffers and the size of each buffer is Z. The data in each buffer is shifted and XORed according to the encoding polynomial to generate 12 encoded buffer data; the 12 encoded buffer data are then XORed according to the encoding algorithm to generate 12 encoded check data. The length of the input raw data is 12*Z, the encoding delay is 13*Z clock cycles, and the length of the generated encoded check data is 24*Z. The data storage module is used to store 12 original data and 12 encoded check data into 24 RAM0s in sequence. At the same time, it stores the 12 original data and 12 encoded check data into 76 node update RAM1s according to the loaded decoding polynomial and the offset polynomial address. The data in each RAM0 and each RAM1 is a sub-matrix. The verification node update module is used to update the verification nodes of the 76 data in RAM1. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is then written into RAM1. The number of parallel computations for updating the verification node is 12, which is the number of row submatrices, and the number of serial computations is the size of the submatrices; The process of updating the check node is as follows: The number of input data is the number of non-zero submatrices in each row of the polynomial. The absolute value of the input data and the sign bits of the data excluding itself are accumulated. The minimum value of each data excluding itself is found. The sign of the minimum value is converted according to the accumulated sign bits. The updated check node information is then output. The variable node update module is used to combine the updated data of the check node in RAM1 with the original information of RAM0 to update the variable node. Parallel calculation is performed between each submatrix, and serial calculation is performed on the data within each submatrix. The updated data is written into RAM1. The number of parallel computations for variable node updates is 24, which is the number of column submatrices, and the number of serial computations is the size of the submatrices; The iteration module is used to iterate the processes S3 and S4 until the set number of iterations is reached, and then output the decoded data.
5. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the FPGA-based LDPC encoding and decoding method as described in any one of claims 1 to 3.
6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the FPGA-based LDPC encoding and decoding method as described in any one of claims 1 to 3.