Decoding method and decoding apparatus

Abstract

A decoding method and apparatus are provided, which can reduce decoding time, reduce required resources, and improve the robustness of the method, thereby improving decoding performance. The method includes: in the event of a verification failure, when the signs of the posterior information of a variable node are the same in multiple consecutive iterations, directly setting the amplitude of the iterative posterior information of that variable node to the maximum value.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to decoding methods and decoding apparatus. Background Technology

[0002] Low-density parity check (LDPC) codes are commonly used error-correcting codes, widely applied in communication, storage, and other scenarios to protect data and improve system reliability. Iterative decoding methods are commonly used at the decoding end to decode LDPC codes.

[0003] Currently, in the process of decoding LDPC codes using the iterative decoding method, in order to accelerate the convergence speed, in each iteration, when the posterior information of the variable node fails to be verified, the magnitude of the posterior information of the variable node is compared with the magnitude threshold of the posterior information of the variable node. If the magnitude of the posterior information of the variable node is greater than the magnitude threshold of the posterior information of the variable node, the magnitude of the posterior information of the variable node is set to the maximum value, and the current sign bit is maintained.

[0004] However, this method is highly complex, which leads to long decoding times and high resource requirements; in addition, the set amplitude threshold is not robust and may reduce decoding performance. Summary of the Invention

[0005] This application provides a decoding method and decoding apparatus that can reduce decoding time, reduce required resources, and improve the robustness of the method, thereby enhancing decoding performance.

[0006] Firstly, a decoding method is provided. This method can be executed by a decoding device, which can be a communication device, or a device within the communication device (e.g., a module, communication module, circuit or chip responsible for communication functions (such as a modem chip, also known as a baseband chip, or a system-on-a-chip (SoC) chip or system-in-package (SIP) chip containing a modem core), chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the functions of the communication device. An example of the communication device is an access network device or terminal.

[0007] The method includes: verifying N T-th iteration posterior information corresponding to N variable nodes according to the parity check matrix of the low-density parity check code. The N T-th iteration posterior information includes: K extrinsic information transmitted from the variable nodes to the check nodes and S extrinsic information transmitted from the check nodes to the variable nodes obtained from the (T-1)th iteration decoding as posterior information determined by the N variable nodes, where M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer; if the verification fails, determine whether the signs of the T-th iteration posterior information of the nth variable node to the T-C+1th iteration posterior information are the same, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1; if the signs of the T-th iteration posterior information of the nth variable node to the T-C+1th iteration posterior information are the same, set the amplitude of the T-th iteration posterior information of the nth variable node to the maximum value.

[0008] In this method, the condition for setting the amplitude of the posterior information of the nth variable node at its maximum value in the Tth iteration is: determining whether the signs of the posterior information of the variable node from the Tth iteration to the (T-C+1)th iteration are the same. This condition, compared to determining that the amplitude of the variable node's posterior information is greater than a threshold, compares the signs, while the latter compares the posterior information of the variable node. Because the posterior information of the variable node is usually a floating-point number, the complexity of sign comparison is lower than that of posterior information comparison. In other words, this method accelerates decoding convergence while reducing decoding complexity. Furthermore, this method does not require setting an amplitude threshold, which, compared to setting an amplitude threshold related to the channel signal-to-noise ratio, improves the robustness of this method, thereby enhancing decoding performance.

[0009] In one possible design, the method further includes: before the first iteration of decoding, initializing N counters to preset values, with each of the N counters corresponding to one of the N variable nodes;

[0010] Specifically, determining whether the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same includes: if the signs of the posterior information of the nth variable node from the Tth iteration to the (T-1)th iteration are the same, then the counter corresponding to the nth variable node is adjusted, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged is incremented by 1; if the number of consecutive iterations indicated by the change in the counter corresponding to the nth variable node relative to the preset value is greater than or equal to C, then it is determined that the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same.

[0011] The method also includes: if the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then the counter corresponding to the nth variable node is set to a preset value.

[0012] In this possible design, by setting a counter and using the change in the counter to count the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged, it is possible to determine whether the sign of the posterior information of the nth variable node is the same multiple times based on the change in the counter, without having to compare with an amplitude threshold, thus reducing complexity. Furthermore, if the sign of the posterior information of the nth variable node is not the same consecutively, the counter value can be readjusted to ensure the accuracy of the result.

[0013] In one possible design, the preset value is 0, and / or the variation is 1.

[0014] In this possible design, the preset value of the counter and the amount of change of the counter can be determined.

[0015] Secondly, this application provides a decoding apparatus. This decoding apparatus can be a communication device, or a device within a communication device (e.g., a module, communication module, circuit or chip responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the functions of the communication device. As an example, the communication device is an access network device or a terminal.

[0016] This decoding apparatus may include modules that perform the methods / operations / steps / actions described in any possible implementation of the first aspect. These modules may be hardware circuits, software, or a combination of hardware circuits and software.

[0017] In one design, the decoding apparatus may include a processing module and a communication module. The communication module is used to execute the sending and receiving actions in the method described in any possible implementation of the first aspect above, while the processing module is used to execute the processing actions involved in the method described in any possible implementation of the first aspect above.

[0018] For example, the processing module is used to: verify the N T-th iteration posterior information corresponding to N variable nodes according to the parity check matrix of the low-density parity check code. The N T-th iteration posterior information includes: K extrinsic information transmitted from the variable nodes to the verification nodes and S extrinsic information transmitted from the verification nodes to the variable nodes obtained by decoding in the (T-1)-th iteration, which are the posterior information determined by the N variable nodes, where M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer; if the verification fails, it is determined whether the signs of the T-th iteration posterior information of the n-th variable node to the T-C+1-th iteration posterior information are the same, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1; if the signs of the T-th iteration posterior information of the n-th variable node to the T-C+1-th iteration posterior information are the same, the amplitude of the T-th iteration posterior information of the n-th variable node is set to the maximum value.

[0019] In some possible designs, this processing module is also used to: initialize N counters to preset values ​​before the first iteration of decoding, with each of the N counters corresponding to one of the N variable nodes;

[0020] Specifically, when the processing module determines whether the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same, it is used as follows: If the signs of the posterior information of the nth variable node from the Tth iteration to the (T-1)th iteration are the same, then the counter corresponding to the nth variable node is adjusted, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged, the number of consecutive iterations is incremented by 1; if the number of consecutive iterations indicated by the change in the counter corresponding to the nth variable node relative to the preset value is greater than or equal to C, then it is determined that the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same.

[0021] The processing module is also used to: if the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then set the counter corresponding to the nth variable node to a preset value.

[0022] In some possible designs, this preset value is 0, and / or the variation is 1.

[0023] Thirdly, a decoding apparatus is provided, including a processor, wherein instructions are executed by the processor to cause a method as described in the first aspect or any possible implementation thereof to be implemented.

[0024] Optionally, the device may further include a storage medium that stores the instructions executed by the processor.

[0025] Fourthly, a chip is provided, including processing circuitry for running programs or instructions to implement methods as described in the first aspect or any possible implementation thereof.

[0026] Optionally, the chip may further include a memory for storing programs or instructions.

[0027] Optionally, the chip may also include the transceiver circuit, or an input / output interface.

[0028] Fifthly, a computer-readable storage medium is provided, the computer-readable storage medium including instructions that, when executed by a processor, cause the method as described in the first aspect or any possible implementation thereof to be implemented.

[0029] In a sixth aspect, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed, cause the method as described in the first aspect or any possible implementation thereof to be implemented.

[0030] A seventh aspect provides a communication system comprising: means for performing the first aspect or any possible implementation thereof.

[0031] It is understood that the technical effects of any of the second to seventh aspects of this application can be referred to the relevant content in the first aspect, and will not be repeated here. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the Tanner diagram corresponding to the parity check matrix of the LDPC code in an embodiment of this application;

[0033] Figure 2 This is a possible, non-limiting system schematic diagram of an embodiment of this application;

[0034] Figures 3-4 This is a schematic diagram of the protocol layer architecture of the CU-DU in an embodiment of this application;

[0035] Figures 5-6 This is a schematic diagram of the communication system according to an embodiment of this application;

[0036] Figure 7 This is a flowchart of a decoding method according to an embodiment of this application;

[0037] Figure 8 This is a schematic diagram illustrating the algorithm implementation of multiple iterations in an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of the structure of a decoding device according to an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of the composition of a decoding device according to an embodiment of this application. Detailed Implementation

[0040] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural.

[0041] In the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0042] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0043] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0044] It is understood that in this application, "...when" and "if" both refer to the corresponding processing that will be carried out under certain objective circumstances, and are not limited to a specific time, nor do they require a judgment action to be performed during implementation, nor do they imply any other limitations.

[0045] It is understood that some optional features in the embodiments of this application can be implemented independently in certain scenarios without relying on other features, such as the current solution on which they are based, to solve the corresponding technical problems and achieve the corresponding effects. Alternatively, they can be combined with other features as needed in certain scenarios. Correspondingly, the apparatus given in the embodiments of this application can also implement these features or functions, which will not be elaborated here.

[0046] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referred to each other. In the various embodiments of this application, unless otherwise specified or there is a logical conflict, the terminology and / or descriptions between different embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. The following descriptions of the embodiments of this application do not constitute a limitation on the scope of protection of this application.

[0047] To facilitate understanding of the technical solutions of the embodiments of this application, a brief introduction to the relevant technologies of this application is given below.

[0048] (1) Low-density parity check (LDPC) code

[0049] LDPC codes: A type of linear block code with a sparse parity-check matrix, meaning that the number of zero elements in the parity-check matrix is ​​much greater than the number of non-zero elements, or in other words, the row weight and column weight of the parity-check matrix are very small compared to the code length of LDPC.

[0050] The parity-check matrix of an LDPC code can be represented by a Tanner diagram. The Tanner diagram contains two types of nodes: one type of node represents codeword bits and can be called variable nodes; the other type of node represents parity check nodes, which represent parity check constraints. Each parity check node represents a parity check constraint.

[0051] Figure 1 This is a schematic diagram of the Tanner diagram corresponding to the parity-check matrix of the LDPC code in an embodiment of this application. Figure 1 As shown, the Tanner diagram represents the parity-check matrix H of the LDPC. For example, for a parity-check matrix H of size M rows and N columns, the Tanner diagram contains two types of nodes: N variable nodes and M parity nodes. Figure 1 The middle circle represents VN n The nodes are variables, n = 0, 1, 2, 3; the squares represent CN. mLet m = 0, 1, 2 be the check nodes. N variable nodes correspond to the N columns of the parity-check matrix H, and M check nodes correspond to the M rows of the parity-check matrix H. The loops in the Tanner graph consist of interconnected vertices, with one vertex serving as both the start and end point, and each node is visited only once. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The check nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connection between two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the parity-check matrix H is 1; otherwise, the corresponding element is 0. Figure 1 The corresponding LDPC parity-check matrix H is represented by the following formula (1).

[0052]

[0053] like Figure 1 As shown in the figure, N represents the number of variable nodes, M represents the number of check nodes, and q n→m Indicates from VN n Transmitted to CN m External information, r m→n Indicates from CN m Pass to VN n External information.

[0054] Currently, in practical applications, the normalized min-sum algorithm (NMSA) is commonly used in LDPC code decoding, employing logarithmic field confidence representation. Figure 1 Taking the Tanner graph corresponding to the parity-check matrix of the LDPC code shown as an example, the steps of one iteration based on NMSA are as follows:

[0055] Step 1: Initialize channel information and external information.

[0056] 1. Based on the following formula (2), the variable node VN n The channel information is initialized based on the log-likelihood ratio (LLR).

[0057]

[0058] In the formula, n represents the nth variable node, n = 0, 1, ..., N-1; r n VN n Received channel information; x ny represents the bit value sent from the transmitter; y represents x. n The sign value of the complex number corresponding to the receiving end; p(|) represents the transition probability; ln() represents the logarithm to the base e.

[0059] 2. Initialize the external information to 0 based on the following formula (3).

[0060]

[0061] In the formula, q n→m Indicates from VN n Uploaded to CN m External information; r m→n Indicates from CN m Transfer to VN n External information; The Tanner diagram representing the parity-check matrix of the LDPC code.

[0062] Step 2: Variable Node VN n Based on the following formula (4), the verification node CN is... m To convey external information.

[0063]

[0064] In the formula, This represents the check nodes other than the m-th check node, and C(n)\m represents the check nodes other than CN. m In addition, VN n The set of all other connected verification nodes.

[0065] Step 3: Verify node CN m Based on the following formula (5), the variable node VN is... n To convey external information.

[0066]

[0067] In the formula, α∈(0,1) is the normalization factor; This represents all variable nodes except the nth variable node; V(m)\n except VN n In addition, CN m The set of all other variable nodes connected; min() represents the minimum value function; sgn() represents the sign function, which is expressed by the following formula (6).

[0068]

[0069] Step 4: Posterior information λ of variable nodes n Calculation and judgment.

[0070] The posterior information of the variable nodes is calculated based on the following formula (7).

[0071] λ n =r n +Σ m∈C(n) r m→n (7)

[0072] In the formula, C(n) represents VN n The set of all connected verification nodes.

[0073] The posterior information of the variable node is used to make a decision based on the following formula (8).

[0074]

[0075] Step 5: Verification Is it equal to 0?

[0076] If the verification is successful, that is Then exit the iteration and return. This is the decoding result. If the verification fails, steps two through four will be repeated for further verification and judgment until the maximum number of iterations is reached, at which point the result is returned. As the decoding result.

[0077] It is understandable that steps two through five can be referred to as one iteration.

[0078] To accelerate the convergence speed of NMSA, a common approach is to set a threshold for the magnitude of the posterior information of variable nodes. If the magnitude of the posterior information of a variable node exceeds this threshold, the magnitude of the posterior information is set to its maximum value, while the current sign bit is maintained. This method can be implemented using the following pseudocode.

[0079] setλ th #Set the threshold for the magnitude of the posterior information of the variable node, λ th >0 and λ th Related to signal tonoise ratio (SNR)

[0080] setλ max #Set the maximum posterior information magnitude of the variable node, λ max >0 and λ max The value is relatively large

[0081] for iter in [0,1,2,…,I] max -1] #I max Represents the maximum number of iterations, traversing I max Second iteration

[0082] forn in[0,1,…,N-1] # Iterate through N variable nodes

[0083] if abs(λ n )>λ th #If the magnitude of the posterior information of the nth variable node is greater than the threshold

[0084] λ n =sgn(λ n )·λ max # Set the posterior information magnitude of the nth variable node to the maximum value and keep the current sign bit. Here, abs() represents the absolute value function; sgn() represents the sign function.

[0085] However, when using this method for decoding, λ n With λ th The comparisons between them are floating-point number comparisons, which have high complexity, leading to long decoding times and high resource requirements. Furthermore, λ... th The setting is related to SNR, which is not robust and may reduce decoding performance.

[0086] To address the aforementioned issues, this application provides a new technical solution to reduce decoding complexity and improve decoding performance.

[0087] The technical solutions of this application embodiment can be used in various communication systems, including 3GPP communication systems such as 4th generation (4G) systems (e.g., Long Term Evolution (LTE) systems), 5G systems (e.g., New Radio (NR) systems), hybrid LTE and 5G networks, non-terrestrial networks (NTNs), or other future communication systems. The communication system can also be a non-3GPP communication system; there is no limitation on this.

[0088] The communication systems described above are merely illustrative examples, and are not limited to those described herein. The communication systems provided in this application do not impose any limitations on the solutions described herein. This will be explained uniformly here and will not be repeated below.

[0089] Figure 2 This is a possible, non-limiting system diagram illustrating an embodiment of this application. Figure 2As shown, the communication system 20 includes a radio access network (RAN) 200 and a core network (CN) 300. RAN 200 includes at least one RAN node (e.g., Figure 2 210a and 210b (collectively referred to as 210) and at least one terminal (such as Figure 2 RAN 200 (220a-220j, collectively referred to as 220) primarily provides wireless connectivity and is located between terminal 220 and core network 300. RAN 200 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 2 (Not shown in the image). Terminal 220 is connected to RAN node 210 wirelessly. RAN node 210 is connected to core network 300 wirelessly or via wired connection. The core network equipment in core network 300 and RAN node 210 in RAN 200 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0090] RAN 200 can be a 3GPP-related cellular system, such as a 4G, 5G mobile communication system, or a future-oriented evolution system. RAN 200 can also be an open access network (openRAN, O-RAN, or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 200 can also be a communication system that integrates two or more of the above systems.

[0091] RAN node 210, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and assists terminals in achieving wireless access. Multiple RAN nodes 210 in communication system 20 can be of the same type or different types. In some scenarios, the roles of RAN node 210 and terminal 220 are relative, for example... Figure 2 Network element 220i can be a helicopter or a drone, and it can be configured as a mobile base station. For terminals 220j that access RAN 200 through network element 220i, network element 220i is a base station; however, for base station 210a, network element 220i is a terminal. RAN node 210 and terminal 220 are sometimes referred to as communication devices, for example... Figure 2 Network elements 210a and 210b can be understood as communication devices with base station functions, while network elements 220a-220j can be understood as communication devices with terminal functions.

[0092] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system, etc. Figure 2 210a), micro base stations or indoor stations (such as Figure 2 The RAN node can be a base transceiver station (BTS) in a Global System for Mobile Communication (GSM) or Code Division Multiple Access (CDMA) network, a node base station (NB) in a Wideband Code Division Multiple Access (WCDMA) network, a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node functions.

[0093] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0094] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0095] It is understood that in the description of the following embodiments, the network device can be a CU node, a DU node, or a device including both CU nodes and DU nodes. Furthermore, a CU can be classified as a network device in the access network (RAN) or a network device in the core network (CN), and no limitation is imposed here.

[0096] Terminal 220 can also be referred to as terminal equipment, user equipment (UE), access terminal, UE unit, UE station, mobile station, mobile station, remote station, remote terminal, mobile device, UE terminal, mobile terminal, wireless communication equipment, multimedia equipment, streaming media equipment, UE agent, or UE device, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, and smart cities, etc. The terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle, drone, helicopter, airplane, ship, robot, robotic arm, smart home device, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), handheld device with wireless communication capabilities, computing device or other processing device connected to a wireless modem, in-vehicle device, terminal in future networks, or terminal in a future evolved public land mobile network (PLMN) network, etc. The embodiments of this application do not limit the device form of the terminal.

[0097] In some scenarios, communication between RAN node 210 and terminal 220 follows a specific protocol layer structure, which may include a control plane protocol layer and a user plane protocol layer. The control plane protocol layer may include at least one of the following: radio resource control (RRC) layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, media access control (MAC) layer, or physical (PHY) layer, etc. The user plane protocol layer may include at least one of the following: service data adaptation protocol (SDAP) layer, PDCP layer, RLC layer, MAC layer, or physical layer, etc.

[0098] As one possible implementation, the CU and DU respectively implement some of the protocol layer functions of the access network device. For example, some protocol layer functions are implemented in the CU, and the remaining or all protocol layer functions are implemented in the DU. The CU can control one or more DUs.

[0099] For example, Figure 3 This is a schematic diagram of the protocol layer architecture of the CU-DU according to an embodiment of this application. Figure 3 In the protocol layer architecture of the CU-DU shown, the CU can deploy the RRC layer, SDAP layer, and PDCP layer. In other words, the CU can be understood as a logical node carrying the RRC, SDAP, and PDCP layers of the access network equipment. Therefore, the CU has the processing capabilities of the RRC, PDCP, and SDAP layers. Of course, the CU can also implement or carry other control functions. Similarly, the DU can deploy the RLC layer, MAC layer, and PHY layer. In other words, the DU can be understood as a logical node carrying the RLC, MAC, and PHY layers. Therefore, the DU has the processing capabilities of the RLC, MAC, and PHY layers. Of course, the DU can also implement or carry other functions.

[0100] Optionally, the CU connects to network nodes such as the core network through interfaces, which can be E2 interfaces, etc. Furthermore, the CU can also implement some core network functions. The CU (e.g., PDCP layer and higher layers) connects to the DU (e.g., RLC layer and lower layers) through interfaces, which can be interfaces such as F1. In some examples, these interfaces (e.g., F1 interface) can provide control plane (C-Plane) and user plane (U-Plane) functions (e.g., interface management, system information management, UE context management, RRC message transmission, etc.). For example, F1 supports control plane functions through F1-C and user plane functions through F1-U.

[0101] In one example, the CU may include CU-CP and CU-UP. Figure 4 This is a schematic diagram of the protocol layer architecture of the CU-DU according to an embodiment of this application. Figure 4 In the protocol layer architecture of the CU-DU shown, CU-CP can be understood as a logical node carrying the RRC layer and the PDCP control plane (controlplane part of PDCP, PDCP-C), used to implement the control plane functions of the CU. CU-CP can communicate with the DU through F1-C. CU-UP can be understood as a logical node carrying the SDAP layer and the PDCP user plane (userplane part of PDCP, PDCP-U), used to implement the user plane functions of the CU. CU-UP can communicate with the DU through F1-U, and CU-CP can communicate with CU-UP through E1.

[0102] CU-CP can interact with network elements in the core network used to implement control plane functions. These network elements can be access and mobility function network elements, such as the AMF network element in a 5G system. CU-UP can interact with network elements in the core network used to implement user plane functions. These network elements can be, for example, UPF network elements.

[0103] The functional division of CU and DU described above is merely an example and does not constitute a limitation on CU and DU. Furthermore, the functions of CU and DU can be configured as needed. For example, CU or DU can be configured as a node with more protocol layer functions, or as a node with partial protocol layer processing functions. For instance, some functions of the RLC layer and the protocol layer functions above the RLC layer can be placed in the CU, while the remaining functions of the RLC layer and the protocol layer functions below the RLC layer can be placed in the DU. As another example, the functions of CU or DU can be divided according to service type or other system requirements, such as by latency, placing functions that need to meet low latency requirements in the DU and functions that do not need to meet such latency requirements in the CU.

[0104] For example, in some examples, the CU may not carry the PDCP layer, i.e., it may only carry the RRC layer. CU-CP may not carry PDCP-C, CU-UP may not carry PDCP-U, or CU-UP may not exist. In other examples, the DU may not carry the RLC layer. Furthermore, it is also possible to have only the DU without a CU.

[0105] Table 1 shows the correspondence between network elements in the ORAN system and the protocol layers they can implement.

[0106] Table 1

[0107] Net Element 3GPP protocol layer functions CU-CP RRC, PDCP-C CU-UP SDAP, PDCP-U DU RLC, MAC+PHY-high RU PHY-low

[0108] In scenarios where multiple network devices assist terminals in achieving wireless access, Figure 5 This is a schematic diagram of the communication system according to an embodiment of this application. Figure 5 The communication system shown includes CN, CU, DU, RU, and a terminal. CU, DU, and RU cooperate to assist the terminal in achieving wireless access.

[0109] In some implementations, CU and DU are included in BBU. In other implementations, CU, DU, and RU constitute RAN.

[0110] The CU performs some functions of layer 2 (L2) and layer 3 (L3), the DU performs some functions of layer 1 (L1) and layer 2, and the RU performs the calculations of layer 1 and the digital functions of the RF.

[0111] The midhaul interface carries traffic between the CU and DU, the backhaul interface carries traffic between the CU and CN, and the fronthaul interface carries traffic between the RU and DU. The integrated DU includes the functions of both the DU and RU mentioned above.

[0112] The CU and / or DU hardware includes a chassis platform, motherboard, peripherals, and cooling system. The motherboard contains processing units, memory, internal I / O interfaces, and external connection ports. Its hardware accelerators are designed with interfaces, and hardware functional components include: storage for software, hardware, and system debugging interfaces, and a single-board management controller.

[0113] The CU and / or DU include processors and hardware accelerators. The processors may include x86 processors or non-x86 processors, and the hardware accelerators may include FPGAs, GPUs, or other accelerators.

[0114] Taking DU as an example, DU can be implemented using a multi-core processor and one or more hardware accelerators. Parts of the DU protocol stack can be implemented in software running on a multi-core processor, while computationally intensive L1 and L2 functions can be offloaded to FPGA- or GPU-based hardware accelerators; or all L1 functions can be offloaded to FPGA- or GPU-based hardware accelerators, while other protocol stack components are implemented in software running on the processor; or the entire protocol stack can be implemented in software running on the processor. The hardware accelerator supports interconnection with x86 or non-x86 processors. Similarly, the accelerator has a multi-channel PCIe interface pointing to the CPU and external connections via GbE.

[0115] An RU can include three parts: an O-RAN processing unit (OPU), an O-RU digital processing unit (DPU), and a radio frequency (RF) processing unit.

[0116] The OPU receives eCPRI frames from the O-RAN fronthaul and performs fronthaul interface, lowest-level L1 (encoding, scrambling, modulation, layer mapping, precoding), synchronization, beamforming, and resource unit mapping. The OPU can be a CPU, FPGA, or ASIC.

[0117] The DPU can perform synchronous operation, DDC (digital downconversion in UL), DUC (digital upconversion in DL), CFR, and DPD, improving power amplifier efficiency by reducing PAPR / ACLR at the RF front end; the DPU can be an FPGA or an ASIC.

[0118] The RF processing unit may include a transceiver module, up / down converters, power amplifiers (PAs), low-noise amplifiers (LNAs), and Tx / Rx filters. All conversions between the analog and digital domains (DAC and ADC), such as RF sampling, frequency conversion using RF, IF, and LO mixing during up-conversion and down-conversion, are performed within the transceiver module. In some implementations, the physical and logical partitions within the RF processing unit do not require specific boundaries.

[0119] Figure 6 This is a schematic diagram of the communication system structure according to an embodiment of this application. In this embodiment, exemplarily, the core network equipment in the core network 300 refers to equipment in the core network (CN) that provides service support to the terminal. The core network equipment may further include at least one of the following: access and mobility management function (AMF) network elements, session management function (SMF) network elements, user plane function (UPF) network elements, policy control function (PCF) network elements, unified data management (UDM) network elements, authentication server function (AUSF) network elements, application function (AF) network elements, network exposure function (NEF) network elements, data network (DN) network elements, and network data analytics function (NWDAF) network elements, etc. Of course, the core network 300 may also include other core network equipment, without limitation.

[0120] The AMF (Agency Flow Management) network element is primarily responsible for mobility management in mobile networks, such as user location updates, user registration, user handover, reachability detection, SMF (Service Flow Management) node selection, and mobility state transition management. The SMF (Service Flow Management) network element is primarily responsible for session management in mobile networks, such as session establishment, modification, and release, and user plane node selection. The UPF (User Plane Functional Element) network element is responsible for connecting to external networks and processing user packets, such as forwarding, charging, packet routing and forwarding, mobility anchors, uplink classifiers to support routing service flows to the data network, and branch points to support multi-homed PDU sessions. The PCF (Programmable Flow Management) network element is primarily responsible for providing policies to the AMF and SMF, such as Quality of Service (QoS) policies, slice selection policies, flow-based charging control, and detection and gating based on service data flows and applications. The UDM (User Flow Management) network element is used to store user data, such as subscription information and authentication / authorization information. The AUSF (User USF) network element is primarily used to provide authentication services. The AF (Agency Flow Management) network element is responsible for providing services to the 3GPP network, influencing service flow routing, access network capability exposure, and policy control. NEF network elements are primarily used to securely expose services and capabilities provided by 3GPP network functions, such as third-party services, edge computing, and AF. DN network elements are primarily used to provide services, such as carrier services, internet access, or third-party services. NWDAF network elements are primarily used for collecting and analyzing network data using technologies such as big data and artificial intelligence.

[0121] It should be noted that in this application, network elements can also be referred to as entities or functional entities. For example, an AMF network element can also be referred to as an AMF entity or an AMF functional entity. Furthermore, the aforementioned SMF network elements, UPF network elements, PCF network elements, UDM network elements, AUSF network elements, AF network elements, NEF network elements, DN network elements, and NWDAF network elements may have other names in future communication systems, and this application does not impose specific limitations on them.

[0122] It should be noted that core network equipment can correspond to different devices in different systems. For example, in 3G, it can correspond to the Serving GPRS Support Node (SGSN) and / or the Gateway GPRS Support Node (GGSN) for General Packet Radio Service (GPRS); in 4G, it can correspond to the Mobility Management Entity (MME) and / or the Serving Gateway (S-GW); and in 5G, it can correspond to AMF, SMF, or UPF network elements.

[0123] It should be noted that the communication system described in the embodiments of this application is for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and does not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0124] The method provided in the embodiments of this application will be described below in conjunction with the aforementioned communication system. It should be noted that the message names, parameter names, or information names in the following embodiments of this application are merely examples, and may be other names in other embodiments. The method provided in this application is not specifically limited in this regard.

[0125] It is understood that the methods in the embodiments of this application can be applied to terminals or RAN nodes. Terminals or RAN nodes can execute some or all of the steps in the embodiments of this application. These steps or operations are merely examples, and the embodiments of this application can also perform other operations or variations of various operations. Furthermore, the various steps can be executed in different orders as presented in the embodiments of this application, and it is not necessary to execute all the operations in the embodiments of this application.

[0126] It is understood that the execution subject of the method in the embodiments of this application can be a terminal or a RAN node, and this application does not limit the execution subject. For example, the method executed by the terminal or RAN node in this application can also be executed by a module (e.g., a chip, chip system, or processor) applied to the terminal or RAN node, or it can be implemented by a logical node, logical module, or software that can implement all or part of the functions of the terminal or RAN node.

[0127] Figure 7 This is a flowchart of a decoding method according to an embodiment of this application. The method may include the following steps:

[0128] S701. Verify the N posterior information of the Tth iteration corresponding to the N variable nodes according to the parity check matrix of the low-density parity check code. The N posterior information of the Tth iteration includes: the posterior information determined by the N variable nodes based on the K external information transmitted from the variable nodes to the check nodes and the S external information transmitted from the check nodes to the variable nodes obtained by decoding the (T-1)th iteration, where M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer.

[0129] Understandably, T is less than or equal to the maximum number of iterations.

[0130] The posterior information is the posterior information of the variable nodes; the K external information transmitted from the variable nodes to the verification nodes is the external information transmitted from the N variable nodes to the M verification nodes; the S external information transmitted from the verification nodes to the variable nodes is the external information transmitted from the M verification nodes to the N variable nodes.

[0131] For example, combining the above steps based on NMSA iteration, the M verification nodes in S701 correspond to CN0 to CN. M-1 The N variable nodes can be VN0 to VN N-1 The N posterior information of the Tth iteration can be from λ0 to λ N-1 .

[0132] by Figure 1 For example, K pieces of external information transmitted from the variable node to the verification node correspond to q. 0→0 q 0→2 q 1→0 q 1→1 q 2→0 q 2→1 q 2→2 q 3→1 and q 3→2 S external information transmitted from the verification node to the variable node corresponds to r 0→0 r 0→1 r 0→2 r 1→1 r 1→2 r 1→3 r 2→0 r 2→2 and r 2→3 The N posterior information of the Tth iteration can be λ n λ, n = 0, 1, 2, 3. n Determined based on the above formula (7).

[0133] The verification method can be: verification Check if it equals 0. If the check is successful, that is... Then exit the iteration and return. As the result of decoding.

[0134] S702. If the verification fails, determine whether the signs of the post-T iteration information of the nth variable node among the N variable nodes are the same as those of the post-T-C+1 iteration information, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1.

[0135] Understandably, C is less than the maximum number of iterations.

[0136] In one possible implementation, for the nth variable node among N variable nodes, after obtaining the posterior information for each iteration, the iteration number and the corresponding posterior information can be stored. For example, when determining whether the signs of the posterior information from the Tth iteration to the (T-C+1)th iteration are the same for the nth variable node among N variable nodes, this can be determined based on the stored iteration number and the corresponding posterior information.

[0137] In another possible implementation, the change in the counter can be used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged. For example, when determining whether the signs of the posterior information of the nth variable node in N variable nodes are the same from the Tth iteration to the (T-C+1)th iteration, the change in the counter can be used to determine whether the signs of the posterior information from the Tth iteration to the (T-C+1)th iteration are the same.

[0138] S703. If the signs of the posterior information of the nth variable node in the Tth iteration are the same as those in the (T-C+1)th iteration, the magnitude of the posterior information of the nth variable node in the Tth iteration is set to the maximum value.

[0139] For example, the sign of the posterior information of the nth variable node in the Tth iteration can be positive or negative, i.e., "+" or "-". For instance, when the value of the posterior information of the nth variable node in the Tth iteration is 0.5, the sign of the posterior information is positive; when the value of the posterior information of the nth variable node in the Tth iteration is -0.5, the sign of the posterior information is negative.

[0140] For example, the maximum magnitude λ of the posterior information can be preset. max When the signs of the posterior information of the nth variable node in the Tth iteration are the same as those in the (T-C+1)th iteration, λ is... n =λ max .

[0141] It should be noted that during the decoding process, as the iterations proceed, when the variable node tends to converge, the sign of its posterior information no longer changes with the iterations. In other words, when the sign of the posterior information of the variable node no longer changes for several consecutive times, setting the amplitude of the posterior information of the variable node to the maximum value can accelerate the convergence of decoding.

[0142] Based on the above method, the condition for setting the amplitude of the posterior information of the nth variable node at its maximum value in the Tth iteration is: determining whether the signs of the posterior information of the variable node from the Tth iteration to the (T-C+1)th iteration are the same. This condition, compared to determining that the amplitude of the variable node's posterior information is greater than a threshold, compares the signs, while the latter compares the posterior information of the variable node. Because the posterior information of the variable node is usually a floating-point number, the complexity of sign comparison is lower than that of posterior information comparison. In other words, this method accelerates decoding convergence while reducing decoding complexity. Furthermore, this method does not require setting an amplitude threshold, which improves the robustness of the method compared to setting an amplitude threshold related to the channel signal-to-noise ratio, thereby enhancing decoding performance.

[0143] As one possible implementation, before the first iteration of decoding, N counters are initialized to preset values, and the N counters correspond one-to-one with the N variable nodes;

[0144] Among them, determining whether the signs of the posterior information of the nth variable node in the Tth iteration to the posterior information of the (T-C+1)th iteration are the same includes:

[0145] If the posterior information of the nth variable node in the Tth iteration has the same sign as the posterior information in the (T-1)th iteration, then the counter corresponding to the nth variable node is adjusted, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged, plus 1.

[0146] If the number of consecutive iterations indicated by the change in the counter corresponding to the nth variable node relative to the preset value is greater than or equal to C, then the signs of the posterior information of the Tth iteration to the posterior information of the T-C+1th iteration of the nth variable node are the same.

[0147] Accordingly, the method also includes:

[0148] If the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then the counter corresponding to the nth variable node is set to the preset value.

[0149] As one possible implementation, the default value is 0, and / or the change is 1.

[0150] It should be noted that the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same, which can also be understood as the signs of the posterior information of the nth variable node being the same for C-1 consecutive iterations.

[0151] Thus, by comparing the changes in the counter, it is possible to determine whether the sign of the posterior information of the nth variable node remains unchanged for multiple consecutive times. It also transforms the comparison between floating-point numbers into a comparison between integers, reducing complexity. Furthermore, the setting of the constant C is independent of SNR, ensuring the robustness of this method and thus accelerating the convergence speed.

[0152] For example, the implementation of the above method can be completed based on the following pseudocode.

[0153]

[0154] Here, sgn() represents the sign function.

[0155] In some implementations, count th The numerical value can be set based on the results of multiple simulation experiments. The value can be set as small as possible while ensuring the decoding performance of this method.

[0156] Figure 8 This is a schematic diagram illustrating the algorithm implementation of multiple iterations in an embodiment of this application. Figure 8 As shown, the counter threshold is count. th If C = 3, the iteration counts (iter) are 1, 2, 3, and 4 respectively, the preset value of the counter is 0, and the counter change is 1, then there are four possible cases.

[0157] Case 1: The magnitude of the posterior information obtained after the first iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the second iteration of the nth variable node is less than or equal to 0, i.e., λ n ≤0.

[0158] In other words, if the sign of the posterior information of the second iteration of the nth variable node is different from that of the posterior information of the first iteration, then the counter value is set to 0, i.e., count[n] = 0.

[0159] Case 2: The magnitude of the posterior information obtained after the first iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the second iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the 3rd iteration of the nth variable node is less than or equal to 0, i.e., λ n ≤0.

[0160] In other words, if the sign of the posterior information of the nth variable node in the second iteration is the same as that in the first iteration, the counter value is incremented by 1, i.e., count[n] = 1. If the sign of the posterior information of the nth variable node in the third iteration is different from that in the second iteration, the counter value is set to 0, i.e., count[n] = 0.

[0161] Case 3: The magnitude of the posterior information obtained after the first iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the second iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the 3rd iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the 4th iteration of the nth variable node is less than or equal to 0, i.e., λ n ≤0.

[0162] In other words, if the sign of the posterior information of the nth variable node in the second iteration is the same as that in the first iteration, the counter value is incremented by 1, i.e., count[n] = 1. If the sign of the posterior information of the nth variable node in the third iteration is the same as that in the second iteration, the counter value is incremented by 1, i.e., count[n] = 2. If the sign of the posterior information of the nth variable node in the fourth iteration is different from that in the third iteration, the counter value is set to 0, i.e., count[n] = 0.

[0163] Case 4: The magnitude of the posterior information obtained after the first iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the second iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the 3rd iteration of the nth variable node is greater than 0, i.e., λ n >0; the magnitude of the posterior information obtained after the 4th iteration of the nth variable node is greater than 0, i.e., λ n >0.

[0164] In other words, if the sign of the posterior information of the nth variable node in the second iteration is the same as the sign of the posterior information in the first iteration, then the counter value is incremented by 1, i.e., count[n] = 1. If the sign of the posterior information of the nth variable node in the third iteration is the same as the sign of the posterior information in the second iteration, then the counter value is incremented by 1, i.e., count[n] = 2. If the sign of the posterior information of the nth variable node in the fourth iteration is the same as the sign of the posterior information in the third iteration, then the counter value is incremented by 1, i.e., count[n] = 3.

[0165] At this point, count[n] equals the counter threshold, so the magnitude of the posterior information of the nth variable node in the 4th iteration is set to the maximum value, and the current sign bit is maintained, i.e., λ. n =sgn(λ n )·λ max .

[0166] The method provided in this application has been described above. In addition, this application also provides a decoding device for implementing the functions described in the above method embodiments.

[0167] It is understood that, in order to achieve the above-mentioned functions, the decoding device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0168] This application embodiment can divide the decoding device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0169] Figure 9 This is a schematic diagram of the structure of a decoding device 90 according to an embodiment of this application. The decoding device 90 includes a processing module 901.

[0170] In some embodiments, the decoding device 90 may further include a storage module. Figure 9 (Not shown in the image) is used to store program instructions and data.

[0171] In some embodiments, the processing module 901 may be used to perform the steps of the processing class in the above method embodiments, and / or other processes to support the technology described herein.

[0172] In one possible implementation, the processing module 901 is used to verify N T-th iteration posterior information corresponding to N variable nodes according to the parity check matrix of the low-density parity check code. The N T-th iteration posterior information includes: K extrinsic information transmitted from the variable nodes to the verification nodes and S extrinsic information transmitted from the verification nodes to the variable nodes obtained from the (T-1)th iteration decoding, which are the posterior information determined by the N variable nodes, where M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer. If the verification fails, it is determined whether the signs of the T-th iteration posterior information to the T-C+1th iteration posterior information of the nth variable node are the same, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1. If the signs of the T-th iteration posterior information to the T-C+1th iteration posterior information of the nth variable node are the same, the amplitude of the T-th iteration posterior information of the nth variable node is set to the maximum value.

[0173] In one possible implementation, the processing module 901 is further configured to: initialize N counters to preset values ​​before the first iteration of decoding, wherein the N counters correspond one-to-one with the N variable nodes;

[0174] Specifically, the processing module 901 is used to: if the posterior information of the nth variable node in the Tth iteration has the same sign as the posterior information in the (T-1)th iteration, then adjust the counter corresponding to the nth variable node, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged, increment by 1; if the number of consecutive iterations indicated by the change in the counter corresponding to the nth variable node relative to the preset value is greater than or equal to C, then determine that the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same.

[0175] The processing module 901 is further configured to: if the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then set the counter corresponding to the nth variable node to a preset value.

[0176] In one possible implementation, the preset value is 0, and / or the change is 1.

[0177] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0178] In this application, the decoding device 90 can be presented in an integrated manner, divided into various functional modules. Here, "module" can refer to an application-specific integrated circuit (ASIC), a circuit, a processor and memory that executes one or more software or firmware programs, integrated logic circuits, and / or other devices that can provide the above functions.

[0179] In some embodiments, when Figure 9 When the decoding device 90 is a chip or chip system, the function / implementation process of the processing module 901 can be implemented by the processor (or processing circuit) of the chip or chip system.

[0180] Since the decoding device 90 provided in this embodiment can execute the above method, the technical effects it can achieve can be referred to the above method embodiment, and will not be repeated here.

[0181] As one possible product form, the device described in the embodiments of this application can be implemented using one or more field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gate logic, discrete hardware components, any other suitable circuits, or any combination of circuits capable of performing the various functions described throughout this application.

[0182] As another possible product form, the terminal or RAN node in this application can adopt... Figure 10 The shown composition structure, or including Figure 10 The components shown. Figure 10 This is a schematic diagram of the composition of a decoding device 1000 according to an embodiment of this application. The decoding device 1000 can be a terminal or a chip or system-on-a-chip in a terminal; or it can be a RAN node or a module, chip or system-on-a-chip in a RAN node.

[0183] like Figure 10 As shown, the decoding device 1000 includes at least one processor 1001 and at least one communication interface. Figure 10 (This is merely an example illustration, using a communication interface 1004 and a processor 1001 as examples.) Optionally, the decoding device 1000 may also include a communication bus 1002, a memory 1003, and a computer-readable medium 1007.

[0184] Processor 1001 can be a general-purpose central processing unit (CPU), a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor (e.g., x86, RISC microprocessor (advanced RISC machine, ARM)), a microcontroller, a PLD, a field-programmable gate array (FPGA), a graphics processing unit (GPU), a state machine, gated logic, discrete hardware circuitry, or any combination thereof. Processor 1001 can also be other devices with processing capabilities, such as circuits, devices, or software modules, without limitation.

[0185] The communication bus 1002 is used to connect different components in the decoding device 1000, enabling communication between them. The communication bus 1002 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0186] The communication bus 1002 may include any number of interconnect buses and bridges. The communication bus 1002 couples various circuits together, including one or more processors 1001 (typically represented by a processor), memory 1003, and computer-readable medium 1007 (typically represented by a computer-readable medium). The communication bus 1002 may also connect various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits.

[0187] Communication interface 1004 is used for communicating with other devices or communication networks. Exemplarily, communication interface 1004 can be a module, circuit, transceiver, or any device capable of communication. Optionally, communication interface 1004 can also be an input / output interface located within processor 1001, used to implement signal input and signal output for the processor. Communication interface 1004 can provide communication between communication bus 1002 and the transceiver, or communication between communication bus 1002 and other interfaces.

[0188] The memory 1003 may be a device with storage function, used to store instructions and / or data. The instructions may be computer programs.

[0189] For example, the memory 1003 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and / or instructions; it may also be a random access memory (RAM) or other type of dynamic storage device capable of storing information and / or instructions; it may also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, etc., without limitation.

[0190] Processor 1001 is responsible for managing communication bus 1002 and general processing functions, including executing software stored on computer-readable medium 1007. When executed by processor 1001, the software causes the processing system to perform the various functions described below for any particular device.

[0191] The processor 1001, memory 1003, and computer-readable medium 1007 can perform the following functions: encoding, decoding, rate matching, rate dematching, scrambling, descrambling, modulation, demodulation, layer mapping, fast fourier transform (FFT), inverse fast fourier transform (FFT), inverse discrete fourier transform (IDFT), precoding, resource element (RE) mapping, channel equalization, RE demapping, digital beamforming (BF), adding cyclic prefix (CP), removing CP, etc.

[0192] It should be noted that the memory 1003 can exist independently of the processor 1001, or it can be integrated with the processor 1001. The memory 1003 can be located inside or outside the decoding device 1000, without limitation. The processor 1001 can be used to execute the instructions stored in the memory 1003 to implement the methods provided in the following embodiments of this application.

[0193] As an optional implementation, the decoding device 1000 may also include an output device 1005 and an input device 1006. The output device 1005 communicates with the processor 1001 and can display information in various ways. For example, the output device 1005 may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device 1006 communicates with the processor 1001 and can receive user input in various ways. For example, the input device 1006 may be a mouse, keyboard, touchscreen device, or sensor device, etc.

[0194] For example, the output device 1005 and input device 1006 described above can also be integrated into a transceiver, which can be used to communicate with various other devices via a communication interface or device through a wireless transmission medium. The transceiver can be coupled to an antenna array, and the transceiver and antenna array can be used together to communicate with a corresponding network device type. The transceiver provides at least one interface (e.g., a network interface and / or a user interface) for communication via the communication bus 1002 or via an external transmission medium. The transceiver can implement both transmitting and receiving functions. When the transceiver implements the transmitting function, it can be called a transmitting module (sometimes also called a transmitting unit), and when the transceiver implements the receiving function, it can be called a receiving module (sometimes also called a receiving unit). The transmitting module and the receiving module can be the same functional module, called a transceiver module, which implements both transmitting and receiving functions; or the transmitting module and the receiving module can be different functional modules, and the transceiver module can also be a collective term for these functional modules.

[0195] In some embodiments, the hardware implementation will be apparent to those skilled in the art as described above. Figure 9 The decoding device 90 shown can employ Figure 10 The decoding device shown is in the form of 1000.

[0196] As an example, Figure 9 The function / implementation process of the processing module 901 can be achieved through... Figure 10 The processor 1001 in the decoding device 1000 shown calls computer execution instructions stored in memory 1003 to implement the function.

[0197] It should be noted that, Figure 10The structures shown do not constitute a specific limitation on the terminal or RAN node. For example, in other embodiments of this application, the terminal or RAN node may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0198] In some embodiments, this application also provides a decoding apparatus, which includes a processor for implementing the methods in any of the above method embodiments.

[0199] As one possible implementation, the decoding device further includes a memory. This memory stores necessary computer programs and data. The computer program may include instructions, which the processor can invoke to instruct the decoding device to execute the methods described in any of the above method embodiments. Alternatively, the memory may not be present in the decoding device.

[0200] As another possible implementation, the decoding device also includes an interface circuit, which is a code / data read / write interface circuit, used to receive computer execution instructions (which are stored in memory and may be read directly from memory or may be transmitted through other devices) and transmit them to the processor.

[0201] As another possible implementation, the decoding device also includes a communication interface for communicating with modules outside the decoding device.

[0202] It is understood that the decoding device can be a chip or a chip system. When the decoding device is a chip system, it can be composed of chips or may include chips and other discrete devices. This application does not specifically limit this.

[0203] This application also provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a computer, implements the functions of any of the above-described method embodiments.

[0204] This application also provides a computer program product that, when executed by a computer, implements the functions of any of the above method embodiments.

[0205] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0206] It is understood that the systems, apparatuses, and methods described in this application can also be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0207] The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. The components shown as units may or may not be physical units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0208] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0209] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive (SSD)). In embodiments of this application, the computer may include the aforementioned apparatus.

[0210] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0211] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the scope of this application. Accordingly, this specification and drawings are merely illustrative descriptions of the application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of the claims and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A decoding method, characterized in that, The method includes: The N posterior information of the Tth iteration corresponding to the N variable nodes are verified according to the parity check matrix of the low-density parity check code. The N posterior information of the Tth iteration includes: K extrinsic information transmitted from the variable nodes to the verification nodes and S extrinsic information transmitted from the verification nodes to the variable nodes obtained by decoding the (T-1)th iteration, which are the posterior information determined by the N variable nodes. M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer. If the verification fails, determine whether the signs of the posterior information of the nth variable node in the Tth iteration to the posterior information of the (T-C+1)th iteration are the same, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1. If the signs of the posterior information of the nth variable node in the Tth iteration are the same as those in the (T-C+1)th iteration, the magnitude of the posterior information of the nth variable node in the Tth iteration is set to the maximum value.

2. The method according to claim 1, characterized in that, The method further includes: Before the first iteration of decoding, N counters are initialized to preset values, and the N counters correspond one-to-one with the N variable nodes; Determining whether the signs of the posterior information of the nth variable node from the Tth iteration to the (T-C+1)th iteration are the same includes: If the posterior information of the nth variable node in the Tth iteration has the same sign as the posterior information in the (T-1)th iteration, then the counter corresponding to the nth variable node is adjusted, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged is incremented by 1. If the number of consecutive iterations indicated by the change of the counter corresponding to the nth variable node relative to the preset value is greater than or equal to C, then it is determined that the signs of the posterior information of the Tth iteration to the posterior information of the T-C+1th iteration of the nth variable node are the same. The method further includes: If the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then the counter corresponding to the nth variable node is set to the preset value.

3. The method according to claim 2, characterized in that, The preset value is 0, and / or the change amount is 1.

4. A decoding device, characterized in that, The device includes: a processing module; The processing module is used to verify the N T-th iteration posterior information corresponding to N variable nodes according to the parity check matrix of the low-density parity check code. The N T-th iteration posterior information includes: K extrinsic information transmitted from the variable node to the verification node and S extrinsic information transmitted from the verification node to the variable node obtained by decoding the (T-1)-th iteration, which are the posterior information determined by the N variable nodes, where M is a positive integer, T is a positive integer, N is a positive integer, K is a positive integer, and S is a positive integer. If the verification fails, it is determined whether the signs of the T-th iteration posterior information to the T-C+1-th iteration posterior information of the n-th variable node are the same, where n is a positive integer and n is less than or equal to N, and C is a positive integer greater than 1. If the signs of the T-th iteration posterior information to the T-C+1-th iteration posterior information of the n-th variable node are the same, the amplitude of the T-th iteration posterior information of the n-th variable node is set to the maximum value.

5. The apparatus according to claim 4, characterized in that, The processing module is further configured to: Before the first iteration of decoding, N counters are initialized to preset values, and the N counters correspond one-to-one with the N variable nodes; Specifically, the processing module is configured to: if the posterior information of the nth variable node in the Tth iteration has the same sign as the posterior information in the (T-1)th iteration, then adjust the counter corresponding to the nth variable node, and the change in the counter corresponding to the nth variable node is used to indicate the number of consecutive iterations in which the sign of the posterior information of the nth variable node remains unchanged, increment by 1; if the number of consecutive iterations indicated by the change in the counter corresponding to the nth variable node relative to a preset value is greater than or equal to C, then determine that the posterior information of the nth variable node in the Tth iteration to the posterior information in the (T-C+1)th iteration has the same sign. The processing module is further configured to: if the sign of the posterior information of the nth variable node in the Tth iteration is different from that in the (T-1)th iteration, then set the counter corresponding to the nth variable node to the preset value.

6. The apparatus according to claim 5, characterized in that, The preset value is 0, and / or the change amount is 1.

7. A decoding device, characterized in that, The decoding apparatus includes a processor; the processor is configured to run a computer program or instructions to cause the decoding apparatus to perform the method as described in any one of claims 1-3.

8. A chip or chip system, characterized in that, The chip or chip system includes a processor coupled to a memory for storing programs or instructions that, when executed by the processor, cause the method as described in any one of claims 1-3 to be performed.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions or programs that, when executed on a computer, cause the method described in any one of claims 1-3 to be performed.

10. A computer program product, characterized in that, The computer program product includes computer instructions; when some or all of the computer instructions are run on a computer, the method described in any one of claims 1-3 is performed.

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