A display device

Abstract

The application discloses a display device, and belongs to the technical field of display. A power management basic circuit in the display device is used for providing a target voltage for a display power supply circuit. The display power supply circuit is used for voltage conversion on the target voltage, obtaining a display driving voltage, and providing the display driving voltage for a display panel to drive the display panel to display. The target voltage at least includes a gate high voltage VGH and a gate low voltage VGL, or the target voltage at least includes an analog positive power supply voltage AVDD. The display device in the application reduces the circuit layout complexity of the display driving architecture in the display device, effectively reduces the energy loss caused by multiple voltage conversions in the display power supply process, significantly reduces the static power consumption and dynamic switching loss of the display device, is also beneficial to reducing the number of components applied by the display driving architecture in the display device and releasing the wiring space, and thus reduces the material cost of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display device. Background Technology

[0002] In order to enable the display panel to display normally, the display driver architecture in the display device usually needs to provide the display panel with a variety of different types of display driver voltages to meet the driving requirements of the display panel in the processes of scanning drive, pixel initialization and pixel data writing.

[0003] However, the circuit layout of the display driver architecture in related display devices is quite complex. This complex layout not only increases the overall power consumption of the display device but also increases the number of peripheral components in the display driver architecture, leading to a decrease in the overall integration of the display device and an increase in material costs.

[0004] Therefore, how to reduce the complexity of the circuit layout of the display driver architecture while stably providing multiple display driving voltages for the display panel is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] A display device is provided that aims to reduce the circuit layout complexity of the display driving architecture while stably providing multiple display driving voltages to the display panel, thereby reducing the overall power consumption and material cost of the display device and improving the overall integration of the display device.

[0006] To achieve the above objectives, a display device is provided, comprising: a display panel, a display power supply circuit, and a power management integrated circuit; the input terminal of the display power supply circuit is connected to the output terminal of the power management integrated circuit; the output terminal of the display power supply circuit is connected to the input terminal of the display panel. The power management integrated circuit is used to provide a target voltage for the display power supply circuit; The display power supply circuit is used to convert the target voltage to obtain a display driving voltage, and to provide the display driving voltage to the display panel to drive the display panel to display. The target voltage includes at least a gate high voltage VGH and a gate low voltage VGL, or the target voltage includes at least an analog positive power supply voltage AVDD.

[0007] The display device provided in this application includes a power management integrated circuit that directly provides a target voltage to the display power supply circuit, comprising at least a gate high voltage VGH and a gate low voltage VGL, or at least an analog positive power supply voltage AVDD. This target voltage is used by the display power supply circuit to generate a display driving voltage for driving the display panel. This reduces the complexity of the circuit layout of the display driving architecture in the display device, simplifies the power supply path within the display device, reduces voltage conversion stages in the display power supply process, effectively reduces energy loss caused by multiple voltage conversions during the display power supply process, and significantly reduces the static power consumption and dynamic switching losses of the display device. Furthermore, the reduced complexity of the circuit layout of the display driving architecture helps to reduce the number of components used in the display driving architecture, thereby reducing the material cost of the display device. It also frees up wiring space on the printed circuit board in the display device, reducing the wiring complexity and signal interference risk of the printed circuit board, and greatly improving the system integration and operational reliability of the display device. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the circuit structure of the display driver architecture in related technologies; Figure 2 This is a voltage generation path diagram in the display driver architecture of related technologies; Figure 3 This is one of the structural schematic diagrams of a display device according to an exemplary embodiment of the present disclosure; Figure 4 This is one of the voltage generation path diagrams of the display device according to an exemplary embodiment of this disclosure; Figure 5 This is a second schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure; Figure 6 This is a second voltage generation path diagram of a display device according to an exemplary embodiment of the present disclosure; Figure 7 This is the third schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure; Figure 8 This is the third voltage generation path diagram of the display device according to an exemplary embodiment of the present disclosure; Figure 9 This is the fourth schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure; Figure 10 This is the fourth voltage generation path diagram of a display device according to an exemplary embodiment of this disclosure.

[0010] Figure label: 100: Traditional display device; 11: Display panel; 12: Display driver chip; 13: Power management integrated circuit; 300: Display device; 32: Display power supply circuit; LDO1: First low dropout linear regulator; LDO2: Second low dropout linear regulator; LDO3: Third low dropout linear regulator; LDO4: Fourth low dropout linear regulator; LDO5: Fifth low dropout linear regulator; CP1: First charge pump; CP2: Second charge pump; CP3: Third charge pump; CP4: Fourth charge pump; GND: Ground terminal; C3-C20: Stabilizing capacitors; C21-C24: Charge pump capacitors.

[0011] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0013] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0014] Typically, a display panel contains a pixel array comprising multiple pixel units for image display. The display panel also typically includes pixel circuitry to drive the pixel units in the pixel array to emit light and maintain the display signal, and gate drivers to drive the pixel units in the pixel array to turn on and off line by line.

[0015] Typically, the display driving voltage used to drive the display panel for display can include, but is not limited to, the regulated gate high voltage VRGH, the regulated gate low voltage VRGL, the initial positive voltage VINITP, the initial negative voltage VINITN, the gate maximum positive voltage (VGMP), and the gate maximum negative voltage (VGSP).

[0016] Specifically, the regulated gate high voltage VRGH and the regulated gate low voltage VRGL are used to provide driving voltage to the gate driver in the display panel during the display stage, so as to output high-level scanning signals and low-level scanning signals to the gate of the thin-film transistor in the pixel array during the scanning stage, thereby controlling the conduction and turn-off of the thin-film transistor and realizing the writing and retention of pixel data.

[0017] The initialization positive voltage VINITP and initialization negative voltage VINITN are specifically used to reset the pixel circuit during the initialization phase, so as to pull the control nodes of the pixel electrodes or driving transistors in the pixel circuit to the preset initial potential, thereby eliminating the residual charge of the previous frame and providing stable initial conditions for subsequent pixel data writing.

[0018] The maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are specifically used to provide the maximum positive gate drive voltage and the maximum negative gate drive voltage to the gate driver, so as to determine the voltage swing of the gate scan signal, thereby realizing the progressive scan drive of the pixel array of the display panel.

[0019] In order to meet the driving requirements of the display panel in the processes of scanning drive, pixel initialization and pixel data writing, traditional display devices in related technologies provide the display panel with a variety of different types of display driving voltages by adopting a multi-level display driving architecture.

[0020] Figure 1 This is a schematic diagram of the circuit structure of a display device in related technologies. Figure 2 This is a voltage generation path diagram in a display device of related technology. Please refer to... Figure 1 and Figure 2 In a conventional display device 100, the power management integrated circuit 13 (PMIC) typically outputs basic power supply voltages such as analog positive power supply voltage (Analog VDD, AVDD), input power supply voltage (Voltage Common Input, VCI), interface positive voltage (VDD Input, VDDI), and digital power supply voltage (Digital VDD Power, DVDDP).

[0021] The multi-stage charge pump or other voltage conversion circuit in the display driver chip 12 includes: performing multiple voltage conversions or negative voltage conversions on the basic power supply voltage output by the power management integrated circuit 13 to obtain the display driving voltage required by the display panel 11.

[0022] Specifically, after the analog positive power supply voltage AVDD, the interface positive voltage VDDI, and the input power supply voltage VCI are converted by a charge pump or other voltage conversion circuits, intermediate voltages such as gate high voltage VGH, gate low voltage VGL, and analog negative power supply voltage (Analog VEE, AVEE) can be obtained.

[0023] After the aforementioned intermediate voltage is converted again by a charge pump or other voltage conversion circuit, display driving voltages such as initial positive voltage VINITP, initial negative voltage VINITN, regulated gate high voltage VRGH, and regulated gate low voltage VRGL can be obtained, which are used to drive the display panel 11 to display.

[0024] However, the aforementioned conventional display device 100 still has certain limitations in practical applications. First, the display driver chip 12 includes multiple stages of charge pumps or other voltage conversion circuits, making the circuit layout of the display driver chip 12 relatively complex. The display driving voltage needs to be generated step by step through multiple stages of charge pumps or other voltage conversion circuits, resulting in a long path for the power supply load current, leading to higher static power consumption and dynamic switching losses during the voltage conversion process, thus increasing the overall power consumption of the conventional display device 100.

[0025] Secondly, during the voltage conversion process, components such as capacitors and inductors are required for energy storage and voltage regulation. Multi-stage charge pumps or other voltage conversion circuits require a large number of components for energy storage and voltage regulation, which increases the material cost of traditional display devices by 100% while reducing the integration of printed circuit boards.

[0026] Third, the multiple base supply voltages output by the power management integrated circuit 13 increase the number of power signal traces on the flexible printed circuit (FPC), thereby increasing the complexity of the FPC wiring design and the risk of signal interference.

[0027] In addition, the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP in the display driving voltage are also generated by the display driver chip 12 based on the analog positive power supply voltage AVDD, which increases the complexity of the internal circuit structure of the display driver chip 12 and also increases the power consumption level inside the display driver chip 12.

[0028] In this regard, this application provides a display device.

[0029] Figure 3 This is one of the structural schematic diagrams of a display device according to an exemplary embodiment of the present disclosure. Figure 4 This is one of the voltage generation path diagrams for a display device according to an exemplary embodiment of this disclosure. Figure 5 This is a second schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. Figure 6 This is a second voltage generation path diagram of a display device according to an exemplary embodiment of this disclosure. Figure 7 This is the third schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. Figure 8 This is the third voltage generation path diagram of a display device according to an exemplary embodiment of this disclosure. Figure 9 This is the fourth schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. Figure 10 This is the fourth voltage generation path diagram of a display device according to an exemplary embodiment of this disclosure.

[0030] Please refer to Figures 3 to 10 The display device 300 includes: a display panel 11, a display power supply circuit 32, and a power management integrated circuit 13; the input terminal of the display power supply circuit 32 is connected to the output terminal of the power management integrated circuit 13; the output terminal of the display power supply circuit 32 is connected to the input terminal of the display panel 11.

[0031] The power management integrated circuit 13 is used to provide the target voltage for the display power supply circuit.

[0032] The display power supply circuit 32 is used to convert the target voltage to obtain the display driving voltage and provide the display driving voltage to the display panel 11 to drive the display panel 11 to display.

[0033] The target voltage includes at least the gate high voltage VGH and the gate low voltage VGL, or the analog positive power supply voltage AVDD.

[0034] Specifically, the display device 300 in this embodiment can be an electronic device with display function, such as a smartphone, tablet computer, laptop computer, television, smart wearable device (such as a smartwatch), or vehicle display screen. This application embodiment does not limit the specific type of the display device 300.

[0035] In this embodiment, the display panel 11 is a panel assembly used for image display in the display device 300. The display panel 11 can be a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) panel, a mini light-emitting diode (Mini-LED) backlight display, or a quantum dot light-emitting diode (QLED) display, etc. In this embodiment, the specific type of the display panel 11 is not limited.

[0036] Optionally, in this embodiment, the pixel unit in the display panel 11 includes an oxide thin film transistor (Oxide TFT, such as IGZO semiconductor material).

[0037] In this embodiment, the power management integrated circuit 13 refers to an integrated circuit used in the display device 300 to manage, distribute, and convert electrical energy. In this embodiment, the power management integrated circuit 13 is used to output a target voltage to the display power supply circuit 32.

[0038] It is understood that in this embodiment, the input terminal of the power management integrated circuit 13 is connected to the power supply.

[0039] In this embodiment, the display power supply circuit 32 is a circuit module in the display device 300 responsible for generating the display driving voltage for the display panel 11 to display. After receiving the target voltage from the power management integrated circuit 13, the display power supply circuit 32 can generate the display driving voltage required by the display panel 11 through internal voltage conversion logic (such as buck, boost, etc.).

[0040] In this embodiment, the display driving voltage refers to various voltage signals used to directly drive the pixel array, gate driver, and pixel circuit in the display panel 11 to operate normally. The display driving voltage may include, but is not limited to, regulated gate high voltage VRGH, regulated gate low voltage VGL_REG, initialization positive voltage VINITP, and initialization negative voltage VINITN.

[0041] It should be noted that the target voltage in this embodiment is the voltage combination directly output by the power management integrated circuit 13 to the display power supply circuit 32. The target voltage has two possible combinations: one is that the target voltage includes at least the gate high voltage VGH and the gate low voltage VGL; the other is that the target voltage includes at least the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD.

[0042] Accordingly, the display driving circuit in this embodiment can at least perform voltage conversion between the gate high voltage VGH and the gate low voltage VGL to obtain a display driving voltage for driving the display panel 11 to display; or, the display driving circuit in this embodiment can at least perform voltage conversion between the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain a display driving voltage for driving the display panel 11 to display.

[0043] It should be noted that in the conventional display device 100, after the gate high voltage VGH and gate low voltage VGL are generated by the charge pump or other voltage conversion circuit inside the display driving architecture based on other base voltages (such as analog positive power supply voltage AVDD, interface positive voltage VDDI, and input power supply voltage VCI, etc.), the gate high voltage VGH and gate low voltage VGL are converted again by the charge pump or other voltage conversion circuit to obtain the display driving voltage used to drive the display panel 11 for display. This results in a more complex circuit layout of the display driving architecture in the conventional display device 100.

[0044] For the display panel 11 employing oxide thin-film transistors (such as IGZO semiconductor material), oxide TFTs possess high electron mobility and extremely low leakage current characteristics. This allows oxide TFTs to achieve the same or even better switching characteristics while requiring significantly lower absolute values ​​of the gate high voltage VGH and gate low voltage VGL compared to traditional amorphous silicon (a-Si) thin-film transistors. This reduction in the absolute values ​​of the gate high voltage VGH and gate low voltage VGL required by the display panel 11 provides physical support for the power management integrated circuit 13 to output the gate high voltage VGH and gate low voltage VGL.

[0045] Furthermore, the inductor-based DC-DC converter (such as a Boost converter and an Inverting converter) integrated in the power management integrated circuit 13 enables the power management base circuit to efficiently generate and supply the gate high voltage VGH and gate low voltage VGL to the display control circuit directly based on the power supply.

[0046] Therefore, in one embodiment of this application, the gate high voltage VGH and gate low voltage VGL can be directly provided by the power management integrated circuit 13, eliminating the multi-level conversion link for generating VGH and VGL inside the display driving architecture in the conventional display device 300, simplifying the circuit layout of the display power supply circuit 32, and thus reducing the power consumption of the display power supply circuit 32.

[0047] It should be noted that, unlike the display driving architecture in the traditional display device 100 which uses multi-stage charge pumps or other voltage conversion circuits to convert the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain the display driving voltage, in one embodiment of this application, the display power supply circuit 32, based on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD provided by the voltage management integrated circuit, can obtain the display driving voltage through only one voltage conversion. This also eliminates the multi-stage conversion steps inside the display driving architecture of the traditional display device 100, simplifies the circuit layout of the display power supply circuit 32, and thus reduces the power consumption of the display power supply circuit 32.

[0048] In this embodiment, the power management integrated circuit of the display device directly provides a target voltage, including at least a gate high voltage VGH and a gate low voltage VGL, or at least an analog positive power supply voltage AVDD, to the display power supply circuit. This target voltage allows the display power supply circuit to generate a display driving voltage to drive the display panel. This reduces the circuit layout complexity of the display driving architecture in the display device, simplifies the power supply path within the device, reduces voltage conversion stages in the power supply process, effectively reduces energy loss due to multiple voltage conversions, and significantly reduces the static power consumption and dynamic switching losses of the display device. Furthermore, the reduced circuit layout complexity of the display driving architecture helps to reduce the number of components used in the display driving architecture, thereby reducing the material cost of the display device. It also frees up wiring space on the printed circuit board, reducing the complexity of the printed circuit board traces and the risk of signal interference, greatly improving the system integration and operational reliability of the display device.

[0049] Please refer to Figure 3 and Figure 4 In a first embodiment of the display device 300 provided in this application, the target voltage includes a gate high voltage VGH and a gate low voltage VGL.

[0050] The display power supply circuit 32 includes: a first low-dropout linear regulator LDO1 and a second low-dropout linear regulator LDO2; the input terminals of the first low-dropout linear regulator LDO1 and the second low-dropout linear regulator LDO2 are respectively connected to the output terminals of the power management integrated circuit 13; the output terminals of the first low-dropout linear regulator LDO1 and the second low-dropout linear regulator LDO2 are respectively connected to the input terminals of the display panel 11.

[0051] The power management integrated circuit 13 is used to provide a gate high voltage VGH for the first low dropout linear regulator LDO1 and a gate low voltage VGL for the second low dropout linear regulator LDO2.

[0052] The first low-dropout linear regulator LDO1 is used to step down the gate high voltage VGH to obtain a regulated gate high voltage VRGH and an initialization positive voltage VINITP as the display drive voltage output to the display panel 11.

[0053] The second low-dropout linear regulator LDO2 is used to boost the gate low voltage VGL to obtain a regulated gate low voltage VRGL and an initial negative voltage VINITN as the display drive voltage output to the display panel 11.

[0054] Among them, the regulated gate high voltage VRGH and the regulated gate low voltage VRGL are used to provide gate driving voltage for the gate driver in the display panel 11 during the display stage; the initialization positive voltage VINITP and the initialization negative voltage VINITN are used to reset the pixel circuit in the display panel 11 during the initialization stage so that the nodes in the pixel circuit reach the preset initial potential.

[0055] Specifically, the core structure of a low-dropout linear regulator under a positive voltage architecture consists of a power regulator (such as a PMOS or PNP transistor) operating in the linear region and a feedback error amplifier. The physical essence of a low-dropout linear regulator under a positive voltage architecture is to generate a dynamically changing voltage drop through the regulator within the positive voltage range, thereby consuming excess voltage in the input voltage that is higher than the target output voltage.

[0056] In this embodiment, the voltage range of the gate high voltage VGH output by the power management integrated circuit 13 can be between 0V and +15V, while the voltage range of the regulated gate high voltage VRGH required by the display panel 11 can be between +5V and +15V, and the voltage range of the initialization positive voltage VINITP required by the display panel 11 can be between +2.7V and +8V.

[0057] Although the gate high voltage VGH, the regulated gate high voltage VRGH, and the initial positive voltage VINITP are all positive voltages, the voltage value of the gate high voltage VGH is usually higher than that of the regulated gate high voltage VRGH and the initial positive voltage VINITP. Therefore, the first low-dropout linear regulator LDO1 in this embodiment adopts a low-dropout linear regulator under a positive voltage architecture. Based on the voltage amplitude relationship between the gate high voltage VGH, the regulated gate high voltage VRGH, and the initial positive voltage VINITP, the gate high voltage VGH can be stepped down by the linear adjustment of the internal transistors to generate and output the regulated gate high voltage VRGH and the initial positive voltage VINITP to the display panel 11.

[0058] It should be noted that after the first low-dropout linear regulator LDO1 generates the regulated gate high voltage VRGH, it can output the regulated gate high voltage VRGH to the gate driver in the display panel 11, so that the gate driver can output a high-level scan signal to the gate of the thin-film transistor in the pixel array during the scanning phase, thereby controlling the conduction of the thin-film transistor in the pixel array and realizing the writing of pixel data.

[0059] After the first low-dropout linear regulator LDO1 generates the initial positive voltage VINITP, it can output the initial positive voltage VINITP to the pixel electrode in the display panel 11 so that the pixel electrode can be reset during the initialization phase, pulling the pixel electrode or the control node of the driving transistor in the pixel circuit to the preset positive initial potential, thereby eliminating the residual charge of the previous frame.

[0060] The core structure of a low-dropout linear regulator (LDL) in a negative voltage architecture consists of a power regulator (such as an NMOS or NPN transistor) operating in the linear region and a feedback error amplifier. The physical essence of a LDL is to use the regulator to generate a dynamically changing voltage drop, absorbing excess voltage in the input voltage that is higher than the target output voltage. In contrast, the physical essence of a low-dropout linear regulator in a negative voltage architecture is to use the regulator to generate a dynamically changing voltage drop within the negative voltage range, absorbing excess voltage in the input voltage that is lower than the target output voltage.

[0061] In this embodiment, the gate low voltage VGL output by the power management integrated circuit 13 can range from -15V to -0.5V, while the voltage range of the regulated gate low voltage VRGL required by the display panel 11 can also range from -15V to -0.5V, and the voltage range of the initialization negative voltage VINITN required by the display panel 11 can range from -12V to -0.2V. Therefore, although the gate low voltage VGL, the regulated gate low voltage VRGL, and the initialization negative voltage VINITN are all negative voltages, the voltage value of the gate low voltage VGL can be lower than the voltage values ​​of the regulated gate low voltage VRGL and the initialization negative voltage VINITN.

[0062] Therefore, in this embodiment, the second low-dropout linear regulator LDO2 adopts a low-dropout linear regulator with a negative voltage architecture. Based on the voltage magnitude relationship between the gate low voltage VGL, the regulated gate low voltage VRGL, and the initial negative voltage VINITN, after the gate low voltage VGL is input to the second low-dropout linear regulator LDO2, the second low-dropout linear regulator LDO2 can boost the gate low voltage VGL through the linear adjustment of its internal transistors, generating and outputting the regulated gate low voltage VRGL and the initial negative voltage VINITN to the display panel 11.

[0063] It should be noted that while the first low-dropout linear regulator LDO1 steps down the gate high voltage VGH, the extremely high power supply ripple rejection ratio inside the first low-dropout linear regulator LDO1 can filter out the switching noise generated by the front-end switching power supply of the power management integrated circuit 13 in the gate high voltage VGH. In this way, it can generate and output a smooth, fluctuation-free regulated gate high voltage VRGH and an initialization positive voltage VINITP to the display panel 11.

[0064] Similarly, while the second low-dropout linear regulator LDO2 boosts the gate low voltage VGL, the extremely high power supply ripple rejection ratio inside the second low-dropout linear regulator LDO2 can filter out the switching noise generated by the front-end switching power supply of the power management integrated circuit 13 in the gate low voltage VGL. In this way, a smooth and ripple-free regulated gate low voltage VRGL and an initialization negative voltage VINITN can be generated and output to the display panel 11.

[0065] After the second low-dropout linear regulator LDO2 generates the regulated gate low voltage VRGL, it can output the regulated gate low voltage VRGL to the gate driver in the display panel 11, so that the gate driver can output a low-level scan signal to the gate of the thin-film transistor in the pixel array during the scanning phase, thereby controlling the turn-off of the thin-film transistor and realizing the retention of pixel data.

[0066] After the second low-dropout linear regulator LDO2 generates the initial negative voltage VINITN, it can output the initial negative voltage VINITN to the pixel electrode in the display panel 11 so that the pixel electrode can be reset during the initialization phase, pulling the control node of the pixel electrode or driving transistor in the pixel circuit to the preset negative initial potential, and providing stable initial conditions for subsequent pixel data writing.

[0067] The display power supply circuit in this embodiment, by setting a first low-dropout linear regulator and a second low-dropout linear regulator, receives the gate high voltage VGH and gate low voltage VGL from the power management integrated circuit, respectively. Based on the linear adjustment characteristics of the low-dropout linear regulator under the positive and negative voltage architecture, it directly generates the regulated gate high voltage, regulated gate low voltage, initial positive voltage, and initial negative voltage required by the display panel. This simplifies the logic topology of the display driver architecture in the display device, significantly reduces the output voltage ripple, and reduces the number of external voltage regulator capacitors and traces, freeing up the printed circuit board space occupied by the aforementioned voltage regulator capacitors and traces. It balances the high-performance display requirements of the display device with the system integration advantages of low material costs. Furthermore, the display power supply circuit in this embodiment not only ensures the accuracy and consistency of the pixel circuit node potential reset during the initialization phase of the display panel, but also provides a highly stable driving voltage for the gate driver, eliminating the display flicker and uneven brightness caused by voltage ripple, and significantly improving the visual uniformity and dark display quality of the display image.

[0068] In some embodiments, the first low-dropout linear regulator LDO1 is also used to perform voltage conversion on the gate high voltage VGH to obtain the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP as display driving voltages output to the display panel 11.

[0069] Among them, the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver.

[0070] Specifically, during the actual driving process of the display panel 11, when the gate driver outputs scan pulses, in addition to requiring high-precision regulated gate high voltage VRGH and regulated gate low voltage VRGL as reference driving levels, it also needs to establish the maximum positive and maximum negative boundaries of the gate signal's allowable fluctuation based on the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP. The voltage range of the maximum positive gate voltage VGMP can be +2.7 to +8.0V; the voltage range of the maximum negative gate voltage VGSP can be +0.1 to +5.0V.

[0071] Since the gate high voltage VGH is not less than the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP, the first low dropout linear regulator LDO1, based on the voltage amplitude relationship between the gate high voltage VGH and the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP, can perform voltage reduction processing on the gate high voltage VGH through the linear adjustment of the internal transistor, generate the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP and output them to the display panel 11.

[0072] After the first low-dropout linear regulator LDO1 generates the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, it can output the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the gate driver so that the gate driver can obtain the maximum positive gate drive voltage and the maximum negative gate drive voltage to determine the voltage swing of the gate scan signal, thereby realizing the progressive scan drive of the 11-pixel array of the display panel.

[0073] In this embodiment, the display driving circuit uses a first low-dropout linear regulator to generate the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP based on the high gate voltage VGH. This simplifies the components and wiring in the display driving architecture while ensuring the consistency of the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP in terms of absolute amplitude and ripple characteristics.

[0074] Please refer to Figure 3 In some embodiments, the first low-dropout linear regulator LDO1 and the second low-dropout linear regulator LDO2 both include multiple output terminals; each output terminal of the first low-dropout linear regulator LDO1 is used to output at least one regulated gate high voltage VRGH and at least one initialization positive voltage VINITP to the display panel 11 respectively; each output terminal of the second low-dropout linear regulator LDO2 is used to output at least one regulated gate low voltage VRGL and at least one initialization negative voltage VINITN to the display panel 11 respectively.

[0075] The power supply circuit 32 also includes multiple voltage-stabilizing capacitors; each output terminal of the first low-dropout linear regulator LDO1 and each output terminal of the second low-dropout linear regulator LDO2 are respectively connected to one end of a voltage-stabilizing capacitor, and the other end of each voltage-stabilizing capacitor is connected to the ground terminal GND.

[0076] Optionally, in this embodiment, the first low-dropout linear regulator LDO1 provides two regulated gate high voltages VRGH (the first regulated gate high voltage VRGH1 and the second regulated gate high voltage VRGH2) to the display panel 11 through the first output terminal and the second output terminal, respectively; the first low-dropout linear regulator LDO1 provides one initialization positive voltage VINITP to the display panel 11 through the third output terminal.

[0077] Accordingly, one end of the voltage regulator C13 in the power supply circuit 32 is connected to the first output terminal of the first low dropout linear regulator LDO1; one end of the voltage regulator C12 is connected to the second output terminal of the first low dropout linear regulator LDO1; and one end of the voltage regulator C11 is connected to the third output terminal of the first low dropout linear regulator LDO1.

[0078] Among them, the voltage regulator capacitor C13 is used to regulate the first voltage regulator gate high voltage VRGH1; the voltage regulator capacitor C12 is used to regulate the second voltage regulator gate high voltage VRGH2.

[0079] Optionally, in this embodiment, the second low-dropout linear regulator LDO2 provides two regulated gate low voltages VRGL (first regulated gate low voltage VRGL1 and second regulated gate low voltage VRGL2) to the display panel 11 through the first output terminal, the second output terminal, and the display panel 11, respectively; the second low-dropout linear regulator LDO2 provides three initialization negative voltages VINITN (first initialization negative voltage VINITN1, second initialization negative voltage VINITN2, and third initialization negative voltage VINITN3) to the display panel 11 through the third output terminal, the fourth output terminal, and the fifth output terminal, respectively.

[0080] Accordingly, one end of the voltage regulator C4 in the power supply circuit 32 is connected to the first output terminal of the second low-dropout linear regulator LDO2; one end of the voltage regulator C3 is connected to the second output terminal of the second low-dropout linear regulator LDO2; one end of the voltage regulator C7 is connected to the third output terminal of the second low-dropout linear regulator LDO2; one end of the voltage regulator C5 is connected to the fourth output terminal of the second low-dropout linear regulator LDO2; and one end of the voltage regulator C6 is connected to the fifth output terminal of the second low-dropout linear regulator LDO2.

[0081] Among them, the voltage regulator capacitor C4 is used to regulate the first voltage regulator gate low voltage VRGL1; the voltage regulator capacitor C3 is used to regulate the second voltage regulator gate low voltage VRGL2; the voltage regulator capacitor C7 is used to regulate the first initial negative voltage VINITN1; the voltage regulator capacitor C5 is used to regulate the second initial negative voltage VINITN2; and the voltage regulator capacitor C4 is used to regulate the third initial negative voltage VINITN3. It should be noted that the power management integrated circuit 13 includes a first output terminal and a second output terminal. The gate high voltage VGH is output to the first low dropout linear regulator LDO1 through the first output terminal of the power management integrated circuit 13; the gate low voltage VGL is output to the second low dropout linear regulator LDO2 through the second output terminal of the power management integrated circuit 13.

[0082] Accordingly, one end of the voltage regulator capacitor C14 in the power supply circuit 32 is connected to the first output terminal of the power management integrated circuit 13; one end of the voltage regulator capacitor C18 is connected to the second output terminal of the power management integrated circuit 13. The voltage regulator capacitor C14 is used to regulate the gate high voltage VGH; the voltage regulator capacitor C18 is used to regulate the gate low voltage VGL.

[0083] Table 1 is one of the comparison tables between the display driving architecture in the related art and the voltage stabilizing capacitor in the first embodiment of the display device 300 provided in this application. As shown in Table 1, compared with the conventional display driving architecture in the related art, the display driving circuit in the first embodiment of the display device 300 provided in this application removes the charge pump capacitors CP1, CP2, CP3, and CP4, as well as the voltage stabilizing capacitors C8, C15, and C19, reducing a total of 8 capacitors.

[0084]

[0085] It should be noted that the connection relationships between the capacitors and multi-stage charge pumps or other voltage conversion circuits in the display driver architecture of related technologies can be referred to... Figure 1 As shown, this embodiment will not be described in detail. The "×" in Table 1 indicates that the corresponding voltage regulator capacitor was not set.

[0086] The display device in this embodiment directly generates the regulated gate high voltage VRGH, initial positive voltage VINITP, regulated gate low voltage VRGL, and initial negative voltage VINITN required for the display panel based on the gate high voltage VGH and gate low voltage VGL using a single-stage low-dropout linear voltage regulator. This eliminates the need for multiple voltage regulator capacitors required for multi-stage charge pump boost / inversion conversion, significantly reducing the material manufacturing cost of the display device. Furthermore, the reduction in the number of voltage regulator capacitors in the display driver circuit frees up wiring space on the printed circuit board in the display device, effectively reducing the risk of electromagnetic crosstalk and the probability of component solder joint failure caused by high-density wiring, thereby improving the overall high integration and long-term operational reliability of the display driver architecture.

[0087] Please refer to Figure 5 and Figure 6 As a second embodiment of the display device 300 provided in this application, the target voltage also includes the input power supply voltage VCI and / or the interface positive voltage VDDI.

[0088] The display power supply circuit also includes a first charge pump CP1; the input terminal of the first charge pump CP1 is connected to the output terminal of the power management integrated circuit 13, and the output terminal of the first charge pump CP1 is connected to the display panel 11.

[0089] The power management integrated circuit 13 is also used to provide the input power supply voltage VCI and the interface positive voltage VDDI for the first charge pump CP1.

[0090] The first charge pump CP1 is used to convert the input power supply voltage VCI and the interface positive voltage VDDI to obtain the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP as display drive voltages output to the display panel 11.

[0091] Among them, the maximum positive gate voltage VGMP and / or the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver.

[0092] It is understood that in the second embodiment of the display device 300 provided in this application, the target voltage includes the gate high voltage VGH, the gate low voltage VGL, and the input power supply voltage VCI and / or the interface positive voltage VDDI. The display driving circuit in this embodiment includes a first low dropout linear regulator LDO1, a second low dropout linear regulator LDO2, and a first charge pump CP1.

[0093] In this embodiment, the input power supply voltage VCI provided by the power management integrated circuit 13 to the first charge pump CP1 is typically the input voltage of the display device 300, and the voltage range of the input power supply voltage VCI can be +2.65V to +4.5V. The interface positive voltage VDDI provided by the power management integrated circuit 13 to the first charge pump CP1 is typically the input / output positive power supply voltage of the display device 300, and the voltage range of the interface positive voltage VDDI can be +1.65V to +1.95V.

[0094] The input power supply voltage VCI and the interface positive voltage VDDI serve as the basic low-voltage power supply provided by the power management integrated circuit 13, possessing extremely high current supply capability. The first charge pump CP1 performs independent switched-capacitor conversion (boost / invert) based on the input power supply voltage VCI and / or the interface positive voltage VDDI, and can independently generate a wide range of gate maximum positive voltage VGMP and gate maximum negative voltage VGSP, thereby providing sufficient dynamic voltage margin for the gate driver.

[0095] It should be noted that the first charge pump CP1 in this embodiment does not use a single fixed voltage multiplier conversion, but rather a configurable multi-mode combination architecture based on a switched capacitor network. It controls the series-parallel state switching between multiple flying capacitors and the input power supply voltage VCI and / or the interface positive voltage VDDI through an internal clock signal, and combines a boost and buck / inverting combination circuit to achieve accurate generation of the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP.

[0096] It should be noted that the first charge pump CP1 in this embodiment is internally configured with a flexible switching matrix, which can switch between different configuration modes in real time according to the dynamic voltage margin required by the display panel 11 to generate a superimposed voltage. The above configuration modes may include, but are not limited to, 2VCI mode, 3VCI mode, and VCI+VDDI hybrid mode.

[0097] In the 2VCI mode, during the charging phase, the flying capacitor is connected in parallel to the input power supply voltage VCI for charging (the voltage across the capacitor is the input power supply voltage VCI); during the discharging phase, the charged flying capacitor is connected in series with the input power supply voltage VCI and superimposed, thereby generating a superimposed voltage with a voltage value twice that of the input power supply voltage VCI according to the principle of charge conservation.

[0098] 3VCI mode refers to the process of superimposing three input power supply voltages VCI through parallel charging and series discharging, thereby generating a superimposed voltage with a voltage value three times that of the input power supply voltage VCI.

[0099] In the VCI+VDDI hybrid mode, the first charge pump CP1 charges different flying capacitors using both the input power supply voltage VCI and the interface positive voltage VDDI during the charging phase. Then, during the discharging phase, the capacitor charged with the input power supply voltage VCI is connected in series with the capacitor charged with the interface positive voltage VDDI, thereby generating a superimposed voltage equal to the sum of the input power supply voltage VCI and the interface positive voltage VDDI. In VCI+VDDI hybrid mode, the first charge pump CP1 can obtain a more precise non-integer multiple superimposed voltage, avoiding voltage overshoot and power consumption waste caused by integer multiple superimposed voltages.

[0100] The boost circuit in the first charge pump CP1 can boost and stabilize the integer or non-integer multiple superimposed voltage generated by the above configuration mode to the required positive level amplitude after further boosting and stabilization smoothing, thereby generating the gate maximum positive voltage VGMP.

[0101] The buck / inverting (BUCK) combination circuit in the first charge pump CP1 can generate an integer multiple or non-integer multiple superimposed voltage through the above configuration mode based on the input power supply voltage VCI and / or the interface positive voltage VDDI. After further inversion, bucking and voltage regulation smoothing processing, the voltage is stepped down and stabilized to the required low level amplitude, thereby generating the gate maximum negative voltage VGSP.

[0102] After the first charge pump CP1 generates the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, it can output the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the gate driver so that the gate driver can obtain the maximum positive gate drive voltage and the maximum negative gate drive voltage to determine the voltage swing of the gate scan signal, thereby realizing the progressive scan drive of the 11-pixel array of the display panel.

[0103] In this embodiment, the display power supply circuit independently generates the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP based on the input power supply voltage VCI and / or the interface positive voltage VDDI provided by the power management integrated circuit. This provides a precise and wide dynamic voltage variation range for the gate driver in the display panel. At the same time, by using the input power supply voltage VCI and / or the interface positive voltage VDDI as the input of the first charge pump, the risk of bus voltage drop caused by directly drawing a large transient current from the higher voltage gate high voltage VGH or gate low voltage VGL output by the power management integrated circuit 13 is effectively avoided. This enhances the transient response capability and anti-interference capability of the power supply architecture in the display device to cope with complex display screens and sudden high load conditions, and improves the operational reliability and screen stability of the display panel under multi-frequency switching and high dynamic range display.

[0104] Please refer to Figure 5 In some embodiments, the first charge pump CP1 includes multiple output terminals; the multiple output terminals of the first charge pump CP1 are used to output the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the display panel 11 respectively; each output terminal of the first charge pump CP1 is connected to one end of a voltage stabilizing capacitor.

[0105] The display driving circuit also includes a first charge pump CP1 capacitor, one end of which is connected to the input terminal of the first charge pump CP1, and the other end of which is connected to the output terminal of the first charge pump CP1.

[0106] Optionally, in this embodiment, the first charge pump CP1 provides the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the display panel 11 through the first output terminal and the second output terminal, respectively.

[0107] Accordingly, one end of the voltage regulator C9 in the power supply circuit 32 is connected to the first output terminal of the first low-dropout linear regulator LDO1; one end of the voltage regulator C10 is connected to the second output terminal of the first low-dropout linear regulator LDO1. Specifically, voltage regulator C9 is used to regulate the maximum positive gate voltage VGMP; and voltage regulator C10 is used to regulate the maximum negative gate voltage VGSP.

[0108] It should be noted that the power management integrated circuit 13 in this embodiment also includes a third output terminal and a fourth output terminal. The input power supply voltage VCI is output to the first charge pump CP1 through the third output terminal of the power management integrated circuit 13; the interface positive voltage VDDI is output to the first charge pump CP1 through the fourth output terminal of the power management integrated circuit 13.

[0109] Accordingly, one end of the voltage regulator capacitor C17 in the power supply circuit 32 is connected to the third output terminal of the power management integrated circuit 13; one end of the voltage regulator capacitor C19 is connected to the fourth output terminal of the power management integrated circuit 13. The voltage regulator capacitor C17 is used to regulate the input power supply voltage VCI; the voltage regulator capacitor C19 is used to regulate the interface positive voltage VDDI.

[0110] It should be noted that in this embodiment, the first charge pump capacitor CP1 is used to regulate the input power supply voltage VCI.

[0111] Table 2 is a comparison table of the display driving architecture in related technologies and the voltage stabilizing capacitors in the second embodiment of the display device 300 provided in this application. As shown in Table 2, compared with the conventional display driving architecture in related technologies, the display driving circuit in the second embodiment of the display device 300 provided in this application removes the charge pump capacitors CP2, CP3, and CP4, as well as the voltage stabilizing capacitors C8 and C15, reducing a total of 5 capacitors.

[0112]

[0113] The display device in this embodiment directly generates the maximum positive gate voltage VGMP and maximum negative gate voltage VGSP required for the display panel based on the input power supply voltage VCI using a single-stage charge pump. This eliminates the need for multiple voltage regulator capacitors required for multi-stage charge pump boost / inversion conversion, significantly reducing the material manufacturing cost of the display device. Furthermore, the reduction in the number of capacitors in the display driving circuit frees up wiring space on the printed circuit board in the display device, effectively reducing the risk of electromagnetic crosstalk and the probability of component solder joint failure caused by high-density wiring, thereby improving the overall high integration and long-term operational reliability of the display driving architecture.

[0114] Please refer to Figure 7 and Figure 8 As a third embodiment of the display device 300 provided in this application, the target voltage includes the analog positive power supply voltage AVDD.

[0115] The display power supply circuit 32 includes: a third low dropout linear regulator LDO3; the input terminal of the third low dropout linear regulator LDO3 is connected to the output terminal of the power management integrated circuit 13; the output terminal of the third low dropout linear regulator LDO3 is connected to the input terminal of the display panel 11.

[0116] The power management integrated circuit 13 is used to provide an analog positive power supply voltage AVDD for the third low-dropout linear regulator LDO3.

[0117] The third low-dropout linear regulator LDO3 is used to step down the analog positive power supply voltage AVDD to obtain the initial positive voltage VINITP as the display drive voltage output to the display panel 11.

[0118] The initialization positive voltage VINITP is used to reset the pixel circuit in the display panel 11 during the initialization phase, so that the nodes in the pixel circuit reach the preset initial potential.

[0119] Specifically, in this embodiment, the digital power supply voltage DVDDP provided by the power management integrated circuit 13 is usually the basic digital power supply of the logic control module of the display device 300. It has the characteristics of low voltage and high current. The voltage range of the digital power supply voltage DVDDP can be between +1.2V and +1.8V.

[0120] The analog positive power supply voltage AVDD provided by the power management integrated circuit 13 is typically the voltage of the basic analog power supply of the display panel 11, and has a high potential reference. The voltage range of the analog positive power supply voltage AVDD can be between +5.0V and +8.0V.

[0121] Although both the simulated positive power supply voltage AVDD and the initial positive voltage VINITP are positive voltages, the voltage value of the simulated positive power supply voltage AVDD is usually higher than that of the initial positive voltage VINITP. Therefore, the third low-dropout linear regulator LDO3 in this embodiment adopts a low-dropout linear regulator under a positive voltage architecture. Based on the voltage amplitude relationship between the simulated positive power supply voltage AVDD and the initial positive voltage VINITP, it can linearly adjust the internal transistors to step down the simulated positive power supply voltage AVDD, generate, and output the initial positive voltage VINITP to the display panel 11.

[0122] It should be noted that while the third low-dropout linear regulator LDO3 steps down the analog positive power supply voltage AVDD, its extremely high power supply ripple rejection ratio can filter out the switching noise generated by the front-end switching power supply of the power management integrated circuit 13 in the analog positive power supply voltage AVDD, thereby generating and outputting a smooth, fluctuation-free initial positive voltage VINITP.

[0123] After the third low-dropout linear regulator LDO3 generates the initial positive voltage VINITP, it can output the initial positive voltage VINITP to the pixel electrode in the display panel 11 so that the pixel electrode can be reset during the initialization phase, pulling the pixel electrode or the control node of the driving transistor in the pixel circuit to the preset positive initial potential, thereby eliminating the residual charge of the previous frame.

[0124] The display driver circuit in this embodiment reuses the existing analog positive power supply voltage AVDD in the power management basic circuit. It uses a third low-dropout linear regulator to directly generate the initial positive voltage VINITP based on the analog positive power supply voltage AVDD, which simplifies the logic topology of the display driver architecture in the display device. While significantly reducing the output voltage ripple, it also reduces the number of external voltage regulator capacitors and traces, freeing up the printed circuit board space occupied by the aforementioned voltage regulator capacitors and traces. This approach balances the high-performance display requirements of the display device with the system integration advantages of low material costs.

[0125] In some embodiments, the third low-dropout linear regulator LDO3 is also used to perform voltage conversion on the analog positive power supply voltage AVDD to obtain the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP as display drive voltages output to the display panel 11.

[0126] Among them, the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver.

[0127] Specifically, since the simulated positive power supply voltage AVDD is not less than the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, the third low-dropout linear regulator LDO3, based on the voltage amplitude relationship between the simulated positive power supply voltage AVDD and the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, can perform voltage reduction processing on the simulated positive power supply voltage AVDD through the linear adjustment of the internal transistor, generate the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, and output them to the display panel 11.

[0128] After the third low-dropout linear regulator LDO3 generates the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP, it can output the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the gate driver so that the gate driver can obtain the maximum positive gate drive voltage and the maximum negative gate drive voltage to determine the voltage swing of the gate scan signal, thereby realizing the progressive scan drive of the 11-pixel array of the display panel.

[0129] In this embodiment, the third low-dropout linear regulator in the display driver circuit generates the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP based on the analog positive power supply voltage AVDD. This simplifies the components and wiring in the display driver architecture while ensuring the consistency of the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP in terms of absolute amplitude and ripple characteristics.

[0130] Please refer to Figure 7 In some embodiments, the target voltage also includes the digital power supply voltage DVDDP.

[0131] The display power supply circuit 32 further includes: a first display power supply circuit and a second display power supply circuit; the input terminals of the first display power supply circuit and the second display power supply circuit are respectively connected to the output terminal of the power management integrated circuit 13; the output terminals of the first display power supply circuit and the second display power supply circuit are respectively connected to the input terminal of the display panel 11.

[0132] The power management integrated circuit 13 is used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to the first display power supply circuit and the second display power supply circuit, respectively.

[0133] The first display power supply circuit is used to convert the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain a regulated gate high voltage VRGH as the display driving voltage output to the display panel 11.

[0134] The second display power supply circuit is used to convert the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain the initialization negative voltage VINITN and the regulated gate low voltage VRGL as display drive voltages output to the display panel 11.

[0135] Among them, the regulated gate high voltage VRGH and the regulated gate low voltage VRGL are used to provide gate driving voltage for the gate driver in the display panel 11; the initialization negative voltage VINITN is used to reset the pixel circuit in the display panel 11 during the initialization phase so that the nodes in the pixel circuit reach the preset initial potential.

[0136] Specifically, after the first display power supply circuit in this embodiment receives the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD provided by the power management integrated circuit 13, it can perform charge superposition and boosting processing on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD, which have different potential characteristics and driving capabilities, through internal voltage conversion logic, thereby converting the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD into a regulated gate high voltage VRGH.

[0137] Similarly, after the second display power supply circuit in this embodiment receives the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD provided by the power management integrated circuit 13, it can invert the positive voltage digital power supply voltage DVDDP and the analog positive power supply voltage AVDD through the internal inversion and negative pump voltage conversion logic, and then perform voltage conversion to obtain the regulated gate low voltage VRGL and the initial negative voltage VINITN.

[0138] In this embodiment, by introducing a first display power supply circuit and a second display power supply circuit, the display driving voltages with different polarities and large voltage amplitude requirements are modularly split and independently converted. The basic potential and high current supply capability of the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD are fully reused, which can provide the display panel with a high-precision, low-noise and anti-crosstalk regulated gate high voltage VRGH, regulated gate low voltage VRGL and initialization negative voltage VINITN.

[0139] Please refer to Figure 7 In some embodiments, the first display power supply circuit includes: a third charge pump CP3 and a fourth low-dropout linear regulator LDO4; the input terminal of the third charge pump CP3 is connected to the output terminal of the power management integrated circuit 13; the output terminal of the third charge pump CP3 is connected to the input terminal of the fourth low-dropout linear regulator LDO4; and the output terminal of the fourth low-dropout linear regulator LDO4 is connected to the input terminal of the display panel 11.

[0140] The power management integrated circuit 13 is specifically used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD for the third charge pump CP3.

[0141] The third charge pump CP3 is used to generate a gate high voltage VGH based on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD, which is then output to the fourth low-dropout linear regulator LDO4.

[0142] The fourth low-dropout linear regulator LDO4 is used to step down the gate high voltage VGH to obtain the regulated gate high voltage VRGH output to the display panel 11.

[0143] Specifically, in this embodiment, the first display power supply circuit adopts a composite circuit architecture that combines a pre-charge pump boost and a post-low dropout linear regulator.

[0144] After receiving the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD provided by the power management integrated circuit 13, the third charge pump CP3 can perform charge superposition and multi-stage boosting on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD through the parallel charging and series discharging logic of the internal switched capacitor matrix, thereby generating a high gate voltage VGH.

[0145] However, the switching capacitor switching process of the charge pump inevitably introduces high-frequency switching ripple, resulting in the generated gate high voltage VGH typically containing a certain amount of voltage noise. Therefore, in this embodiment, the fourth low-dropout linear regulator LDO4 is a low-dropout linear regulator with a positive voltage architecture, used as a post-regulator to perform secondary processing on the gate high voltage VGH.

[0146] Specifically, in this embodiment, the voltage range of the gate high voltage VGH output by the power management integrated circuit 13 can be between 0V and +15V, while the voltage range of the regulated gate high voltage VRGH required by the display panel 11 can be between +5V and +15V, and the voltage range of the initialization positive voltage VINITP required by the display panel 11 can be between +2.7V and +8V.

[0147] Although both the gate high voltage VGH and the regulated gate high voltage VRGH are positive voltages, the gate high voltage VGH is typically higher than the regulated gate high voltage VRGH. Therefore, the fourth low-dropout linear regulator LDO4 in this embodiment is a low-dropout linear regulator with a positive voltage architecture. Based on the voltage amplitude relationship between the gate high voltage VGH and the regulated gate high voltage VRGH, it can linearly adjust the internal transistors to step down the gate high voltage VGH, generate, and output the regulated gate high voltage VRGH to the display panel 11.

[0148] It should be noted that after the gate high voltage VGH is input to the fourth low dropout linear regulator LDO4, the fourth low dropout linear regulator LDO4 can use its extremely high internal power supply ripple rejection ratio to completely filter out the high-frequency switching noise generated by the third charge pump CP3 during the pre-stage conversion process, thereby generating and outputting a smooth, fluctuation-free regulated gate high voltage VRGH.

[0149] After the fourth low-dropout linear regulator LDO4 generates the regulated gate high voltage VRGH, it can output the regulated gate high voltage VRGH to the gate driver in the display panel 11, so that the gate driver can output a high-level scan signal to the gate of the thin film transistor in the pixel array during the scanning phase, thereby controlling the conduction of the thin film transistor in the pixel array and realizing accurate writing of pixel data.

[0150] In this embodiment, the first display power supply circuit combines the efficient wide-range boost characteristics of the charge pump with the high-precision filtering characteristics of the low-dropout linear regulator through the cascaded cooperation of the fourth charge pump and the fourth low-dropout linear regulator. It fully reuses the high reference potential of the analog positive power supply voltage AVDD, effectively reducing the number of boost stages and internal flying capacitors required for the charge pump to reach the target high voltage. This significantly reduces energy loss and heat dissipation during the boost process and reduces the internal layout area of ​​the printed circuit board inside the display device. At the same time, the linear buck and filtering processing performed by the fourth low-dropout linear regulator eliminates the high-frequency switching ripple caused by the fourth charge pump, providing the gate driver with a regulated high gate voltage VRGH with high signal-to-noise ratio and high voltage accuracy, ensuring the accuracy of pixel data writing to the display panel and the uniformity of the image display.

[0151] Please refer to Figure 7 In some embodiments, the second display power supply circuit includes: a fifth low-dropout linear regulator (LDO5), a second charge pump (CP2), and a fourth charge pump (CP4); the input terminal of the second charge pump (CP2) is connected to the output terminal of the power management integrated circuit 13; the first output terminal of the second charge pump (CP2) is connected to the input terminal of the display panel 11, and the second output terminal of the second charge pump (CP2) is connected to the input terminal of the fourth charge pump (CP4); the output terminal of the fourth charge pump (CP4) is connected to the input terminal of the fifth low-dropout linear regulator (LDO5); and the output terminal of the fifth low-dropout linear regulator (LDO5) is connected to the input terminal of the display panel 11.

[0152] The power management integrated circuit 13 is used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to the second charge pump CP2.

[0153] The second charge pump CP2 is used to generate an analog negative power supply voltage AVEE and a digital negative power supply voltage -DVDDP based on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD, and output them to the fourth charge pump CP4 to generate an initialization negative voltage VINITN as the display drive voltage to be output to the display panel 11.

[0154] The fourth charge pump CP4 is used to generate a gate low voltage VGL based on the analog negative power supply voltage AVEE and the digital power supply voltage DVDDP to output to the fifth low dropout linear regulator LDO5.

[0155] The fifth low-dropout linear regulator LDO5 is used to boost the gate low voltage VGL to obtain the initial negative voltage VINITN and the regulated gate low voltage VRGL as the display drive voltage output to the display panel 11.

[0156] Specifically, in this embodiment, the second display power supply circuit adopts a composite circuit architecture of multi-level cascade and multiplexed outputs.

[0157] After receiving the positive digital power supply voltage DVDDP and the analog positive power supply voltage AVDD from the power management integrated circuit 13, the second charge pump CP2 can invert the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD through the inversion mechanism of the internal switched capacitor, thereby generating the negative analog negative power supply voltage AVEE and the negative digital power supply voltage -DVDDP, which are then output to the fourth charge pump CP4. The voltage range of the analog negative power supply voltage AVEE can be -5.0V to -8.0V; the voltage range of the negative digital power supply voltage -DVDDP can be between -1.2V and -1.8V.

[0158] After the second charge pump CP2 generates the analog negative power supply voltage AVEE and the digital negative power supply voltage -DVDDP, it can also perform charge superposition and multi-stage voltage reduction processing on the analog negative power supply voltage AVEE and the digital negative power supply voltage -DVDDP through the parallel charging and series discharging logic of the internal switched capacitor matrix, and generate the initial negative voltage VINITN to be output to the display panel 11.

[0159] The fourth charge pump CP4 can perform charge superposition and multi-stage voltage reduction processing on the analog negative power supply voltage AVEE and the digital negative power supply voltage -DVDDP through the parallel charging and series discharging logic of the internal switched capacitor matrix, generating a low gate voltage VGL.

[0160] However, since the switching capacitor switching process of the charge pump inevitably introduces high-frequency switching ripple, the gate low voltage VGL generated by the fourth charge pump CP4 usually contains a certain amount of voltage noise. Therefore, in this embodiment, the fifth low-dropout linear regulator LDO5 adopts a low-dropout linear regulator under a negative voltage architecture as a post-regulator to perform secondary processing on the gate low voltage VGL.

[0161] Specifically, in this embodiment, the gate low voltage VGL generated by the fourth charge pump CP4 can range from -16V to -0.5V, while the voltage range of the regulated gate low voltage VRGL required by the display panel 11 can range from -15V to -0.5V, and the voltage range of the initial negative voltage VINITN required by the display panel 11 can range from -12V to -0.2V. Therefore, although the gate low voltage VGL, the regulated gate low voltage VRGL, and the initial negative voltage VINITN are all negative voltages, the voltage value of the gate low voltage VGL can be lower than the voltage values ​​of the regulated gate low voltage VRGL and the initial negative voltage VINITN.

[0162] Therefore, the fifth low-dropout linear regulator (LDO5) in this embodiment adopts a low-dropout linear regulator with a negative voltage architecture. Based on the voltage magnitude relationship between the gate low voltage VGL, the regulated gate low voltage VRGL, and the initial negative voltage VINITN, after the gate low voltage VGL is input to the fifth low-dropout linear regulator (LDO5), the fifth low-dropout linear regulator (LDO5) can boost the gate low voltage VGL through the linear adjustment of its internal transistors, generating and outputting the regulated gate low voltage VRGL and the initial negative voltage VINITN to the display panel 11.

[0163] It should be noted that while the fifth low-dropout linear regulator LDO5 boosts the gate low voltage VGL, its extremely high power supply ripple rejection ratio can filter out the switching noise introduced by the pre-charge pump in the gate low voltage VGL. This allows it to generate and output a smooth, fluctuation-free regulated gate low voltage VRGL and an initialization negative voltage VINITN to the display panel 11.

[0164] After the fifth low-dropout linear regulator LDO5 generates the regulated gate low voltage VRGL, it can output the regulated gate low voltage VRGL to the gate driver in the display panel 11 so that the gate driver can output a low-level scan signal during the scanning phase to control the thin-film transistor to turn off in order to maintain pixel data.

[0165] After the fifth low-dropout linear regulator LDO5 generates the initial negative voltage VINITN, it can output the initial negative voltage VINITN to the pixel electrode in the display panel 11 so that the pixel electrode can be reset during the initialization phase, pulling the control node of the pixel electrode or driving transistor in the pixel circuit to the preset negative initial potential, and providing stable initial conditions for subsequent pixel data writing.

[0166] In this embodiment, the second display power supply circuit, through the synergistic cascading of the second charge pump, the fifth charge pump, and the fifth low-dropout linear regulator, reduces the number of charge pumps and external voltage regulator capacitors required in the display driving architecture of the display device. This optimizes the circuit layout of the display driving architecture and significantly reduces dynamic switching losses and system material costs during negative voltage generation. Furthermore, this embodiment uses the fifth low-dropout linear regulator in the post-negative voltage architecture to boost and filter the low gate voltage VRGL, eliminating the high-frequency noise superposition caused by the cascading of the two-stage charge pumps. This provides a high-precision and low-noise negative driving voltage for the turn-off of the thin-film transistor and the reset of the pixel node.

[0167] Please refer to Figure 7 In some embodiments, the third low-dropout linear regulator LDO3, the fourth low-dropout linear regulator LDO4, and the fifth low-dropout linear regulator LDO5 each include multiple output terminals.

[0168] The power supply circuit 32 also includes multiple voltage-stabilizing capacitors; each output terminal of the fifth low-dropout linear regulator LDO5, each output terminal of the third low-dropout linear regulator LDO3, and each output terminal of the fourth low-dropout linear regulator LDO4 are connected to one end of a voltage-stabilizing capacitor, and the other end of each voltage-stabilizing capacitor is connected to the ground terminal GND.

[0169] Optionally, in this embodiment, the third low-dropout linear regulator LDO3 provides an initialization positive voltage VINITP to the display panel 11 through its first output terminal. In this embodiment, the third low-dropout linear regulator LDO3 provides the maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP to the display panel 11 through its second and third output terminals, respectively.

[0170] Accordingly, one end of the voltage regulator C11 in the power supply circuit 32 is connected to the first output terminal of the third low-dropout linear regulator LDO3; one end of the voltage regulator C9 is connected to the second output terminal of the third low-dropout linear regulator LDO3; and one end of the voltage regulator C10 is connected to the third output terminal of the third low-dropout linear regulator LDO3. Specifically, voltage regulator C11 is used to regulate the initial positive voltage VINITP; voltage regulator C9 is used to regulate the maximum positive gate voltage VGMP; and voltage regulator C10 is used to regulate the maximum negative gate voltage VGSP.

[0171] Optionally, in this embodiment, the fourth low-dropout linear regulator LDO4 provides two regulated gate high voltages VRGH to the display panel 11 through the first output terminal and the second output terminal (namely, the first regulated gate high voltage VRGH1 and the second regulated gate high voltage VRGH2).

[0172] Accordingly, one end of the voltage regulator capacitor C13 in the power supply circuit 32 is connected to the first output terminal of the fourth low dropout linear regulator LDO4; one end of the voltage regulator capacitor C12 is connected to the second output terminal of the fourth low dropout linear regulator LDO4.

[0173] Optionally, the second charge pump CP2 provides a first initialization negative voltage VINITN1 to the display panel 11 through its output terminal. One end of the voltage regulator capacitor C7 in the display power supply circuit 32 is connected to the output terminal of the second charge pump CP2. The voltage regulator capacitor C7 is used to regulate the first initialization negative voltage VINITN1.

[0174] Optionally, in this embodiment, the fifth low-dropout linear regulator LDO5 provides two initialization negative voltages VINITN (VINITN2 and VINITN3, respectively) to the display panel 11 through the first and second output terminals. The fifth low-dropout linear regulator LDO5 also provides two regulated gate low voltages VRGL (VRGL1 and VRGL2, respectively) to the display panel 11 through the third and fourth output terminals.

[0175] Accordingly, one end of the voltage regulator capacitor C5 in the power supply circuit 32 is connected to the first output terminal of the fifth low-dropout linear regulator LDO5; one end of the voltage regulator capacitor C6 is connected to the second output terminal of the fourth low-dropout linear regulator LDO4; one end of the voltage regulator capacitor C4 is connected to the third output terminal of the fifth low-dropout linear regulator LDO5; and one end of the voltage regulator capacitor C3 is connected to the fourth output terminal of the fifth low-dropout linear regulator LDO5.

[0176] Among them, the voltage regulator capacitor C5 is used to regulate the second initial negative voltage VINITN2; the voltage regulator capacitor C6 is used to regulate the third initial negative voltage VINITN3.

[0177] It should be noted that the display driving circuit also includes a second charge pump capacitor C22, a third charge pump capacitor C23, and a fourth charge pump capacitor C24. One end of the second charge pump capacitor C22 is connected to the input terminal of the second charge pump CP2, and the other end is connected to the output terminal of the second charge pump CP2. One end of the third charge pump capacitor C23 is connected to the input terminal of the third charge pump CP3, and the other end is connected to the output terminal of the third charge pump CP3. One end of the fourth charge pump capacitor C24 is connected to the input terminal of the fourth charge pump CP4, and the other end is connected to the output terminal of the fourth charge pump CP4.

[0178] Table 3 is the third comparison table of the voltage regulator capacitors in the display driving architecture of related technologies and the third embodiment of the display device provided in this application. As shown in Table 3, compared with the conventional display driving architecture in related technologies, the display driving circuit in the third embodiment of the display device 300 provided in this application removes the voltage regulator capacitors C17, C18 and C19, reducing a total of three capacitors.

[0179]

[0180] The display device in this embodiment reuses the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD already output by the power management basic circuit. It uses a third low-dropout linear regulator to directly generate the initial positive voltage VINITP based on the analog positive power supply voltage AVDD, eliminating the need for multiple voltage regulator capacitors and reducing the material manufacturing cost of the display device. Furthermore, the reduction in the number of voltage regulator capacitors in the display driver circuit frees up wiring space on the printed circuit board in the display device, effectively reducing the risk of electromagnetic crosstalk and the probability of component soldering failure caused by high-density wiring, thereby improving the overall high integration and long-term operational reliability of the display driver architecture.

[0181] Please refer to Figure 9 and Figure 10 As a fourth embodiment of the display device 300 provided in this application, the target voltage also includes a gate low voltage VGL.

[0182] The power management integrated circuit 13 is also used to provide a gate low voltage VGL for the fifth low dropout linear regulator LDO5.

[0183] It is understood that in the fourth embodiment of the display device 300 provided in this application, the target voltage includes the digital power supply voltage DVDDP, the analog positive power supply voltage AVDD, and the gate low voltage VGL.

[0184] It is understood that the fifth low-dropout linear regulator LDO5 in this embodiment receives two gate low voltages VGL, which are provided by the fourth charge pump CP4 and the power management integrated circuit 13, respectively.

[0185] It should be noted that the power management integrated circuit 13 includes a first output terminal and a second output terminal. The analog positive power supply voltage AVDD is output to the second charge pump CP2, the third charge pump CP3 and the third low dropout linear regulator LDO3 through the first output terminal of the power management integrated circuit 13; the digital power supply voltage DVDDP is output to the second charge pump CP2 and the third charge pump CP3 through the second output terminal of the power management integrated circuit 13.

[0186] Accordingly, one end of the voltage regulator capacitor C15 in the power supply circuit 32 is connected to the first output terminal of the power management integrated circuit 13; one end of the voltage regulator capacitor C16 is connected to the second output terminal of the power management integrated circuit 13. Specifically, the voltage regulator capacitor C15 is used to regulate the analog positive power supply voltage AVDD; and the voltage regulator capacitor C18 is used to regulate the digital power supply voltage DVDDP.

[0187] The power management integrated circuit 13 also includes a third output. The gate low voltage VGL is output to the fifth low-dropout linear regulator LDO5 through the third output of the power management integrated circuit 13.

[0188] Accordingly, one end of the voltage regulator capacitor C18 in the power supply circuit 32 is connected to the third output terminal of the power management integrated circuit 13. The voltage regulator capacitor C18 is used to regulate the gate low voltage VGL.

[0189] Table 4 is the fourth comparison table of the voltage regulator capacitors in the display driving architecture of related technologies and the fourth embodiment of the display device provided in this application. As shown in Table 4, compared with the conventional display driving architecture in related technologies, the display driving circuit in the fourth embodiment of the display device 300 provided in this application removes the voltage regulator capacitors C17 and C19, reducing the number of capacitors by two.

[0190]

[0191] In this embodiment, the power management integrated circuit provides an additional gate low voltage (VGL) to the fifth low-dropout linear regulator. Combined with the gate low voltage (VGL) generated by the fourth charge pump, this enhances the current supply capability and shock resistance of the fifth low-dropout linear regulator under transient high loads. This ensures that the display drive voltage generated by the fifth low-dropout linear regulator has a stronger anti-interference margin, further guaranteeing stable refresh of the display panel image. Furthermore, this embodiment eliminates two voltage regulator capacitors through optimized power supply logic and input source multiplexing, reducing not only the material manufacturing cost of the display device but also freeing up wiring space on the printed circuit board.

[0192] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A display device, characterized in that, include: The system comprises a display panel, a display power supply circuit, and a power management integrated circuit; the input terminal of the display power supply circuit is connected to the output terminal of the power management integrated circuit; and the output terminal of the display power supply circuit is connected to the input terminal of the display panel. The power management integrated circuit is used to provide a target voltage for the display power supply circuit; The display power supply circuit is used to convert the target voltage to obtain a display driving voltage, and to provide the display driving voltage to the display panel to drive the display panel to display. The target voltage includes at least a gate high voltage VGH and a gate low voltage VGL, or the target voltage includes at least an analog positive power supply voltage AVDD.

2. The display device according to claim 1, characterized in that, The target voltage includes the gate high voltage VGH and the gate low voltage VGL; The display power supply circuit includes: a first low-dropout linear regulator and a second low-dropout linear regulator; the input terminals of the first low-dropout linear regulator and the second low-dropout linear regulator are respectively connected to the output terminal of the power management integrated circuit; the output terminals of the first low-dropout linear regulator and the second low-dropout linear regulator are respectively connected to the input terminal of the display panel. The power management integrated circuit is used to provide the gate high voltage VGH for the first low dropout linear regulator and the gate low voltage VGL for the second low dropout linear regulator; The first low-dropout linear regulator is used to step down the gate high voltage VGH to obtain a regulated gate high voltage VRGH and an initialization positive voltage VINITP as the display driving voltage output to the display panel. The second low-dropout linear regulator is used to boost the gate low voltage VGL to obtain a regulated gate low voltage VRGL and an initial negative voltage VINITN as the display driving voltage output to the display panel. The regulated gate high voltage VRGH and the regulated gate low voltage VRGL are used to provide gate driving voltage to the gate driver in the display panel during the display phase; the initialization positive voltage VINITP and the initialization negative voltage VINITN are used to reset the pixel circuit in the display panel during the initialization phase, so that the nodes in the pixel circuit reach a preset initial potential.

3. The display device according to claim 2, characterized in that, The first low-dropout linear regulator is also used to perform voltage conversion on the gate high voltage VGH to obtain the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP as the display driving voltage output to the display panel; The maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver.

4. The display device according to claim 2 or 3, characterized in that, The target voltage also includes the input power supply voltage VCI and / or the interface positive voltage VDDI; The display power supply circuit further includes a first charge pump; the input terminal of the first charge pump is connected to the output terminal of the power management integrated circuit, and the output terminal of the first charge pump is connected to the display panel. The power management integrated circuit is also used to provide the input power supply voltage VCI and the interface positive voltage VDDI to the first charge pump; The first charge pump is used to perform voltage conversion on the input power supply voltage VCI and / or the interface positive voltage VDDI to obtain the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP as the display driving voltage output to the display panel; The maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver.

5. The display device according to claim 1, characterized in that, The target voltage includes the analog positive power supply voltage AVDD; The display power supply circuit includes: a third low-dropout linear regulator; the input terminal of the third low-dropout linear regulator is connected to the output terminal of the power management integrated circuit; the output terminal of the third low-dropout linear regulator is connected to the input terminal of the display panel. The power management integrated circuit is used to provide the analog positive power supply voltage AVDD to the third low-dropout linear regulator; The third low-dropout linear regulator is used to step down the analog positive power supply voltage AVDD to obtain an initial positive voltage VINITP as the display driving voltage output to the display panel. The initial positive voltage VINITP is used to reset the pixel circuit in the display panel during the initialization phase, so that the nodes in the pixel circuit reach a preset initial potential.

6. The display device according to claim 5, characterized in that, The third low-dropout linear regulator is also used to perform voltage conversion on the analog positive power supply voltage AVDD to generate the gate maximum positive voltage VGMP and the gate maximum negative voltage VGSP as the display driving voltage output to the display panel; The maximum positive gate voltage VGMP and the maximum negative gate voltage VGSP are used to provide the voltage variation range of the gate drive signal for the gate driver in the display panel.

7. The display device according to claim 5, characterized in that, The target voltage also includes the digital power supply voltage DVDDP; The display power supply circuit further includes: a first display power supply circuit and a second display power supply circuit; the input terminals of the first display power supply circuit and the second display power supply circuit are respectively connected to the output terminal of the power management integrated circuit; the output terminals of the first display power supply circuit and the second display power supply circuit are respectively connected to the input terminal of the display panel. The power management integrated circuit is used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to the first display power supply circuit and the second display power supply circuit, respectively. The first display power supply circuit is used to convert the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain a regulated gate high voltage VRGH as the display driving voltage output to the display panel; The second display power supply circuit is used to perform voltage conversion between the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to obtain an initialization negative voltage VINITN and a Zener gate low voltage VRGL as the display driving voltages output to the display panel; The regulated gate high voltage VRGH and the regulated gate low voltage VRGL are used to provide gate driving voltage for the gate driver in the display panel; the initialization negative voltage VINITN is used to reset the pixel circuit in the display panel during the initialization phase, so that the nodes in the pixel circuit reach a preset initial potential.

8. The display device according to claim 7, characterized in that, The first display power supply circuit includes: a third charge pump and a fourth low-dropout linear regulator; the input terminal of the third charge pump is connected to the output terminal of the power management integrated circuit; the output terminal of the third charge pump is connected to the input terminal of the fourth low-dropout linear regulator; and the output terminal of the fourth low-dropout linear regulator is connected to the input terminal of the display panel. The power management integrated circuit is specifically used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to the third charge pump; The third charge pump is used to generate the gate high voltage VGH based on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to output to the fourth low dropout linear regulator; The fourth low-dropout linear regulator is used to step down the gate high voltage VGH to obtain the regulated gate high voltage VRGH output to the display panel.

9. The display device according to claim 7, characterized in that, The second display power supply circuit includes: a fifth low-dropout linear regulator, a second charge pump, and a fourth charge pump; the input terminal of the second charge pump is connected to the output terminal of the power management integrated circuit; the first output terminal of the second charge pump is connected to the input terminal of the display panel, and the second output terminal of the second charge pump is connected to the input terminal of the fourth charge pump; the output terminal of the fourth charge pump is connected to the input terminal of the fifth low-dropout linear regulator; and the output terminal of the fifth low-dropout linear regulator is connected to the input terminal of the display panel. The power management integrated circuit is used to provide the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD to the second charge pump; The second charge pump is used to generate an analog negative power supply voltage AVEE and a digital negative power supply voltage -DVDDP based on the digital power supply voltage DVDDP and the analog positive power supply voltage AVDD, and output them to the fourth charge pump to generate the initial negative voltage VINITN as the display driving voltage to be output to the display panel; The fourth charge pump is used to generate the gate low voltage VGL based on the analog negative power supply voltage AVEE and the digital power supply voltage DVDDP to output to the fifth low dropout linear regulator; The fifth low-dropout linear regulator is used to boost the gate low voltage VGL to obtain the initial negative voltage VINITN and the regulated gate low voltage VRGL as the display driving voltage output to the display panel.

10. The display device according to any one of claims 5 to 9, characterized in that, The target voltage also includes the gate low voltage VGL; The power management integrated circuit is also used to provide the gate low voltage VGL for the fifth low-dropout linear regulator.

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