A low voltage ideal diode controller circuit

Abstract

The application discloses a low-voltage ideal diode controller circuit, which comprises a charge pump, an LDO, a GATE driver, six comparators and a plurality of reference sources. The charge pump generates a voltage higher than VIN to drive an external NMOS tube, and the LDO converts VIN into VCC to supply power for internal circuits. The six comparators realize input overvoltage, input undervoltage, VCC undervoltage, LDO enable control, reverse current control and MOS state indication functions respectively. The application realizes extremely low voltage difference when forward conduction by intelligently controlling the external MOSFET, greatly reduces power consumption, supports a super-wide working range of VIN from 0V to 18V, meets the low-voltage core backup demand, has input overvoltage / undervoltage protection, reverse current blocking and fault indication functions, and the peripheral circuit configuration is flexible, and the inrush current can be effectively suppressed by adjusting the bootstrap capacitor or the RC network to adapt to the hot plug scene.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-voltage ideal diode controller circuit, which can be specifically used as a primary power backup or hot-swappable power supply. Background Technology

[0002] In airborne and missile-borne single-unit systems, the DC 28V bus voltage is typically converted to a 12V intermediate bus voltage via a BUCK module, and then converted to low-voltage voltages (e.g., 5V, 3.3V, 1.0V) through three load point power supply conversions to power core devices such as MCUs, SOCs, and FPGAs. To ensure the safety and reliability of the power supply system, using a main backup power supply or dual power supplies in parallel has become a common industry practice. Furthermore, these single-unit systems typically consist of a power board and multiple function boards. The function boards are connected via flexible flat cables, while the function boards and power board are usually hard-connected via connectors. During insertion and removal, the unstable contact at the moment of connection often generates surge voltages or currents, which can lead to device failure in severe cases.

[0003] Traditional power supply backup and parallel connection schemes typically use Schottky diodes, such as... Figure 1 As shown, the forward voltage drop of a Schottky diode is typically between 0.4V and 0.7V. When the load current is large, the conduction loss on the diode increases significantly, leading to severe heat generation. To meet heat dissipation requirements, special PCB heat dissipation designs are often required, such as large-area copper plating or adding heat dissipation vias, or even additional heatsinks or custom heat sinks. These measures not only increase the size and weight of the power board but also increase system cost and design complexity.

[0004] Furthermore, Schottky diode solutions have significant limitations in low-voltage applications. Because diodes have a fixed forward voltage drop, the output voltage margin is further compressed under low input voltage conditions, potentially causing downstream loads to malfunction. When the input voltage is lower than the diode's forward voltage drop, the diode solution may even become completely unusable. Simultaneously, traditional diode solutions lack surge suppression capabilities and cannot effectively handle overcurrent generated during hot-plugging, failing to meet the protection requirements of high-reliability systems.

[0005] To address the problems existing in the prior art, this invention proposes a low-voltage ideal diode controller circuit, which aims to achieve low on-state voltage drop, low power consumption, flexible power backup and surge protection functions by intelligently controlling the on / off state of an external MOSFET. Summary of the Invention

[0006] To solve the above-mentioned technical problems, the present invention provides a low-voltage ideal diode controller circuit, comprising: Power input terminal VIN, power output terminal VOUT, gate drive terminal GATE, logic power supply terminal VCC, charge pump output terminal CPO, driver source terminal SOURCE, input overvoltage detection terminal OV, input undervoltage detection terminal UV, status indicator terminal STAT, fault indicator terminal FAULT; A charge pump, whose output is connected to the CPO, is used to generate a voltage higher than VIN; An LDO (Low Voltage DO) is connected to VIN at its input and VCC at its output. It is used to convert the external input voltage VIN into a low voltage VCC to power the internal circuitry. The GATE driver, whose input is connected to the charge pump and SOURCE and whose output is connected to GATE, is used to drive the gate of an external NMOSFET. Multiple reference voltage sources provide reference voltages of 25mV, 4.1V, 2.57V, 1V, 0.5V, and 0.7V, respectively; The first comparator CP1 has its positive input connected to the 0.5V reference source and its inverting input connected to 0V, and is used to detect input overvoltage. The second comparator CP2 has its inverting input connected to the 0.5V reference source and its non-inverting input connected to UV, and is used to detect input undervoltage. The third comparator CP3 has its positive input connected to the 2.57V reference source and its inverting input connected to VCC, and is used to detect VCC undervoltage. The fourth comparator CP4 has its input connected to VIN, VCC and the 4.1V reference source. It is used to control the enable of the LDO. When VCC is powered externally and VCC > VIN, it generates a control signal to turn off the LDO. The fifth comparator CP5 has its inverting input connected to the 1V reference source and its non-inverting input connected to the REV terminal. It is used to control the reverse current. When the REV voltage is higher than 1V, the current is allowed to flow from VOUT to VIN. The sixth comparator CP6 has its positive input connected to the 0.7V reference source, its inverting input connected to SOURCE, and its output connected to STAT. When the voltage between GATE and SOURCE is greater than 0.7V, STAT outputs a low level to indicate that the external MOS is turned on.

[0007] In one embodiment of the present invention, under normal use, a 0.1μF ceramic capacitor is connected to ground at the VCC terminal, and the VIN operating voltage range is 2.9V to 18V; when VCC is powered by an external power source, VIN can be as low as 0V.

[0008] In one embodiment of the present invention, under normal use, a bootstrap capacitor is connected between the CPO terminal and the SOURCE terminal; in hot-swappable application environments, the bootstrap capacitor is not connected, and the MOS is slowly turned on using the internal pF level capacitor of the chip; when it is necessary to quickly turn on the MOS, the CPO terminal is connected to an external power supply through a current-limiting resistor.

[0009] In one embodiment of the present invention, the UV terminal is connected to VCC when the input undervoltage function is not used, and the OV terminal is connected to GND when the input overvoltage function is not used; when the input undervoltage and overvoltage functions are used, the undervoltage and overvoltage thresholds of VIN are set by external voltage divider resistors R1, R2, and R3, wherein: Overvoltage threshold: ; Undervoltage threshold: .

[0010] In one embodiment of the present invention, the STAT terminal and the FAULT terminal are connected to the output terminal or other power rails not exceeding 18V via pull-up resistors for outputting status indication signals.

[0011] In one embodiment of the present invention, the enable control logic of the LDO is as follows: when VIN > 4.1V, VCC is floating and powered by the internal LDO; when VIN < 2.9V, VCC requires external power supply (2.9V to 6.0V), and the internal LDO is turned off; when 2.9V < VIN < 4.1V, VCC can be floating (following VIN) or powered by external power; when VCC > VIN, the internal LDO is turned off; when VCC < VIN, the LDO remains on.

[0012] In one embodiment of the present invention, the GATE driver adjusts the GATE voltage according to the load: under light load, the GATE driver adjusts to stabilize the voltage difference between VIN and VOUT at 25mV; when VIN-VOUT>75mV, the GATE voltage is quickly pulled up to SOURCE+6.1V, making the external NMOSFET fully conduct.

[0013] In one embodiment of the invention, the FAULT terminal is pulled low when the voltage difference between VIN and VOUT is greater than 250mV, to indicate that the load current is too high or the external MOSFET is open.

[0014] In one embodiment of the invention, the REV terminal is typically grounded to prevent reverse current; when it is necessary to allow reverse current, a control voltage higher than 1V is applied to the REV terminal.

[0015] In one embodiment of the present invention, the controller circuit further includes an external NMOSFET, the source of which is connected to VIN and SOURCE, the drain of which is connected to VOUT, and the gate of which is connected to GATE; the body diode of the external NMOSFET provides an initial conduction path when the MOS is turned off.

[0016] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The low-voltage ideal diode controller circuit of the present invention replaces the Schottky diode with an external MOSFET through intelligent control, reducing the forward conduction voltage to 25mV (light load) or determined by the MOSFET on-resistance (heavy load), greatly reducing losses and eliminating the need for additional heat dissipation design; it also supports an ultra-wide VIN range from 0V to 18V, and can be powered by an external VCC at low voltage, making it suitable for low-voltage core backup scenarios; at the same time, there is no voltage drop during the main / standby power switching process, ensuring continuous power supply to the downstream load; specifically, it effectively suppresses inrush current by using internal slow start or external RC to delay GATE opening; the peripheral circuit is simple, the overvoltage / undervoltage threshold is adjustable, the bootstrap capacitor is optional, and it can adapt to different application requirements. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a schematic diagram of a traditional diode solution; Figure 2 This is a functional block diagram of the controller provided by the present invention; Figure 3(a) is a circuit diagram of the low-voltage ideal diode controller circuit described in this invention; Figure 3(b) is a schematic diagram of the low-voltage ideal diode controller circuit described in this invention; Figure 4 This is a waveform test diagram of main and backup power switching provided by the present invention; Figure 5 This is the positive voltage versus load current curve described in this invention. Detailed Implementation

[0019] Reference Figure 2 As shown in Figure 3(a), this embodiment provides a low-voltage ideal diode controller circuit. The controller is packaged in a ceramic-encapsulated CDFN12 package, and its leads include: power input VIN, logic power supply VCC, charge pump output CPO, driver source SOURCE, gate drive GATE, power output VOUT, input undervoltage detection UV, input overvoltage detection OV, reverse current control REV, status indicator STAT, fault indicator FAULT, and ground GND. A metal heat sink is provided on the bottom of the package to enhance heat dissipation.

[0020] The internal structure of the controller is as follows Figure 2 As shown, the system includes: a charge pump, an LDO (low dropout linear regulator), a gate driver, six comparators CP1–CP6, and five reference voltage sources providing reference voltages of 25mV, 0.5V, 0.7V, 1V, 2.57V, and 4.1V, respectively. The connections between the modules are as follows: The input terminal of the charge pump is connected to VIN, and the output terminal is connected to CPO. It is used to generate a voltage higher than VIN to power the GATE driver. The LDO's input terminal is connected to VIN, and its output terminal is connected to VCC. It is used to convert the external input voltage into a stable low-voltage power supply to power the internal circuitry. The positive power supply terminal of the GATE driver is connected to CPO, the negative power supply terminal is connected to SOURCE, and the output terminal is connected to GATE, which is used to control the gate of the external NMOSFET. The positive input of comparator CP1 is connected to a 0.5V reference source, and the negative input is connected to 0V, which is used to detect input overvoltage. The inverting input of comparator CP2 is connected to a 0.5V reference source, and the non-inverting input is connected to UV, which is used to detect input undervoltage. The positive input of comparator CP3 is connected to a 2.57V reference source, and the inverting input is connected to VCC to detect VCC undervoltage. The inputs of comparator CP4 are connected to VIN, VCC and a 4.1V reference source, respectively, to control the enable of the LDO; The inverting input of comparator CP5 is connected to a 1V reference source, and the non-inverting input is connected to REV to control the reverse current. The comparator CP6 has a 0.7V reference source at its positive input, a SOURCE at its inverting input, and a STAT at its output, which is used to indicate the on-state of the external MOSFET.

[0021] The external circuit is shown in Figure 3(a), including: an external NMOS transistor Q, a bootstrap capacitor C1, and resistors R1 to R6. The specific connection method is as follows: The VIN terminal is connected to the source of Q, the VOUT terminal is connected to the drain of Q, the GATE terminal is connected to the gate of Q, and the SOURCE terminal is connected to the source of Q. A 0.1μF ceramic capacitor is connected between the VCC terminal and ground for power supply filtering. A 0.1μF bootstrap capacitor C1 is connected between the CPO terminal and the SOURCE terminal to generate the gate drive voltage; The input overvoltage and undervoltage thresholds are set using voltage divider resistors R1, R2, and R3: the OV terminal is connected to the junction of R1 and R2, and the UV terminal is connected to the junction of R2 and R3. The calculation formula is as follows: when the OV function is not used, ground the OV; when the UV function is not used, connect the UV to VCC. ;

[0022] The STAT and FAULT terminals are connected to the VOUT terminal (or other power rails not exceeding 18V) via pull-up resistors R4 and R5, respectively. The REV terminal should be grounded directly, and reverse current is prohibited.

[0023] In this embodiment, the external NMOS transistor Q is selected as model Si7336, with the following main parameters: VDSS=30V, ID=27A, and a typical on-resistance RDS(ON) of 4.2mΩ. The input voltage VIN is set to 12V, and the maximum load current is 20A.

[0024] The circuit described in this embodiment works as follows: After power-on, if VIN > 4.1V, the internal LDO will operate, generating approximately 4.1V VCC to power the internal circuitry; if VIN is below 2.9V, an external power supply (2.9V~6V) is required from the VCC terminal.

[0025] The charge pump starts up, generating a voltage higher than VIN (approximately VIN+6V) at the CPO terminal, providing power to the GATE driver.

[0026] Under light load, the GATE driver adjusts the GATE voltage to stabilize the voltage difference between VIN and VOUT at 25mV (controlled by a 25mV reference source).

[0027] When the load increases and causes VIN-VOUT > 75mV, the GATE voltage is quickly pulled up to SOURCE+6.1V, which makes the external NMOSFET fully turn on. At this time, the voltage drop is the load current multiplied by RDS(ON).

[0028] If VIN-VOUT > 250mV, the FAULT terminal is pulled low, indicating that the load current is too high or the MOSFET is open.

[0029] Input overvoltage protection: When the voltage at the OV terminal exceeds 0.5V, CP1 outputs an overvoltage signal, and the controller shuts down GATE.

[0030] Input undervoltage protection: When the UV terminal voltage is lower than 0.5V, CP2 outputs an undervoltage signal and the controller shuts down GATE.

[0031] Reverse current control: REV is grounded, CP5 outputs a low level, and reverse current is prohibited; if reverse current is required, a voltage higher than 1V can be applied to the REV terminal.

[0032] Status indication: When the voltage between GATE and SOURCE is greater than 0.7V, CP6 outputs a high level and the STAT terminal is pulled low, indicating that the MOSFET is turned on.

[0033] Furthermore, referring to Figure 3(b), this embodiment illustrates an application scenario for ultra-low voltage power supply mode. When the input voltage VIN needs to operate at an extremely low voltage (e.g., 0V to 2.9V), VCC is powered by an external power supply. The external power supply (2.9V to 6V) is directly connected to the VCC terminal, and the internal LDO is automatically turned off (because VCC > VIN). At this time, VIN can be as low as 0V, but it must be ensured that VIN ≤ VCC. For example, if VCC = 3.3V, then VIN can operate in the range of 0 to 3.3V, which is suitable for the main backup scenario of low-voltage processor core power supply. The peripheral circuit is basically the same as in Embodiment 1, only the VCC power supply method is different.

[0034] In this mode, the controller can still detect input undervoltage / overvoltage normally (through external voltage divider resistors) and achieve the ideal diode function, significantly reducing conduction losses.

[0035] This embodiment is designed for hot-swappable applications and aims to suppress inrush currents generated during hot-swapping of the circuit board. The specific connection method is shown in Figure 3(a), but the following modifications are required: The bootstrap capacitor C1 is not connected between CPO and SOURCE. The gate voltage is slowly built up by utilizing the internal pF-level parasitic capacitance of the chip to achieve soft start.

[0036] To further slow down the gate voltage rise rate, an RC series network (e.g., resistor R6 and capacitor C2 in series) can be connected to ground at the GATE terminal to control the MOSFET turn-on speed and thus limit the inrush current.

[0037] If a fast MOSFET needs to be turned on (e.g., for fast master-slave switching), the CPO terminal can be connected to an external power supply (e.g., 12V) through a current-limiting resistor, while omitting the bootstrap capacitor to achieve a fast response.

[0038] This embodiment verifies the controller's performance during seamless switching between primary and backup power supplies. Two circuits as shown in Figure 3(a) are used, connected to the primary power supply (VIN1=12V) and the backup power supply (VIN2=5V) respectively. The two outputs are connected in parallel to the same load. Test procedure: First, power on the backup power supply (5V), then power on the primary power supply (12V), then disconnect the primary power supply and observe the waveform of the output voltage VOUT. Figure 4 As shown.

[0039] Test results show that VOUT smoothly jumps from 5V to 12V and then smoothly returns to 5V. There is no obvious drop or overshoot during the switching process, achieving seamless voltage switching and proving the reliability and fast response capability of the controller in a dual-power redundant power supply system.

[0040] This embodiment is used to verify the low conduction loss characteristics of the controller. The circuit is connected as shown in Figure 3(a), with VIN fixed at 12V. The load current is gradually increased from 0A to 20A in 1A increments. The voltage difference between VIN and VOUT is measured, and the curve is plotted as shown. Figure 5 As shown.

[0041] Test results show that under a load current of 20A, the VIN-VOUT voltage difference is only 84mV (calculated based on Q's RDS(ON) = 4.2mΩ), which is far lower than the 0.4V to 0.7V of a traditional Schottky diode. This characteristic significantly reduces system power consumption, making it particularly suitable for power supply systems with high current and low voltage output.

[0042] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low-voltage ideal diode controller circuit, characterized in that, include: Power input terminal VIN, power output terminal VOUT, gate drive terminal GATE, logic power supply terminal VCC, charge pump output terminal CPO, driver source terminal SOURCE, input overvoltage detection terminal OV, input undervoltage detection terminal UV, status indicator terminal STAT, fault indicator terminal FAULT; A charge pump, whose output is connected to the CPO, is used to generate a voltage higher than VIN; An LDO (Low Voltage DO) is connected to VIN at its input and VCC at its output. It is used to convert the external input voltage VIN into a low voltage VCC to power the internal circuitry. The GATE driver, whose input is connected to the charge pump and SOURCE and whose output is connected to GATE, is used to drive the gate of an external NMOSFET. Multiple reference voltage sources provide reference voltages of 25mV, 4.1V, 2.57V, 1V, 0.5V, and 0.7V, respectively; The first comparator CP1 has its positive input connected to the 0.5V reference source and its inverting input connected to 0V, and is used to detect input overvoltage. The second comparator CP2 has its inverting input connected to the 0.5V reference source and its non-inverting input connected to UV, and is used to detect input undervoltage. The third comparator CP3 has its positive input connected to the 2.57V reference source and its inverting input connected to VCC, and is used to detect VCC undervoltage. The fourth comparator CP4 has its input connected to VIN, VCC and the 4.1V reference source. It is used to control the enable of the LDO. When VCC is powered externally and VCC > VIN, it generates a control signal to turn off the LDO. The fifth comparator CP5 has its inverting input connected to the 1V reference source and its non-inverting input connected to the REV terminal. It is used to control the reverse current. When the REV voltage is higher than 1V, the current is allowed to flow from VOUT to VIN. The sixth comparator CP6 has its positive input connected to the 0.7V reference source, its inverting input connected to SOURCE, and its output connected to STAT. When the voltage between GATE and SOURCE is greater than 0.7V, STAT outputs a low level to indicate that the external MOS is turned on.

2. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, Under normal use, a 0.1μF ceramic capacitor is connected to ground at the VCC terminal, and the VIN operating voltage range is 2.9V to 18V; when VCC is powered externally, VIN can be as low as 0V.

3. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, In normal use, a bootstrap capacitor is connected between the CPO terminal and the SOURCE terminal; in hot-swappable applications, this bootstrap capacitor is not connected, and the MOS is slowly turned on using the internal pF-level capacitor; when the MOS needs to be turned on quickly, the CPO terminal is connected to an external power supply through a current-limiting resistor.

4. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The UV terminal is connected to VCC when the input undervoltage function is not used, and the OV terminal is connected to GND when the input overvoltage function is not used. When the input undervoltage and overvoltage functions are used, the undervoltage and overvoltage thresholds of VIN are set by external voltage divider resistors R1, R2, and R3, where: Overvoltage threshold: ; Undervoltage threshold: .

5. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The STAT and FAULT terminals are connected to the output terminal or other power rails not exceeding 18V via pull-up resistors to output status indication signals.

6. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The enable control logic of the LDO is as follows: when VIN > 4.1V, VCC is left floating and powered by the internal LDO; when VIN < 2.9V, VCC needs external power and the internal LDO is turned off. When 2.9V < VIN < 4.1V, VCC can be left floating or powered externally. When VCC > VIN, the internal LDO is turned off, and when VCC < VIN, the LDO remains on.

7. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The GATE driver adjusts the GATE voltage according to the load: under light load, the GATE driver adjusts to stabilize the voltage difference between VIN and VOUT at 25mV; when VIN-VOUT>75mV, the GATE voltage is quickly pulled up to SOURCE+6.1V, making the external NMOSFET fully conduct.

8. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The FAULT terminal is pulled low when the voltage difference between VIN and VOUT is greater than 250mV, which is used to indicate that the load current is too large or the external MOSFET is open.

9. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, The REV terminal is usually grounded to prevent reverse current; when reverse current needs to be allowed, a control voltage higher than 1V is applied to the REV terminal.

10. The low-voltage ideal diode controller circuit according to claim 1, characterized in that, Furthermore, the controller circuit also includes an external NMOSFET, with its source connected to VIN and SOURCE, its drain connected to VOUT, and its gate connected to GATE; the body diode of the external NMOSFET provides the initial conduction path when the MOS is turned off.

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