Low noise rail-to-rail input amplifier with base compensation

Abstract

The application discloses a low-noise rail-to-rail input amplifier with base compensation, and belongs to the technical field of microelectronic integrated circuits, comprising a PTAT current generating circuit, a bias voltage generating circuit, a compensation switching circuit, a PNP input pair base current compensation circuit, an NPN input pair base current compensation circuit, a PNP input rail and an NPN input rail. The application adopts the base compensation structure in the rail-to-rail input amplifier composed of transistors, realizes the accurate and smooth compensation of the base current, and completes the switching of the PNP input rail and the NPN input rail according to the height of the input voltage, realizes the wide input swing of the amplifier, and has the advantages of reducing the additional noise and input current, providing the large output current of the drive nF level capacitor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic integrated circuit technology, and specifically relates to a low-noise rail-to-rail input amplifier with base compensation. Background Technology

[0002] As modern electronic systems continue to evolve towards lower voltage, single power supply, and higher precision, operational amplifiers, as core front-end devices in analog signal processing, face increasingly stringent performance requirements. To maximize the system's dynamic range and signal-to-noise ratio at low supply voltages, rail-to-rail input stage technology is widely used. Rail-to-rail input stages allow the amplifier's input common-mode voltage range to cover the entire spectrum from the negative to the positive power supply rail, ensuring that the amplifier can process large-amplitude input signals without distortion in weak signal detection, portable medical devices, and sophisticated data acquisition systems.

[0003] In applications requiring ultra-low noise and high precision, bipolar junction transistors (BJTs) are frequently used as input stage devices in high-precision amplifiers due to their extremely low intrinsic flicker noise (1 / f noise) and high transconductance. Traditional bipolar rail-to-rail input stages typically employ a parallel architecture of complementary NPN and PNP differential pairs to achieve full common-mode range coverage. However, this structure has an inherent drawback: when the input common-mode voltage varies across the entire power rail range, the NPN and PNP differential pairs alternately turn on and off with the voltage levels. Because the base currents of the NPN and PNP transistors are in opposite directions and due to manufacturing limitations, they are often not perfectly matched. This causes a sharp polarity reversal and amplitude jump in the amplifier's input bias current when the common-mode voltage crosses the crossover region. This jump not only leads to severe system-level offset voltage errors but also significantly degrades the common-mode rejection ratio (CMRR).

[0004] To eliminate the aforementioned input bias current fluctuations, existing technologies typically incorporate base current compensation / cancellation circuits, which mirror and inject reverse current to cancel the input bias current. However, traditional base compensation techniques often face a trade-off between "compensation accuracy" and "noise performance." The numerous active transistors and passive components within the compensation circuit inevitably introduce additional current and voltage noise into the amplifier's input; especially in the transition region where NPN and PNP differential pairs alternate conduction, the switching of complex compensation loops can easily induce local noise peaks and dynamic distortion. Therefore, how to achieve accurate and smooth base current compensation across the entire common-mode input range while effectively suppressing the additional noise introduced by the compensation circuit and maintaining the overall ultra-low noise characteristics of the amplifier is a pressing technical challenge in the field of high-precision analog integrated circuit design. Summary of the Invention

[0005] To address the inherent contradiction between "compensation accuracy" and "noise performance" in traditional base compensation technology, this invention provides a low-noise rail-to-rail input amplifier with base compensation. This amplifier achieves a wide input swing while reducing additional noise and input current, and provides a large output current capable of driving nF-level capacitors.

[0006] The technical solution adopted in this invention is as follows:

[0007] A low-noise rail-to-rail input amplifier with base compensation includes a PTAT (proportional to absolute temperature) current generation circuit, a bias voltage generation circuit, a compensation switching circuit, a PNP input to base current compensation circuit, an NPN input to base current compensation circuit, a PNP input rail, and an NPN input rail.

[0008] The PTAT current generation circuit is connected to the PNP input-to-base current compensation circuit and the PNP input rail, and is used to provide basic bias current for the global circuit.

[0009] The bias voltage generating circuit is used to generate the track switching voltage V. B1 and compensation switching voltage V B2 ;

[0010] The PNP and NPN input rails are connected via a first transistor, the base of which is connected to a bias voltage generation circuit, based on V. B1 Control the switch of the first transistor to complete the track switching between the PNP input rail and the NPN input rail;

[0011] The NPN input-to-base current compensation circuit is connected to the NPN input rail and generates a bias voltage V connected to the collector of the first transistor.B3 The multi-output current mirror structure is used to replicate the base current of the matching transistor as the base compensation current of the NPN, which flows back to the input stage of the NPN input rail to achieve the function of compensating the base current of the input stage of the NPN input rail.

[0012] The PNP input-to-base current compensation circuit is connected to the PNP input rail. It uses a multi-output current mirror structure to replicate the base current of the matching transistor as the PNP base compensation current, which flows back to the input stage of the PNP input rail to compensate for the base current of the input stage of the PNP input rail.

[0013] The compensation switching circuit is connected to the PNP input-to-base current compensation circuit, the NPN input-to-base current compensation circuit, and the bias voltage generation circuit, based on V. B2 and V B3 The circuit controls the switching on and off of the PNP base compensation current, thereby switching between the PNP input-to-base current compensation circuit and the NPN input-to-base current compensation circuit.

[0014] Furthermore, the NPN input-to-base current compensation circuit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; wherein the emitter of the second transistor is coupled to ground via a resistor, and the base generates V0. B3 The collector of the fourth transistor is connected to the emitter of the third transistor; the collector of the third transistor is connected to the power supply terminal VCC, and the base is connected to the collector of the fourth transistor; the fourth, fifth, and sixth transistors form a multi-output current mirror structure, with the base and collector of the fourth transistor shorted, the bases of the fifth and sixth transistors interconnected and connected to the base of the fourth transistor, the emitters of the fourth, fifth, and sixth transistors coupled to VCC via resistors, and the collectors of the fifth and sixth transistors coupled to the inverting input signal V. in- and in-phase input signal V in+ .

[0015] Furthermore, the PNP input-to-base current compensation circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; wherein, the emitter of the seventh transistor is coupled to VCC via a resistor, its base is connected to the PTAT current generating circuit, and its collector is connected to the emitter of the eighth transistor; the collector of the eighth transistor is connected to ground, and its base is connected to the collector of the ninth transistor; the ninth, tenth, and eleventh transistors constitute a multi-output current mirror structure, the base and collector of the ninth transistor are shorted, the bases of the tenth and eleventh transistors are interconnected and connected to the base of the ninth transistor, the emitters of the ninth, tenth, and eleventh transistors are coupled to ground via resistors, and the collectors of the tenth and eleventh transistors are respectively coupled to the in-phase input signal VCC. in+ and inverted input signal V in- .

[0016] Furthermore, the compensation switching circuit includes a comparator and a first MOS transistor; wherein, the non-inverting input terminal of the comparator is coupled to V. B3 The inverting input is coupled to V. B2 The output terminal is connected to the gate of the first MOS transistor to control the conduction and turn-off of the first MOS transistor; the drain of the first MOS transistor is connected to the collector of the ninth transistor, and the source is connected to the ground terminal.

[0017] Furthermore, the PNP input rail includes a PNP input stage, a PNP follower stage, and a PNP output stage;

[0018] The PNP input stage includes a twelfth transistor and a differential pair consisting of a thirteenth and a fourteenth transistor; wherein the emitter of the twelfth transistor is resistor-coupled to VCC, its base is connected to the PTAT current generation circuit, and its collector is connected to the emitter of the first transistor; the bases of the thirteenth and fourteenth transistors are respectively connected to VCC. in- and V in+ The emitters are all connected to the collector of the twelfth transistor, and the collectors are all coupled to the ground terminal via resistors;

[0019] The PNP follower stage includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; wherein the emitters of the fifteenth and sixteenth transistors are both coupled to VCC via resistors, the bases of both transistors are connected to the PTAT current generating circuit, and the collectors are respectively connected to the emitters of the seventeenth and eighteenth transistors; the bases of the seventeenth and eighteenth transistors are respectively connected to the collectors of the thirteenth and fourteenth transistors, and the collectors of both transistors are connected to the ground terminal;

[0020] The PNP output stage includes a current mirror structure composed of a nineteenth transistor and a twentieth transistor, and a differential input pair composed of a twenty-first transistor and a twenty-second transistor. The emitters of both the nineteenth and twentieth transistors are resistor-coupled to VCC, and their collectors are connected to the collectors of the twenty-first and twenty-second transistors, respectively. The base of the nineteenth transistor is shorted to its collector and connected to the base of the twentieth transistor. The emitters of the twenty-first and twenty-second transistors are interconnected and resistor-coupled to ground, and their bases are connected to the collectors of the fifteenth and sixteenth transistors, respectively.

[0021] The collector side of the twentieth transistor is the main output terminal V. OUT .

[0022] Furthermore, the NPN input rail includes an NPN input stage, an NPN follower stage, and an NPN output stage;

[0023] The NPN input stage includes a current mirror structure composed of a 23rd transistor and a 24th transistor, and a differential pair composed of a 25th transistor and a 26th transistor. The emitters of both the 23rd and 24th transistors are resistively coupled to ground. The base and collector of the 23rd transistor are shorted and connected to the collector of the first transistor and the base of the 24th transistor. The emitters of both the 25th and 26th transistors are connected to the collector of the 24th transistor, and both emitters are resistively coupled to VCC. The bases are respectively connected to VCC. in- and V in+ ;

[0024] The NPN follower stage includes a 27th transistor, a 28th transistor, a 29th transistor, and a 30th transistor; wherein the emitters of the 27th and 28th transistors are both coupled to ground via resistors, the bases of both transistors are connected to the base of the 24th transistor, and the collectors are connected to the emitters of the 29th and 30th transistors, respectively; the collectors of the 29th and 30th transistors are both connected to VCC, and the bases of both transistors are connected to the collectors of the 25th and 26th transistors, respectively.

[0025] The NPN output stage includes a current mirror structure composed of transistors 31 and 32, and a differential input pair composed of transistors 33 and 34. The emitters of transistors 31 and 32 are both resistor-coupled to ground, and their collectors are connected to the collectors of transistors 33 and 34, respectively. The base of transistor 31 is shorted to its collector and connected to the base of transistor 32. The emitters of transistors 33 and 34 are interconnected and resistor-coupled to VCC, and their bases are connected to the collectors of transistors 27 and 28, respectively.

[0026] The collector side of the thirty-second transistor is the main output terminal V. OUT .

[0027] Furthermore, the PTAT current generation circuit includes a current mirror structure composed of a 35th transistor and a 36th transistor, as well as a 37th transistor, a 38th transistor, a 39th transistor, and a second MOS transistor. The emitters of the 35th and 36th transistors are both resistor-coupled to ground, and their collectors are connected to the collectors of the 37th and 38th transistors, respectively. The base of the 36th transistor is short-circuited to its collector and connected to the base of the 35th transistor. The emitters of the 37th and 38th transistors are resistor-coupled to VCC, and their bases are interconnected and coupled to the PVBI (PNP base voltage input) terminal. The source of the second MOS transistor is connected to the emitter of the 36th transistor, its gate is connected to the collector of the 37th transistor, and its drain is connected to the collector of the 39th transistor. The emitter of the 39th transistor is resistor-coupled to VCC, its base is short-circuited to its collector, and connected to the PVBO (PNP base voltage output) terminal, used to provide basic bias current for the global circuit.

[0028] Furthermore, the bias voltage generating circuit includes a 40th transistor, a 41st transistor, a first resistor, a second resistor, and a third resistor; wherein the first resistor, the second resistor, and the third resistor are connected in sequence, the first resistor is also connected to VCC, and the third resistor is also connected to the collector of the 40th transistor; the emitter of the 40th transistor is coupled to the ground terminal, the base is short-circuited with the collector, and VCC is output from the base. B2 The emitter of the forty-first transistor is coupled to VCC, the base is connected to the common node of the first and second resistors, the collector is connected to the common node of the second and third resistors, and V is output from the collector. B1 .

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] 1. This invention proposes a low-noise rail-to-rail input amplifier with base compensation. By employing a base compensation structure in the rail-to-rail input amplifier composed of transistors, precise and smooth compensation of the base current is achieved. The switching between PNP and NPN input rails is completed according to the input voltage, thus realizing a wide input swing of the amplifier.

[0031] 2. This invention adopts a full bipolar process. Compared with MOSFET (metal-oxide-semiconductor transistor), its main noise sources are shot noise of transistor collector current and thermal noise of load resistance. It has lower flicker noise, thereby effectively suppressing the additional noise brought by the compensation circuit and maintaining the ultra-low noise characteristics of the amplifier as a whole.

[0032] 3. Due to the base compensation design, this invention has a lower input current and a larger output current, and can be used to drive nF level capacitors. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the circuit structure of the low-noise rail-to-rail input amplifier with base compensation proposed in Example 1;

[0034] Figure 2 The simulation results show the input swing of the low-noise rail-to-rail input amplifier with base compensation in Example 1 under unity-gain configuration.

[0035] Figure 3 The graph shows the input current versus temperature of the low-noise rail-to-rail input amplifier with base compensation proposed in Example 1.

[0036] Figure 4 The noise frequency response curve of the low-noise rail-to-rail input amplifier with base compensation proposed in Example 1 is shown.

[0037] Figure 5 The output current variation curve of the low-noise rail-to-rail input amplifier with base compensation proposed in Example 1 is shown. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0039] Example 1

[0040] This embodiment proposes a low-noise rail-to-rail input amplifier with base compensation, the circuit structure of which is as follows: Figure 1As shown, it includes a PTAT current generation circuit, a bias voltage generation circuit, a compensation switching circuit, a PNP input to base current compensation circuit, an NPN input to base current compensation circuit, a PNP input rail, and an NPN input rail.

[0041] The PTAT current generation circuit, connected to the PNP input-to-base current compensation circuit and the PNP input rail, specifically includes transistors Q1, Q2, Q5, MOSFET M1, and a current mirror structure composed of transistors Q3 and Q4. The emitters of transistors Q3 and Q4 are coupled to ground via resistors R1 and R2, respectively, and their collectors are connected to the collectors of transistors Q1 and Q2, respectively. The base and collector of transistor Q4 are short-circuited and connected to the base of transistor Q3. The emitters of transistors Q1 and Q2 are coupled to VCC via resistors, and their bases are interconnected and coupled to the PVBI terminal. The source of MOSFET M1 is connected to the emitter of transistor Q4, its gate is connected to the collector of transistor Q1, and its drain is connected to the collector of transistor Q5. The emitter of transistor Q5 is coupled to VCC via a resistor, its base and collector are short-circuited, and connected to the PVBO terminal, providing basic bias current for the global circuit.

[0042] The bias voltage generating circuit includes transistor Q. 41 transistor Q 17 Resistors R6, R7, and R8 are connected sequentially. Resistor R6 is also connected to VCC, and resistor R8 is also connected to transistor Q. 41 The collector of the transistor; transistor Q 41 The emitter is coupled to ground, the base is shorted to the collector, and a compensation switching voltage V is output from the base. B2 Transistor Q 17 The emitter is coupled to VCC, the base is connected to the common node of resistors R6 and R7, and the collector is connected to the common node of resistors R7 and R8. The voltage V is switched from the collector output rail. B1 .

[0043] The NPN input-to-base current compensation circuit is connected to the NPN input rail and generates a current that is connected to transistor Q. 18 collector bias voltage V B3 A multi-output current mirror structure is used to replicate the base current of the matching transistor as the NPN base compensation current, which flows back to the input stage of the NPN input rail to compensate for the base current of the input stage of the NPN input rail; specifically, this includes transistor Q. 36 transistor Q 37 transistor Q 38 transistor Q 39 and transistor Q40 Among them, transistor Q 36 The emitter is coupled to ground via a resistor, and a bias voltage V is generated at the base. B3 The collector is connected to transistor Q. 37 The emitter of the transistor; transistor Q 37 The collector is connected to the power supply terminal VCC, and the base is connected to the transistor Q. 38 The collector of the transistor; transistor Q 38 transistor Q 39 and transistor Q 40 Constructing a multi-output current mirror structure, transistor Q 38 When the base and collector of transistor Q are shorted, 39 and transistor Q 40 The base interconnect is connected to transistor Q. 38 The base of the transistor Q 38 transistor Q 39 and transistor Q 40 The emitter of transistor Q is coupled to VCC via a resistor. 39 The collector is coupled to the inverting input signal V. in- transistor Q 40 The collector is coupled to the in-phase input signal V. in+ .

[0044] The PNP input-to-base current compensation circuit is connected to the PNP input rail. It utilizes a multi-output current mirror structure to replicate the base current of the matching transistor as the PNP base compensation current, which flows back to the input stage of the PNP input rail to compensate for the base current of the input stage. Specifically, it includes transistor Q. 31 transistor Q 32 transistor Q 33 transistor Q 34 and transistor Q 35 Among them, transistor Q 31 The emitter is coupled to VCC via a resistor, the base is connected to the PVBO terminal of the PTAT current generation circuit, and the collector is connected to transistor Q. 32 The emitter of the transistor; transistor Q 32 The collector is connected to ground, and the base is connected to transistor Q. 33 The collector of the transistor; transistor Q 33 transistor Q 34 and transistor Q 35 Constructing a multi-output current mirror structure, transistor Q 33 When the base and collector of transistor Q are shorted, 34 and transistor Q 35 The base interconnect is connected to transistor Q. 33 The base of the transistor Q 33transistor Q 34 and transistor Q 35 The emitter of transistor Q is coupled to ground via a resistor. 34 The collector is coupled to the in-phase input signal V. in+ transistor Q 35 The collector is coupled to the inverting input signal V. in- .

[0045] The compensation switching circuit is connected to the PNP input-to-base current compensation circuit, the NPN input-to-base current compensation circuit, and the bias voltage generation circuit, based on V. B2 and V B3 The circuit controls the switching on and off of the PNP base compensation current, thereby switching between the PNP input-to-base current compensation circuit and the NPN input-to-base current compensation circuit. Specifically, it includes a comparator and a MOSFET M2; the non-inverting input of the comparator is coupled to V... B3 The inverting input is coupled to V. B2 The output terminal is connected to the gate of MOSFET M2 to control the on and off states of MOSFET M2; the drain of MOSFET M2 is connected to transistor Q. 33 The collector and source are connected to the ground terminal.

[0046] The PNP and NPN input rails are connected via transistor Q. 18 Connection, transistor Q 18 The base is connected to the bias voltage generation circuit, based on V B1 Control transistor Q 18 The switch is used to switch between the PNP and NPN input rails.

[0047] The PNP and NPN input rails adopt a three-stage circuit structure. The input stage uses bipolar transistors as input pairs and resistors as loads to provide a certain gain. The follower stage acts as a voltage follower, mainly to improve the common-mode level. The output stage adopts an input pair structure with emitter negative feedback resistors and a current mirror composed of bipolar transistors as a load to provide higher gain.

[0048] The PNP input rail includes a PNP input stage, a PNP follower stage, and a PNP output stage;

[0049] The PNP input stage includes transistor Q6 and a differential pair consisting of transistors Q7 and Q8; wherein, the emitter of transistor Q6 is coupled to VCC via a resistor, the base is connected to the PVBO terminal of the PTAT current generation circuit, and the collector is connected to transistor Q8. 18 The emitter of transistor Q7; the bases of transistors Q8 are connected to V. in- and V in+The emitter of transistor Q6 is connected to the collector of transistor Q7, the collector of transistor Q7 is coupled to the ground terminal through resistor R3, and the collector of transistor Q8 is coupled to the ground terminal through resistor R4.

[0050] The PNP follower stage includes transistor Q9 and transistor Q. 10 transistor Q 11 and transistor Q 12 Among them, transistor Q9 and transistor Q 10 The emitters of all transistors are coupled to VCC via resistors, the bases are connected to the PVBO terminal of the PTAT current generation circuit, and the collectors are connected to transistor Q. 11 transistor Q 12 The emitter of the transistor; transistor Q 11 The base of transistor Q is connected to the collector of transistor Q7. 12 The base of the transistor is connected to the collector of the transistor Q8, and the collectors of both are connected to the ground terminal.

[0051] The PNP output stage includes transistor Q. 13 and transistor Q 14 The current mirror structure formed by the transistor Q, and the current mirror structure formed by the transistor Q. 15 and transistor Q 16 The differential input pair is formed; where transistor Q 13 and transistor Q 14 The emitters of both transistors are coupled to VCC via resistors, and their collectors are connected to transistor Q. 15 transistor Q 16 The collector of the transistor; transistor Q 13 The base and collector of the transistor are shorted together and connected to transistor Q. 14 The base of the transistor; the Q-cell transistor 15 and transistor Q 16 The emitter of transistor Q is interconnected and coupled to ground via resistor R5. 15 The base of transistor Q is connected to the collector of transistor Q9. 16 The base is connected to transistor Q. 10 The collector;

[0052] The transistor Q 14 The collector side is the main output terminal V OUT .

[0053] The NPN input track includes an NPN input stage, an NPN follower stage, and an NPN output stage;

[0054] The NPN input stage includes transistor Q. 19 and transistor Q 20 The current mirror structure formed by the transistor Q, and the current mirror structure formed by the transistor Q. 21 and transistor Q22 The differential pair formed; where transistor Q 19 and transistor Q 20 The emitters of transistors Q are all coupled to ground via resistors. 19 The base and collector of the transistor are shorted together and connected to transistor Q. 18 collector and transistor Q 20 The base of the transistor; the Q-cell transistor 21 and transistor Q 22 The emitter of each transistor is connected to the transistor Q. 20 The collector of the transistor; transistor Q 21 The emitter is coupled to VCC via resistor R9, and the base is connected to V. in+ Transistor Q 22 The emitter is connected to resistor R 10 Coupled to VCC, base connected to V in- ;

[0055] The NPN follower stage includes transistor Q. 23 transistor Q 24 transistor Q 25 and transistor Q 26 Among them, transistor Q 25 and transistor Q 26 The emitters of all transistors are coupled to ground via resistors, and the bases of all transistors are connected to transistor Q. 20 The base and collector are respectively connected to transistor Q. 23 transistor Q 24 The emitter of the transistor; transistor Q 23 and transistor Q 24 The collectors of all transistors are connected to VCC, and transistor Q... 23 The base is connected to transistor Q. 21 The collector of the transistor Q 24 The base is connected to transistor Q. 22 The collector;

[0056] The NPN output stage includes transistor Q. 29 and transistor Q 30 The current mirror structure formed by the transistor Q, and the current mirror structure formed by the transistor Q. 27 and transistor Q 28 The differential input pair is formed; where transistor Q 29 and transistor Q 30 The emitters of both transistors are coupled to ground via resistors, and their collectors are connected to transistor Q. 27 transistor Q 28 The collector of the transistor; transistor Q 29 The base and collector of the transistor are shorted together and connected to transistor Q. 30 The base of the transistor; the Q-cell transistor 27and transistor Q 28 The emitters are interconnected and connected via resistor R 11 Coupled to VCC, transistor Q 27 The base is connected to transistor Q. 25 The collector of the transistor Q 28 The base is connected to transistor Q. 26 The collector;

[0057] The transistor Q 30 The collector side is the main output terminal V OUT .

[0058] In this embodiment, the principle of track switching between the PNP input rail and the NPN input rail is as follows: the emitter of the differential pair composed of transistors Q7 and Q8 is connected to transistor Q... 18 Connect the emitters of V to V in- and V in+ The larger one and V B1 For comparison, when V in- and V in+ The larger one exceeds V B1 At that time, transistor Q 18 When the transistor Q6 is turned on, all the current is diverted away. At this time, the PNP input pair is turned off, and the NPN input rail starts working, thus completing the rail switching.

[0059] The principle behind the switching of base current compensation between the PNP input-to-base current compensation circuit and the NPN input-to-base current compensation circuit is as follows: the transistor Q is switched using a comparator. 19 base voltage V B3 With the set bias voltage V B2 For comparison, when V B3 More than V B2 When, it means that transistor Q 18 The current flows completely into transistor Q. 19 The amplifier operates entirely on NPN input pairs, thus shutting off the base compensation current of the PNP input pairs.

[0060] This embodiment uses the circuit design software Cadence Virtuoso for circuit design and simulation. The SMIC 0.18um BCD process is selected from the technology library, and the simulation results are as follows:

[0061] like Figure 2 As shown, under a power supply voltage of 5 V, the input voltage range is approximately 0.2 V to 4.8 V, which conforms to the wide input swing design.

[0062] like Figure 3As shown, the maximum point noise at 0.01 Hz is 37.3 nV / √Hz; the maximum integral noise from 10 Hz to 100 kHz is approximately 0.93 μV. RMS The main source of noise is the shot noise of the PNP input pair, which accounts for 69.3% of the total noise. The second largest source is the thermal noise of the load resistors R3 and R4, which accounts for 13.1% of the total noise, which is in line with the low-noise design.

[0063] like Figure 4 As shown, under the condition of an input stage current of 200 μA, the maximum input current is only 47.3 nA under all temperature and process angle conditions, at SS and -55℃, which meets the requirements of low input current design.

[0064] like Figure 5 As shown, the maximum output current of this amplifier is 330 μA, which meets the requirements of a large output current design.

[0065] It should be noted that this is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-noise rail-to-rail input amplifier with base compensation, characterized in that, It includes a PTAT current generation circuit, a bias voltage generation circuit, a compensation switching circuit, a PNP input to base current compensation circuit, an NPN input to base current compensation circuit, a PNP input rail, and an NPN input rail. The PTAT current generation circuit is connected to the PNP input-to-base current compensation circuit and the PNP input rail, and is used to provide basic bias current for the global circuit. The bias voltage generating circuit is used to generate the track switching voltage V. B1 and compensation switching voltage V B2 ; The PNP and NPN input rails are connected via a first transistor, the base of which is connected to a bias voltage generation circuit, based on V. B1 Control the switch of the first transistor to complete the track switching between the PNP input rail and the NPN input rail; The NPN input-to-base current compensation circuit is connected to the NPN input rail and generates a bias voltage V connected to the collector of the first transistor. B3 The multi-output current mirror structure is used to replicate the base current of the matching transistor as the base compensation current of the NPN, which flows back to the input stage of the NPN input rail to achieve the function of compensating the base current of the input stage of the NPN input rail. The PNP input-to-base current compensation circuit is connected to the PNP input rail. It uses a multi-output current mirror structure to replicate the base current of the matching transistor as the PNP base compensation current, which flows back to the input stage of the PNP input rail to compensate for the base current of the input stage of the PNP input rail. The compensation switching circuit is connected to the PNP input-to-base current compensation circuit, the NPN input-to-base current compensation circuit, and the bias voltage generation circuit, based on V. B2 and V B3 The circuit controls the switching on and off of the PNP base compensation current, thereby switching between the PNP input-to-base current compensation circuit and the NPN input-to-base current compensation circuit.

2. The low-noise rail-to-rail input amplifier with base compensation according to claim 1, characterized in that, The NPN input base current compensation circuit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; wherein, the emitter of the second transistor is coupled to ground via a resistor, and the base generates V0. B3 The collector of the fourth transistor is connected to the emitter of the third transistor; the collector of the third transistor is connected to the power supply terminal VCC, and the base is connected to the collector of the fourth transistor; the fourth, fifth, and sixth transistors form a multi-output current mirror structure, with the base and collector of the fourth transistor shorted, the bases of the fifth and sixth transistors interconnected and connected to the base of the fourth transistor, the emitters of the fourth, fifth, and sixth transistors coupled to VCC via resistors, and the collectors of the fifth and sixth transistors coupled to the inverting input signal V. in- and in-phase input signal V in+ .

3. The low-noise rail-to-rail input amplifier with base compensation according to claim 2, characterized in that, The PNP input-to-base current compensation circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor. The emitter of the seventh transistor is resistor-coupled to VCC, its base is connected to the PTAT current generation circuit, and its collector is connected to the emitter of the eighth transistor. The collector of the eighth transistor is connected to ground, and its base is connected to the collector of the ninth transistor. The ninth, tenth, and eleventh transistors form a multi-output current mirror structure. The base and collector of the ninth transistor are short-circuited, the bases of the tenth and eleventh transistors are interconnected and connected to the base of the ninth transistor, the emitters of the ninth, tenth, and eleventh transistors are resistor-coupled to ground, and the collectors of the tenth and eleventh transistors are respectively coupled to the in-phase input signal VCC. in+ and inverted input signal V in- .

4. The low-noise rail-to-rail input amplifier with base compensation according to claim 3, characterized in that, The compensation switching circuit includes a comparator and a first MOSFET; wherein, the non-inverting input terminal of the comparator is coupled to V. B3 The inverting input is coupled to V. B2 The output terminal is connected to the gate of the first MOS transistor to control the conduction and turn-off of the first MOS transistor; the drain of the first MOS transistor is connected to the collector of the ninth transistor, and the source is connected to the ground terminal.

5. The low-noise rail-to-rail input amplifier with base compensation according to claim 4, characterized in that, The PNP input rail includes a PNP input stage, a PNP follower stage, and a PNP output stage; The PNP input stage includes a twelfth transistor and a differential pair consisting of a thirteenth and a fourteenth transistor; wherein the emitter of the twelfth transistor is resistor-coupled to VCC, its base is connected to the PTAT current generation circuit, and its collector is connected to the emitter of the first transistor; the bases of the thirteenth and fourteenth transistors are respectively connected to VCC. in- and V in+ The emitters are all connected to the collector of the twelfth transistor, and the collectors are all coupled to the ground terminal via resistors; The PNP follower stage includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; wherein the emitters of the fifteenth and sixteenth transistors are both coupled to VCC via resistors, the bases of both transistors are connected to the PTAT current generating circuit, and the collectors are respectively connected to the emitters of the seventeenth and eighteenth transistors; the bases of the seventeenth and eighteenth transistors are respectively connected to the collectors of the thirteenth and fourteenth transistors, and the collectors of both transistors are connected to the ground terminal; The PNP output stage includes a current mirror structure composed of a nineteenth transistor and a twentieth transistor, and a differential input pair composed of a twenty-first transistor and a twenty-second transistor. The emitters of both the nineteenth and twentieth transistors are resistor-coupled to VCC, and their collectors are connected to the collectors of the twenty-first and twenty-second transistors, respectively. The base of the nineteenth transistor is shorted to its collector and connected to the base of the twentieth transistor. The emitters of the twenty-first and twenty-second transistors are interconnected and resistor-coupled to ground, and their bases are connected to the collectors of the fifteenth and sixteenth transistors, respectively. The collector side of the twentieth transistor is the main output terminal V. OUT .

6. The low-noise rail-to-rail input amplifier with base compensation according to claim 5, characterized in that, The NPN input track includes an NPN input stage, an NPN follower stage, and an NPN output stage; The NPN input stage includes a current mirror structure composed of a 23rd transistor and a 24th transistor, and a differential pair composed of a 25th transistor and a 26th transistor. The emitters of both the 23rd and 24th transistors are resistively coupled to ground. The base and collector of the 23rd transistor are shorted and connected to the collector of the first transistor and the base of the 24th transistor. The emitters of both the 25th and 26th transistors are connected to the collector of the 24th transistor, and both emitters are resistively coupled to VCC. The bases are respectively connected to VCC. in- and V in+ ; The NPN follower stage includes a 27th transistor, a 28th transistor, a 29th transistor, and a 30th transistor; wherein the emitters of the 27th and 28th transistors are both coupled to ground via resistors, the bases of both transistors are connected to the base of the 24th transistor, and the collectors are connected to the emitters of the 29th and 30th transistors, respectively; the collectors of the 29th and 30th transistors are both connected to VCC, and the bases of both transistors are connected to the collectors of the 25th and 26th transistors, respectively. The NPN output stage includes a current mirror structure composed of transistors 31 and 32, and a differential input pair composed of transistors 33 and 34. The emitters of transistors 31 and 32 are both resistor-coupled to ground, and their collectors are connected to the collectors of transistors 33 and 34, respectively. The base of transistor 31 is shorted to its collector and connected to the base of transistor 32. The emitters of transistors 33 and 34 are interconnected and resistor-coupled to VCC, and their bases are connected to the collectors of transistors 27 and 28, respectively. The collector side of the thirty-second transistor is the main output terminal V. OUT .

7. The low-noise rail-to-rail input amplifier with base compensation according to any one of claims 1 to 6, characterized in that, The PTAT current generation circuit includes a current mirror structure composed of transistors 35 and 36, as well as transistors 37, 38, and 39, and a second MOS transistor. The emitters of transistors 35 and 36 are both resistor-coupled to ground, and their collectors are connected to the collectors of transistors 37 and 38, respectively. The base of transistor 36 is shorted to its collector and connected to the base of transistor 35. The emitters of transistors 37 and 38 are resistor-coupled to VCC, and their bases are interconnected and coupled to the PVBI terminal. The source of the second MOS transistor is connected to the emitter of transistor 36, its gate is connected to the collector of transistor 37, and its drain is connected to the collector of transistor 39. The emitter of transistor 39 is resistor-coupled to VCC, its base is shorted to its collector and connected to the PVBO terminal, providing a basic bias current for the global circuit.

8. The low-noise rail-to-rail input amplifier with base compensation according to any one of claims 1 to 6, characterized in that, The bias voltage generating circuit includes a 40th transistor, a 41st transistor, a first resistor, a second resistor, and a third resistor; wherein the first resistor, the second resistor, and the third resistor are connected in sequence, the first resistor is also connected to VCC, and the third resistor is also connected to the collector of the 40th transistor; the emitter of the 40th transistor is coupled to ground, the base is shorted to the collector, and VCC is output from the base. B2 The emitter of the forty-first transistor is coupled to VCC, the base is connected to the common node of the first and second resistors, the collector is connected to the common node of the second and third resistors, and V is output from the collector. B1 .

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