Port-driven low-latency routing method and system based on PCIe network architecture

By assigning unique codes to switch ports in the PCIe network architecture and embedding the target path in the data packets, the problems of path opacity and imprecise QoS scheduling in the PCIe interconnect architecture are solved, achieving low-latency and efficient data packet forwarding, which is suitable for high-performance computing and real-time communication.

CN122226682APending Publication Date: 2026-06-16SHANGHAI XINLIJI SEMICON CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI XINLIJI SEMICON CO LTD
Filing Date
2025-11-25
Publication Date
2026-06-16

AI Technical Summary

Technical Problem

The existing PCIe interconnect architecture struggles to achieve explicit path-level control and efficient QoS scheduling in high-density, multi-host collaborative scenarios, resulting in high packet forwarding complexity, opaque paths, and imprecise traffic scheduling, which fails to meet the needs of high-performance computing and real-time communication.

Method used

A port-driven low-latency routing method is adopted. By assigning a unique port code to each switch port, a global port mapping table is built, and the target path in the custom prefix is ​​embedded in the data packet. The switch forwards the data packet directly according to the port code, avoiding the need to look up the BDF routing table.

Benefits of technology

It significantly reduces packet forwarding latency and complexity, improves data throughput efficiency, simplifies chip logic structure, and achieves deterministic and stable link latency, making it suitable for high-performance computing and real-time communication.

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Abstract

The application discloses a port driving type low-delay routing method and system based on a PCIe network architecture, the method comprising the following steps: pre-allocating a unique port code for each port, and constructing a global port mapping table, wherein the global port mapping table comprises a port code and port information corresponding to each port, and the port information comprises address information of a device connected to the port; when a source device sends a data packet to a target device, the source device determines a source port code and a target port code according to the global port mapping table; a target path from the source port to the target port is determined based on the topology structure of the PCIe network architecture and is written into a custom prefix of the data packet; the switch analyzes the target path in the custom prefix, determines a current target transmission port according to the target path, and transmits the data packet to the current target transmission port. The application can significantly reduce switching delay and forwarding complexity, and improve communication efficiency and link controllability in a high-density interconnection scenario.
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